drivers/staging/gma500/psb_drv.h

   1 /**************************************************************************
   2  * Copyright (c) 2007-2011, Intel Corporation.
   3  * All Rights Reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  *
  18  **************************************************************************/
  19
  20 #ifndef _PSB_DRV_H_
  21 #define _PSB_DRV_H_
  22
  23 #include <linux/kref.h>
  24
  25 #include <drm/drmP.h>
  26 #include "drm_global.h"
  27 #include "gem_glue.h"
  28 #include "psb_drm.h"
  29 #include "psb_reg.h"
  30 #include "psb_intel_drv.h"
  31 #include "gtt.h"
  32 #include "power.h"
  33 #include "mrst.h"
  34
  35 /* Append new drm mode definition here, align with libdrm definition */
  36 #define DRM_MODE_SCALE_NO_SCALE         2
  37 #define DRM_MODE_CONNECTOR_MIPI         15
  38
  39 enum {
  40         CHIP_PSB_8108 = 0,              /* Poulsbo */
  41         CHIP_PSB_8109 = 1,              /* Poulsbo */
  42         CHIP_MRST_4100 = 2,             /* Moorestown/Oaktrail */
  43         CHIP_MFLD_0130 = 3,             /* Medfield */
  44 };
  45
  46 #define IS_MRST(dev) (((dev)->pci_device & 0xfffc) == 0x4100)
  47 #define IS_MFLD(dev) (((dev)->pci_device & 0xfff8) == 0x0130)
  48
  49 /*
  50  * Driver definitions
  51  */
  52
  53 #define DRIVER_NAME "gma500"
  54 #define DRIVER_DESC "DRM driver for the Intel GMA500"
  55
  56 #define PSB_DRM_DRIVER_DATE "2011-06-06"
  57 #define PSB_DRM_DRIVER_MAJOR 1
  58 #define PSB_DRM_DRIVER_MINOR 0
  59 #define PSB_DRM_DRIVER_PATCHLEVEL 0
  60
  61 /*
  62  *      Hardware offsets
  63  */
  64 #define PSB_VDC_OFFSET           0x00000000
  65 #define PSB_VDC_SIZE             0x000080000
  66 #define MRST_MMIO_SIZE           0x0000C0000
  67 #define MDFLD_MMIO_SIZE          0x000100000
  68 #define PSB_SGX_SIZE             0x8000
  69 #define PSB_SGX_OFFSET           0x00040000
  70 #define MRST_SGX_OFFSET          0x00080000
  71 /*
  72  *      PCI resource identifiers
  73  */
  74 #define PSB_MMIO_RESOURCE        0
  75 #define PSB_GATT_RESOURCE        2
  76 #define PSB_GTT_RESOURCE         3
  77 /*
  78  *      PCI configuration
  79  */
  80 #define PSB_GMCH_CTRL            0x52
  81 #define PSB_BSM                  0x5C
  82 #define _PSB_GMCH_ENABLED        0x4
  83 #define PSB_PGETBL_CTL           0x2020
  84 #define _PSB_PGETBL_ENABLED      0x00000001
  85 #define PSB_SGX_2D_SLAVE_PORT    0x4000
  86
  87 /* To get rid of */
  88 #define PSB_TT_PRIV0_LIMIT       (256*1024*1024)
  89 #define PSB_TT_PRIV0_PLIMIT      (PSB_TT_PRIV0_LIMIT >> PAGE_SHIFT)
  90
  91 /*
  92  *      SGX side MMU definitions (these can probably go)
  93  */
  94
  95 /*
  96  *      Flags for external memory type field.
  97  */
  98 #define PSB_MMU_CACHED_MEMORY     0x0001        /* Bind to MMU only */
  99 #define PSB_MMU_RO_MEMORY         0x0002        /* MMU RO memory */
 100 #define PSB_MMU_WO_MEMORY         0x0004        /* MMU WO memory */
 101 /*
 102  *      PTE's and PDE's
 103  */
 104 #define PSB_PDE_MASK              0x003FFFFF
 105 #define PSB_PDE_SHIFT             22
 106 #define PSB_PTE_SHIFT             12
 107 /*
 108  *      Cache control
 109  */
 110 #define PSB_PTE_VALID             0x0001        /* PTE / PDE valid */
 111 #define PSB_PTE_WO                0x0002        /* Write only */
 112 #define PSB_PTE_RO                0x0004        /* Read only */
 113 #define PSB_PTE_CACHED            0x0008        /* CPU cache coherent */
 114
 115 /*
 116  *      VDC registers and bits
 117  */
 118 #define PSB_MSVDX_CLOCKGATING     0x2064
 119 #define PSB_TOPAZ_CLOCKGATING     0x2068
 120 #define PSB_HWSTAM                0x2098
 121 #define PSB_INSTPM                0x20C0
 122 #define PSB_INT_IDENTITY_R        0x20A4
 123 #define _MDFLD_PIPEC_EVENT_FLAG   (1<<2)
 124 #define _MDFLD_PIPEC_VBLANK_FLAG  (1<<3)
 125 #define _PSB_DPST_PIPEB_FLAG      (1<<4)
 126 #define _MDFLD_PIPEB_EVENT_FLAG   (1<<4)
 127 #define _PSB_VSYNC_PIPEB_FLAG     (1<<5)
 128 #define _PSB_DPST_PIPEA_FLAG      (1<<6)
 129 #define _PSB_PIPEA_EVENT_FLAG     (1<<6)
 130 #define _PSB_VSYNC_PIPEA_FLAG     (1<<7)
 131 #define _MDFLD_MIPIA_FLAG         (1<<16)
 132 #define _MDFLD_MIPIC_FLAG         (1<<17)
 133 #define _PSB_IRQ_SGX_FLAG         (1<<18)
 134 #define _PSB_IRQ_MSVDX_FLAG       (1<<19)
 135 #define _LNC_IRQ_TOPAZ_FLAG       (1<<20)
 136
 137 /* This flag includes all the display IRQ bits excepts the vblank irqs. */
 138 #define _MDFLD_DISP_ALL_IRQ_FLAG (_MDFLD_PIPEC_EVENT_FLAG | \
 139                                   _MDFLD_PIPEB_EVENT_FLAG | \
 140                                   _PSB_PIPEA_EVENT_FLAG | \
 141                                   _PSB_VSYNC_PIPEA_FLAG | \
 142                                   _MDFLD_MIPIA_FLAG | \
 143                                   _MDFLD_MIPIC_FLAG)
 144 #define PSB_INT_IDENTITY_R        0x20A4
 145 #define PSB_INT_MASK_R            0x20A8
 146 #define PSB_INT_ENABLE_R          0x20A0
 147
 148 #define _PSB_MMU_ER_MASK      0x0001FF00
 149 #define _PSB_MMU_ER_HOST      (1 << 16)
 150 #define GPIOA                   0x5010
 151 #define GPIOB                   0x5014
 152 #define GPIOC                   0x5018
 153 #define GPIOD                   0x501c
 154 #define GPIOE                   0x5020
 155 #define GPIOF                   0x5024
 156 #define GPIOG                   0x5028
 157 #define GPIOH                   0x502c
 158 #define GPIO_CLOCK_DIR_MASK             (1 << 0)
 159 #define GPIO_CLOCK_DIR_IN               (0 << 1)
 160 #define GPIO_CLOCK_DIR_OUT              (1 << 1)
 161 #define GPIO_CLOCK_VAL_MASK             (1 << 2)
 162 #define GPIO_CLOCK_VAL_OUT              (1 << 3)
 163 #define GPIO_CLOCK_VAL_IN               (1 << 4)
 164 #define GPIO_CLOCK_PULLUP_DISABLE       (1 << 5)
 165 #define GPIO_DATA_DIR_MASK              (1 << 8)
 166 #define GPIO_DATA_DIR_IN                (0 << 9)
 167 #define GPIO_DATA_DIR_OUT               (1 << 9)
 168 #define GPIO_DATA_VAL_MASK              (1 << 10)
 169 #define GPIO_DATA_VAL_OUT               (1 << 11)
 170 #define GPIO_DATA_VAL_IN                (1 << 12)
 171 #define GPIO_DATA_PULLUP_DISABLE        (1 << 13)
 172
 173 #define VCLK_DIVISOR_VGA0   0x6000
 174 #define VCLK_DIVISOR_VGA1   0x6004
 175 #define VCLK_POST_DIV       0x6010
 176
 177 #define PSB_COMM_2D (PSB_ENGINE_2D << 4)
 178 #define PSB_COMM_3D (PSB_ENGINE_3D << 4)
 179 #define PSB_COMM_TA (PSB_ENGINE_TA << 4)
 180 #define PSB_COMM_HP (PSB_ENGINE_HP << 4)
 181 #define PSB_COMM_USER_IRQ (1024 >> 2)
 182 #define PSB_COMM_USER_IRQ_LOST (PSB_COMM_USER_IRQ + 1)
 183 #define PSB_COMM_FW (2048 >> 2)
 184
 185 #define PSB_UIRQ_VISTEST               1
 186 #define PSB_UIRQ_OOM_REPLY             2
 187 #define PSB_UIRQ_FIRE_TA_REPLY         3
 188 #define PSB_UIRQ_FIRE_RASTER_REPLY     4
 189
 190 #define PSB_2D_SIZE (256*1024*1024)
 191 #define PSB_MAX_RELOC_PAGES 1024
 192
 193 #define PSB_LOW_REG_OFFS 0x0204
 194 #define PSB_HIGH_REG_OFFS 0x0600
 195
 196 #define PSB_NUM_VBLANKS 2
 197
 198
 199 #define PSB_2D_SIZE (256*1024*1024)
 200 #define PSB_MAX_RELOC_PAGES 1024
 201
 202 #define PSB_LOW_REG_OFFS 0x0204
 203 #define PSB_HIGH_REG_OFFS 0x0600
 204
 205 #define PSB_NUM_VBLANKS 2
 206 #define PSB_WATCHDOG_DELAY (DRM_HZ * 2)
 207 #define PSB_LID_DELAY (DRM_HZ / 10)
 208
 209 #define MDFLD_PNW_B0 0x04
 210 #define MDFLD_PNW_C0 0x08
 211
 212 #define MDFLD_DSR_2D_3D_0       (1 << 0)
 213 #define MDFLD_DSR_2D_3D_2       (1 << 1)
 214 #define MDFLD_DSR_CURSOR_0      (1 << 2)
 215 #define MDFLD_DSR_CURSOR_2      (1 << 3)
 216 #define MDFLD_DSR_OVERLAY_0     (1 << 4)
 217 #define MDFLD_DSR_OVERLAY_2     (1 << 5)
 218 #define MDFLD_DSR_MIPI_CONTROL  (1 << 6)
 219 #define MDFLD_DSR_DAMAGE_MASK_0 (1 << 0) | (1 << 2) | (1 << 4)
 220 #define MDFLD_DSR_DAMAGE_MASK_2 (1 << 1) | (1 << 3) | (1 << 5)
 221 #define MDFLD_DSR_2D_3D         (MDFLD_DSR_2D_3D_0 | MDFLD_DSR_2D_3D_2)
 222
 223 #define MDFLD_DSR_RR            45
 224 #define MDFLD_DPU_ENABLE        (1 << 31)
 225 #define MDFLD_DSR_FULLSCREEN    (1 << 30)
 226 #define MDFLD_DSR_DELAY         (DRM_HZ / MDFLD_DSR_RR)
 227
 228 #define PSB_PWR_STATE_ON                1
 229 #define PSB_PWR_STATE_OFF               2
 230
 231 #define PSB_PMPOLICY_NOPM               0
 232 #define PSB_PMPOLICY_CLOCKGATING        1
 233 #define PSB_PMPOLICY_POWERDOWN          2
 234
 235 #define PSB_PMSTATE_POWERUP             0
 236 #define PSB_PMSTATE_CLOCKGATED          1
 237 #define PSB_PMSTATE_POWERDOWN           2
 238 #define PSB_PCIx_MSI_ADDR_LOC           0x94
 239 #define PSB_PCIx_MSI_DATA_LOC           0x98
 240
 241 /* Medfield crystal settings */
 242 #define KSEL_CRYSTAL_19 1
 243 #define KSEL_BYPASS_19 5
 244 #define KSEL_BYPASS_25 6
 245 #define KSEL_BYPASS_83_100 7
 246
 247 struct opregion_header;
 248 struct opregion_acpi;
 249 struct opregion_swsci;
 250 struct opregion_asle;
 251
 252 struct psb_intel_opregion {
 253         struct opregion_header *header;
 254         struct opregion_acpi *acpi;
 255         struct opregion_swsci *swsci;
 256         struct opregion_asle *asle;
 257         int enabled;
 258 };
 259
 260 struct psb_ops;
 261
 262 struct drm_psb_private {
 263         struct drm_device *dev;
 264         const struct psb_ops *ops;
 265
 266         struct psb_gtt gtt;
 267
 268         /* GTT Memory manager */
 269         struct psb_gtt_mm *gtt_mm;
 270         struct page *scratch_page;
 271         u32 *gtt_map;
 272         uint32_t stolen_base;
 273         void *vram_addr;
 274         unsigned long vram_stolen_size;
 275         int gtt_initialized;
 276         u16 gmch_ctrl;          /* Saved GTT setup */
 277         u32 pge_ctl;
 278
 279         struct mutex gtt_mutex;
 280         struct resource *gtt_mem;       /* Our PCI resource */
 281
 282         struct psb_mmu_driver *mmu;
 283         struct psb_mmu_pd *pf_pd;
 284
 285         /*
 286          * Register base
 287          */
 288
 289         uint8_t *sgx_reg;
 290         uint8_t *vdc_reg;
 291         uint32_t gatt_free_offset;
 292
 293         /*
 294          * Fencing / irq.
 295          */
 296
 297         uint32_t vdc_irq_mask;
 298         uint32_t pipestat[PSB_NUM_PIPE];
 299
 300         spinlock_t irqmask_lock;
 301
 302         /*
 303          * Power
 304          */
 305
 306         bool suspended;
 307         bool display_power;
 308         int display_count;
 309
 310         /*
 311          * Modesetting
 312          */
 313         struct psb_intel_mode_device mode_dev;
 314
 315         struct drm_crtc *plane_to_crtc_mapping[PSB_NUM_PIPE];
 316         struct drm_crtc *pipe_to_crtc_mapping[PSB_NUM_PIPE];
 317         uint32_t num_pipe;
 318
 319         /*
 320          * OSPM info (Power management base) (can go ?)
 321          */
 322         uint32_t ospm_base;
 323
 324         /*
 325          * Sizes info
 326          */
 327
 328         struct drm_psb_sizes_arg sizes;
 329
 330         u32 fuse_reg_value;
 331         u32 video_device_fuse;
 332
 333         /* PCI revision ID for B0:D2:F0 */
 334         uint8_t platform_rev_id;
 335
 336         /*
 337          * LVDS info
 338          */
 339         int backlight_duty_cycle;       /* restore backlight to this value */
 340         bool panel_wants_dither;
 341         struct drm_display_mode *panel_fixed_mode;
 342         struct drm_display_mode *lfp_lvds_vbt_mode;
 343         struct drm_display_mode *sdvo_lvds_vbt_mode;
 344
 345         struct bdb_lvds_backlight *lvds_bl; /* LVDS backlight info from VBT */
 346         struct psb_intel_i2c_chan *lvds_i2c_bus;
 347
 348         /* Feature bits from the VBIOS */
 349         unsigned int int_tv_support:1;
 350         unsigned int lvds_dither:1;
 351         unsigned int lvds_vbt:1;
 352         unsigned int int_crt_support:1;
 353         unsigned int lvds_use_ssc:1;
 354         int lvds_ssc_freq;
 355         bool is_lvds_on;
 356         bool is_mipi_on;
 357         u32 mipi_ctrl_display;
 358
 359         unsigned int core_freq;
 360         uint32_t iLVDS_enable;
 361
 362         /* Runtime PM state */
 363         int rpm_enabled;
 364
 365         /* MID specific */
 366         struct mrst_vbt vbt_data;
 367         struct mrst_gct_data gct_data;
 368
 369         /* MIPI Panel type etc */
 370         int panel_id;
 371         bool dual_mipi;         /* dual display - DPI & DBI */
 372         bool dpi_panel_on;      /* The DPI panel power is on */
 373         bool dpi_panel_on2;     /* The DPI panel power is on */
 374         bool dbi_panel_on;      /* The DBI panel power is on */
 375         bool dbi_panel_on2;     /* The DBI panel power is on */
 376         u32 dsr_fb_update;      /* DSR FB update counter */
 377
 378         /* Moorestown HDMI state */
 379         struct mrst_hdmi_dev *hdmi_priv;
 380
 381         /* Moorestown pipe config register value cache */
 382         uint32_t pipeconf;
 383         uint32_t pipeconf1;
 384         uint32_t pipeconf2;
 385
 386         /* Moorestown plane control register value cache */
 387         uint32_t dspcntr;
 388         uint32_t dspcntr1;
 389         uint32_t dspcntr2;
 390
 391         /*
 392          * Register state
 393          */
 394         uint32_t saveDSPACNTR;
 395         uint32_t saveDSPBCNTR;
 396         uint32_t savePIPEACONF;
 397         uint32_t savePIPEBCONF;
 398         uint32_t savePIPEASRC;
 399         uint32_t savePIPEBSRC;
 400         uint32_t saveFPA0;
 401         uint32_t saveFPA1;
 402         uint32_t saveDPLL_A;
 403         uint32_t saveDPLL_A_MD;
 404         uint32_t saveHTOTAL_A;
 405         uint32_t saveHBLANK_A;
 406         uint32_t saveHSYNC_A;
 407         uint32_t saveVTOTAL_A;
 408         uint32_t saveVBLANK_A;
 409         uint32_t saveVSYNC_A;
 410         uint32_t saveDSPASTRIDE;
 411         uint32_t saveDSPASIZE;
 412         uint32_t saveDSPAPOS;
 413         uint32_t saveDSPABASE;
 414         uint32_t saveDSPASURF;
 415         uint32_t saveDSPASTATUS;
 416         uint32_t saveFPB0;
 417         uint32_t saveFPB1;
 418         uint32_t saveDPLL_B;
 419         uint32_t saveDPLL_B_MD;
 420         uint32_t saveHTOTAL_B;
 421         uint32_t saveHBLANK_B;
 422         uint32_t saveHSYNC_B;
 423         uint32_t saveVTOTAL_B;
 424         uint32_t saveVBLANK_B;
 425         uint32_t saveVSYNC_B;
 426         uint32_t saveDSPBSTRIDE;
 427         uint32_t saveDSPBSIZE;
 428         uint32_t saveDSPBPOS;
 429         uint32_t saveDSPBBASE;
 430         uint32_t saveDSPBSURF;
 431         uint32_t saveDSPBSTATUS;
 432         uint32_t saveVCLK_DIVISOR_VGA0;
 433         uint32_t saveVCLK_DIVISOR_VGA1;
 434         uint32_t saveVCLK_POST_DIV;
 435         uint32_t saveVGACNTRL;
 436         uint32_t saveADPA;
 437         uint32_t saveLVDS;
 438         uint32_t saveDVOA;
 439         uint32_t saveDVOB;
 440         uint32_t saveDVOC;
 441         uint32_t savePP_ON;
 442         uint32_t savePP_OFF;
 443         uint32_t savePP_CONTROL;
 444         uint32_t savePP_CYCLE;
 445         uint32_t savePFIT_CONTROL;
 446         uint32_t savePaletteA[256];
 447         uint32_t savePaletteB[256];
 448         uint32_t saveBLC_PWM_CTL2;
 449         uint32_t saveBLC_PWM_CTL;
 450         uint32_t saveCLOCKGATING;
 451         uint32_t saveDSPARB;
 452         uint32_t saveDSPATILEOFF;
 453         uint32_t saveDSPBTILEOFF;
 454         uint32_t saveDSPAADDR;
 455         uint32_t saveDSPBADDR;
 456         uint32_t savePFIT_AUTO_RATIOS;
 457         uint32_t savePFIT_PGM_RATIOS;
 458         uint32_t savePP_ON_DELAYS;
 459         uint32_t savePP_OFF_DELAYS;
 460         uint32_t savePP_DIVISOR;
 461         uint32_t saveBSM;
 462         uint32_t saveVBT;
 463         uint32_t saveBCLRPAT_A;
 464         uint32_t saveBCLRPAT_B;
 465         uint32_t saveDSPALINOFF;
 466         uint32_t saveDSPBLINOFF;
 467         uint32_t savePERF_MODE;
 468         uint32_t saveDSPFW1;
 469         uint32_t saveDSPFW2;
 470         uint32_t saveDSPFW3;
 471         uint32_t saveDSPFW4;
 472         uint32_t saveDSPFW5;
 473         uint32_t saveDSPFW6;
 474         uint32_t saveCHICKENBIT;
 475         uint32_t saveDSPACURSOR_CTRL;
 476         uint32_t saveDSPBCURSOR_CTRL;
 477         uint32_t saveDSPACURSOR_BASE;
 478         uint32_t saveDSPBCURSOR_BASE;
 479         uint32_t saveDSPACURSOR_POS;
 480         uint32_t saveDSPBCURSOR_POS;
 481         uint32_t save_palette_a[256];
 482         uint32_t save_palette_b[256];
 483         uint32_t saveOV_OVADD;
 484         uint32_t saveOV_OGAMC0;
 485         uint32_t saveOV_OGAMC1;
 486         uint32_t saveOV_OGAMC2;
 487         uint32_t saveOV_OGAMC3;
 488         uint32_t saveOV_OGAMC4;
 489         uint32_t saveOV_OGAMC5;
 490         uint32_t saveOVC_OVADD;
 491         uint32_t saveOVC_OGAMC0;
 492         uint32_t saveOVC_OGAMC1;
 493         uint32_t saveOVC_OGAMC2;
 494         uint32_t saveOVC_OGAMC3;
 495         uint32_t saveOVC_OGAMC4;
 496         uint32_t saveOVC_OGAMC5;
 497
 498         /* MSI reg save */
 499         uint32_t msi_addr;
 500         uint32_t msi_data;
 501
 502         /* Medfield specific register save state */
 503         uint32_t saveHDMIPHYMISCCTL;
 504         uint32_t saveHDMIB_CONTROL;
 505         uint32_t saveDSPCCNTR;
 506         uint32_t savePIPECCONF;
 507         uint32_t savePIPECSRC;
 508         uint32_t saveHTOTAL_C;
 509         uint32_t saveHBLANK_C;
 510         uint32_t saveHSYNC_C;
 511         uint32_t saveVTOTAL_C;
 512         uint32_t saveVBLANK_C;
 513         uint32_t saveVSYNC_C;
 514         uint32_t saveDSPCSTRIDE;
 515         uint32_t saveDSPCSIZE;
 516         uint32_t saveDSPCPOS;
 517         uint32_t saveDSPCSURF;
 518         uint32_t saveDSPCSTATUS;
 519         uint32_t saveDSPCLINOFF;
 520         uint32_t saveDSPCTILEOFF;
 521         uint32_t saveDSPCCURSOR_CTRL;
 522         uint32_t saveDSPCCURSOR_BASE;
 523         uint32_t saveDSPCCURSOR_POS;
 524         uint32_t save_palette_c[256];
 525         uint32_t saveOV_OVADD_C;
 526         uint32_t saveOV_OGAMC0_C;
 527         uint32_t saveOV_OGAMC1_C;
 528         uint32_t saveOV_OGAMC2_C;
 529         uint32_t saveOV_OGAMC3_C;
 530         uint32_t saveOV_OGAMC4_C;
 531         uint32_t saveOV_OGAMC5_C;
 532
 533         /* DSI register save */
 534         uint32_t saveDEVICE_READY_REG;
 535         uint32_t saveINTR_EN_REG;
 536         uint32_t saveDSI_FUNC_PRG_REG;
 537         uint32_t saveHS_TX_TIMEOUT_REG;
 538         uint32_t saveLP_RX_TIMEOUT_REG;
 539         uint32_t saveTURN_AROUND_TIMEOUT_REG;
 540         uint32_t saveDEVICE_RESET_REG;
 541         uint32_t saveDPI_RESOLUTION_REG;
 542         uint32_t saveHORIZ_SYNC_PAD_COUNT_REG;
 543         uint32_t saveHORIZ_BACK_PORCH_COUNT_REG;
 544         uint32_t saveHORIZ_FRONT_PORCH_COUNT_REG;
 545         uint32_t saveHORIZ_ACTIVE_AREA_COUNT_REG;
 546         uint32_t saveVERT_SYNC_PAD_COUNT_REG;
 547         uint32_t saveVERT_BACK_PORCH_COUNT_REG;
 548         uint32_t saveVERT_FRONT_PORCH_COUNT_REG;
 549         uint32_t saveHIGH_LOW_SWITCH_COUNT_REG;
 550         uint32_t saveINIT_COUNT_REG;
 551         uint32_t saveMAX_RET_PAK_REG;
 552         uint32_t saveVIDEO_FMT_REG;
 553         uint32_t saveEOT_DISABLE_REG;
 554         uint32_t saveLP_BYTECLK_REG;
 555         uint32_t saveHS_LS_DBI_ENABLE_REG;
 556         uint32_t saveTXCLKESC_REG;
 557         uint32_t saveDPHY_PARAM_REG;
 558         uint32_t saveMIPI_CONTROL_REG;
 559         uint32_t saveMIPI;
 560         uint32_t saveMIPI_C;
 561
 562         /* DPST register save */
 563         uint32_t saveHISTOGRAM_INT_CONTROL_REG;
 564         uint32_t saveHISTOGRAM_LOGIC_CONTROL_REG;
 565         uint32_t savePWM_CONTROL_LOGIC;
 566
 567         /*
 568          * DSI info.
 569          */
 570         void * dbi_dsr_info;
 571         void * dbi_dpu_info;
 572         void * dsi_configs[2];
 573         /*
 574          * LID-Switch
 575          */
 576         spinlock_t lid_lock;
 577         struct timer_list lid_timer;
 578         struct psb_intel_opregion opregion;
 579         u32 *lid_state;
 580         u32 lid_last_state;
 581
 582         /*
 583          * Watchdog
 584          */
 585
 586         uint32_t apm_reg;
 587         uint16_t apm_base;
 588
 589         /*
 590          * Used for modifying backlight from
 591          * xrandr -- consider removing and using HAL instead
 592          */
 593         struct backlight_device *backlight_device;
 594         struct drm_property *backlight_property;
 595         uint32_t blc_adj1;
 596         uint32_t blc_adj2;
 597
 598         void *fbdev;
 599         /* DPST state */
 600         uint32_t dsr_idle_count;
 601         bool is_in_idle;
 602         bool dsr_enable;
 603         void (*exit_idle)(struct drm_device *dev, u32 update_src, void *p_surfaceAddr, bool check_hw_on_only);
 604
 605         /* 2D acceleration */
 606         struct mutex mutex_2d;
 607
 608         /* FIXME: Arrays anyone ? */
 609         struct mdfld_dsi_encoder *encoder0;
 610         struct mdfld_dsi_encoder *encoder2;
 611         struct mdfld_dsi_dbi_output * dbi_output;
 612         struct mdfld_dsi_dbi_output * dbi_output2;
 613         u32 bpp;
 614         u32 bpp2;
 615
 616         bool dispstatus;
 617 };
 618
 619
 620 /*
 621  *      Operations for each board type
 622  */
 623
 624 struct psb_ops {
 625         const char *name;
 626         unsigned int accel_2d:1;
 627         int pipes;              /* Number of output pipes */
 628         int crtcs;              /* Number of CRTCs */
 629         int sgx_offset;         /* Base offset of SGX device */
 630
 631         /* Sub functions */
 632         struct drm_crtc_helper_funcs const *crtc_helper;
 633         struct drm_crtc_funcs const *crtc_funcs;
 634
 635         /* Setup hooks */
 636         int (*chip_setup)(struct drm_device *dev);
 637         void (*chip_teardown)(struct drm_device *dev);
 638
 639         /* Display management hooks */
 640         int (*output_init)(struct drm_device *dev);
 641         /* Power management hooks */
 642         void (*init_pm)(struct drm_device *dev);
 643         int (*save_regs)(struct drm_device *dev);
 644         int (*restore_regs)(struct drm_device *dev);
 645         int (*power_up)(struct drm_device *dev);
 646         int (*power_down)(struct drm_device *dev);
 647 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
 648         /* Backlight */
 649         int (*backlight_init)(struct drm_device *dev);
 650 #endif
 651 };
 652
 653
 654
 655 struct psb_mmu_driver;
 656
 657 extern int drm_crtc_probe_output_modes(struct drm_device *dev, int, int);
 658 extern int drm_pick_crtcs(struct drm_device *dev);
 659
 660 static inline struct drm_psb_private *psb_priv(struct drm_device *dev)
 661 {
 662         return (struct drm_psb_private *) dev->dev_private;
 663 }
 664
 665 /*
 666  * MMU stuff.
 667  */
 668
 669 extern struct psb_mmu_driver *psb_mmu_driver_init(uint8_t __iomem * registers,
 670                                         int trap_pagefaults,
 671                                         int invalid_type,
 672                                         struct drm_psb_private *dev_priv);
 673 extern void psb_mmu_driver_takedown(struct psb_mmu_driver *driver);
 674 extern struct psb_mmu_pd *psb_mmu_get_default_pd(struct psb_mmu_driver
 675                                                  *driver);
 676 extern void psb_mmu_mirror_gtt(struct psb_mmu_pd *pd, uint32_t mmu_offset,
 677                                uint32_t gtt_start, uint32_t gtt_pages);
 678 extern struct psb_mmu_pd *psb_mmu_alloc_pd(struct psb_mmu_driver *driver,
 679                                            int trap_pagefaults,
 680                                            int invalid_type);
 681 extern void psb_mmu_free_pagedir(struct psb_mmu_pd *pd);
 682 extern void psb_mmu_flush(struct psb_mmu_driver *driver, int rc_prot);
 683 extern void psb_mmu_remove_pfn_sequence(struct psb_mmu_pd *pd,
 684                                         unsigned long address,
 685                                         uint32_t num_pages);
 686 extern int psb_mmu_insert_pfn_sequence(struct psb_mmu_pd *pd,
 687                                        uint32_t start_pfn,
 688                                        unsigned long address,
 689                                        uint32_t num_pages, int type);
 690 extern int psb_mmu_virtual_to_pfn(struct psb_mmu_pd *pd, uint32_t virtual,
 691                                   unsigned long *pfn);
 692
 693 /*
 694  * Enable / disable MMU for different requestors.
 695  */
 696
 697
 698 extern void psb_mmu_set_pd_context(struct psb_mmu_pd *pd, int hw_context);
 699 extern int psb_mmu_insert_pages(struct psb_mmu_pd *pd, struct page **pages,
 700                                 unsigned long address, uint32_t num_pages,
 701                                 uint32_t desired_tile_stride,
 702                                 uint32_t hw_tile_stride, int type);
 703 extern void psb_mmu_remove_pages(struct psb_mmu_pd *pd,
 704                                  unsigned long address, uint32_t num_pages,
 705                                  uint32_t desired_tile_stride,
 706                                  uint32_t hw_tile_stride);
 707 /*
 708  *psb_irq.c
 709  */
 710
 711 extern irqreturn_t psb_irq_handler(DRM_IRQ_ARGS);
 712 extern int psb_irq_enable_dpst(struct drm_device *dev);
 713 extern int psb_irq_disable_dpst(struct drm_device *dev);
 714 extern void psb_irq_preinstall(struct drm_device *dev);
 715 extern int psb_irq_postinstall(struct drm_device *dev);
 716 extern void psb_irq_uninstall(struct drm_device *dev);
 717 extern void psb_irq_turn_on_dpst(struct drm_device *dev);
 718 extern void psb_irq_turn_off_dpst(struct drm_device *dev);
 719
 720 extern void psb_irq_uninstall_islands(struct drm_device *dev, int hw_islands);
 721 extern int psb_vblank_wait2(struct drm_device *dev, unsigned int *sequence);
 722 extern int psb_vblank_wait(struct drm_device *dev, unsigned int *sequence);
 723 extern int psb_enable_vblank(struct drm_device *dev, int crtc);
 724 extern void psb_disable_vblank(struct drm_device *dev, int crtc);
 725 void
 726 psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
 727
 728 void
 729 psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
 730
 731 extern u32 psb_get_vblank_counter(struct drm_device *dev, int crtc);
 732
 733 extern int mdfld_enable_te(struct drm_device *dev, int pipe);
 734 extern void mdfld_disable_te(struct drm_device *dev, int pipe);
 735
 736 /*
 737  * intel_opregion.c
 738  */
 739 extern int gma_intel_opregion_init(struct drm_device *dev);
 740 extern int gma_intel_opregion_exit(struct drm_device *dev);
 741
 742 /*
 743  * framebuffer.c
 744  */
 745 extern int psbfb_probed(struct drm_device *dev);
 746 extern int psbfb_remove(struct drm_device *dev,
 747                         struct drm_framebuffer *fb);
 748 /*
 749  * accel_2d.c
 750  */
 751 extern void psbfb_copyarea(struct fb_info *info,
 752                                         const struct fb_copyarea *region);
 753 extern int psbfb_sync(struct fb_info *info);
 754 extern void psb_spank(struct drm_psb_private *dev_priv);
 755 extern int psb_accel_ioctl(struct drm_device *dev, void *data,
 756                                                         struct drm_file *file);
 757
 758 /*
 759  * psb_reset.c
 760  */
 761
 762 extern void psb_lid_timer_init(struct drm_psb_private *dev_priv);
 763 extern void psb_lid_timer_takedown(struct drm_psb_private *dev_priv);
 764 extern void psb_print_pagefault(struct drm_psb_private *dev_priv);
 765
 766 /* modesetting */
 767 extern void psb_modeset_init(struct drm_device *dev);
 768 extern void psb_modeset_cleanup(struct drm_device *dev);
 769 extern int psb_fbdev_init(struct drm_device *dev);
 770
 771 /* backlight.c */
 772 int gma_backlight_init(struct drm_device *dev);
 773 void gma_backlight_exit(struct drm_device *dev);
 774
 775 /* mrst_crtc.c */
 776 extern const struct drm_crtc_helper_funcs mrst_helper_funcs;
 777
 778 /* mrst_lvds.c */
 779 extern void mrst_lvds_init(struct drm_device *dev,
 780                     struct psb_intel_mode_device *mode_dev);
 781
 782 /* psb_intel_display.c */
 783 extern const struct drm_crtc_helper_funcs psb_intel_helper_funcs;
 784 extern const struct drm_crtc_funcs psb_intel_crtc_funcs;
 785
 786 /* psb_intel_lvds.c */
 787 extern void psb_intel_lvds_prepare(struct drm_encoder *encoder);
 788 extern void psb_intel_lvds_commit(struct drm_encoder *encoder);
 789 extern const struct drm_connector_helper_funcs
 790                                         psb_intel_lvds_connector_helper_funcs;
 791 extern const struct drm_connector_funcs psb_intel_lvds_connector_funcs;
 792
 793 /* gem.c */
 794 extern int psb_gem_init_object(struct drm_gem_object *obj);
 795 extern void psb_gem_free_object(struct drm_gem_object *obj);
 796 extern int psb_gem_get_aperture(struct drm_device *dev, void *data,
 797                         struct drm_file *file);
 798 extern int psb_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
 799                         struct drm_mode_create_dumb *args);
 800 extern int psb_gem_dumb_destroy(struct drm_file *file, struct drm_device *dev,
 801                         uint32_t handle);
 802 extern int psb_gem_dumb_map_gtt(struct drm_file *file, struct drm_device *dev,
 803                         uint32_t handle, uint64_t *offset);
 804 extern int psb_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
 805 extern int psb_gem_create_ioctl(struct drm_device *dev, void *data,
 806                         struct drm_file *file);
 807 extern int psb_gem_mmap_ioctl(struct drm_device *dev, void *data,
 808                                         struct drm_file *file);
 809
 810 /* psb_device.c */
 811 extern const struct psb_ops psb_chip_ops;
 812
 813 /* mrst_device.c */
 814 extern const struct psb_ops mrst_chip_ops;
 815
 816 /* mdfld_device.c */
 817 extern const struct psb_ops mdfld_chip_ops;
 818
 819 /* cdv_device.c */
 820 extern const struct psb_ops cdv_chip_ops;
 821
 822 /*
 823  * Debug print bits setting
 824  */
 825 #define PSB_D_GENERAL (1 << 0)
 826 #define PSB_D_INIT    (1 << 1)
 827 #define PSB_D_IRQ     (1 << 2)
 828 #define PSB_D_ENTRY   (1 << 3)
 829 /* debug the get H/V BP/FP count */
 830 #define PSB_D_HV      (1 << 4)
 831 #define PSB_D_DBI_BF  (1 << 5)
 832 #define PSB_D_PM      (1 << 6)
 833 #define PSB_D_RENDER  (1 << 7)
 834 #define PSB_D_REG     (1 << 8)
 835 #define PSB_D_MSVDX   (1 << 9)
 836 #define PSB_D_TOPAZ   (1 << 10)
 837
 838 extern int drm_psb_no_fb;
 839 extern int drm_idle_check_interval;
 840
 841 /*
 842  *      Utilities
 843  */
 844
 845 static inline u32 MRST_MSG_READ32(uint port, uint offset)
 846 {
 847         int mcr = (0xD0<<24) | (port << 16) | (offset << 8);
 848         uint32_t ret_val = 0;
 849         struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
 850         pci_write_config_dword(pci_root, 0xD0, mcr);
 851         pci_read_config_dword(pci_root, 0xD4, &ret_val);
 852         pci_dev_put(pci_root);
 853         return ret_val;
 854 }
 855 static inline void MRST_MSG_WRITE32(uint port, uint offset, u32 value)
 856 {
 857         int mcr = (0xE0<<24) | (port << 16) | (offset << 8) | 0xF0;
 858         struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
 859         pci_write_config_dword(pci_root, 0xD4, value);
 860         pci_write_config_dword(pci_root, 0xD0, mcr);
 861         pci_dev_put(pci_root);
 862 }
 863 static inline u32 MDFLD_MSG_READ32(uint port, uint offset)
 864 {
 865         int mcr = (0x10<<24) | (port << 16) | (offset << 8);
 866         uint32_t ret_val = 0;
 867         struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
 868         pci_write_config_dword(pci_root, 0xD0, mcr);
 869         pci_read_config_dword(pci_root, 0xD4, &ret_val);
 870         pci_dev_put(pci_root);
 871         return ret_val;
 872 }
 873 static inline void MDFLD_MSG_WRITE32(uint port, uint offset, u32 value)
 874 {
 875         int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0;
 876         struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
 877         pci_write_config_dword(pci_root, 0xD4, value);
 878         pci_write_config_dword(pci_root, 0xD0, mcr);
 879         pci_dev_put(pci_root);
 880 }
 881
 882 static inline uint32_t REGISTER_READ(struct drm_device *dev, uint32_t reg)
 883 {
 884         struct drm_psb_private *dev_priv = dev->dev_private;
 885         return ioread32(dev_priv->vdc_reg + reg);
 886 }
 887
 888 #define REG_READ(reg)          REGISTER_READ(dev, (reg))
 889
 890 static inline void REGISTER_WRITE(struct drm_device *dev, uint32_t reg,
 891                                       uint32_t val)
 892 {
 893         struct drm_psb_private *dev_priv = dev->dev_private;
 894         iowrite32((val), dev_priv->vdc_reg + (reg));
 895 }
 896
 897 #define REG_WRITE(reg, val)     REGISTER_WRITE(dev, (reg), (val))
 898
 899 static inline void REGISTER_WRITE16(struct drm_device *dev,
 900                                         uint32_t reg, uint32_t val)
 901 {
 902         struct drm_psb_private *dev_priv = dev->dev_private;
 903         iowrite16((val), dev_priv->vdc_reg + (reg));
 904 }
 905
 906 #define REG_WRITE16(reg, val)     REGISTER_WRITE16(dev, (reg), (val))
 907
 908 static inline void REGISTER_WRITE8(struct drm_device *dev,
 909                                        uint32_t reg, uint32_t val)
 910 {
 911         struct drm_psb_private *dev_priv = dev->dev_private;
 912         iowrite8((val), dev_priv->vdc_reg + (reg));
 913 }
 914
 915 #define REG_WRITE8(reg, val)            REGISTER_WRITE8(dev, (reg), (val))
 916
 917 #define PSB_WVDC32(_val, _offs)         iowrite32(_val, dev_priv->vdc_reg + (_offs))
 918 #define PSB_RVDC32(_offs)               ioread32(dev_priv->vdc_reg + (_offs))
 919
 920 /* #define TRAP_SGX_PM_FAULT 1 */
 921 #ifdef TRAP_SGX_PM_FAULT
 922 #define PSB_RSGX32(_offs)                                               \
 923 ({                                                                      \
 924         if (inl(dev_priv->apm_base + PSB_APM_STS) & 0x3) {              \
 925                 printk(KERN_ERR                                         \
 926                         "access sgx when it's off!! (READ) %s, %d\n",   \
 927                __FILE__, __LINE__);                                     \
 928                 melay(1000);                                            \
 929         }                                                               \
 930         ioread32(dev_priv->sgx_reg + (_offs));                          \
 931 })
 932 #else
 933 #define PSB_RSGX32(_offs)               ioread32(dev_priv->sgx_reg + (_offs))
 934 #endif
 935 #define PSB_WSGX32(_val, _offs)         iowrite32(_val, dev_priv->sgx_reg + (_offs))
 936
 937 #define MSVDX_REG_DUMP 0
 938
 939 #define PSB_WMSVDX32(_val, _offs)       iowrite32(_val, dev_priv->msvdx_reg + (_offs))
 940 #define PSB_RMSVDX32(_offs)             ioread32(dev_priv->msvdx_reg + (_offs))
 941
 942 #endif