2 * SGI Visual Workstation support and quirks, unmaintained.
4 * Split out from setup.c by davej@suse.de
6 * Copyright (C) 1999 Bent Hagemark, Ingo Molnar
8 * SGI Visual Workstation interrupt controller
10 * The Cobalt system ASIC in the Visual Workstation contains a "Cobalt" APIC
11 * which serves as the main interrupt controller in the system. Non-legacy
12 * hardware in the system uses this controller directly. Legacy devices
13 * are connected to the PIIX4 which in turn has its 8259(s) connected to
14 * a of the Cobalt APIC entry.
16 * 09/02/2000 - Updated for 2.4 by jbarnes@sgi.com
18 * 25/11/2002 - Updated for 2.5 by Andrey Panin <pazke@orbita1.ru>
20 #include <linux/interrupt.h>
21 #include <linux/module.h>
22 #include <linux/init.h>
23 #include <linux/smp.h>
25 #include <asm/visws/cobalt.h>
26 #include <asm/visws/piix4.h>
27 #include <asm/arch_hooks.h>
28 #include <asm/io_apic.h>
29 #include <asm/fixmap.h>
30 #include <asm/reboot.h>
31 #include <asm/setup.h>
37 #include <asm/genapic.h>
39 #include <linux/kernel_stat.h>
41 #include <asm/i8259.h>
42 #include <asm/irq_vectors.h>
43 #include <asm/visws/lithium.h>
45 #include <linux/sched.h>
46 #include <linux/kernel.h>
47 #include <linux/pci.h>
48 #include <linux/pci_ids.h>
50 extern int no_broadcast
;
54 char visws_board_type
= -1;
55 char visws_board_rev
= -1;
57 int is_visws_box(void)
59 return visws_board_type
>= 0;
62 static int __init
visws_time_init(void)
64 printk(KERN_INFO
"Starting Cobalt Timer system clock\n");
66 /* Set the countdown value */
67 co_cpu_write(CO_CPU_TIMEVAL
, CO_TIME_HZ
/HZ
);
70 co_cpu_write(CO_CPU_CTRL
, co_cpu_read(CO_CPU_CTRL
) | CO_CTRL_TIMERUN
);
72 /* Enable (unmask) the timer interrupt */
73 co_cpu_write(CO_CPU_CTRL
, co_cpu_read(CO_CPU_CTRL
) & ~CO_CTRL_TIMEMASK
);
76 * Zero return means the generic timer setup code will set up
77 * the standard vector:
82 static int __init
visws_pre_intr_init(void)
84 init_VISWS_APIC_irqs();
87 * We dont want ISA irqs to be set up by the generic code:
92 /* Quirk for machine specific memory setup. */
94 #define MB (1024 * 1024)
96 unsigned long sgivwfb_mem_phys
;
97 unsigned long sgivwfb_mem_size
;
98 EXPORT_SYMBOL(sgivwfb_mem_phys
);
99 EXPORT_SYMBOL(sgivwfb_mem_size
);
101 long long mem_size __initdata
= 0;
103 static char * __init
visws_memory_setup(void)
105 long long gfx_mem_size
= 8 * MB
;
107 mem_size
= boot_params
.alt_mem_k
;
110 printk(KERN_WARNING
"Bootloader didn't set memory size, upgrade it !\n");
115 * this hardcodes the graphics memory to 8 MB
116 * it really should be sized dynamically (or at least
117 * set as a boot param)
119 if (!sgivwfb_mem_size
) {
120 printk(KERN_WARNING
"Defaulting to 8 MB framebuffer size\n");
121 sgivwfb_mem_size
= 8 * MB
;
127 sgivwfb_mem_size
&= ~((1 << 20) - 1);
128 sgivwfb_mem_phys
= mem_size
- gfx_mem_size
;
130 e820_add_region(0, LOWMEMSIZE(), E820_RAM
);
131 e820_add_region(HIGH_MEMORY
, mem_size
- sgivwfb_mem_size
- HIGH_MEMORY
, E820_RAM
);
132 e820_add_region(sgivwfb_mem_phys
, sgivwfb_mem_size
, E820_RESERVED
);
137 static void visws_machine_emergency_restart(void)
140 * Visual Workstations restart after this
141 * register is poked on the PIIX4
143 outb(PIIX4_RESET_VAL
, PIIX4_RESET_PORT
);
146 static void visws_machine_power_off(void)
148 unsigned short pm_status
;
149 /* extern unsigned int pci_bus0; */
151 while ((pm_status
= inw(PMSTS_PORT
)) & 0x100)
152 outw(pm_status
, PMSTS_PORT
);
154 outw(PM_SUSPEND_ENABLE
, PMCNTRL_PORT
);
158 #define PCI_CONF1_ADDRESS(bus, devfn, reg) \
159 (0x80000000 | (bus << 16) | (devfn << 8) | (reg & ~3))
161 /* outl(PCI_CONF1_ADDRESS(pci_bus0, SPECIAL_DEV, SPECIAL_REG), 0xCF8); */
162 outl(PIIX_SPECIAL_STOP
, 0xCFC);
165 static int __init
visws_get_smp_config(unsigned int early
)
168 * Prevent MP-table parsing by the generic code:
174 * The Visual Workstation is Intel MP compliant in the hardware
175 * sense, but it doesn't have a BIOS(-configuration table).
176 * No problem for Linux.
179 static void __init
MP_processor_info(struct mpc_cpu
*m
)
181 int ver
, logical_apicid
;
182 physid_mask_t apic_cpus
;
184 if (!(m
->cpuflag
& CPU_ENABLED
))
187 logical_apicid
= m
->apicid
;
188 printk(KERN_INFO
"%sCPU #%d %u:%u APIC version %d\n",
189 m
->cpuflag
& CPU_BOOTPROCESSOR
? "Bootup " : "",
190 m
->apicid
, (m
->cpufeature
& CPU_FAMILY_MASK
) >> 8,
191 (m
->cpufeature
& CPU_MODEL_MASK
) >> 4, m
->apicver
);
193 if (m
->cpuflag
& CPU_BOOTPROCESSOR
)
194 boot_cpu_physical_apicid
= m
->apicid
;
197 if ((ver
>= 0x14 && m
->apicid
>= 0xff) || m
->apicid
>= 0xf) {
198 printk(KERN_ERR
"Processor #%d INVALID. (Max ID: %d).\n",
199 m
->apicid
, MAX_APICS
);
203 apic_cpus
= apic
->apicid_to_cpu_present(m
->apicid
);
204 physids_or(phys_cpu_present_map
, phys_cpu_present_map
, apic_cpus
);
209 printk(KERN_ERR
"BIOS bug, APIC version is 0 for CPU#%d! "
210 "fixing up to 0x10. (tell your hw vendor)\n",
214 apic_version
[m
->apicid
] = ver
;
217 static int __init
visws_find_smp_config(unsigned int reserve
)
219 struct mpc_cpu
*mp
= phys_to_virt(CO_CPU_TAB_PHYS
);
220 unsigned short ncpus
= readw(phys_to_virt(CO_CPU_NUM_PHYS
));
222 if (ncpus
> CO_CPU_MAX
) {
223 printk(KERN_WARNING
"find_visws_smp: got cpu count of %d at %p\n",
229 if (ncpus
> setup_max_cpus
)
230 ncpus
= setup_max_cpus
;
232 #ifdef CONFIG_X86_LOCAL_APIC
233 smp_found_config
= 1;
236 MP_processor_info(mp
++);
238 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
243 static int visws_trap_init(void);
245 static struct x86_quirks visws_x86_quirks __initdata
= {
246 .arch_time_init
= visws_time_init
,
247 .arch_pre_intr_init
= visws_pre_intr_init
,
248 .arch_memory_setup
= visws_memory_setup
,
249 .arch_intr_init
= NULL
,
250 .arch_trap_init
= visws_trap_init
,
251 .mach_get_smp_config
= visws_get_smp_config
,
252 .mach_find_smp_config
= visws_find_smp_config
,
255 void __init
visws_early_detect(void)
259 visws_board_type
= (char)(inb_p(PIIX_GPI_BD_REG
) & PIIX_GPI_BD_REG
)
260 >> PIIX_GPI_BD_SHIFT
;
262 if (visws_board_type
< 0)
266 * Install special quirks for timer, interrupt and memory setup:
267 * Fall back to generic behavior for traps:
268 * Override generic MP-table parsing:
270 x86_quirks
= &visws_x86_quirks
;
273 * Install reboot quirks:
275 pm_power_off
= visws_machine_power_off
;
276 machine_ops
.emergency_restart
= visws_machine_emergency_restart
;
279 * Do not use broadcast IPIs:
283 #ifdef CONFIG_X86_IO_APIC
285 * Turn off IO-APIC detection and initialization:
287 skip_ioapic_setup
= 1;
292 * First, we have to initialize the 307 part to allow us access
293 * to the GPIO registers. Let's map them at 0x0fc0 which is right
294 * after the PIIX4 PM section.
296 outb_p(SIO_DEV_SEL
, SIO_INDEX
);
297 outb_p(SIO_GP_DEV
, SIO_DATA
); /* Talk to GPIO regs. */
299 outb_p(SIO_DEV_MSB
, SIO_INDEX
);
300 outb_p(SIO_GP_MSB
, SIO_DATA
); /* MSB of GPIO base address */
302 outb_p(SIO_DEV_LSB
, SIO_INDEX
);
303 outb_p(SIO_GP_LSB
, SIO_DATA
); /* LSB of GPIO base address */
305 outb_p(SIO_DEV_ENB
, SIO_INDEX
);
306 outb_p(1, SIO_DATA
); /* Enable GPIO registers. */
309 * Now, we have to map the power management section to write
310 * a bit which enables access to the GPIO registers.
311 * What lunatic came up with this shit?
313 outb_p(SIO_DEV_SEL
, SIO_INDEX
);
314 outb_p(SIO_PM_DEV
, SIO_DATA
); /* Talk to GPIO regs. */
316 outb_p(SIO_DEV_MSB
, SIO_INDEX
);
317 outb_p(SIO_PM_MSB
, SIO_DATA
); /* MSB of PM base address */
319 outb_p(SIO_DEV_LSB
, SIO_INDEX
);
320 outb_p(SIO_PM_LSB
, SIO_DATA
); /* LSB of PM base address */
322 outb_p(SIO_DEV_ENB
, SIO_INDEX
);
323 outb_p(1, SIO_DATA
); /* Enable PM registers. */
326 * Now, write the PM register which enables the GPIO registers.
328 outb_p(SIO_PM_FER2
, SIO_PM_INDEX
);
329 outb_p(SIO_PM_GP_EN
, SIO_PM_DATA
);
332 * Now, initialize the GPIO registers.
333 * We want them all to be inputs which is the
334 * power on default, so let's leave them alone.
335 * So, let's just read the board rev!
337 raw
= inb_p(SIO_GP_DATA1
);
338 raw
&= 0x7f; /* 7 bits of valid board revision ID. */
340 if (visws_board_type
== VISWS_320
) {
343 } else if (raw
< 0xc) {
348 } else if (visws_board_type
== VISWS_540
) {
351 visws_board_rev
= raw
;
354 printk(KERN_INFO
"Silicon Graphics Visual Workstation %s (rev %d) detected\n",
355 (visws_board_type
== VISWS_320
? "320" :
356 (visws_board_type
== VISWS_540
? "540" :
357 "unknown")), visws_board_rev
);
360 #define A01234 (LI_INTA_0 | LI_INTA_1 | LI_INTA_2 | LI_INTA_3 | LI_INTA_4)
361 #define BCD (LI_INTB | LI_INTC | LI_INTD)
362 #define ALLDEVS (A01234 | BCD)
364 static __init
void lithium_init(void)
366 set_fixmap(FIX_LI_PCIA
, LI_PCI_A_PHYS
);
367 set_fixmap(FIX_LI_PCIB
, LI_PCI_B_PHYS
);
369 if ((li_pcia_read16(PCI_VENDOR_ID
) != PCI_VENDOR_ID_SGI
) ||
370 (li_pcia_read16(PCI_DEVICE_ID
) != PCI_DEVICE_ID_SGI_LITHIUM
)) {
371 printk(KERN_EMERG
"Lithium hostbridge %c not found\n", 'A');
372 /* panic("This machine is not SGI Visual Workstation 320/540"); */
375 if ((li_pcib_read16(PCI_VENDOR_ID
) != PCI_VENDOR_ID_SGI
) ||
376 (li_pcib_read16(PCI_DEVICE_ID
) != PCI_DEVICE_ID_SGI_LITHIUM
)) {
377 printk(KERN_EMERG
"Lithium hostbridge %c not found\n", 'B');
378 /* panic("This machine is not SGI Visual Workstation 320/540"); */
381 li_pcia_write16(LI_PCI_INTEN
, ALLDEVS
);
382 li_pcib_write16(LI_PCI_INTEN
, ALLDEVS
);
385 static __init
void cobalt_init(void)
388 * On normal SMP PC this is used only with SMP, but we have to
389 * use it and set it up here to start the Cobalt clock
391 set_fixmap(FIX_APIC_BASE
, APIC_DEFAULT_PHYS_BASE
);
393 printk(KERN_INFO
"Local APIC Version %#x, ID %#x\n",
394 (unsigned int)apic_read(APIC_LVR
),
395 (unsigned int)apic_read(APIC_ID
));
397 set_fixmap(FIX_CO_CPU
, CO_CPU_PHYS
);
398 set_fixmap(FIX_CO_APIC
, CO_APIC_PHYS
);
399 printk(KERN_INFO
"Cobalt Revision %#lx, APIC ID %#lx\n",
400 co_cpu_read(CO_CPU_REV
), co_apic_read(CO_APIC_ID
));
402 /* Enable Cobalt APIC being careful to NOT change the ID! */
403 co_apic_write(CO_APIC_ID
, co_apic_read(CO_APIC_ID
) | CO_APIC_ENABLE
);
405 printk(KERN_INFO
"Cobalt APIC enabled: ID reg %#lx\n",
406 co_apic_read(CO_APIC_ID
));
409 static int __init
visws_trap_init(void)
418 * IRQ controller / APIC support:
421 static DEFINE_SPINLOCK(cobalt_lock
);
424 * Set the given Cobalt APIC Redirection Table entry to point
425 * to the given IDT vector/index.
427 static inline void co_apic_set(int entry
, int irq
)
429 co_apic_write(CO_APIC_LO(entry
), CO_APIC_LEVEL
| (irq
+ FIRST_EXTERNAL_VECTOR
));
430 co_apic_write(CO_APIC_HI(entry
), 0);
434 * Cobalt (IO)-APIC functions to handle PCI devices.
436 static inline int co_apic_ide0_hack(void)
438 extern char visws_board_type
;
439 extern char visws_board_rev
;
441 if (visws_board_type
== VISWS_320
&& visws_board_rev
== 5)
446 static int is_co_apic(unsigned int irq
)
452 case 0: return CO_APIC_CPU
;
453 case CO_IRQ_IDE0
: return co_apic_ide0_hack();
454 case CO_IRQ_IDE1
: return CO_APIC_IDE1
;
461 * This is the SGI Cobalt (IO-)APIC:
464 static void enable_cobalt_irq(unsigned int irq
)
466 co_apic_set(is_co_apic(irq
), irq
);
469 static void disable_cobalt_irq(unsigned int irq
)
471 int entry
= is_co_apic(irq
);
473 co_apic_write(CO_APIC_LO(entry
), CO_APIC_MASK
);
474 co_apic_read(CO_APIC_LO(entry
));
478 * "irq" really just serves to identify the device. Here is where we
479 * map this to the Cobalt APIC entry where it's physically wired.
480 * This is called via request_irq -> setup_irq -> irq_desc->startup()
482 static unsigned int startup_cobalt_irq(unsigned int irq
)
485 struct irq_desc
*desc
= irq_to_desc(irq
);
487 spin_lock_irqsave(&cobalt_lock
, flags
);
488 if ((desc
->status
& (IRQ_DISABLED
| IRQ_INPROGRESS
| IRQ_WAITING
)))
489 desc
->status
&= ~(IRQ_DISABLED
| IRQ_INPROGRESS
| IRQ_WAITING
);
490 enable_cobalt_irq(irq
);
491 spin_unlock_irqrestore(&cobalt_lock
, flags
);
495 static void ack_cobalt_irq(unsigned int irq
)
499 spin_lock_irqsave(&cobalt_lock
, flags
);
500 disable_cobalt_irq(irq
);
501 apic_write(APIC_EOI
, APIC_EIO_ACK
);
502 spin_unlock_irqrestore(&cobalt_lock
, flags
);
505 static void end_cobalt_irq(unsigned int irq
)
508 struct irq_desc
*desc
= irq_to_desc(irq
);
510 spin_lock_irqsave(&cobalt_lock
, flags
);
511 if (!(desc
->status
& (IRQ_DISABLED
| IRQ_INPROGRESS
)))
512 enable_cobalt_irq(irq
);
513 spin_unlock_irqrestore(&cobalt_lock
, flags
);
516 static struct irq_chip cobalt_irq_type
= {
517 .typename
= "Cobalt-APIC",
518 .startup
= startup_cobalt_irq
,
519 .shutdown
= disable_cobalt_irq
,
520 .enable
= enable_cobalt_irq
,
521 .disable
= disable_cobalt_irq
,
522 .ack
= ack_cobalt_irq
,
523 .end
= end_cobalt_irq
,
528 * This is the PIIX4-based 8259 that is wired up indirectly to Cobalt
529 * -- not the manner expected by the code in i8259.c.
531 * there is a 'master' physical interrupt source that gets sent to
532 * the CPU. But in the chipset there are various 'virtual' interrupts
533 * waiting to be handled. We represent this to Linux through a 'master'
534 * interrupt controller type, and through a special virtual interrupt-
535 * controller. Device drivers only see the virtual interrupt sources.
537 static unsigned int startup_piix4_master_irq(unsigned int irq
)
541 return startup_cobalt_irq(irq
);
544 static void end_piix4_master_irq(unsigned int irq
)
548 spin_lock_irqsave(&cobalt_lock
, flags
);
549 enable_cobalt_irq(irq
);
550 spin_unlock_irqrestore(&cobalt_lock
, flags
);
553 static struct irq_chip piix4_master_irq_type
= {
554 .typename
= "PIIX4-master",
555 .startup
= startup_piix4_master_irq
,
556 .ack
= ack_cobalt_irq
,
557 .end
= end_piix4_master_irq
,
561 static struct irq_chip piix4_virtual_irq_type
= {
562 .typename
= "PIIX4-virtual",
563 .shutdown
= disable_8259A_irq
,
564 .enable
= enable_8259A_irq
,
565 .disable
= disable_8259A_irq
,
570 * PIIX4-8259 master/virtual functions to handle interrupt requests
571 * from legacy devices: floppy, parallel, serial, rtc.
573 * None of these get Cobalt APIC entries, neither do they have IDT
574 * entries. These interrupts are purely virtual and distributed from
575 * the 'master' interrupt source: CO_IRQ_8259.
577 * When the 8259 interrupts its handler figures out which of these
578 * devices is interrupting and dispatches to its handler.
580 * CAREFUL: devices see the 'virtual' interrupt only. Thus disable/
581 * enable_irq gets the right irq. This 'master' irq is never directly
582 * manipulated by any driver.
584 static irqreturn_t
piix4_master_intr(int irq
, void *dev_id
)
590 spin_lock_irqsave(&i8259A_lock
, flags
);
592 /* Find out what's interrupting in the PIIX4 master 8259 */
593 outb(0x0c, 0x20); /* OCW3 Poll command */
597 * Bit 7 == 0 means invalid/spurious
599 if (unlikely(!(realirq
& 0x80)))
604 if (unlikely(realirq
== 2)) {
608 if (unlikely(!(realirq
& 0x80)))
611 realirq
= (realirq
& 7) + 8;
614 /* mask and ack interrupt */
615 cached_irq_mask
|= 1 << realirq
;
616 if (unlikely(realirq
> 7)) {
618 outb(cached_slave_mask
, 0xa1);
619 outb(0x60 + (realirq
& 7), 0xa0);
620 outb(0x60 + 2, 0x20);
623 outb(cached_master_mask
, 0x21);
624 outb(0x60 + realirq
, 0x20);
627 spin_unlock_irqrestore(&i8259A_lock
, flags
);
629 desc
= irq_to_desc(realirq
);
632 * handle this 'virtual interrupt' as a Cobalt one now.
634 kstat_incr_irqs_this_cpu(realirq
, desc
);
636 if (likely(desc
->action
!= NULL
))
637 handle_IRQ_event(realirq
, desc
->action
);
639 if (!(desc
->status
& IRQ_DISABLED
))
640 enable_8259A_irq(realirq
);
645 spin_unlock_irqrestore(&i8259A_lock
, flags
);
649 static struct irqaction master_action
= {
650 .handler
= piix4_master_intr
,
651 .name
= "PIIX4-8259",
654 static struct irqaction cascade_action
= {
655 .handler
= no_action
,
660 void init_VISWS_APIC_irqs(void)
664 for (i
= 0; i
< CO_IRQ_APIC0
+ CO_APIC_LAST
+ 1; i
++) {
665 struct irq_desc
*desc
= irq_to_desc(i
);
667 desc
->status
= IRQ_DISABLED
;
672 desc
->chip
= &cobalt_irq_type
;
674 else if (i
== CO_IRQ_IDE0
) {
675 desc
->chip
= &cobalt_irq_type
;
677 else if (i
== CO_IRQ_IDE1
) {
678 desc
->chip
= &cobalt_irq_type
;
680 else if (i
== CO_IRQ_8259
) {
681 desc
->chip
= &piix4_master_irq_type
;
683 else if (i
< CO_IRQ_APIC0
) {
684 desc
->chip
= &piix4_virtual_irq_type
;
686 else if (IS_CO_APIC(i
)) {
687 desc
->chip
= &cobalt_irq_type
;
691 setup_irq(CO_IRQ_8259
, &master_action
);
692 setup_irq(2, &cascade_action
);