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ath9k: Remove duplicate variables
[linux-2.6/libata-dev.git] / drivers / net / wireless / ath / ath9k / hw.c
blob9f1b34d9861abc2fe4ff124e38051e6a3e1482d0
1 /*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/io.h>
18 #include <asm/unaligned.h>
19
20 #include "ath9k.h"
21 #include "initvals.h"
22
23 static int btcoex_enable;
24 module_param(btcoex_enable, bool, 0);
25 MODULE_PARM_DESC(btcoex_enable, "Enable Bluetooth coexistence support");
26
27 #define ATH9K_CLOCK_RATE_CCK 22
28 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
29 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
30
31 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
32 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
33 enum ath9k_ht_macmode macmode);
34 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
35 struct ar5416_eeprom_def *pEepData,
36 u32 reg, u32 value);
37 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
38 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
39
40 /********************/
41 /* Helper Functions */
42 /********************/
43
44 static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks)
45 {
46 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
47
48 if (!ah->curchan) /* should really check for CCK instead */
49 return clks / ATH9K_CLOCK_RATE_CCK;
50 if (conf->channel->band == IEEE80211_BAND_2GHZ)
51 return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM;
52
53 return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM;
54 }
55
56 static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks)
57 {
58 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
59
60 if (conf_is_ht40(conf))
61 return ath9k_hw_mac_usec(ah, clks) / 2;
62 else
63 return ath9k_hw_mac_usec(ah, clks);
64 }
65
66 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
67 {
68 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
69
70 if (!ah->curchan) /* should really check for CCK instead */
71 return usecs *ATH9K_CLOCK_RATE_CCK;
72 if (conf->channel->band == IEEE80211_BAND_2GHZ)
73 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
74 return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
75 }
76
77 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
78 {
79 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
80
81 if (conf_is_ht40(conf))
82 return ath9k_hw_mac_clks(ah, usecs) * 2;
83 else
84 return ath9k_hw_mac_clks(ah, usecs);
85 }
86
87 /*
88 * Read and write, they both share the same lock. We do this to serialize
89 * reads and writes on Atheros 802.11n PCI devices only. This is required
90 * as the FIFO on these devices can only accept sanely 2 requests. After
91 * that the device goes bananas. Serializing the reads/writes prevents this
92 * from happening.
93 */
94
95 void ath9k_iowrite32(struct ath_hw *ah, u32 reg_offset, u32 val)
96 {
97 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
98 unsigned long flags;
99 spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
100 iowrite32(val, ah->ah_sc->mem + reg_offset);
101 spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
102 } else
103 iowrite32(val, ah->ah_sc->mem + reg_offset);
104 }
105
106 unsigned int ath9k_ioread32(struct ath_hw *ah, u32 reg_offset)
107 {
108 u32 val;
109 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
110 unsigned long flags;
111 spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
112 val = ioread32(ah->ah_sc->mem + reg_offset);
113 spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
114 } else
115 val = ioread32(ah->ah_sc->mem + reg_offset);
116 return val;
117 }
118
119 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
120 {
121 int i;
122
123 BUG_ON(timeout < AH_TIME_QUANTUM);
124
125 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
126 if ((REG_READ(ah, reg) & mask) == val)
127 return true;
128
129 udelay(AH_TIME_QUANTUM);
130 }
131
132 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
133 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
134 timeout, reg, REG_READ(ah, reg), mask, val);
135
136 return false;
137 }
138
139 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
140 {
141 u32 retval;
142 int i;
143
144 for (i = 0, retval = 0; i < n; i++) {
145 retval = (retval << 1) | (val & 1);
146 val >>= 1;
147 }
148 return retval;
149 }
150
151 bool ath9k_get_channel_edges(struct ath_hw *ah,
152 u16 flags, u16 *low,
153 u16 *high)
154 {
155 struct ath9k_hw_capabilities *pCap = &ah->caps;
156
157 if (flags & CHANNEL_5GHZ) {
158 *low = pCap->low_5ghz_chan;
159 *high = pCap->high_5ghz_chan;
160 return true;
161 }
162 if ((flags & CHANNEL_2GHZ)) {
163 *low = pCap->low_2ghz_chan;
164 *high = pCap->high_2ghz_chan;
165 return true;
166 }
167 return false;
168 }
169
170 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
171 const struct ath_rate_table *rates,
172 u32 frameLen, u16 rateix,
173 bool shortPreamble)
174 {
175 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
176 u32 kbps;
177
178 kbps = rates->info[rateix].ratekbps;
179
180 if (kbps == 0)
181 return 0;
182
183 switch (rates->info[rateix].phy) {
184 case WLAN_RC_PHY_CCK:
185 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
186 if (shortPreamble && rates->info[rateix].short_preamble)
187 phyTime >>= 1;
188 numBits = frameLen << 3;
189 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
190 break;
191 case WLAN_RC_PHY_OFDM:
192 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
193 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
194 numBits = OFDM_PLCP_BITS + (frameLen << 3);
195 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
196 txTime = OFDM_SIFS_TIME_QUARTER
197 + OFDM_PREAMBLE_TIME_QUARTER
198 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
199 } else if (ah->curchan &&
200 IS_CHAN_HALF_RATE(ah->curchan)) {
201 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
202 numBits = OFDM_PLCP_BITS + (frameLen << 3);
203 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
204 txTime = OFDM_SIFS_TIME_HALF +
205 OFDM_PREAMBLE_TIME_HALF
206 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
207 } else {
208 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
209 numBits = OFDM_PLCP_BITS + (frameLen << 3);
210 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
211 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
212 + (numSymbols * OFDM_SYMBOL_TIME);
213 }
214 break;
215 default:
216 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
217 "Unknown phy %u (rate ix %u)\n",
218 rates->info[rateix].phy, rateix);
219 txTime = 0;
220 break;
221 }
222
223 return txTime;
224 }
225
226 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
227 struct ath9k_channel *chan,
228 struct chan_centers *centers)
229 {
230 int8_t extoff;
231
232 if (!IS_CHAN_HT40(chan)) {
233 centers->ctl_center = centers->ext_center =
234 centers->synth_center = chan->channel;
235 return;
236 }
237
238 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
239 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
240 centers->synth_center =
241 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
242 extoff = 1;
243 } else {
244 centers->synth_center =
245 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
246 extoff = -1;
247 }
248
249 centers->ctl_center =
250 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
251 centers->ext_center =
252 centers->synth_center + (extoff *
253 ((ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
254 HT40_CHANNEL_CENTER_SHIFT : 15));
255 }
256
257 /******************/
258 /* Chip Revisions */
259 /******************/
260
261 static void ath9k_hw_read_revisions(struct ath_hw *ah)
262 {
263 u32 val;
264
265 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
266
267 if (val == 0xFF) {
268 val = REG_READ(ah, AR_SREV);
269 ah->hw_version.macVersion =
270 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
271 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
272 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
273 } else {
274 if (!AR_SREV_9100(ah))
275 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
276
277 ah->hw_version.macRev = val & AR_SREV_REVISION;
278
279 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
280 ah->is_pciexpress = true;
281 }
282 }
283
284 static int ath9k_hw_get_radiorev(struct ath_hw *ah)
285 {
286 u32 val;
287 int i;
288
289 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
290
291 for (i = 0; i < 8; i++)
292 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
293 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
294 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
295
296 return ath9k_hw_reverse_bits(val, 8);
297 }
298
299 /************************************/
300 /* HW Attach, Detach, Init Routines */
301 /************************************/
302
303 static void ath9k_hw_disablepcie(struct ath_hw *ah)
304 {
305 if (AR_SREV_9100(ah))
306 return;
307
308 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
309 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
310 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
311 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
312 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
313 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
314 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
315 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
316 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
317
318 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
319 }
320
321 static bool ath9k_hw_chip_test(struct ath_hw *ah)
322 {
323 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
324 u32 regHold[2];
325 u32 patternData[4] = { 0x55555555,
326 0xaaaaaaaa,
327 0x66666666,
328 0x99999999 };
329 int i, j;
330
331 for (i = 0; i < 2; i++) {
332 u32 addr = regAddr[i];
333 u32 wrData, rdData;
334
335 regHold[i] = REG_READ(ah, addr);
336 for (j = 0; j < 0x100; j++) {
337 wrData = (j << 16) | j;
338 REG_WRITE(ah, addr, wrData);
339 rdData = REG_READ(ah, addr);
340 if (rdData != wrData) {
341 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
342 "address test failed "
343 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
344 addr, wrData, rdData);
345 return false;
346 }
347 }
348 for (j = 0; j < 4; j++) {
349 wrData = patternData[j];
350 REG_WRITE(ah, addr, wrData);
351 rdData = REG_READ(ah, addr);
352 if (wrData != rdData) {
353 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
354 "address test failed "
355 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
356 addr, wrData, rdData);
357 return false;
358 }
359 }
360 REG_WRITE(ah, regAddr[i], regHold[i]);
361 }
362 udelay(100);
363
364 return true;
365 }
366
367 static const char *ath9k_hw_devname(u16 devid)
368 {
369 switch (devid) {
370 case AR5416_DEVID_PCI:
371 return "Atheros 5416";
372 case AR5416_DEVID_PCIE:
373 return "Atheros 5418";
374 case AR9160_DEVID_PCI:
375 return "Atheros 9160";
376 case AR5416_AR9100_DEVID:
377 return "Atheros 9100";
378 case AR9280_DEVID_PCI:
379 case AR9280_DEVID_PCIE:
380 return "Atheros 9280";
381 case AR9285_DEVID_PCIE:
382 return "Atheros 9285";
383 case AR5416_DEVID_AR9287_PCI:
384 case AR5416_DEVID_AR9287_PCIE:
385 return "Atheros 9287";
386 }
387
388 return NULL;
389 }
390
391 static void ath9k_hw_init_config(struct ath_hw *ah)
392 {
393 int i;
394
395 ah->config.dma_beacon_response_time = 2;
396 ah->config.sw_beacon_response_time = 10;
397 ah->config.additional_swba_backoff = 0;
398 ah->config.ack_6mb = 0x0;
399 ah->config.cwm_ignore_extcca = 0;
400 ah->config.pcie_powersave_enable = 0;
401 ah->config.pcie_clock_req = 0;
402 ah->config.pcie_waen = 0;
403 ah->config.analog_shiftreg = 1;
404 ah->config.ht_enable = 1;
405 ah->config.ofdm_trig_low = 200;
406 ah->config.ofdm_trig_high = 500;
407 ah->config.cck_trig_high = 200;
408 ah->config.cck_trig_low = 100;
409 ah->config.enable_ani = 1;
410 ah->config.diversity_control = ATH9K_ANT_VARIABLE;
411 ah->config.antenna_switch_swap = 0;
412
413 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
414 ah->config.spurchans[i][0] = AR_NO_SPUR;
415 ah->config.spurchans[i][1] = AR_NO_SPUR;
416 }
417
418 ah->config.intr_mitigation = true;
419
420 /*
421 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
422 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
423 * This means we use it for all AR5416 devices, and the few
424 * minor PCI AR9280 devices out there.
425 *
426 * Serialization is required because these devices do not handle
427 * well the case of two concurrent reads/writes due to the latency
428 * involved. During one read/write another read/write can be issued
429 * on another CPU while the previous read/write may still be working
430 * on our hardware, if we hit this case the hardware poops in a loop.
431 * We prevent this by serializing reads and writes.
432 *
433 * This issue is not present on PCI-Express devices or pre-AR5416
434 * devices (legacy, 802.11abg).
435 */
436 if (num_possible_cpus() > 1)
437 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
438 }
439
440 static void ath9k_hw_init_defaults(struct ath_hw *ah)
441 {
442 ah->hw_version.magic = AR5416_MAGIC;
443 ah->regulatory.country_code = CTRY_DEFAULT;
444 ah->hw_version.subvendorid = 0;
445
446 ah->ah_flags = 0;
447 if (ah->hw_version.devid == AR5416_AR9100_DEVID)
448 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
449 if (!AR_SREV_9100(ah))
450 ah->ah_flags = AH_USE_EEPROM;
451
452 ah->regulatory.power_limit = MAX_RATE_POWER;
453 ah->regulatory.tp_scale = ATH9K_TP_SCALE_MAX;
454 ah->atim_window = 0;
455 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
456 ah->beacon_interval = 100;
457 ah->enable_32kHz_clock = DONT_USE_32KHZ;
458 ah->slottime = (u32) -1;
459 ah->acktimeout = (u32) -1;
460 ah->ctstimeout = (u32) -1;
461 ah->globaltxtimeout = (u32) -1;
462
463 ah->gbeacon_rate = 0;
464
465 ah->power_mode = ATH9K_PM_UNDEFINED;
466 }
467
468 static int ath9k_hw_rfattach(struct ath_hw *ah)
469 {
470 bool rfStatus = false;
471 int ecode = 0;
472
473 rfStatus = ath9k_hw_init_rf(ah, &ecode);
474 if (!rfStatus) {
475 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
476 "RF setup failed, status: %u\n", ecode);
477 return ecode;
478 }
479
480 return 0;
481 }
482
483 static int ath9k_hw_rf_claim(struct ath_hw *ah)
484 {
485 u32 val;
486
487 REG_WRITE(ah, AR_PHY(0), 0x00000007);
488
489 val = ath9k_hw_get_radiorev(ah);
490 switch (val & AR_RADIO_SREV_MAJOR) {
491 case 0:
492 val = AR_RAD5133_SREV_MAJOR;
493 break;
494 case AR_RAD5133_SREV_MAJOR:
495 case AR_RAD5122_SREV_MAJOR:
496 case AR_RAD2133_SREV_MAJOR:
497 case AR_RAD2122_SREV_MAJOR:
498 break;
499 default:
500 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
501 "Radio Chip Rev 0x%02X not supported\n",
502 val & AR_RADIO_SREV_MAJOR);
503 return -EOPNOTSUPP;
504 }
505
506 ah->hw_version.analog5GhzRev = val;
507
508 return 0;
509 }
510
511 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
512 {
513 u32 sum;
514 int i;
515 u16 eeval;
516
517 sum = 0;
518 for (i = 0; i < 3; i++) {
519 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
520 sum += eeval;
521 ah->macaddr[2 * i] = eeval >> 8;
522 ah->macaddr[2 * i + 1] = eeval & 0xff;
523 }
524 if (sum == 0 || sum == 0xffff * 3)
525 return -EADDRNOTAVAIL;
526
527 return 0;
528 }
529
530 static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
531 {
532 u32 rxgain_type;
533
534 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
535 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
536
537 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
538 INIT_INI_ARRAY(&ah->iniModesRxGain,
539 ar9280Modes_backoff_13db_rxgain_9280_2,
540 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
541 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
542 INIT_INI_ARRAY(&ah->iniModesRxGain,
543 ar9280Modes_backoff_23db_rxgain_9280_2,
544 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
545 else
546 INIT_INI_ARRAY(&ah->iniModesRxGain,
547 ar9280Modes_original_rxgain_9280_2,
548 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
549 } else {
550 INIT_INI_ARRAY(&ah->iniModesRxGain,
551 ar9280Modes_original_rxgain_9280_2,
552 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
553 }
554 }
555
556 static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
557 {
558 u32 txgain_type;
559
560 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
561 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
562
563 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
564 INIT_INI_ARRAY(&ah->iniModesTxGain,
565 ar9280Modes_high_power_tx_gain_9280_2,
566 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
567 else
568 INIT_INI_ARRAY(&ah->iniModesTxGain,
569 ar9280Modes_original_tx_gain_9280_2,
570 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
571 } else {
572 INIT_INI_ARRAY(&ah->iniModesTxGain,
573 ar9280Modes_original_tx_gain_9280_2,
574 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
575 }
576 }
577
578 static int ath9k_hw_post_init(struct ath_hw *ah)
579 {
580 int ecode;
581
582 if (!ath9k_hw_chip_test(ah))
583 return -ENODEV;
584
585 ecode = ath9k_hw_rf_claim(ah);
586 if (ecode != 0)
587 return ecode;
588
589 ecode = ath9k_hw_eeprom_init(ah);
590 if (ecode != 0)
591 return ecode;
592
593 DPRINTF(ah->ah_sc, ATH_DBG_CONFIG, "Eeprom VER: %d, REV: %d\n",
594 ah->eep_ops->get_eeprom_ver(ah), ah->eep_ops->get_eeprom_rev(ah));
595
596 ecode = ath9k_hw_rfattach(ah);
597 if (ecode != 0)
598 return ecode;
599
600 if (!AR_SREV_9100(ah)) {
601 ath9k_hw_ani_setup(ah);
602 ath9k_hw_ani_init(ah);
603 }
604
605 return 0;
606 }
607
608 static bool ath9k_hw_devid_supported(u16 devid)
609 {
610 switch (devid) {
611 case AR5416_DEVID_PCI:
612 case AR5416_DEVID_PCIE:
613 case AR5416_AR9100_DEVID:
614 case AR9160_DEVID_PCI:
615 case AR9280_DEVID_PCI:
616 case AR9280_DEVID_PCIE:
617 case AR9285_DEVID_PCIE:
618 case AR5416_DEVID_AR9287_PCI:
619 case AR5416_DEVID_AR9287_PCIE:
620 return true;
621 default:
622 break;
623 }
624 return false;
625 }
626
627 static bool ath9k_hw_macversion_supported(u32 macversion)
628 {
629 switch (macversion) {
630 case AR_SREV_VERSION_5416_PCI:
631 case AR_SREV_VERSION_5416_PCIE:
632 case AR_SREV_VERSION_9160:
633 case AR_SREV_VERSION_9100:
634 case AR_SREV_VERSION_9280:
635 case AR_SREV_VERSION_9285:
636 case AR_SREV_VERSION_9287:
637 return true;
638 /* Not yet */
639 case AR_SREV_VERSION_9271:
640 default:
641 break;
642 }
643 return false;
644 }
645
646 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
647 {
648 if (AR_SREV_9160_10_OR_LATER(ah)) {
649 if (AR_SREV_9280_10_OR_LATER(ah)) {
650 ah->iq_caldata.calData = &iq_cal_single_sample;
651 ah->adcgain_caldata.calData =
652 &adc_gain_cal_single_sample;
653 ah->adcdc_caldata.calData =
654 &adc_dc_cal_single_sample;
655 ah->adcdc_calinitdata.calData =
656 &adc_init_dc_cal;
657 } else {
658 ah->iq_caldata.calData = &iq_cal_multi_sample;
659 ah->adcgain_caldata.calData =
660 &adc_gain_cal_multi_sample;
661 ah->adcdc_caldata.calData =
662 &adc_dc_cal_multi_sample;
663 ah->adcdc_calinitdata.calData =
664 &adc_init_dc_cal;
665 }
666 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
667 }
668 }
669
670 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
671 {
672 if (AR_SREV_9271(ah)) {
673 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271_1_0,
674 ARRAY_SIZE(ar9271Modes_9271_1_0), 6);
675 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271_1_0,
676 ARRAY_SIZE(ar9271Common_9271_1_0), 2);
677 return;
678 }
679
680 if (AR_SREV_9287_11_OR_LATER(ah)) {
681 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
682 ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
683 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
684 ARRAY_SIZE(ar9287Common_9287_1_1), 2);
685 if (ah->config.pcie_clock_req)
686 INIT_INI_ARRAY(&ah->iniPcieSerdes,
687 ar9287PciePhy_clkreq_off_L1_9287_1_1,
688 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
689 else
690 INIT_INI_ARRAY(&ah->iniPcieSerdes,
691 ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
692 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
693 2);
694 } else if (AR_SREV_9287_10_OR_LATER(ah)) {
695 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
696 ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
697 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
698 ARRAY_SIZE(ar9287Common_9287_1_0), 2);
699
700 if (ah->config.pcie_clock_req)
701 INIT_INI_ARRAY(&ah->iniPcieSerdes,
702 ar9287PciePhy_clkreq_off_L1_9287_1_0,
703 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
704 else
705 INIT_INI_ARRAY(&ah->iniPcieSerdes,
706 ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
707 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
708 2);
709 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
710
711
712 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
713 ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
714 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
715 ARRAY_SIZE(ar9285Common_9285_1_2), 2);
716
717 if (ah->config.pcie_clock_req) {
718 INIT_INI_ARRAY(&ah->iniPcieSerdes,
719 ar9285PciePhy_clkreq_off_L1_9285_1_2,
720 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
721 } else {
722 INIT_INI_ARRAY(&ah->iniPcieSerdes,
723 ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
724 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
725 2);
726 }
727 } else if (AR_SREV_9285_10_OR_LATER(ah)) {
728 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
729 ARRAY_SIZE(ar9285Modes_9285), 6);
730 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
731 ARRAY_SIZE(ar9285Common_9285), 2);
732
733 if (ah->config.pcie_clock_req) {
734 INIT_INI_ARRAY(&ah->iniPcieSerdes,
735 ar9285PciePhy_clkreq_off_L1_9285,
736 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
737 } else {
738 INIT_INI_ARRAY(&ah->iniPcieSerdes,
739 ar9285PciePhy_clkreq_always_on_L1_9285,
740 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
741 }
742 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
743 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
744 ARRAY_SIZE(ar9280Modes_9280_2), 6);
745 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
746 ARRAY_SIZE(ar9280Common_9280_2), 2);
747
748 if (ah->config.pcie_clock_req) {
749 INIT_INI_ARRAY(&ah->iniPcieSerdes,
750 ar9280PciePhy_clkreq_off_L1_9280,
751 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
752 } else {
753 INIT_INI_ARRAY(&ah->iniPcieSerdes,
754 ar9280PciePhy_clkreq_always_on_L1_9280,
755 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
756 }
757 INIT_INI_ARRAY(&ah->iniModesAdditional,
758 ar9280Modes_fast_clock_9280_2,
759 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
760 } else if (AR_SREV_9280_10_OR_LATER(ah)) {
761 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
762 ARRAY_SIZE(ar9280Modes_9280), 6);
763 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
764 ARRAY_SIZE(ar9280Common_9280), 2);
765 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
766 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
767 ARRAY_SIZE(ar5416Modes_9160), 6);
768 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
769 ARRAY_SIZE(ar5416Common_9160), 2);
770 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
771 ARRAY_SIZE(ar5416Bank0_9160), 2);
772 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
773 ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
774 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
775 ARRAY_SIZE(ar5416Bank1_9160), 2);
776 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
777 ARRAY_SIZE(ar5416Bank2_9160), 2);
778 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
779 ARRAY_SIZE(ar5416Bank3_9160), 3);
780 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
781 ARRAY_SIZE(ar5416Bank6_9160), 3);
782 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
783 ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
784 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
785 ARRAY_SIZE(ar5416Bank7_9160), 2);
786 if (AR_SREV_9160_11(ah)) {
787 INIT_INI_ARRAY(&ah->iniAddac,
788 ar5416Addac_91601_1,
789 ARRAY_SIZE(ar5416Addac_91601_1), 2);
790 } else {
791 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
792 ARRAY_SIZE(ar5416Addac_9160), 2);
793 }
794 } else if (AR_SREV_9100_OR_LATER(ah)) {
795 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
796 ARRAY_SIZE(ar5416Modes_9100), 6);
797 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
798 ARRAY_SIZE(ar5416Common_9100), 2);
799 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
800 ARRAY_SIZE(ar5416Bank0_9100), 2);
801 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
802 ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
803 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
804 ARRAY_SIZE(ar5416Bank1_9100), 2);
805 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
806 ARRAY_SIZE(ar5416Bank2_9100), 2);
807 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
808 ARRAY_SIZE(ar5416Bank3_9100), 3);
809 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
810 ARRAY_SIZE(ar5416Bank6_9100), 3);
811 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
812 ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
813 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
814 ARRAY_SIZE(ar5416Bank7_9100), 2);
815 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
816 ARRAY_SIZE(ar5416Addac_9100), 2);
817 } else {
818 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
819 ARRAY_SIZE(ar5416Modes), 6);
820 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
821 ARRAY_SIZE(ar5416Common), 2);
822 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
823 ARRAY_SIZE(ar5416Bank0), 2);
824 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
825 ARRAY_SIZE(ar5416BB_RfGain), 3);
826 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
827 ARRAY_SIZE(ar5416Bank1), 2);
828 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
829 ARRAY_SIZE(ar5416Bank2), 2);
830 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
831 ARRAY_SIZE(ar5416Bank3), 3);
832 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
833 ARRAY_SIZE(ar5416Bank6), 3);
834 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
835 ARRAY_SIZE(ar5416Bank6TPC), 3);
836 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
837 ARRAY_SIZE(ar5416Bank7), 2);
838 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
839 ARRAY_SIZE(ar5416Addac), 2);
840 }
841 }
842
843 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
844 {
845 if (AR_SREV_9287_11(ah))
846 INIT_INI_ARRAY(&ah->iniModesRxGain,
847 ar9287Modes_rx_gain_9287_1_1,
848 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
849 else if (AR_SREV_9287_10(ah))
850 INIT_INI_ARRAY(&ah->iniModesRxGain,
851 ar9287Modes_rx_gain_9287_1_0,
852 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
853 else if (AR_SREV_9280_20(ah))
854 ath9k_hw_init_rxgain_ini(ah);
855
856 if (AR_SREV_9287_11(ah)) {
857 INIT_INI_ARRAY(&ah->iniModesTxGain,
858 ar9287Modes_tx_gain_9287_1_1,
859 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
860 } else if (AR_SREV_9287_10(ah)) {
861 INIT_INI_ARRAY(&ah->iniModesTxGain,
862 ar9287Modes_tx_gain_9287_1_0,
863 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
864 } else if (AR_SREV_9280_20(ah)) {
865 ath9k_hw_init_txgain_ini(ah);
866 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
867 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
868
869 /* txgain table */
870 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
871 INIT_INI_ARRAY(&ah->iniModesTxGain,
872 ar9285Modes_high_power_tx_gain_9285_1_2,
873 ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2), 6);
874 } else {
875 INIT_INI_ARRAY(&ah->iniModesTxGain,
876 ar9285Modes_original_tx_gain_9285_1_2,
877 ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2), 6);
878 }
879
880 }
881 }
882
883 static void ath9k_hw_init_11a_eeprom_fix(struct ath_hw *ah)
884 {
885 u32 i, j;
886
887 if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
888 test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes)) {
889
890 /* EEPROM Fixup */
891 for (i = 0; i < ah->iniModes.ia_rows; i++) {
892 u32 reg = INI_RA(&ah->iniModes, i, 0);
893
894 for (j = 1; j < ah->iniModes.ia_columns; j++) {
895 u32 val = INI_RA(&ah->iniModes, i, j);
896
897 INI_RA(&ah->iniModes, i, j) =
898 ath9k_hw_ini_fixup(ah,
899 &ah->eeprom.def,
900 reg, val);
901 }
902 }
903 }
904 }
905
906 int ath9k_hw_init(struct ath_hw *ah)
907 {
908 int r = 0;
909
910 if (!ath9k_hw_devid_supported(ah->hw_version.devid))
911 return -EOPNOTSUPP;
912
913 ath9k_hw_init_defaults(ah);
914 ath9k_hw_init_config(ah);
915
916 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
917 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Couldn't reset chip\n");
918 return -EIO;
919 }
920
921 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
922 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
923 return -EIO;
924 }
925
926 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
927 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
928 (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
929 ah->config.serialize_regmode =
930 SER_REG_MODE_ON;
931 } else {
932 ah->config.serialize_regmode =
933 SER_REG_MODE_OFF;
934 }
935 }
936
937 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "serialize_regmode is %d\n",
938 ah->config.serialize_regmode);
939
940 if (!ath9k_hw_macversion_supported(ah->hw_version.macVersion)) {
941 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
942 "Mac Chip Rev 0x%02x.%x is not supported by "
943 "this driver\n", ah->hw_version.macVersion,
944 ah->hw_version.macRev);
945 return -EOPNOTSUPP;
946 }
947
948 if (AR_SREV_9100(ah)) {
949 ah->iq_caldata.calData = &iq_cal_multi_sample;
950 ah->supp_cals = IQ_MISMATCH_CAL;
951 ah->is_pciexpress = false;
952 }
953
954 if (AR_SREV_9271(ah))
955 ah->is_pciexpress = false;
956
957 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
958
959 ath9k_hw_init_cal_settings(ah);
960
961 ah->ani_function = ATH9K_ANI_ALL;
962 if (AR_SREV_9280_10_OR_LATER(ah))
963 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
964
965 ath9k_hw_init_mode_regs(ah);
966
967 if (ah->is_pciexpress)
968 ath9k_hw_configpcipowersave(ah, 0);
969 else
970 ath9k_hw_disablepcie(ah);
971
972 r = ath9k_hw_post_init(ah);
973 if (r)
974 return r;
975
976 ath9k_hw_init_mode_gain_regs(ah);
977 ath9k_hw_fill_cap_info(ah);
978 ath9k_hw_init_11a_eeprom_fix(ah);
979
980 r = ath9k_hw_init_macaddr(ah);
981 if (r) {
982 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
983 "Failed to initialize MAC address\n");
984 return r;
985 }
986
987 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
988 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
989 else
990 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
991
992 ath9k_init_nfcal_hist_buffer(ah);
993
994 return 0;
995 }
996
997 static void ath9k_hw_init_bb(struct ath_hw *ah,
998 struct ath9k_channel *chan)
999 {
1000 u32 synthDelay;
1001
1002 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1003 if (IS_CHAN_B(chan))
1004 synthDelay = (4 * synthDelay) / 22;
1005 else
1006 synthDelay /= 10;
1007
1008 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
1009
1010 udelay(synthDelay + BASE_ACTIVATE_DELAY);
1011 }
1012
1013 static void ath9k_hw_init_qos(struct ath_hw *ah)
1014 {
1015 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
1016 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
1017
1018 REG_WRITE(ah, AR_QOS_NO_ACK,
1019 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
1020 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
1021 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
1022
1023 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
1024 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
1025 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
1026 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
1027 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
1028 }
1029
1030 static void ath9k_hw_init_pll(struct ath_hw *ah,
1031 struct ath9k_channel *chan)
1032 {
1033 u32 pll;
1034
1035 if (AR_SREV_9100(ah)) {
1036 if (chan && IS_CHAN_5GHZ(chan))
1037 pll = 0x1450;
1038 else
1039 pll = 0x1458;
1040 } else {
1041 if (AR_SREV_9280_10_OR_LATER(ah)) {
1042 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1043
1044 if (chan && IS_CHAN_HALF_RATE(chan))
1045 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1046 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1047 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1048
1049 if (chan && IS_CHAN_5GHZ(chan)) {
1050 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
1051
1052
1053 if (AR_SREV_9280_20(ah)) {
1054 if (((chan->channel % 20) == 0)
1055 || ((chan->channel % 10) == 0))
1056 pll = 0x2850;
1057 else
1058 pll = 0x142c;
1059 }
1060 } else {
1061 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
1062 }
1063
1064 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1065
1066 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1067
1068 if (chan && IS_CHAN_HALF_RATE(chan))
1069 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1070 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1071 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1072
1073 if (chan && IS_CHAN_5GHZ(chan))
1074 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1075 else
1076 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1077 } else {
1078 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1079
1080 if (chan && IS_CHAN_HALF_RATE(chan))
1081 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1082 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1083 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1084
1085 if (chan && IS_CHAN_5GHZ(chan))
1086 pll |= SM(0xa, AR_RTC_PLL_DIV);
1087 else
1088 pll |= SM(0xb, AR_RTC_PLL_DIV);
1089 }
1090 }
1091 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
1092
1093 udelay(RTC_PLL_SETTLE_DELAY);
1094
1095 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1096 }
1097
1098 static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
1099 {
1100 int rx_chainmask, tx_chainmask;
1101
1102 rx_chainmask = ah->rxchainmask;
1103 tx_chainmask = ah->txchainmask;
1104
1105 switch (rx_chainmask) {
1106 case 0x5:
1107 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1108 AR_PHY_SWAP_ALT_CHAIN);
1109 case 0x3:
1110 if (((ah)->hw_version.macVersion <= AR_SREV_VERSION_9160)) {
1111 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1112 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1113 break;
1114 }
1115 case 0x1:
1116 case 0x2:
1117 case 0x7:
1118 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1119 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1120 break;
1121 default:
1122 break;
1123 }
1124
1125 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1126 if (tx_chainmask == 0x5) {
1127 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1128 AR_PHY_SWAP_ALT_CHAIN);
1129 }
1130 if (AR_SREV_9100(ah))
1131 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1132 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1133 }
1134
1135 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1136 enum nl80211_iftype opmode)
1137 {
1138 ah->mask_reg = AR_IMR_TXERR |
1139 AR_IMR_TXURN |
1140 AR_IMR_RXERR |
1141 AR_IMR_RXORN |
1142 AR_IMR_BCNMISC;
1143
1144 if (ah->config.intr_mitigation)
1145 ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1146 else
1147 ah->mask_reg |= AR_IMR_RXOK;
1148
1149 ah->mask_reg |= AR_IMR_TXOK;
1150
1151 if (opmode == NL80211_IFTYPE_AP)
1152 ah->mask_reg |= AR_IMR_MIB;
1153
1154 REG_WRITE(ah, AR_IMR, ah->mask_reg);
1155 REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1156
1157 if (!AR_SREV_9100(ah)) {
1158 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1159 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1160 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1161 }
1162 }
1163
1164 static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1165 {
1166 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
1167 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us);
1168 ah->acktimeout = (u32) -1;
1169 return false;
1170 } else {
1171 REG_RMW_FIELD(ah, AR_TIME_OUT,
1172 AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
1173 ah->acktimeout = us;
1174 return true;
1175 }
1176 }
1177
1178 static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1179 {
1180 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
1181 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us);
1182 ah->ctstimeout = (u32) -1;
1183 return false;
1184 } else {
1185 REG_RMW_FIELD(ah, AR_TIME_OUT,
1186 AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
1187 ah->ctstimeout = us;
1188 return true;
1189 }
1190 }
1191
1192 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1193 {
1194 if (tu > 0xFFFF) {
1195 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
1196 "bad global tx timeout %u\n", tu);
1197 ah->globaltxtimeout = (u32) -1;
1198 return false;
1199 } else {
1200 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1201 ah->globaltxtimeout = tu;
1202 return true;
1203 }
1204 }
1205
1206 static void ath9k_hw_init_user_settings(struct ath_hw *ah)
1207 {
1208 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1209 ah->misc_mode);
1210
1211 if (ah->misc_mode != 0)
1212 REG_WRITE(ah, AR_PCU_MISC,
1213 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1214 if (ah->slottime != (u32) -1)
1215 ath9k_hw_setslottime(ah, ah->slottime);
1216 if (ah->acktimeout != (u32) -1)
1217 ath9k_hw_set_ack_timeout(ah, ah->acktimeout);
1218 if (ah->ctstimeout != (u32) -1)
1219 ath9k_hw_set_cts_timeout(ah, ah->ctstimeout);
1220 if (ah->globaltxtimeout != (u32) -1)
1221 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1222 }
1223
1224 const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1225 {
1226 return vendorid == ATHEROS_VENDOR_ID ?
1227 ath9k_hw_devname(devid) : NULL;
1228 }
1229
1230 void ath9k_hw_detach(struct ath_hw *ah)
1231 {
1232 if (!AR_SREV_9100(ah))
1233 ath9k_hw_ani_disable(ah);
1234
1235 ath9k_hw_rf_free(ah);
1236 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1237 kfree(ah);
1238 ah = NULL;
1239 }
1240
1241 /*******/
1242 /* INI */
1243 /*******/
1244
1245 static void ath9k_hw_override_ini(struct ath_hw *ah,
1246 struct ath9k_channel *chan)
1247 {
1248 u32 val;
1249
1250 if (AR_SREV_9271(ah)) {
1251 /*
1252 * Enable spectral scan to solution for issues with stuck
1253 * beacons on AR9271 1.0. The beacon stuck issue is not seeon on
1254 * AR9271 1.1
1255 */
1256 if (AR_SREV_9271_10(ah)) {
1257 val = REG_READ(ah, AR_PHY_SPECTRAL_SCAN) | AR_PHY_SPECTRAL_SCAN_ENABLE;
1258 REG_WRITE(ah, AR_PHY_SPECTRAL_SCAN, val);
1259 }
1260 else if (AR_SREV_9271_11(ah))
1261 /*
1262 * change AR_PHY_RF_CTL3 setting to fix MAC issue
1263 * present on AR9271 1.1
1264 */
1265 REG_WRITE(ah, AR_PHY_RF_CTL3, 0x3a020001);
1266 return;
1267 }
1268
1269 /*
1270 * Set the RX_ABORT and RX_DIS and clear if off only after
1271 * RXE is set for MAC. This prevents frames with corrupted
1272 * descriptor status.
1273 */
1274 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1275
1276
1277 if (!AR_SREV_5416_20_OR_LATER(ah) ||
1278 AR_SREV_9280_10_OR_LATER(ah))
1279 return;
1280 /*
1281 * Disable BB clock gating
1282 * Necessary to avoid issues on AR5416 2.0
1283 */
1284 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1285 }
1286
1287 static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
1288 struct ar5416_eeprom_def *pEepData,
1289 u32 reg, u32 value)
1290 {
1291 struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1292
1293 switch (ah->hw_version.devid) {
1294 case AR9280_DEVID_PCI:
1295 if (reg == 0x7894) {
1296 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1297 "ini VAL: %x EEPROM: %x\n", value,
1298 (pBase->version & 0xff));
1299
1300 if ((pBase->version & 0xff) > 0x0a) {
1301 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1302 "PWDCLKIND: %d\n",
1303 pBase->pwdclkind);
1304 value &= ~AR_AN_TOP2_PWDCLKIND;
1305 value |= AR_AN_TOP2_PWDCLKIND &
1306 (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1307 } else {
1308 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1309 "PWDCLKIND Earlier Rev\n");
1310 }
1311
1312 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1313 "final ini VAL: %x\n", value);
1314 }
1315 break;
1316 }
1317
1318 return value;
1319 }
1320
1321 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
1322 struct ar5416_eeprom_def *pEepData,
1323 u32 reg, u32 value)
1324 {
1325 if (ah->eep_map == EEP_MAP_4KBITS)
1326 return value;
1327 else
1328 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1329 }
1330
1331 static void ath9k_olc_init(struct ath_hw *ah)
1332 {
1333 u32 i;
1334
1335 for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
1336 ah->originalGain[i] =
1337 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
1338 AR_PHY_TX_GAIN);
1339 ah->PDADCdelta = 0;
1340 }
1341
1342 static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
1343 struct ath9k_channel *chan)
1344 {
1345 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1346
1347 if (IS_CHAN_B(chan))
1348 ctl |= CTL_11B;
1349 else if (IS_CHAN_G(chan))
1350 ctl |= CTL_11G;
1351 else
1352 ctl |= CTL_11A;
1353
1354 return ctl;
1355 }
1356
1357 static int ath9k_hw_process_ini(struct ath_hw *ah,
1358 struct ath9k_channel *chan,
1359 enum ath9k_ht_macmode macmode)
1360 {
1361 int i, regWrites = 0;
1362 struct ieee80211_channel *channel = chan->chan;
1363 u32 modesIndex, freqIndex;
1364
1365 switch (chan->chanmode) {
1366 case CHANNEL_A:
1367 case CHANNEL_A_HT20:
1368 modesIndex = 1;
1369 freqIndex = 1;
1370 break;
1371 case CHANNEL_A_HT40PLUS:
1372 case CHANNEL_A_HT40MINUS:
1373 modesIndex = 2;
1374 freqIndex = 1;
1375 break;
1376 case CHANNEL_G:
1377 case CHANNEL_G_HT20:
1378 case CHANNEL_B:
1379 modesIndex = 4;
1380 freqIndex = 2;
1381 break;
1382 case CHANNEL_G_HT40PLUS:
1383 case CHANNEL_G_HT40MINUS:
1384 modesIndex = 3;
1385 freqIndex = 2;
1386 break;
1387
1388 default:
1389 return -EINVAL;
1390 }
1391
1392 REG_WRITE(ah, AR_PHY(0), 0x00000007);
1393 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1394 ah->eep_ops->set_addac(ah, chan);
1395
1396 if (AR_SREV_5416_22_OR_LATER(ah)) {
1397 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
1398 } else {
1399 struct ar5416IniArray temp;
1400 u32 addacSize =
1401 sizeof(u32) * ah->iniAddac.ia_rows *
1402 ah->iniAddac.ia_columns;
1403
1404 memcpy(ah->addac5416_21,
1405 ah->iniAddac.ia_array, addacSize);
1406
1407 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
1408
1409 temp.ia_array = ah->addac5416_21;
1410 temp.ia_columns = ah->iniAddac.ia_columns;
1411 temp.ia_rows = ah->iniAddac.ia_rows;
1412 REG_WRITE_ARRAY(&temp, 1, regWrites);
1413 }
1414
1415 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1416
1417 for (i = 0; i < ah->iniModes.ia_rows; i++) {
1418 u32 reg = INI_RA(&ah->iniModes, i, 0);
1419 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
1420
1421 REG_WRITE(ah, reg, val);
1422
1423 if (reg >= 0x7800 && reg < 0x78a0
1424 && ah->config.analog_shiftreg) {
1425 udelay(100);
1426 }
1427
1428 DO_DELAY(regWrites);
1429 }
1430
1431 if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
1432 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1433
1434 if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
1435 AR_SREV_9287_10_OR_LATER(ah))
1436 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1437
1438 for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1439 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1440 u32 val = INI_RA(&ah->iniCommon, i, 1);
1441
1442 REG_WRITE(ah, reg, val);
1443
1444 if (reg >= 0x7800 && reg < 0x78a0
1445 && ah->config.analog_shiftreg) {
1446 udelay(100);
1447 }
1448
1449 DO_DELAY(regWrites);
1450 }
1451
1452 ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1453
1454 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1455 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
1456 regWrites);
1457 }
1458
1459 ath9k_hw_override_ini(ah, chan);
1460 ath9k_hw_set_regs(ah, chan, macmode);
1461 ath9k_hw_init_chain_masks(ah);
1462
1463 if (OLC_FOR_AR9280_20_LATER)
1464 ath9k_olc_init(ah);
1465
1466 ah->eep_ops->set_txpower(ah, chan,
1467 ath9k_regd_get_ctl(&ah->regulatory, chan),
1468 channel->max_antenna_gain * 2,
1469 channel->max_power * 2,
1470 min((u32) MAX_RATE_POWER,
1471 (u32) ah->regulatory.power_limit));
1472
1473 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1474 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1475 "ar5416SetRfRegs failed\n");
1476 return -EIO;
1477 }
1478
1479 return 0;
1480 }
1481
1482 /****************************************/
1483 /* Reset and Channel Switching Routines */
1484 /****************************************/
1485
1486 static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1487 {
1488 u32 rfMode = 0;
1489
1490 if (chan == NULL)
1491 return;
1492
1493 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1494 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1495
1496 if (!AR_SREV_9280_10_OR_LATER(ah))
1497 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1498 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1499
1500 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1501 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1502
1503 REG_WRITE(ah, AR_PHY_MODE, rfMode);
1504 }
1505
1506 static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
1507 {
1508 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1509 }
1510
1511 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1512 {
1513 u32 regval;
1514
1515 /*
1516 * set AHB_MODE not to do cacheline prefetches
1517 */
1518 regval = REG_READ(ah, AR_AHB_MODE);
1519 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1520
1521 /*
1522 * let mac dma reads be in 128 byte chunks
1523 */
1524 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1525 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1526
1527 /*
1528 * Restore TX Trigger Level to its pre-reset value.
1529 * The initial value depends on whether aggregation is enabled, and is
1530 * adjusted whenever underruns are detected.
1531 */
1532 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1533
1534 /*
1535 * let mac dma writes be in 128 byte chunks
1536 */
1537 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1538 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1539
1540 /*
1541 * Setup receive FIFO threshold to hold off TX activities
1542 */
1543 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1544
1545 /*
1546 * reduce the number of usable entries in PCU TXBUF to avoid
1547 * wrap around issues.
1548 */
1549 if (AR_SREV_9285(ah)) {
1550 /* For AR9285 the number of Fifos are reduced to half.
1551 * So set the usable tx buf size also to half to
1552 * avoid data/delimiter underruns
1553 */
1554 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1555 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1556 } else if (!AR_SREV_9271(ah)) {
1557 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1558 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1559 }
1560 }
1561
1562 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1563 {
1564 u32 val;
1565
1566 val = REG_READ(ah, AR_STA_ID1);
1567 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1568 switch (opmode) {
1569 case NL80211_IFTYPE_AP:
1570 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1571 | AR_STA_ID1_KSRCH_MODE);
1572 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1573 break;
1574 case NL80211_IFTYPE_ADHOC:
1575 case NL80211_IFTYPE_MESH_POINT:
1576 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1577 | AR_STA_ID1_KSRCH_MODE);
1578 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1579 break;
1580 case NL80211_IFTYPE_STATION:
1581 case NL80211_IFTYPE_MONITOR:
1582 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1583 break;
1584 }
1585 }
1586
1587 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
1588 u32 coef_scaled,
1589 u32 *coef_mantissa,
1590 u32 *coef_exponent)
1591 {
1592 u32 coef_exp, coef_man;
1593
1594 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1595 if ((coef_scaled >> coef_exp) & 0x1)
1596 break;
1597
1598 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1599
1600 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1601
1602 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1603 *coef_exponent = coef_exp - 16;
1604 }
1605
1606 static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
1607 struct ath9k_channel *chan)
1608 {
1609 u32 coef_scaled, ds_coef_exp, ds_coef_man;
1610 u32 clockMhzScaled = 0x64000000;
1611 struct chan_centers centers;
1612
1613 if (IS_CHAN_HALF_RATE(chan))
1614 clockMhzScaled = clockMhzScaled >> 1;
1615 else if (IS_CHAN_QUARTER_RATE(chan))
1616 clockMhzScaled = clockMhzScaled >> 2;
1617
1618 ath9k_hw_get_channel_centers(ah, chan, &centers);
1619 coef_scaled = clockMhzScaled / centers.synth_center;
1620
1621 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1622 &ds_coef_exp);
1623
1624 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1625 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1626 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1627 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1628
1629 coef_scaled = (9 * coef_scaled) / 10;
1630
1631 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1632 &ds_coef_exp);
1633
1634 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1635 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1636 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1637 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1638 }
1639
1640 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1641 {
1642 u32 rst_flags;
1643 u32 tmpReg;
1644
1645 if (AR_SREV_9100(ah)) {
1646 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1647 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1648 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1649 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1650 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1651 }
1652
1653 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1654 AR_RTC_FORCE_WAKE_ON_INT);
1655
1656 if (AR_SREV_9100(ah)) {
1657 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1658 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1659 } else {
1660 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1661 if (tmpReg &
1662 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1663 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1664 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1665 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1666 } else {
1667 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1668 }
1669
1670 rst_flags = AR_RTC_RC_MAC_WARM;
1671 if (type == ATH9K_RESET_COLD)
1672 rst_flags |= AR_RTC_RC_MAC_COLD;
1673 }
1674
1675 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1676 udelay(50);
1677
1678 REG_WRITE(ah, AR_RTC_RC, 0);
1679 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1680 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
1681 "RTC stuck in MAC reset\n");
1682 return false;
1683 }
1684
1685 if (!AR_SREV_9100(ah))
1686 REG_WRITE(ah, AR_RC, 0);
1687
1688 ath9k_hw_init_pll(ah, NULL);
1689
1690 if (AR_SREV_9100(ah))
1691 udelay(50);
1692
1693 return true;
1694 }
1695
1696 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1697 {
1698 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1699 AR_RTC_FORCE_WAKE_ON_INT);
1700
1701 REG_WRITE(ah, AR_RTC_RESET, 0);
1702 udelay(2);
1703 REG_WRITE(ah, AR_RTC_RESET, 1);
1704
1705 if (!ath9k_hw_wait(ah,
1706 AR_RTC_STATUS,
1707 AR_RTC_STATUS_M,
1708 AR_RTC_STATUS_ON,
1709 AH_WAIT_TIMEOUT)) {
1710 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "RTC not waking up\n");
1711 return false;
1712 }
1713
1714 ath9k_hw_read_revisions(ah);
1715
1716 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1717 }
1718
1719 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1720 {
1721 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1722 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1723
1724 switch (type) {
1725 case ATH9K_RESET_POWER_ON:
1726 return ath9k_hw_set_reset_power_on(ah);
1727 case ATH9K_RESET_WARM:
1728 case ATH9K_RESET_COLD:
1729 return ath9k_hw_set_reset(ah, type);
1730 default:
1731 return false;
1732 }
1733 }
1734
1735 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
1736 enum ath9k_ht_macmode macmode)
1737 {
1738 u32 phymode;
1739 u32 enableDacFifo = 0;
1740
1741 if (AR_SREV_9285_10_OR_LATER(ah))
1742 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1743 AR_PHY_FC_ENABLE_DAC_FIFO);
1744
1745 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1746 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1747
1748 if (IS_CHAN_HT40(chan)) {
1749 phymode |= AR_PHY_FC_DYN2040_EN;
1750
1751 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1752 (chan->chanmode == CHANNEL_G_HT40PLUS))
1753 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1754
1755 if (ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1756 phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1757 }
1758 REG_WRITE(ah, AR_PHY_TURBO, phymode);
1759
1760 ath9k_hw_set11nmac2040(ah, macmode);
1761
1762 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1763 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1764 }
1765
1766 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1767 struct ath9k_channel *chan)
1768 {
1769 if (OLC_FOR_AR9280_20_LATER) {
1770 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1771 return false;
1772 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1773 return false;
1774
1775 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1776 return false;
1777
1778 ah->chip_fullsleep = false;
1779 ath9k_hw_init_pll(ah, chan);
1780 ath9k_hw_set_rfmode(ah, chan);
1781
1782 return true;
1783 }
1784
1785 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1786 struct ath9k_channel *chan,
1787 enum ath9k_ht_macmode macmode)
1788 {
1789 struct ieee80211_channel *channel = chan->chan;
1790 u32 synthDelay, qnum;
1791
1792 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1793 if (ath9k_hw_numtxpending(ah, qnum)) {
1794 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
1795 "Transmit frames pending on queue %d\n", qnum);
1796 return false;
1797 }
1798 }
1799
1800 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1801 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1802 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
1803 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1804 "Could not kill baseband RX\n");
1805 return false;
1806 }
1807
1808 ath9k_hw_set_regs(ah, chan, macmode);
1809
1810 if (AR_SREV_9280_10_OR_LATER(ah)) {
1811 ath9k_hw_ar9280_set_channel(ah, chan);
1812 } else {
1813 if (!(ath9k_hw_set_channel(ah, chan))) {
1814 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1815 "Failed to set channel\n");
1816 return false;
1817 }
1818 }
1819
1820 ah->eep_ops->set_txpower(ah, chan,
1821 ath9k_regd_get_ctl(&ah->regulatory, chan),
1822 channel->max_antenna_gain * 2,
1823 channel->max_power * 2,
1824 min((u32) MAX_RATE_POWER,
1825 (u32) ah->regulatory.power_limit));
1826
1827 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1828 if (IS_CHAN_B(chan))
1829 synthDelay = (4 * synthDelay) / 22;
1830 else
1831 synthDelay /= 10;
1832
1833 udelay(synthDelay + BASE_ACTIVATE_DELAY);
1834
1835 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1836
1837 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1838 ath9k_hw_set_delta_slope(ah, chan);
1839
1840 if (AR_SREV_9280_10_OR_LATER(ah))
1841 ath9k_hw_9280_spur_mitigate(ah, chan);
1842 else
1843 ath9k_hw_spur_mitigate(ah, chan);
1844
1845 if (!chan->oneTimeCalsDone)
1846 chan->oneTimeCalsDone = true;
1847
1848 return true;
1849 }
1850
1851 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
1852 {
1853 int bb_spur = AR_NO_SPUR;
1854 int freq;
1855 int bin, cur_bin;
1856 int bb_spur_off, spur_subchannel_sd;
1857 int spur_freq_sd;
1858 int spur_delta_phase;
1859 int denominator;
1860 int upper, lower, cur_vit_mask;
1861 int tmp, newVal;
1862 int i;
1863 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1864 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1865 };
1866 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1867 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1868 };
1869 int inc[4] = { 0, 100, 0, 0 };
1870 struct chan_centers centers;
1871
1872 int8_t mask_m[123];
1873 int8_t mask_p[123];
1874 int8_t mask_amt;
1875 int tmp_mask;
1876 int cur_bb_spur;
1877 bool is2GHz = IS_CHAN_2GHZ(chan);
1878
1879 memset(&mask_m, 0, sizeof(int8_t) * 123);
1880 memset(&mask_p, 0, sizeof(int8_t) * 123);
1881
1882 ath9k_hw_get_channel_centers(ah, chan, &centers);
1883 freq = centers.synth_center;
1884
1885 ah->config.spurmode = SPUR_ENABLE_EEPROM;
1886 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1887 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
1888
1889 if (is2GHz)
1890 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1891 else
1892 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1893
1894 if (AR_NO_SPUR == cur_bb_spur)
1895 break;
1896 cur_bb_spur = cur_bb_spur - freq;
1897
1898 if (IS_CHAN_HT40(chan)) {
1899 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1900 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1901 bb_spur = cur_bb_spur;
1902 break;
1903 }
1904 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1905 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1906 bb_spur = cur_bb_spur;
1907 break;
1908 }
1909 }
1910
1911 if (AR_NO_SPUR == bb_spur) {
1912 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1913 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1914 return;
1915 } else {
1916 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1917 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1918 }
1919
1920 bin = bb_spur * 320;
1921
1922 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1923
1924 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1925 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1926 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1927 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1928 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
1929
1930 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1931 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1932 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1933 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1934 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1935 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
1936
1937 if (IS_CHAN_HT40(chan)) {
1938 if (bb_spur < 0) {
1939 spur_subchannel_sd = 1;
1940 bb_spur_off = bb_spur + 10;
1941 } else {
1942 spur_subchannel_sd = 0;
1943 bb_spur_off = bb_spur - 10;
1944 }
1945 } else {
1946 spur_subchannel_sd = 0;
1947 bb_spur_off = bb_spur;
1948 }
1949
1950 if (IS_CHAN_HT40(chan))
1951 spur_delta_phase =
1952 ((bb_spur * 262144) /
1953 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1954 else
1955 spur_delta_phase =
1956 ((bb_spur * 524288) /
1957 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1958
1959 denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
1960 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
1961
1962 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1963 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1964 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1965 REG_WRITE(ah, AR_PHY_TIMING11, newVal);
1966
1967 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
1968 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
1969
1970 cur_bin = -6000;
1971 upper = bin + 100;
1972 lower = bin - 100;
1973
1974 for (i = 0; i < 4; i++) {
1975 int pilot_mask = 0;
1976 int chan_mask = 0;
1977 int bp = 0;
1978 for (bp = 0; bp < 30; bp++) {
1979 if ((cur_bin > lower) && (cur_bin < upper)) {
1980 pilot_mask = pilot_mask | 0x1 << bp;
1981 chan_mask = chan_mask | 0x1 << bp;
1982 }
1983 cur_bin += 100;
1984 }
1985 cur_bin += inc[i];
1986 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
1987 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
1988 }
1989
1990 cur_vit_mask = 6100;
1991 upper = bin + 120;
1992 lower = bin - 120;
1993
1994 for (i = 0; i < 123; i++) {
1995 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
1996
1997 /* workaround for gcc bug #37014 */
1998 volatile int tmp_v = abs(cur_vit_mask - bin);
1999
2000 if (tmp_v < 75)
2001 mask_amt = 1;
2002 else
2003 mask_amt = 0;
2004 if (cur_vit_mask < 0)
2005 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2006 else
2007 mask_p[cur_vit_mask / 100] = mask_amt;
2008 }
2009 cur_vit_mask -= 100;
2010 }
2011
2012 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2013 | (mask_m[48] << 26) | (mask_m[49] << 24)
2014 | (mask_m[50] << 22) | (mask_m[51] << 20)
2015 | (mask_m[52] << 18) | (mask_m[53] << 16)
2016 | (mask_m[54] << 14) | (mask_m[55] << 12)
2017 | (mask_m[56] << 10) | (mask_m[57] << 8)
2018 | (mask_m[58] << 6) | (mask_m[59] << 4)
2019 | (mask_m[60] << 2) | (mask_m[61] << 0);
2020 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2021 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2022
2023 tmp_mask = (mask_m[31] << 28)
2024 | (mask_m[32] << 26) | (mask_m[33] << 24)
2025 | (mask_m[34] << 22) | (mask_m[35] << 20)
2026 | (mask_m[36] << 18) | (mask_m[37] << 16)
2027 | (mask_m[48] << 14) | (mask_m[39] << 12)
2028 | (mask_m[40] << 10) | (mask_m[41] << 8)
2029 | (mask_m[42] << 6) | (mask_m[43] << 4)
2030 | (mask_m[44] << 2) | (mask_m[45] << 0);
2031 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2032 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2033
2034 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2035 | (mask_m[18] << 26) | (mask_m[18] << 24)
2036 | (mask_m[20] << 22) | (mask_m[20] << 20)
2037 | (mask_m[22] << 18) | (mask_m[22] << 16)
2038 | (mask_m[24] << 14) | (mask_m[24] << 12)
2039 | (mask_m[25] << 10) | (mask_m[26] << 8)
2040 | (mask_m[27] << 6) | (mask_m[28] << 4)
2041 | (mask_m[29] << 2) | (mask_m[30] << 0);
2042 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2043 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2044
2045 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2046 | (mask_m[2] << 26) | (mask_m[3] << 24)
2047 | (mask_m[4] << 22) | (mask_m[5] << 20)
2048 | (mask_m[6] << 18) | (mask_m[7] << 16)
2049 | (mask_m[8] << 14) | (mask_m[9] << 12)
2050 | (mask_m[10] << 10) | (mask_m[11] << 8)
2051 | (mask_m[12] << 6) | (mask_m[13] << 4)
2052 | (mask_m[14] << 2) | (mask_m[15] << 0);
2053 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2054 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2055
2056 tmp_mask = (mask_p[15] << 28)
2057 | (mask_p[14] << 26) | (mask_p[13] << 24)
2058 | (mask_p[12] << 22) | (mask_p[11] << 20)
2059 | (mask_p[10] << 18) | (mask_p[9] << 16)
2060 | (mask_p[8] << 14) | (mask_p[7] << 12)
2061 | (mask_p[6] << 10) | (mask_p[5] << 8)
2062 | (mask_p[4] << 6) | (mask_p[3] << 4)
2063 | (mask_p[2] << 2) | (mask_p[1] << 0);
2064 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2065 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2066
2067 tmp_mask = (mask_p[30] << 28)
2068 | (mask_p[29] << 26) | (mask_p[28] << 24)
2069 | (mask_p[27] << 22) | (mask_p[26] << 20)
2070 | (mask_p[25] << 18) | (mask_p[24] << 16)
2071 | (mask_p[23] << 14) | (mask_p[22] << 12)
2072 | (mask_p[21] << 10) | (mask_p[20] << 8)
2073 | (mask_p[19] << 6) | (mask_p[18] << 4)
2074 | (mask_p[17] << 2) | (mask_p[16] << 0);
2075 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2076 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2077
2078 tmp_mask = (mask_p[45] << 28)
2079 | (mask_p[44] << 26) | (mask_p[43] << 24)
2080 | (mask_p[42] << 22) | (mask_p[41] << 20)
2081 | (mask_p[40] << 18) | (mask_p[39] << 16)
2082 | (mask_p[38] << 14) | (mask_p[37] << 12)
2083 | (mask_p[36] << 10) | (mask_p[35] << 8)
2084 | (mask_p[34] << 6) | (mask_p[33] << 4)
2085 | (mask_p[32] << 2) | (mask_p[31] << 0);
2086 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2087 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2088
2089 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2090 | (mask_p[59] << 26) | (mask_p[58] << 24)
2091 | (mask_p[57] << 22) | (mask_p[56] << 20)
2092 | (mask_p[55] << 18) | (mask_p[54] << 16)
2093 | (mask_p[53] << 14) | (mask_p[52] << 12)
2094 | (mask_p[51] << 10) | (mask_p[50] << 8)
2095 | (mask_p[49] << 6) | (mask_p[48] << 4)
2096 | (mask_p[47] << 2) | (mask_p[46] << 0);
2097 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2098 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2099 }
2100
2101 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
2102 {
2103 int bb_spur = AR_NO_SPUR;
2104 int bin, cur_bin;
2105 int spur_freq_sd;
2106 int spur_delta_phase;
2107 int denominator;
2108 int upper, lower, cur_vit_mask;
2109 int tmp, new;
2110 int i;
2111 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
2112 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
2113 };
2114 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
2115 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
2116 };
2117 int inc[4] = { 0, 100, 0, 0 };
2118
2119 int8_t mask_m[123];
2120 int8_t mask_p[123];
2121 int8_t mask_amt;
2122 int tmp_mask;
2123 int cur_bb_spur;
2124 bool is2GHz = IS_CHAN_2GHZ(chan);
2125
2126 memset(&mask_m, 0, sizeof(int8_t) * 123);
2127 memset(&mask_p, 0, sizeof(int8_t) * 123);
2128
2129 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2130 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
2131 if (AR_NO_SPUR == cur_bb_spur)
2132 break;
2133 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
2134 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
2135 bb_spur = cur_bb_spur;
2136 break;
2137 }
2138 }
2139
2140 if (AR_NO_SPUR == bb_spur)
2141 return;
2142
2143 bin = bb_spur * 32;
2144
2145 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
2146 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
2147 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
2148 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
2149 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
2150
2151 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
2152
2153 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2154 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2155 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2156 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2157 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2158 REG_WRITE(ah, AR_PHY_SPUR_REG, new);
2159
2160 spur_delta_phase = ((bb_spur * 524288) / 100) &
2161 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2162
2163 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
2164 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
2165
2166 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2167 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2168 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2169 REG_WRITE(ah, AR_PHY_TIMING11, new);
2170
2171 cur_bin = -6000;
2172 upper = bin + 100;
2173 lower = bin - 100;
2174
2175 for (i = 0; i < 4; i++) {
2176 int pilot_mask = 0;
2177 int chan_mask = 0;
2178 int bp = 0;
2179 for (bp = 0; bp < 30; bp++) {
2180 if ((cur_bin > lower) && (cur_bin < upper)) {
2181 pilot_mask = pilot_mask | 0x1 << bp;
2182 chan_mask = chan_mask | 0x1 << bp;
2183 }
2184 cur_bin += 100;
2185 }
2186 cur_bin += inc[i];
2187 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2188 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2189 }
2190
2191 cur_vit_mask = 6100;
2192 upper = bin + 120;
2193 lower = bin - 120;
2194
2195 for (i = 0; i < 123; i++) {
2196 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2197
2198 /* workaround for gcc bug #37014 */
2199 volatile int tmp_v = abs(cur_vit_mask - bin);
2200
2201 if (tmp_v < 75)
2202 mask_amt = 1;
2203 else
2204 mask_amt = 0;
2205 if (cur_vit_mask < 0)
2206 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2207 else
2208 mask_p[cur_vit_mask / 100] = mask_amt;
2209 }
2210 cur_vit_mask -= 100;
2211 }
2212
2213 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2214 | (mask_m[48] << 26) | (mask_m[49] << 24)
2215 | (mask_m[50] << 22) | (mask_m[51] << 20)
2216 | (mask_m[52] << 18) | (mask_m[53] << 16)
2217 | (mask_m[54] << 14) | (mask_m[55] << 12)
2218 | (mask_m[56] << 10) | (mask_m[57] << 8)
2219 | (mask_m[58] << 6) | (mask_m[59] << 4)
2220 | (mask_m[60] << 2) | (mask_m[61] << 0);
2221 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2222 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2223
2224 tmp_mask = (mask_m[31] << 28)
2225 | (mask_m[32] << 26) | (mask_m[33] << 24)
2226 | (mask_m[34] << 22) | (mask_m[35] << 20)
2227 | (mask_m[36] << 18) | (mask_m[37] << 16)
2228 | (mask_m[48] << 14) | (mask_m[39] << 12)
2229 | (mask_m[40] << 10) | (mask_m[41] << 8)
2230 | (mask_m[42] << 6) | (mask_m[43] << 4)
2231 | (mask_m[44] << 2) | (mask_m[45] << 0);
2232 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2233 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2234
2235 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2236 | (mask_m[18] << 26) | (mask_m[18] << 24)
2237 | (mask_m[20] << 22) | (mask_m[20] << 20)
2238 | (mask_m[22] << 18) | (mask_m[22] << 16)
2239 | (mask_m[24] << 14) | (mask_m[24] << 12)
2240 | (mask_m[25] << 10) | (mask_m[26] << 8)
2241 | (mask_m[27] << 6) | (mask_m[28] << 4)
2242 | (mask_m[29] << 2) | (mask_m[30] << 0);
2243 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2244 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2245
2246 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2247 | (mask_m[2] << 26) | (mask_m[3] << 24)
2248 | (mask_m[4] << 22) | (mask_m[5] << 20)
2249 | (mask_m[6] << 18) | (mask_m[7] << 16)
2250 | (mask_m[8] << 14) | (mask_m[9] << 12)
2251 | (mask_m[10] << 10) | (mask_m[11] << 8)
2252 | (mask_m[12] << 6) | (mask_m[13] << 4)
2253 | (mask_m[14] << 2) | (mask_m[15] << 0);
2254 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2255 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2256
2257 tmp_mask = (mask_p[15] << 28)
2258 | (mask_p[14] << 26) | (mask_p[13] << 24)
2259 | (mask_p[12] << 22) | (mask_p[11] << 20)
2260 | (mask_p[10] << 18) | (mask_p[9] << 16)
2261 | (mask_p[8] << 14) | (mask_p[7] << 12)
2262 | (mask_p[6] << 10) | (mask_p[5] << 8)
2263 | (mask_p[4] << 6) | (mask_p[3] << 4)
2264 | (mask_p[2] << 2) | (mask_p[1] << 0);
2265 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2266 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2267
2268 tmp_mask = (mask_p[30] << 28)
2269 | (mask_p[29] << 26) | (mask_p[28] << 24)
2270 | (mask_p[27] << 22) | (mask_p[26] << 20)
2271 | (mask_p[25] << 18) | (mask_p[24] << 16)
2272 | (mask_p[23] << 14) | (mask_p[22] << 12)
2273 | (mask_p[21] << 10) | (mask_p[20] << 8)
2274 | (mask_p[19] << 6) | (mask_p[18] << 4)
2275 | (mask_p[17] << 2) | (mask_p[16] << 0);
2276 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2277 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2278
2279 tmp_mask = (mask_p[45] << 28)
2280 | (mask_p[44] << 26) | (mask_p[43] << 24)
2281 | (mask_p[42] << 22) | (mask_p[41] << 20)
2282 | (mask_p[40] << 18) | (mask_p[39] << 16)
2283 | (mask_p[38] << 14) | (mask_p[37] << 12)
2284 | (mask_p[36] << 10) | (mask_p[35] << 8)
2285 | (mask_p[34] << 6) | (mask_p[33] << 4)
2286 | (mask_p[32] << 2) | (mask_p[31] << 0);
2287 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2288 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2289
2290 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2291 | (mask_p[59] << 26) | (mask_p[58] << 24)
2292 | (mask_p[57] << 22) | (mask_p[56] << 20)
2293 | (mask_p[55] << 18) | (mask_p[54] << 16)
2294 | (mask_p[53] << 14) | (mask_p[52] << 12)
2295 | (mask_p[51] << 10) | (mask_p[50] << 8)
2296 | (mask_p[49] << 6) | (mask_p[48] << 4)
2297 | (mask_p[47] << 2) | (mask_p[46] << 0);
2298 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2299 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2300 }
2301
2302 static void ath9k_enable_rfkill(struct ath_hw *ah)
2303 {
2304 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
2305 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
2306
2307 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
2308 AR_GPIO_INPUT_MUX2_RFSILENT);
2309
2310 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
2311 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
2312 }
2313
2314 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2315 bool bChannelChange)
2316 {
2317 u32 saveLedState;
2318 struct ath_softc *sc = ah->ah_sc;
2319 struct ath9k_channel *curchan = ah->curchan;
2320 u32 saveDefAntenna;
2321 u32 macStaId1;
2322 int i, rx_chainmask, r;
2323
2324 ah->extprotspacing = sc->ht_extprotspacing;
2325 ah->txchainmask = sc->tx_chainmask;
2326 ah->rxchainmask = sc->rx_chainmask;
2327
2328 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2329 return -EIO;
2330
2331 if (curchan)
2332 ath9k_hw_getnf(ah, curchan);
2333
2334 if (bChannelChange &&
2335 (ah->chip_fullsleep != true) &&
2336 (ah->curchan != NULL) &&
2337 (chan->channel != ah->curchan->channel) &&
2338 ((chan->channelFlags & CHANNEL_ALL) ==
2339 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
2340 (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
2341 !IS_CHAN_A_5MHZ_SPACED(ah->curchan)))) {
2342
2343 if (ath9k_hw_channel_change(ah, chan, sc->tx_chan_width)) {
2344 ath9k_hw_loadnf(ah, ah->curchan);
2345 ath9k_hw_start_nfcal(ah);
2346 return 0;
2347 }
2348 }
2349
2350 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
2351 if (saveDefAntenna == 0)
2352 saveDefAntenna = 1;
2353
2354 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2355
2356 saveLedState = REG_READ(ah, AR_CFG_LED) &
2357 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2358 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
2359
2360 ath9k_hw_mark_phy_inactive(ah);
2361
2362 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
2363 REG_WRITE(ah,
2364 AR9271_RESET_POWER_DOWN_CONTROL,
2365 AR9271_RADIO_RF_RST);
2366 udelay(50);
2367 }
2368
2369 if (!ath9k_hw_chip_reset(ah, chan)) {
2370 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Chip reset failed\n");
2371 return -EINVAL;
2372 }
2373
2374 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
2375 ah->htc_reset_init = false;
2376 REG_WRITE(ah,
2377 AR9271_RESET_POWER_DOWN_CONTROL,
2378 AR9271_GATE_MAC_CTL);
2379 udelay(50);
2380 }
2381
2382 if (AR_SREV_9280_10_OR_LATER(ah))
2383 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
2384
2385 if (AR_SREV_9287_10_OR_LATER(ah)) {
2386 /* Enable ASYNC FIFO */
2387 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2388 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
2389 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
2390 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2391 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2392 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2393 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2394 }
2395 r = ath9k_hw_process_ini(ah, chan, sc->tx_chan_width);
2396 if (r)
2397 return r;
2398
2399 /* Setup MFP options for CCMP */
2400 if (AR_SREV_9280_20_OR_LATER(ah)) {
2401 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2402 * frames when constructing CCMP AAD. */
2403 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
2404 0xc7ff);
2405 ah->sw_mgmt_crypto = false;
2406 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2407 /* Disable hardware crypto for management frames */
2408 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
2409 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2410 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2411 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2412 ah->sw_mgmt_crypto = true;
2413 } else
2414 ah->sw_mgmt_crypto = true;
2415
2416 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2417 ath9k_hw_set_delta_slope(ah, chan);
2418
2419 if (AR_SREV_9280_10_OR_LATER(ah))
2420 ath9k_hw_9280_spur_mitigate(ah, chan);
2421 else
2422 ath9k_hw_spur_mitigate(ah, chan);
2423
2424 ah->eep_ops->set_board_values(ah, chan);
2425
2426 ath9k_hw_decrease_chain_power(ah, chan);
2427
2428 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ah->macaddr));
2429 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ah->macaddr + 4)
2430 | macStaId1
2431 | AR_STA_ID1_RTS_USE_DEF
2432 | (ah->config.
2433 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2434 | ah->sta_id1_defaults);
2435 ath9k_hw_set_operating_mode(ah, ah->opmode);
2436
2437 REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
2438 REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
2439
2440 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2441
2442 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
2443 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
2444 ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2445
2446 REG_WRITE(ah, AR_ISR, ~0);
2447
2448 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2449
2450 if (AR_SREV_9280_10_OR_LATER(ah))
2451 ath9k_hw_ar9280_set_channel(ah, chan);
2452 else
2453 if (!(ath9k_hw_set_channel(ah, chan)))
2454 return -EIO;
2455
2456 for (i = 0; i < AR_NUM_DCU; i++)
2457 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2458
2459 ah->intr_txqs = 0;
2460 for (i = 0; i < ah->caps.total_queues; i++)
2461 ath9k_hw_resettxqueue(ah, i);
2462
2463 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
2464 ath9k_hw_init_qos(ah);
2465
2466 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2467 ath9k_enable_rfkill(ah);
2468
2469 ath9k_hw_init_user_settings(ah);
2470
2471 if (AR_SREV_9287_10_OR_LATER(ah)) {
2472 REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
2473 AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
2474 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
2475 AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
2476 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
2477 AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
2478
2479 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
2480 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
2481
2482 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
2483 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
2484 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
2485 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
2486 }
2487 if (AR_SREV_9287_10_OR_LATER(ah)) {
2488 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2489 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
2490 }
2491
2492 REG_WRITE(ah, AR_STA_ID1,
2493 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2494
2495 ath9k_hw_set_dma(ah);
2496
2497 REG_WRITE(ah, AR_OBS, 8);
2498
2499 if (ah->config.intr_mitigation) {
2500 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2501 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2502 }
2503
2504 ath9k_hw_init_bb(ah, chan);
2505
2506 if (!ath9k_hw_init_cal(ah, chan))
2507 return -EIO;
2508
2509 rx_chainmask = ah->rxchainmask;
2510 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2511 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2512 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2513 }
2514
2515 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2516
2517 /*
2518 * For big endian systems turn on swapping for descriptors
2519 */
2520 if (AR_SREV_9100(ah)) {
2521 u32 mask;
2522 mask = REG_READ(ah, AR_CFG);
2523 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2524 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2525 "CFG Byte Swap Set 0x%x\n", mask);
2526 } else {
2527 mask =
2528 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2529 REG_WRITE(ah, AR_CFG, mask);
2530 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2531 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2532 }
2533 } else {
2534 /* Configure AR9271 target WLAN */
2535 if (AR_SREV_9271(ah))
2536 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
2537 #ifdef __BIG_ENDIAN
2538 else
2539 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2540 #endif
2541 }
2542
2543 return 0;
2544 }
2545
2546 /************************/
2547 /* Key Cache Management */
2548 /************************/
2549
2550 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2551 {
2552 u32 keyType;
2553
2554 if (entry >= ah->caps.keycache_size) {
2555 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2556 "keychache entry %u out of range\n", entry);
2557 return false;
2558 }
2559
2560 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2561
2562 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2563 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2564 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2565 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2566 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2567 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2568 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2569 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2570
2571 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2572 u16 micentry = entry + 64;
2573
2574 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2575 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2576 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2577 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2578
2579 }
2580
2581 return true;
2582 }
2583
2584 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2585 {
2586 u32 macHi, macLo;
2587
2588 if (entry >= ah->caps.keycache_size) {
2589 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2590 "keychache entry %u out of range\n", entry);
2591 return false;
2592 }
2593
2594 if (mac != NULL) {
2595 macHi = (mac[5] << 8) | mac[4];
2596 macLo = (mac[3] << 24) |
2597 (mac[2] << 16) |
2598 (mac[1] << 8) |
2599 mac[0];
2600 macLo >>= 1;
2601 macLo |= (macHi & 1) << 31;
2602 macHi >>= 1;
2603 } else {
2604 macLo = macHi = 0;
2605 }
2606 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2607 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2608
2609 return true;
2610 }
2611
2612 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2613 const struct ath9k_keyval *k,
2614 const u8 *mac)
2615 {
2616 const struct ath9k_hw_capabilities *pCap = &ah->caps;
2617 u32 key0, key1, key2, key3, key4;
2618 u32 keyType;
2619
2620 if (entry >= pCap->keycache_size) {
2621 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2622 "keycache entry %u out of range\n", entry);
2623 return false;
2624 }
2625
2626 switch (k->kv_type) {
2627 case ATH9K_CIPHER_AES_OCB:
2628 keyType = AR_KEYTABLE_TYPE_AES;
2629 break;
2630 case ATH9K_CIPHER_AES_CCM:
2631 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2632 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2633 "AES-CCM not supported by mac rev 0x%x\n",
2634 ah->hw_version.macRev);
2635 return false;
2636 }
2637 keyType = AR_KEYTABLE_TYPE_CCM;
2638 break;
2639 case ATH9K_CIPHER_TKIP:
2640 keyType = AR_KEYTABLE_TYPE_TKIP;
2641 if (ATH9K_IS_MIC_ENABLED(ah)
2642 && entry + 64 >= pCap->keycache_size) {
2643 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2644 "entry %u inappropriate for TKIP\n", entry);
2645 return false;
2646 }
2647 break;
2648 case ATH9K_CIPHER_WEP:
2649 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
2650 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2651 "WEP key length %u too small\n", k->kv_len);
2652 return false;
2653 }
2654 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
2655 keyType = AR_KEYTABLE_TYPE_40;
2656 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2657 keyType = AR_KEYTABLE_TYPE_104;
2658 else
2659 keyType = AR_KEYTABLE_TYPE_128;
2660 break;
2661 case ATH9K_CIPHER_CLR:
2662 keyType = AR_KEYTABLE_TYPE_CLR;
2663 break;
2664 default:
2665 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2666 "cipher %u not supported\n", k->kv_type);
2667 return false;
2668 }
2669
2670 key0 = get_unaligned_le32(k->kv_val + 0);
2671 key1 = get_unaligned_le16(k->kv_val + 4);
2672 key2 = get_unaligned_le32(k->kv_val + 6);
2673 key3 = get_unaligned_le16(k->kv_val + 10);
2674 key4 = get_unaligned_le32(k->kv_val + 12);
2675 if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2676 key4 &= 0xff;
2677
2678 /*
2679 * Note: Key cache registers access special memory area that requires
2680 * two 32-bit writes to actually update the values in the internal
2681 * memory. Consequently, the exact order and pairs used here must be
2682 * maintained.
2683 */
2684
2685 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2686 u16 micentry = entry + 64;
2687
2688 /*
2689 * Write inverted key[47:0] first to avoid Michael MIC errors
2690 * on frames that could be sent or received at the same time.
2691 * The correct key will be written in the end once everything
2692 * else is ready.
2693 */
2694 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2695 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2696
2697 /* Write key[95:48] */
2698 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2699 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2700
2701 /* Write key[127:96] and key type */
2702 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2703 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2704
2705 /* Write MAC address for the entry */
2706 (void) ath9k_hw_keysetmac(ah, entry, mac);
2707
2708 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
2709 /*
2710 * TKIP uses two key cache entries:
2711 * Michael MIC TX/RX keys in the same key cache entry
2712 * (idx = main index + 64):
2713 * key0 [31:0] = RX key [31:0]
2714 * key1 [15:0] = TX key [31:16]
2715 * key1 [31:16] = reserved
2716 * key2 [31:0] = RX key [63:32]
2717 * key3 [15:0] = TX key [15:0]
2718 * key3 [31:16] = reserved
2719 * key4 [31:0] = TX key [63:32]
2720 */
2721 u32 mic0, mic1, mic2, mic3, mic4;
2722
2723 mic0 = get_unaligned_le32(k->kv_mic + 0);
2724 mic2 = get_unaligned_le32(k->kv_mic + 4);
2725 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2726 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2727 mic4 = get_unaligned_le32(k->kv_txmic + 4);
2728
2729 /* Write RX[31:0] and TX[31:16] */
2730 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2731 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2732
2733 /* Write RX[63:32] and TX[15:0] */
2734 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2735 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2736
2737 /* Write TX[63:32] and keyType(reserved) */
2738 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2739 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2740 AR_KEYTABLE_TYPE_CLR);
2741
2742 } else {
2743 /*
2744 * TKIP uses four key cache entries (two for group
2745 * keys):
2746 * Michael MIC TX/RX keys are in different key cache
2747 * entries (idx = main index + 64 for TX and
2748 * main index + 32 + 96 for RX):
2749 * key0 [31:0] = TX/RX MIC key [31:0]
2750 * key1 [31:0] = reserved
2751 * key2 [31:0] = TX/RX MIC key [63:32]
2752 * key3 [31:0] = reserved
2753 * key4 [31:0] = reserved
2754 *
2755 * Upper layer code will call this function separately
2756 * for TX and RX keys when these registers offsets are
2757 * used.
2758 */
2759 u32 mic0, mic2;
2760
2761 mic0 = get_unaligned_le32(k->kv_mic + 0);
2762 mic2 = get_unaligned_le32(k->kv_mic + 4);
2763
2764 /* Write MIC key[31:0] */
2765 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2766 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2767
2768 /* Write MIC key[63:32] */
2769 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2770 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2771
2772 /* Write TX[63:32] and keyType(reserved) */
2773 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2774 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2775 AR_KEYTABLE_TYPE_CLR);
2776 }
2777
2778 /* MAC address registers are reserved for the MIC entry */
2779 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2780 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2781
2782 /*
2783 * Write the correct (un-inverted) key[47:0] last to enable
2784 * TKIP now that all other registers are set with correct
2785 * values.
2786 */
2787 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2788 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2789 } else {
2790 /* Write key[47:0] */
2791 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2792 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2793
2794 /* Write key[95:48] */
2795 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2796 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2797
2798 /* Write key[127:96] and key type */
2799 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2800 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2801
2802 /* Write MAC address for the entry */
2803 (void) ath9k_hw_keysetmac(ah, entry, mac);
2804 }
2805
2806 return true;
2807 }
2808
2809 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2810 {
2811 if (entry < ah->caps.keycache_size) {
2812 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2813 if (val & AR_KEYTABLE_VALID)
2814 return true;
2815 }
2816 return false;
2817 }
2818
2819 /******************************/
2820 /* Power Management (Chipset) */
2821 /******************************/
2822
2823 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2824 {
2825 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2826 if (setChip) {
2827 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2828 AR_RTC_FORCE_WAKE_EN);
2829 if (!AR_SREV_9100(ah))
2830 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2831
2832 REG_CLR_BIT(ah, (AR_RTC_RESET),
2833 AR_RTC_RESET_EN);
2834 }
2835 }
2836
2837 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2838 {
2839 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2840 if (setChip) {
2841 struct ath9k_hw_capabilities *pCap = &ah->caps;
2842
2843 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2844 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2845 AR_RTC_FORCE_WAKE_ON_INT);
2846 } else {
2847 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2848 AR_RTC_FORCE_WAKE_EN);
2849 }
2850 }
2851 }
2852
2853 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2854 {
2855 u32 val;
2856 int i;
2857
2858 if (setChip) {
2859 if ((REG_READ(ah, AR_RTC_STATUS) &
2860 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2861 if (ath9k_hw_set_reset_reg(ah,
2862 ATH9K_RESET_POWER_ON) != true) {
2863 return false;
2864 }
2865 }
2866 if (AR_SREV_9100(ah))
2867 REG_SET_BIT(ah, AR_RTC_RESET,
2868 AR_RTC_RESET_EN);
2869
2870 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2871 AR_RTC_FORCE_WAKE_EN);
2872 udelay(50);
2873
2874 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2875 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2876 if (val == AR_RTC_STATUS_ON)
2877 break;
2878 udelay(50);
2879 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2880 AR_RTC_FORCE_WAKE_EN);
2881 }
2882 if (i == 0) {
2883 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2884 "Failed to wakeup in %uus\n", POWER_UP_TIME / 20);
2885 return false;
2886 }
2887 }
2888
2889 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2890
2891 return true;
2892 }
2893
2894 static bool ath9k_hw_setpower_nolock(struct ath_hw *ah,
2895 enum ath9k_power_mode mode)
2896 {
2897 int status = true, setChip = true;
2898 static const char *modes[] = {
2899 "AWAKE",
2900 "FULL-SLEEP",
2901 "NETWORK SLEEP",
2902 "UNDEFINED"
2903 };
2904
2905 if (ah->power_mode == mode)
2906 return status;
2907
2908 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s -> %s\n",
2909 modes[ah->power_mode], modes[mode]);
2910
2911 switch (mode) {
2912 case ATH9K_PM_AWAKE:
2913 status = ath9k_hw_set_power_awake(ah, setChip);
2914 break;
2915 case ATH9K_PM_FULL_SLEEP:
2916 ath9k_set_power_sleep(ah, setChip);
2917 ah->chip_fullsleep = true;
2918 break;
2919 case ATH9K_PM_NETWORK_SLEEP:
2920 ath9k_set_power_network_sleep(ah, setChip);
2921 break;
2922 default:
2923 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2924 "Unknown power mode %u\n", mode);
2925 return false;
2926 }
2927 ah->power_mode = mode;
2928
2929 return status;
2930 }
2931
2932 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2933 {
2934 unsigned long flags;
2935 bool ret;
2936
2937 spin_lock_irqsave(&ah->ah_sc->sc_pm_lock, flags);
2938 ret = ath9k_hw_setpower_nolock(ah, mode);
2939 spin_unlock_irqrestore(&ah->ah_sc->sc_pm_lock, flags);
2940
2941 return ret;
2942 }
2943
2944 void ath9k_ps_wakeup(struct ath_softc *sc)
2945 {
2946 unsigned long flags;
2947
2948 spin_lock_irqsave(&sc->sc_pm_lock, flags);
2949 if (++sc->ps_usecount != 1)
2950 goto unlock;
2951
2952 ath9k_hw_setpower_nolock(sc->sc_ah, ATH9K_PM_AWAKE);
2953
2954 unlock:
2955 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
2956 }
2957
2958 void ath9k_ps_restore(struct ath_softc *sc)
2959 {
2960 unsigned long flags;
2961
2962 spin_lock_irqsave(&sc->sc_pm_lock, flags);
2963 if (--sc->ps_usecount != 0)
2964 goto unlock;
2965
2966 if (sc->ps_enabled &&
2967 !(sc->sc_flags & (SC_OP_WAIT_FOR_BEACON |
2968 SC_OP_WAIT_FOR_CAB |
2969 SC_OP_WAIT_FOR_PSPOLL_DATA |
2970 SC_OP_WAIT_FOR_TX_ACK)))
2971 ath9k_hw_setpower_nolock(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
2972
2973 unlock:
2974 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
2975 }
2976
2977 /*
2978 * Helper for ASPM support.
2979 *
2980 * Disable PLL when in L0s as well as receiver clock when in L1.
2981 * This power saving option must be enabled through the SerDes.
2982 *
2983 * Programming the SerDes must go through the same 288 bit serial shift
2984 * register as the other analog registers. Hence the 9 writes.
2985 */
2986 void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore)
2987 {
2988 u8 i;
2989
2990 if (ah->is_pciexpress != true)
2991 return;
2992
2993 /* Do not touch SerDes registers */
2994 if (ah->config.pcie_powersave_enable == 2)
2995 return;
2996
2997 /* Nothing to do on restore for 11N */
2998 if (restore)
2999 return;
3000
3001 if (AR_SREV_9280_20_OR_LATER(ah)) {
3002 /*
3003 * AR9280 2.0 or later chips use SerDes values from the
3004 * initvals.h initialized depending on chipset during
3005 * ath9k_hw_init()
3006 */
3007 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
3008 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
3009 INI_RA(&ah->iniPcieSerdes, i, 1));
3010 }
3011 } else if (AR_SREV_9280(ah) &&
3012 (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
3013 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
3014 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
3015
3016 /* RX shut off when elecidle is asserted */
3017 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
3018 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
3019 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
3020
3021 /* Shut off CLKREQ active in L1 */
3022 if (ah->config.pcie_clock_req)
3023 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
3024 else
3025 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
3026
3027 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
3028 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
3029 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
3030
3031 /* Load the new settings */
3032 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
3033
3034 } else {
3035 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
3036 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
3037
3038 /* RX shut off when elecidle is asserted */
3039 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
3040 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
3041 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
3042
3043 /*
3044 * Ignore ah->ah_config.pcie_clock_req setting for
3045 * pre-AR9280 11n
3046 */
3047 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
3048
3049 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
3050 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
3051 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
3052
3053 /* Load the new settings */
3054 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
3055 }
3056
3057 udelay(1000);
3058
3059 /* set bit 19 to allow forcing of pcie core into L1 state */
3060 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
3061
3062 /* Several PCIe massages to ensure proper behaviour */
3063 if (ah->config.pcie_waen) {
3064 REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
3065 } else {
3066 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
3067 REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
3068 /*
3069 * On AR9280 chips bit 22 of 0x4004 needs to be set to
3070 * otherwise card may disappear.
3071 */
3072 else if (AR_SREV_9280(ah))
3073 REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
3074 else
3075 REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);
3076 }
3077 }
3078
3079 /**********************/
3080 /* Interrupt Handling */
3081 /**********************/
3082
3083 bool ath9k_hw_intrpend(struct ath_hw *ah)
3084 {
3085 u32 host_isr;
3086
3087 if (AR_SREV_9100(ah))
3088 return true;
3089
3090 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
3091 if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
3092 return true;
3093
3094 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
3095 if ((host_isr & AR_INTR_SYNC_DEFAULT)
3096 && (host_isr != AR_INTR_SPURIOUS))
3097 return true;
3098
3099 return false;
3100 }
3101
3102 bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
3103 {
3104 u32 isr = 0;
3105 u32 mask2 = 0;
3106 struct ath9k_hw_capabilities *pCap = &ah->caps;
3107 u32 sync_cause = 0;
3108 bool fatal_int = false;
3109
3110 if (!AR_SREV_9100(ah)) {
3111 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
3112 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
3113 == AR_RTC_STATUS_ON) {
3114 isr = REG_READ(ah, AR_ISR);
3115 }
3116 }
3117
3118 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
3119 AR_INTR_SYNC_DEFAULT;
3120
3121 *masked = 0;
3122
3123 if (!isr && !sync_cause)
3124 return false;
3125 } else {
3126 *masked = 0;
3127 isr = REG_READ(ah, AR_ISR);
3128 }
3129
3130 if (isr) {
3131 if (isr & AR_ISR_BCNMISC) {
3132 u32 isr2;
3133 isr2 = REG_READ(ah, AR_ISR_S2);
3134 if (isr2 & AR_ISR_S2_TIM)
3135 mask2 |= ATH9K_INT_TIM;
3136 if (isr2 & AR_ISR_S2_DTIM)
3137 mask2 |= ATH9K_INT_DTIM;
3138 if (isr2 & AR_ISR_S2_DTIMSYNC)
3139 mask2 |= ATH9K_INT_DTIMSYNC;
3140 if (isr2 & (AR_ISR_S2_CABEND))
3141 mask2 |= ATH9K_INT_CABEND;
3142 if (isr2 & AR_ISR_S2_GTT)
3143 mask2 |= ATH9K_INT_GTT;
3144 if (isr2 & AR_ISR_S2_CST)
3145 mask2 |= ATH9K_INT_CST;
3146 if (isr2 & AR_ISR_S2_TSFOOR)
3147 mask2 |= ATH9K_INT_TSFOOR;
3148 }
3149
3150 isr = REG_READ(ah, AR_ISR_RAC);
3151 if (isr == 0xffffffff) {
3152 *masked = 0;
3153 return false;
3154 }
3155
3156 *masked = isr & ATH9K_INT_COMMON;
3157
3158 if (ah->config.intr_mitigation) {
3159 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
3160 *masked |= ATH9K_INT_RX;
3161 }
3162
3163 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
3164 *masked |= ATH9K_INT_RX;
3165 if (isr &
3166 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
3167 AR_ISR_TXEOL)) {
3168 u32 s0_s, s1_s;
3169
3170 *masked |= ATH9K_INT_TX;
3171
3172 s0_s = REG_READ(ah, AR_ISR_S0_S);
3173 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
3174 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
3175
3176 s1_s = REG_READ(ah, AR_ISR_S1_S);
3177 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
3178 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
3179 }
3180
3181 if (isr & AR_ISR_RXORN) {
3182 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
3183 "receive FIFO overrun interrupt\n");
3184 }
3185
3186 if (!AR_SREV_9100(ah)) {
3187 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3188 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
3189 if (isr5 & AR_ISR_S5_TIM_TIMER)
3190 *masked |= ATH9K_INT_TIM_TIMER;
3191 }
3192 }
3193
3194 *masked |= mask2;
3195 }
3196
3197 if (AR_SREV_9100(ah))
3198 return true;
3199
3200 if (sync_cause) {
3201 fatal_int =
3202 (sync_cause &
3203 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
3204 ? true : false;
3205
3206 if (fatal_int) {
3207 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
3208 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
3209 "received PCI FATAL interrupt\n");
3210 }
3211 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
3212 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
3213 "received PCI PERR interrupt\n");
3214 }
3215 *masked |= ATH9K_INT_FATAL;
3216 }
3217 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
3218 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
3219 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
3220 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
3221 REG_WRITE(ah, AR_RC, 0);
3222 *masked |= ATH9K_INT_FATAL;
3223 }
3224 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
3225 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
3226 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
3227 }
3228
3229 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
3230 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
3231 }
3232
3233 return true;
3234 }
3235
3236 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
3237 {
3238 u32 omask = ah->mask_reg;
3239 u32 mask, mask2;
3240 struct ath9k_hw_capabilities *pCap = &ah->caps;
3241
3242 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
3243
3244 if (omask & ATH9K_INT_GLOBAL) {
3245 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "disable IER\n");
3246 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
3247 (void) REG_READ(ah, AR_IER);
3248 if (!AR_SREV_9100(ah)) {
3249 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
3250 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
3251
3252 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
3253 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
3254 }
3255 }
3256
3257 mask = ints & ATH9K_INT_COMMON;
3258 mask2 = 0;
3259
3260 if (ints & ATH9K_INT_TX) {
3261 if (ah->txok_interrupt_mask)
3262 mask |= AR_IMR_TXOK;
3263 if (ah->txdesc_interrupt_mask)
3264 mask |= AR_IMR_TXDESC;
3265 if (ah->txerr_interrupt_mask)
3266 mask |= AR_IMR_TXERR;
3267 if (ah->txeol_interrupt_mask)
3268 mask |= AR_IMR_TXEOL;
3269 }
3270 if (ints & ATH9K_INT_RX) {
3271 mask |= AR_IMR_RXERR;
3272 if (ah->config.intr_mitigation)
3273 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
3274 else
3275 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
3276 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
3277 mask |= AR_IMR_GENTMR;
3278 }
3279
3280 if (ints & (ATH9K_INT_BMISC)) {
3281 mask |= AR_IMR_BCNMISC;
3282 if (ints & ATH9K_INT_TIM)
3283 mask2 |= AR_IMR_S2_TIM;
3284 if (ints & ATH9K_INT_DTIM)
3285 mask2 |= AR_IMR_S2_DTIM;
3286 if (ints & ATH9K_INT_DTIMSYNC)
3287 mask2 |= AR_IMR_S2_DTIMSYNC;
3288 if (ints & ATH9K_INT_CABEND)
3289 mask2 |= AR_IMR_S2_CABEND;
3290 if (ints & ATH9K_INT_TSFOOR)
3291 mask2 |= AR_IMR_S2_TSFOOR;
3292 }
3293
3294 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
3295 mask |= AR_IMR_BCNMISC;
3296 if (ints & ATH9K_INT_GTT)
3297 mask2 |= AR_IMR_S2_GTT;
3298 if (ints & ATH9K_INT_CST)
3299 mask2 |= AR_IMR_S2_CST;
3300 }
3301
3302 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
3303 REG_WRITE(ah, AR_IMR, mask);
3304 mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
3305 AR_IMR_S2_DTIM |
3306 AR_IMR_S2_DTIMSYNC |
3307 AR_IMR_S2_CABEND |
3308 AR_IMR_S2_CABTO |
3309 AR_IMR_S2_TSFOOR |
3310 AR_IMR_S2_GTT | AR_IMR_S2_CST);
3311 REG_WRITE(ah, AR_IMR_S2, mask | mask2);
3312 ah->mask_reg = ints;
3313
3314 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3315 if (ints & ATH9K_INT_TIM_TIMER)
3316 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3317 else
3318 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3319 }
3320
3321 if (ints & ATH9K_INT_GLOBAL) {
3322 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "enable IER\n");
3323 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
3324 if (!AR_SREV_9100(ah)) {
3325 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
3326 AR_INTR_MAC_IRQ);
3327 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
3328
3329
3330 REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
3331 AR_INTR_SYNC_DEFAULT);
3332 REG_WRITE(ah, AR_INTR_SYNC_MASK,
3333 AR_INTR_SYNC_DEFAULT);
3334 }
3335 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
3336 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
3337 }
3338
3339 return omask;
3340 }
3341
3342 /*******************/
3343 /* Beacon Handling */
3344 /*******************/
3345
3346 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
3347 {
3348 int flags = 0;
3349
3350 ah->beacon_interval = beacon_period;
3351
3352 switch (ah->opmode) {
3353 case NL80211_IFTYPE_STATION:
3354 case NL80211_IFTYPE_MONITOR:
3355 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3356 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
3357 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
3358 flags |= AR_TBTT_TIMER_EN;
3359 break;
3360 case NL80211_IFTYPE_ADHOC:
3361 case NL80211_IFTYPE_MESH_POINT:
3362 REG_SET_BIT(ah, AR_TXCFG,
3363 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
3364 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3365 TU_TO_USEC(next_beacon +
3366 (ah->atim_window ? ah->
3367 atim_window : 1)));
3368 flags |= AR_NDP_TIMER_EN;
3369 case NL80211_IFTYPE_AP:
3370 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3371 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3372 TU_TO_USEC(next_beacon -
3373 ah->config.
3374 dma_beacon_response_time));
3375 REG_WRITE(ah, AR_NEXT_SWBA,
3376 TU_TO_USEC(next_beacon -
3377 ah->config.
3378 sw_beacon_response_time));
3379 flags |=
3380 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3381 break;
3382 default:
3383 DPRINTF(ah->ah_sc, ATH_DBG_BEACON,
3384 "%s: unsupported opmode: %d\n",
3385 __func__, ah->opmode);
3386 return;
3387 break;
3388 }
3389
3390 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3391 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3392 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3393 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3394
3395 beacon_period &= ~ATH9K_BEACON_ENA;
3396 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3397 beacon_period &= ~ATH9K_BEACON_RESET_TSF;
3398 ath9k_hw_reset_tsf(ah);
3399 }
3400
3401 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3402 }
3403
3404 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3405 const struct ath9k_beacon_state *bs)
3406 {
3407 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3408 struct ath9k_hw_capabilities *pCap = &ah->caps;
3409
3410 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3411
3412 REG_WRITE(ah, AR_BEACON_PERIOD,
3413 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3414 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3415 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3416
3417 REG_RMW_FIELD(ah, AR_RSSI_THR,
3418 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3419
3420 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3421
3422 if (bs->bs_sleepduration > beaconintval)
3423 beaconintval = bs->bs_sleepduration;
3424
3425 dtimperiod = bs->bs_dtimperiod;
3426 if (bs->bs_sleepduration > dtimperiod)
3427 dtimperiod = bs->bs_sleepduration;
3428
3429 if (beaconintval == dtimperiod)
3430 nextTbtt = bs->bs_nextdtim;
3431 else
3432 nextTbtt = bs->bs_nexttbtt;
3433
3434 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3435 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3436 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3437 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3438
3439 REG_WRITE(ah, AR_NEXT_DTIM,
3440 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3441 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3442
3443 REG_WRITE(ah, AR_SLEEP1,
3444 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3445 | AR_SLEEP1_ASSUME_DTIM);
3446
3447 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3448 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3449 else
3450 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3451
3452 REG_WRITE(ah, AR_SLEEP2,
3453 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3454
3455 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3456 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3457
3458 REG_SET_BIT(ah, AR_TIMER_MODE,
3459 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3460 AR_DTIM_TIMER_EN);
3461
3462 /* TSF Out of Range Threshold */
3463 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
3464 }
3465
3466 /*******************/
3467 /* HW Capabilities */
3468 /*******************/
3469
3470 void ath9k_hw_fill_cap_info(struct ath_hw *ah)
3471 {
3472 struct ath9k_hw_capabilities *pCap = &ah->caps;
3473 u16 capField = 0, eeval;
3474
3475 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
3476 ah->regulatory.current_rd = eeval;
3477
3478 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
3479 if (AR_SREV_9285_10_OR_LATER(ah))
3480 eeval |= AR9285_RDEXT_DEFAULT;
3481 ah->regulatory.current_rd_ext = eeval;
3482
3483 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
3484
3485 if (ah->opmode != NL80211_IFTYPE_AP &&
3486 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3487 if (ah->regulatory.current_rd == 0x64 ||
3488 ah->regulatory.current_rd == 0x65)
3489 ah->regulatory.current_rd += 5;
3490 else if (ah->regulatory.current_rd == 0x41)
3491 ah->regulatory.current_rd = 0x43;
3492 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
3493 "regdomain mapped to 0x%x\n", ah->regulatory.current_rd);
3494 }
3495
3496 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
3497 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3498
3499 if (eeval & AR5416_OPFLAGS_11A) {
3500 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3501 if (ah->config.ht_enable) {
3502 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3503 set_bit(ATH9K_MODE_11NA_HT20,
3504 pCap->wireless_modes);
3505 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3506 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3507 pCap->wireless_modes);
3508 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3509 pCap->wireless_modes);
3510 }
3511 }
3512 }
3513
3514 if (eeval & AR5416_OPFLAGS_11G) {
3515 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3516 if (ah->config.ht_enable) {
3517 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3518 set_bit(ATH9K_MODE_11NG_HT20,
3519 pCap->wireless_modes);
3520 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3521 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3522 pCap->wireless_modes);
3523 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3524 pCap->wireless_modes);
3525 }
3526 }
3527 }
3528
3529 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
3530 /*
3531 * For AR9271 we will temporarilly uses the rx chainmax as read from
3532 * the EEPROM.
3533 */
3534 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
3535 !(eeval & AR5416_OPFLAGS_11A) &&
3536 !(AR_SREV_9271(ah)))
3537 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
3538 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
3539 else
3540 /* Use rx_chainmask from EEPROM. */
3541 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
3542
3543 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
3544 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
3545
3546 pCap->low_2ghz_chan = 2312;
3547 pCap->high_2ghz_chan = 2732;
3548
3549 pCap->low_5ghz_chan = 4920;
3550 pCap->high_5ghz_chan = 6100;
3551
3552 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3553 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3554 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3555
3556 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3557 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3558 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3559
3560 if (ah->config.ht_enable)
3561 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3562 else
3563 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3564
3565 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3566 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3567 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3568 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3569
3570 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3571 pCap->total_queues =
3572 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3573 else
3574 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3575
3576 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3577 pCap->keycache_size =
3578 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3579 else
3580 pCap->keycache_size = AR_KEYTABLE_SIZE;
3581
3582 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3583 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3584
3585 if (AR_SREV_9285_10_OR_LATER(ah))
3586 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3587 else if (AR_SREV_9280_10_OR_LATER(ah))
3588 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3589 else
3590 pCap->num_gpio_pins = AR_NUM_GPIO;
3591
3592 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3593 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3594 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3595 } else {
3596 pCap->rts_aggr_limit = (8 * 1024);
3597 }
3598
3599 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3600
3601 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3602 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
3603 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
3604 ah->rfkill_gpio =
3605 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
3606 ah->rfkill_polarity =
3607 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
3608
3609 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3610 }
3611 #endif
3612
3613 if ((ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) ||
3614 (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) ||
3615 (ah->hw_version.macVersion == AR_SREV_VERSION_9160) ||
3616 (ah->hw_version.macVersion == AR_SREV_VERSION_9100) ||
3617 (ah->hw_version.macVersion == AR_SREV_VERSION_9280) ||
3618 (ah->hw_version.macVersion == AR_SREV_VERSION_9285))
3619 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3620 else
3621 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
3622
3623 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
3624 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3625 else
3626 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3627
3628 if (ah->regulatory.current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
3629 pCap->reg_cap =
3630 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3631 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3632 AR_EEPROM_EEREGCAP_EN_KK_U2 |
3633 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3634 } else {
3635 pCap->reg_cap =
3636 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3637 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3638 }
3639
3640 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3641
3642 pCap->num_antcfg_5ghz =
3643 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
3644 pCap->num_antcfg_2ghz =
3645 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3646
3647 if (AR_SREV_9280_10_OR_LATER(ah) && btcoex_enable) {
3648 pCap->hw_caps |= ATH9K_HW_CAP_BT_COEX;
3649 ah->btactive_gpio = 6;
3650 ah->wlanactive_gpio = 5;
3651 }
3652 }
3653
3654 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3655 u32 capability, u32 *result)
3656 {
3657 switch (type) {
3658 case ATH9K_CAP_CIPHER:
3659 switch (capability) {
3660 case ATH9K_CIPHER_AES_CCM:
3661 case ATH9K_CIPHER_AES_OCB:
3662 case ATH9K_CIPHER_TKIP:
3663 case ATH9K_CIPHER_WEP:
3664 case ATH9K_CIPHER_MIC:
3665 case ATH9K_CIPHER_CLR:
3666 return true;
3667 default:
3668 return false;
3669 }
3670 case ATH9K_CAP_TKIP_MIC:
3671 switch (capability) {
3672 case 0:
3673 return true;
3674 case 1:
3675 return (ah->sta_id1_defaults &
3676 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3677 false;
3678 }
3679 case ATH9K_CAP_TKIP_SPLIT:
3680 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
3681 false : true;
3682 case ATH9K_CAP_DIVERSITY:
3683 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3684 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3685 true : false;
3686 case ATH9K_CAP_MCAST_KEYSRCH:
3687 switch (capability) {
3688 case 0:
3689 return true;
3690 case 1:
3691 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3692 return false;
3693 } else {
3694 return (ah->sta_id1_defaults &
3695 AR_STA_ID1_MCAST_KSRCH) ? true :
3696 false;
3697 }
3698 }
3699 return false;
3700 case ATH9K_CAP_TXPOW:
3701 switch (capability) {
3702 case 0:
3703 return 0;
3704 case 1:
3705 *result = ah->regulatory.power_limit;
3706 return 0;
3707 case 2:
3708 *result = ah->regulatory.max_power_level;
3709 return 0;
3710 case 3:
3711 *result = ah->regulatory.tp_scale;
3712 return 0;
3713 }
3714 return false;
3715 case ATH9K_CAP_DS:
3716 return (AR_SREV_9280_20_OR_LATER(ah) &&
3717 (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
3718 ? false : true;
3719 default:
3720 return false;
3721 }
3722 }
3723
3724 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3725 u32 capability, u32 setting, int *status)
3726 {
3727 u32 v;
3728
3729 switch (type) {
3730 case ATH9K_CAP_TKIP_MIC:
3731 if (setting)
3732 ah->sta_id1_defaults |=
3733 AR_STA_ID1_CRPT_MIC_ENABLE;
3734 else
3735 ah->sta_id1_defaults &=
3736 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3737 return true;
3738 case ATH9K_CAP_DIVERSITY:
3739 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3740 if (setting)
3741 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3742 else
3743 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3744 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3745 return true;
3746 case ATH9K_CAP_MCAST_KEYSRCH:
3747 if (setting)
3748 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
3749 else
3750 ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3751 return true;
3752 default:
3753 return false;
3754 }
3755 }
3756
3757 /****************************/
3758 /* GPIO / RFKILL / Antennae */
3759 /****************************/
3760
3761 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
3762 u32 gpio, u32 type)
3763 {
3764 int addr;
3765 u32 gpio_shift, tmp;
3766
3767 if (gpio > 11)
3768 addr = AR_GPIO_OUTPUT_MUX3;
3769 else if (gpio > 5)
3770 addr = AR_GPIO_OUTPUT_MUX2;
3771 else
3772 addr = AR_GPIO_OUTPUT_MUX1;
3773
3774 gpio_shift = (gpio % 6) * 5;
3775
3776 if (AR_SREV_9280_20_OR_LATER(ah)
3777 || (addr != AR_GPIO_OUTPUT_MUX1)) {
3778 REG_RMW(ah, addr, (type << gpio_shift),
3779 (0x1f << gpio_shift));
3780 } else {
3781 tmp = REG_READ(ah, addr);
3782 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3783 tmp &= ~(0x1f << gpio_shift);
3784 tmp |= (type << gpio_shift);
3785 REG_WRITE(ah, addr, tmp);
3786 }
3787 }
3788
3789 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3790 {
3791 u32 gpio_shift;
3792
3793 ASSERT(gpio < ah->caps.num_gpio_pins);
3794
3795 gpio_shift = gpio << 1;
3796
3797 REG_RMW(ah,
3798 AR_GPIO_OE_OUT,
3799 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3800 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3801 }
3802
3803 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3804 {
3805 #define MS_REG_READ(x, y) \
3806 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3807
3808 if (gpio >= ah->caps.num_gpio_pins)
3809 return 0xffffffff;
3810
3811 if (AR_SREV_9287_10_OR_LATER(ah))
3812 return MS_REG_READ(AR9287, gpio) != 0;
3813 else if (AR_SREV_9285_10_OR_LATER(ah))
3814 return MS_REG_READ(AR9285, gpio) != 0;
3815 else if (AR_SREV_9280_10_OR_LATER(ah))
3816 return MS_REG_READ(AR928X, gpio) != 0;
3817 else
3818 return MS_REG_READ(AR, gpio) != 0;
3819 }
3820
3821 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
3822 u32 ah_signal_type)
3823 {
3824 u32 gpio_shift;
3825
3826 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3827
3828 gpio_shift = 2 * gpio;
3829
3830 REG_RMW(ah,
3831 AR_GPIO_OE_OUT,
3832 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3833 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3834 }
3835
3836 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
3837 {
3838 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3839 AR_GPIO_BIT(gpio));
3840 }
3841
3842 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
3843 {
3844 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3845 }
3846
3847 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
3848 {
3849 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3850 }
3851
3852 bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
3853 enum ath9k_ant_setting settings,
3854 struct ath9k_channel *chan,
3855 u8 *tx_chainmask,
3856 u8 *rx_chainmask,
3857 u8 *antenna_cfgd)
3858 {
3859 static u8 tx_chainmask_cfg, rx_chainmask_cfg;
3860
3861 if (AR_SREV_9280(ah)) {
3862 if (!tx_chainmask_cfg) {
3863
3864 tx_chainmask_cfg = *tx_chainmask;
3865 rx_chainmask_cfg = *rx_chainmask;
3866 }
3867
3868 switch (settings) {
3869 case ATH9K_ANT_FIXED_A:
3870 *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3871 *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3872 *antenna_cfgd = true;
3873 break;
3874 case ATH9K_ANT_FIXED_B:
3875 if (ah->caps.tx_chainmask >
3876 ATH9K_ANTENNA1_CHAINMASK) {
3877 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3878 }
3879 *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3880 *antenna_cfgd = true;
3881 break;
3882 case ATH9K_ANT_VARIABLE:
3883 *tx_chainmask = tx_chainmask_cfg;
3884 *rx_chainmask = rx_chainmask_cfg;
3885 *antenna_cfgd = true;
3886 break;
3887 default:
3888 break;
3889 }
3890 } else {
3891 ah->config.diversity_control = settings;
3892 }
3893
3894 return true;
3895 }
3896
3897 /*********************/
3898 /* General Operation */
3899 /*********************/
3900
3901 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
3902 {
3903 u32 bits = REG_READ(ah, AR_RX_FILTER);
3904 u32 phybits = REG_READ(ah, AR_PHY_ERR);
3905
3906 if (phybits & AR_PHY_ERR_RADAR)
3907 bits |= ATH9K_RX_FILTER_PHYRADAR;
3908 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3909 bits |= ATH9K_RX_FILTER_PHYERR;
3910
3911 return bits;
3912 }
3913
3914 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
3915 {
3916 u32 phybits;
3917
3918 REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
3919 phybits = 0;
3920 if (bits & ATH9K_RX_FILTER_PHYRADAR)
3921 phybits |= AR_PHY_ERR_RADAR;
3922 if (bits & ATH9K_RX_FILTER_PHYERR)
3923 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3924 REG_WRITE(ah, AR_PHY_ERR, phybits);
3925
3926 if (phybits)
3927 REG_WRITE(ah, AR_RXCFG,
3928 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3929 else
3930 REG_WRITE(ah, AR_RXCFG,
3931 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3932 }
3933
3934 bool ath9k_hw_phy_disable(struct ath_hw *ah)
3935 {
3936 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
3937 }
3938
3939 bool ath9k_hw_disable(struct ath_hw *ah)
3940 {
3941 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3942 return false;
3943
3944 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
3945 }
3946
3947 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
3948 {
3949 struct ath9k_channel *chan = ah->curchan;
3950 struct ieee80211_channel *channel = chan->chan;
3951
3952 ah->regulatory.power_limit = min(limit, (u32) MAX_RATE_POWER);
3953
3954 ah->eep_ops->set_txpower(ah, chan,
3955 ath9k_regd_get_ctl(&ah->regulatory, chan),
3956 channel->max_antenna_gain * 2,
3957 channel->max_power * 2,
3958 min((u32) MAX_RATE_POWER,
3959 (u32) ah->regulatory.power_limit));
3960 }
3961
3962 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
3963 {
3964 memcpy(ah->macaddr, mac, ETH_ALEN);
3965 }
3966
3967 void ath9k_hw_setopmode(struct ath_hw *ah)
3968 {
3969 ath9k_hw_set_operating_mode(ah, ah->opmode);
3970 }
3971
3972 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
3973 {
3974 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3975 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3976 }
3977
3978 void ath9k_hw_setbssidmask(struct ath_softc *sc)
3979 {
3980 REG_WRITE(sc->sc_ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
3981 REG_WRITE(sc->sc_ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
3982 }
3983
3984 void ath9k_hw_write_associd(struct ath_softc *sc)
3985 {
3986 REG_WRITE(sc->sc_ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
3987 REG_WRITE(sc->sc_ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
3988 ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
3989 }
3990
3991 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
3992 {
3993 u64 tsf;
3994
3995 tsf = REG_READ(ah, AR_TSF_U32);
3996 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3997
3998 return tsf;
3999 }
4000
4001 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
4002 {
4003 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
4004 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
4005 }
4006
4007 void ath9k_hw_reset_tsf(struct ath_hw *ah)
4008 {
4009 ath9k_ps_wakeup(ah->ah_sc);
4010 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
4011 AH_TSF_WRITE_TIMEOUT))
4012 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
4013 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
4014
4015 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
4016 ath9k_ps_restore(ah->ah_sc);
4017 }
4018
4019 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
4020 {
4021 if (setting)
4022 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
4023 else
4024 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
4025 }
4026
4027 bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
4028 {
4029 if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
4030 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us);
4031 ah->slottime = (u32) -1;
4032 return false;
4033 } else {
4034 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
4035 ah->slottime = us;
4036 return true;
4037 }
4038 }
4039
4040 void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode)
4041 {
4042 u32 macmode;
4043
4044 if (mode == ATH9K_HT_MACMODE_2040 &&
4045 !ah->config.cwm_ignore_extcca)
4046 macmode = AR_2040_JOINED_RX_CLEAR;
4047 else
4048 macmode = 0;
4049
4050 REG_WRITE(ah, AR_2040_MODE, macmode);
4051 }
4052
4053 /***************************/
4054 /* Bluetooth Coexistence */
4055 /***************************/
4056
4057 void ath9k_hw_btcoex_enable(struct ath_hw *ah)
4058 {
4059 /* connect bt_active to baseband */
4060 REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL,
4061 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
4062 AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));
4063
4064 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
4065 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
4066
4067 /* Set input mux for bt_active to gpio pin */
4068 REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
4069 AR_GPIO_INPUT_MUX1_BT_ACTIVE,
4070 ah->btactive_gpio);
4071
4072 /* Configure the desired gpio port for input */
4073 ath9k_hw_cfg_gpio_input(ah, ah->btactive_gpio);
4074
4075 /* Configure the desired GPIO port for TX_FRAME output */
4076 ath9k_hw_cfg_output(ah, ah->wlanactive_gpio,
4077 AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);
4078 }
Linux 2.6 libata-dev (mirror)