drivers/pci/msi.h

   1 /*
   2  * Copyright (C) 2003-2004 Intel
   3  * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
   4  */
   5
   6 #ifndef MSI_H
   7 #define MSI_H
   8
   9 #include <asm/msi.h>
  10
  11 /*
  12  * MSI-X Address Register
  13  */
  14 #define PCI_MSIX_FLAGS_QSIZE            0x7FF
  15 #define PCI_MSIX_FLAGS_ENABLE           (1 << 15)
  16 #define PCI_MSIX_FLAGS_BIRMASK          (7 << 0)
  17 #define PCI_MSIX_FLAGS_BITMASK          (1 << 0)
  18
  19 #define PCI_MSIX_ENTRY_SIZE                     16
  20 #define  PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET       0
  21 #define  PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET       4
  22 #define  PCI_MSIX_ENTRY_DATA_OFFSET             8
  23 #define  PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET      12
  24
  25 #define msi_control_reg(base)           (base + PCI_MSI_FLAGS)
  26 #define msi_lower_address_reg(base)     (base + PCI_MSI_ADDRESS_LO)
  27 #define msi_upper_address_reg(base)     (base + PCI_MSI_ADDRESS_HI)
  28 #define msi_data_reg(base, is64bit)     \
  29         ( (is64bit == 1) ? base+PCI_MSI_DATA_64 : base+PCI_MSI_DATA_32 )
  30 #define msi_mask_bits_reg(base, is64bit) \
  31         ( (is64bit == 1) ? base+PCI_MSI_MASK_BIT : base+PCI_MSI_MASK_BIT-4)
  32 #define msi_disable(control)            control &= ~PCI_MSI_FLAGS_ENABLE
  33 #define multi_msi_capable(control) \
  34         (1 << ((control & PCI_MSI_FLAGS_QMASK) >> 1))
  35 #define multi_msi_enable(control, num) \
  36         control |= (((num >> 1) << 4) & PCI_MSI_FLAGS_QSIZE);
  37 #define is_64bit_address(control)       (!!(control & PCI_MSI_FLAGS_64BIT))
  38 #define is_mask_bit_support(control)    (!!(control & PCI_MSI_FLAGS_MASKBIT))
  39 #define msi_enable(control, num) multi_msi_enable(control, num); \
  40         control |= PCI_MSI_FLAGS_ENABLE
  41
  42 #define msix_table_offset_reg(base)     (base + 0x04)
  43 #define msix_pba_offset_reg(base)       (base + 0x08)
  44 #define msix_enable(control)            control |= PCI_MSIX_FLAGS_ENABLE
  45 #define msix_disable(control)           control &= ~PCI_MSIX_FLAGS_ENABLE
  46 #define msix_table_size(control)        ((control & PCI_MSIX_FLAGS_QSIZE)+1)
  47 #define multi_msix_capable              msix_table_size
  48 #define msix_unmask(address)            (address & ~PCI_MSIX_FLAGS_BITMASK)
  49 #define msix_mask(address)              (address | PCI_MSIX_FLAGS_BITMASK)
  50 #define msix_is_pending(address)        (address & PCI_MSIX_FLAGS_PENDMASK)
  51
  52 struct msi_desc {
  53         struct {
  54                 __u8    type    : 5;    /* {0: unused, 5h:MSI, 11h:MSI-X} */
  55                 __u8    maskbit : 1;    /* mask-pending bit supported ?   */
  56                 __u8    state   : 1;    /* {0: free, 1: busy}             */
  57                 __u8    is_64   : 1;    /* Address size: 0=32bit 1=64bit  */
  58                 __u8    pos;            /* Location of the msi capability */
  59                 __u16   entry_nr;       /* specific enabled entry         */
  60                 unsigned default_irq;   /* default pre-assigned irq       */
  61         }msi_attrib;
  62
  63         struct {
  64                 __u16   head;
  65                 __u16   tail;
  66         }link;
  67
  68         void __iomem *mask_base;
  69         struct pci_dev *dev;
  70
  71 #ifdef CONFIG_PM
  72         /* PM save area for MSIX address/data */
  73         struct msi_msg msg_save;
  74 #endif
  75 };
  76
  77 #endif /* MSI_H */