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wl18xx: read FW pc on recovery
[linux-2.6/libata-dev.git] / drivers / net / wireless / ti / wl18xx / main.c
blob82403e356eb8ce09ad658bdade0f62f636168ee7
1 /*
2 * This file is part of wl18xx
3 *
4 * Copyright (C) 2011 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
18 * 02110-1301 USA
19 *
20 */
21
22 #include <linux/module.h>
23 #include <linux/platform_device.h>
24 #include <linux/ip.h>
25
26 #include "../wlcore/wlcore.h"
27 #include "../wlcore/debug.h"
28 #include "../wlcore/io.h"
29 #include "../wlcore/acx.h"
30 #include "../wlcore/tx.h"
31 #include "../wlcore/rx.h"
32 #include "../wlcore/io.h"
33 #include "../wlcore/boot.h"
34
35 #include "reg.h"
36 #include "conf.h"
37 #include "acx.h"
38 #include "tx.h"
39 #include "wl18xx.h"
40
41
42 #define WL18XX_RX_CHECKSUM_MASK 0x40
43
44 static char *ht_mode_param;
45 static char *board_type_param;
46
47 static const u32 wl18xx_board_type_to_scrpad2[NUM_BOARD_TYPES] = {
48 [BOARD_TYPE_FPGA_18XX] = SCR_PAD2_BOARD_TYPE_FPGA,
49 [BOARD_TYPE_HDK_18XX] = SCR_PAD2_BOARD_TYPE_HDK,
50 [BOARD_TYPE_DVP_EVB_18XX] = SCR_PAD2_BOARD_TYPE_DVP_EVB,
51 };
52
53 static const u8 wl18xx_rate_to_idx_2ghz[] = {
54 /* MCS rates are used only with 11n */
55 15, /* WL18XX_CONF_HW_RXTX_RATE_MCS15 */
56 14, /* WL18XX_CONF_HW_RXTX_RATE_MCS14 */
57 13, /* WL18XX_CONF_HW_RXTX_RATE_MCS13 */
58 12, /* WL18XX_CONF_HW_RXTX_RATE_MCS12 */
59 11, /* WL18XX_CONF_HW_RXTX_RATE_MCS11 */
60 10, /* WL18XX_CONF_HW_RXTX_RATE_MCS10 */
61 9, /* WL18XX_CONF_HW_RXTX_RATE_MCS9 */
62 8, /* WL18XX_CONF_HW_RXTX_RATE_MCS8 */
63 7, /* WL18XX_CONF_HW_RXTX_RATE_MCS7 */
64 6, /* WL18XX_CONF_HW_RXTX_RATE_MCS6 */
65 5, /* WL18XX_CONF_HW_RXTX_RATE_MCS5 */
66 4, /* WL18XX_CONF_HW_RXTX_RATE_MCS4 */
67 3, /* WL18XX_CONF_HW_RXTX_RATE_MCS3 */
68 2, /* WL18XX_CONF_HW_RXTX_RATE_MCS2 */
69 1, /* WL18XX_CONF_HW_RXTX_RATE_MCS1 */
70 0, /* WL18XX_CONF_HW_RXTX_RATE_MCS0 */
71
72 11, /* WL18XX_CONF_HW_RXTX_RATE_54 */
73 10, /* WL18XX_CONF_HW_RXTX_RATE_48 */
74 9, /* WL18XX_CONF_HW_RXTX_RATE_36 */
75 8, /* WL18XX_CONF_HW_RXTX_RATE_24 */
76
77 /* TI-specific rate */
78 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_22 */
79
80 7, /* WL18XX_CONF_HW_RXTX_RATE_18 */
81 6, /* WL18XX_CONF_HW_RXTX_RATE_12 */
82 3, /* WL18XX_CONF_HW_RXTX_RATE_11 */
83 5, /* WL18XX_CONF_HW_RXTX_RATE_9 */
84 4, /* WL18XX_CONF_HW_RXTX_RATE_6 */
85 2, /* WL18XX_CONF_HW_RXTX_RATE_5_5 */
86 1, /* WL18XX_CONF_HW_RXTX_RATE_2 */
87 0 /* WL18XX_CONF_HW_RXTX_RATE_1 */
88 };
89
90 static const u8 wl18xx_rate_to_idx_5ghz[] = {
91 /* MCS rates are used only with 11n */
92 15, /* WL18XX_CONF_HW_RXTX_RATE_MCS15 */
93 14, /* WL18XX_CONF_HW_RXTX_RATE_MCS14 */
94 13, /* WL18XX_CONF_HW_RXTX_RATE_MCS13 */
95 12, /* WL18XX_CONF_HW_RXTX_RATE_MCS12 */
96 11, /* WL18XX_CONF_HW_RXTX_RATE_MCS11 */
97 10, /* WL18XX_CONF_HW_RXTX_RATE_MCS10 */
98 9, /* WL18XX_CONF_HW_RXTX_RATE_MCS9 */
99 8, /* WL18XX_CONF_HW_RXTX_RATE_MCS8 */
100 7, /* WL18XX_CONF_HW_RXTX_RATE_MCS7 */
101 6, /* WL18XX_CONF_HW_RXTX_RATE_MCS6 */
102 5, /* WL18XX_CONF_HW_RXTX_RATE_MCS5 */
103 4, /* WL18XX_CONF_HW_RXTX_RATE_MCS4 */
104 3, /* WL18XX_CONF_HW_RXTX_RATE_MCS3 */
105 2, /* WL18XX_CONF_HW_RXTX_RATE_MCS2 */
106 1, /* WL18XX_CONF_HW_RXTX_RATE_MCS1 */
107 0, /* WL18XX_CONF_HW_RXTX_RATE_MCS0 */
108
109 7, /* WL18XX_CONF_HW_RXTX_RATE_54 */
110 6, /* WL18XX_CONF_HW_RXTX_RATE_48 */
111 5, /* WL18XX_CONF_HW_RXTX_RATE_36 */
112 4, /* WL18XX_CONF_HW_RXTX_RATE_24 */
113
114 /* TI-specific rate */
115 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_22 */
116
117 3, /* WL18XX_CONF_HW_RXTX_RATE_18 */
118 2, /* WL18XX_CONF_HW_RXTX_RATE_12 */
119 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_11 */
120 1, /* WL18XX_CONF_HW_RXTX_RATE_9 */
121 0, /* WL18XX_CONF_HW_RXTX_RATE_6 */
122 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_5_5 */
123 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_2 */
124 CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_1 */
125 };
126
127 static const u8 *wl18xx_band_rate_to_idx[] = {
128 [IEEE80211_BAND_2GHZ] = wl18xx_rate_to_idx_2ghz,
129 [IEEE80211_BAND_5GHZ] = wl18xx_rate_to_idx_5ghz
130 };
131
132 enum wl18xx_hw_rates {
133 WL18XX_CONF_HW_RXTX_RATE_MCS15 = 0,
134 WL18XX_CONF_HW_RXTX_RATE_MCS14,
135 WL18XX_CONF_HW_RXTX_RATE_MCS13,
136 WL18XX_CONF_HW_RXTX_RATE_MCS12,
137 WL18XX_CONF_HW_RXTX_RATE_MCS11,
138 WL18XX_CONF_HW_RXTX_RATE_MCS10,
139 WL18XX_CONF_HW_RXTX_RATE_MCS9,
140 WL18XX_CONF_HW_RXTX_RATE_MCS8,
141 WL18XX_CONF_HW_RXTX_RATE_MCS7,
142 WL18XX_CONF_HW_RXTX_RATE_MCS6,
143 WL18XX_CONF_HW_RXTX_RATE_MCS5,
144 WL18XX_CONF_HW_RXTX_RATE_MCS4,
145 WL18XX_CONF_HW_RXTX_RATE_MCS3,
146 WL18XX_CONF_HW_RXTX_RATE_MCS2,
147 WL18XX_CONF_HW_RXTX_RATE_MCS1,
148 WL18XX_CONF_HW_RXTX_RATE_MCS0,
149 WL18XX_CONF_HW_RXTX_RATE_54,
150 WL18XX_CONF_HW_RXTX_RATE_48,
151 WL18XX_CONF_HW_RXTX_RATE_36,
152 WL18XX_CONF_HW_RXTX_RATE_24,
153 WL18XX_CONF_HW_RXTX_RATE_22,
154 WL18XX_CONF_HW_RXTX_RATE_18,
155 WL18XX_CONF_HW_RXTX_RATE_12,
156 WL18XX_CONF_HW_RXTX_RATE_11,
157 WL18XX_CONF_HW_RXTX_RATE_9,
158 WL18XX_CONF_HW_RXTX_RATE_6,
159 WL18XX_CONF_HW_RXTX_RATE_5_5,
160 WL18XX_CONF_HW_RXTX_RATE_2,
161 WL18XX_CONF_HW_RXTX_RATE_1,
162 WL18XX_CONF_HW_RXTX_RATE_MAX,
163 };
164
165 static struct wlcore_conf wl18xx_conf = {
166 .sg = {
167 .params = {
168 [CONF_SG_ACL_BT_MASTER_MIN_BR] = 10,
169 [CONF_SG_ACL_BT_MASTER_MAX_BR] = 180,
170 [CONF_SG_ACL_BT_SLAVE_MIN_BR] = 10,
171 [CONF_SG_ACL_BT_SLAVE_MAX_BR] = 180,
172 [CONF_SG_ACL_BT_MASTER_MIN_EDR] = 10,
173 [CONF_SG_ACL_BT_MASTER_MAX_EDR] = 80,
174 [CONF_SG_ACL_BT_SLAVE_MIN_EDR] = 10,
175 [CONF_SG_ACL_BT_SLAVE_MAX_EDR] = 80,
176 [CONF_SG_ACL_WLAN_PS_MASTER_BR] = 8,
177 [CONF_SG_ACL_WLAN_PS_SLAVE_BR] = 8,
178 [CONF_SG_ACL_WLAN_PS_MASTER_EDR] = 20,
179 [CONF_SG_ACL_WLAN_PS_SLAVE_EDR] = 20,
180 [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MIN_BR] = 20,
181 [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MAX_BR] = 35,
182 [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MIN_BR] = 16,
183 [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MAX_BR] = 35,
184 [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MIN_EDR] = 32,
185 [CONF_SG_ACL_WLAN_ACTIVE_MASTER_MAX_EDR] = 50,
186 [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MIN_EDR] = 28,
187 [CONF_SG_ACL_WLAN_ACTIVE_SLAVE_MAX_EDR] = 50,
188 [CONF_SG_ACL_ACTIVE_SCAN_WLAN_BR] = 10,
189 [CONF_SG_ACL_ACTIVE_SCAN_WLAN_EDR] = 20,
190 [CONF_SG_ACL_PASSIVE_SCAN_BT_BR] = 75,
191 [CONF_SG_ACL_PASSIVE_SCAN_WLAN_BR] = 15,
192 [CONF_SG_ACL_PASSIVE_SCAN_BT_EDR] = 27,
193 [CONF_SG_ACL_PASSIVE_SCAN_WLAN_EDR] = 17,
194 /* active scan params */
195 [CONF_SG_AUTO_SCAN_PROBE_REQ] = 170,
196 [CONF_SG_ACTIVE_SCAN_DURATION_FACTOR_HV3] = 50,
197 [CONF_SG_ACTIVE_SCAN_DURATION_FACTOR_A2DP] = 100,
198 /* passive scan params */
199 [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_A2DP_BR] = 800,
200 [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_A2DP_EDR] = 200,
201 [CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_HV3] = 200,
202 /* passive scan in dual antenna params */
203 [CONF_SG_CONSECUTIVE_HV3_IN_PASSIVE_SCAN] = 0,
204 [CONF_SG_BCN_HV3_COLLISION_THRESH_IN_PASSIVE_SCAN] = 0,
205 [CONF_SG_TX_RX_PROTECTION_BWIDTH_IN_PASSIVE_SCAN] = 0,
206 /* general params */
207 [CONF_SG_STA_FORCE_PS_IN_BT_SCO] = 1,
208 [CONF_SG_ANTENNA_CONFIGURATION] = 0,
209 [CONF_SG_BEACON_MISS_PERCENT] = 60,
210 [CONF_SG_DHCP_TIME] = 5000,
211 [CONF_SG_RXT] = 1200,
212 [CONF_SG_TXT] = 1000,
213 [CONF_SG_ADAPTIVE_RXT_TXT] = 1,
214 [CONF_SG_GENERAL_USAGE_BIT_MAP] = 3,
215 [CONF_SG_HV3_MAX_SERVED] = 6,
216 [CONF_SG_PS_POLL_TIMEOUT] = 10,
217 [CONF_SG_UPSD_TIMEOUT] = 10,
218 [CONF_SG_CONSECUTIVE_CTS_THRESHOLD] = 2,
219 [CONF_SG_STA_RX_WINDOW_AFTER_DTIM] = 5,
220 [CONF_SG_STA_CONNECTION_PROTECTION_TIME] = 30,
221 /* AP params */
222 [CONF_AP_BEACON_MISS_TX] = 3,
223 [CONF_AP_RX_WINDOW_AFTER_BEACON] = 10,
224 [CONF_AP_BEACON_WINDOW_INTERVAL] = 2,
225 [CONF_AP_CONNECTION_PROTECTION_TIME] = 0,
226 [CONF_AP_BT_ACL_VAL_BT_SERVE_TIME] = 25,
227 [CONF_AP_BT_ACL_VAL_WL_SERVE_TIME] = 25,
228 /* CTS Diluting params */
229 [CONF_SG_CTS_DILUTED_BAD_RX_PACKETS_TH] = 0,
230 [CONF_SG_CTS_CHOP_IN_DUAL_ANT_SCO_MASTER] = 0,
231 },
232 .state = CONF_SG_PROTECTIVE,
233 },
234 .rx = {
235 .rx_msdu_life_time = 512000,
236 .packet_detection_threshold = 0,
237 .ps_poll_timeout = 15,
238 .upsd_timeout = 15,
239 .rts_threshold = IEEE80211_MAX_RTS_THRESHOLD,
240 .rx_cca_threshold = 0,
241 .irq_blk_threshold = 0xFFFF,
242 .irq_pkt_threshold = 0,
243 .irq_timeout = 600,
244 .queue_type = CONF_RX_QUEUE_TYPE_LOW_PRIORITY,
245 },
246 .tx = {
247 .tx_energy_detection = 0,
248 .sta_rc_conf = {
249 .enabled_rates = 0,
250 .short_retry_limit = 10,
251 .long_retry_limit = 10,
252 .aflags = 0,
253 },
254 .ac_conf_count = 4,
255 .ac_conf = {
256 [CONF_TX_AC_BE] = {
257 .ac = CONF_TX_AC_BE,
258 .cw_min = 15,
259 .cw_max = 63,
260 .aifsn = 3,
261 .tx_op_limit = 0,
262 },
263 [CONF_TX_AC_BK] = {
264 .ac = CONF_TX_AC_BK,
265 .cw_min = 15,
266 .cw_max = 63,
267 .aifsn = 7,
268 .tx_op_limit = 0,
269 },
270 [CONF_TX_AC_VI] = {
271 .ac = CONF_TX_AC_VI,
272 .cw_min = 15,
273 .cw_max = 63,
274 .aifsn = CONF_TX_AIFS_PIFS,
275 .tx_op_limit = 3008,
276 },
277 [CONF_TX_AC_VO] = {
278 .ac = CONF_TX_AC_VO,
279 .cw_min = 15,
280 .cw_max = 63,
281 .aifsn = CONF_TX_AIFS_PIFS,
282 .tx_op_limit = 1504,
283 },
284 },
285 .max_tx_retries = 100,
286 .ap_aging_period = 300,
287 .tid_conf_count = 4,
288 .tid_conf = {
289 [CONF_TX_AC_BE] = {
290 .queue_id = CONF_TX_AC_BE,
291 .channel_type = CONF_CHANNEL_TYPE_EDCF,
292 .tsid = CONF_TX_AC_BE,
293 .ps_scheme = CONF_PS_SCHEME_LEGACY,
294 .ack_policy = CONF_ACK_POLICY_LEGACY,
295 .apsd_conf = {0, 0},
296 },
297 [CONF_TX_AC_BK] = {
298 .queue_id = CONF_TX_AC_BK,
299 .channel_type = CONF_CHANNEL_TYPE_EDCF,
300 .tsid = CONF_TX_AC_BK,
301 .ps_scheme = CONF_PS_SCHEME_LEGACY,
302 .ack_policy = CONF_ACK_POLICY_LEGACY,
303 .apsd_conf = {0, 0},
304 },
305 [CONF_TX_AC_VI] = {
306 .queue_id = CONF_TX_AC_VI,
307 .channel_type = CONF_CHANNEL_TYPE_EDCF,
308 .tsid = CONF_TX_AC_VI,
309 .ps_scheme = CONF_PS_SCHEME_LEGACY,
310 .ack_policy = CONF_ACK_POLICY_LEGACY,
311 .apsd_conf = {0, 0},
312 },
313 [CONF_TX_AC_VO] = {
314 .queue_id = CONF_TX_AC_VO,
315 .channel_type = CONF_CHANNEL_TYPE_EDCF,
316 .tsid = CONF_TX_AC_VO,
317 .ps_scheme = CONF_PS_SCHEME_LEGACY,
318 .ack_policy = CONF_ACK_POLICY_LEGACY,
319 .apsd_conf = {0, 0},
320 },
321 },
322 .frag_threshold = IEEE80211_MAX_FRAG_THRESHOLD,
323 .tx_compl_timeout = 350,
324 .tx_compl_threshold = 10,
325 .basic_rate = CONF_HW_BIT_RATE_1MBPS,
326 .basic_rate_5 = CONF_HW_BIT_RATE_6MBPS,
327 .tmpl_short_retry_limit = 10,
328 .tmpl_long_retry_limit = 10,
329 .tx_watchdog_timeout = 5000,
330 },
331 .conn = {
332 .wake_up_event = CONF_WAKE_UP_EVENT_DTIM,
333 .listen_interval = 1,
334 .suspend_wake_up_event = CONF_WAKE_UP_EVENT_N_DTIM,
335 .suspend_listen_interval = 3,
336 .bcn_filt_mode = CONF_BCN_FILT_MODE_ENABLED,
337 .bcn_filt_ie_count = 2,
338 .bcn_filt_ie = {
339 [0] = {
340 .ie = WLAN_EID_CHANNEL_SWITCH,
341 .rule = CONF_BCN_RULE_PASS_ON_APPEARANCE,
342 },
343 [1] = {
344 .ie = WLAN_EID_HT_OPERATION,
345 .rule = CONF_BCN_RULE_PASS_ON_CHANGE,
346 },
347 },
348 .synch_fail_thold = 10,
349 .bss_lose_timeout = 100,
350 .beacon_rx_timeout = 10000,
351 .broadcast_timeout = 20000,
352 .rx_broadcast_in_ps = 1,
353 .ps_poll_threshold = 10,
354 .bet_enable = CONF_BET_MODE_ENABLE,
355 .bet_max_consecutive = 50,
356 .psm_entry_retries = 8,
357 .psm_exit_retries = 16,
358 .psm_entry_nullfunc_retries = 3,
359 .dynamic_ps_timeout = 40,
360 .forced_ps = false,
361 .keep_alive_interval = 55000,
362 .max_listen_interval = 20,
363 },
364 .itrim = {
365 .enable = false,
366 .timeout = 50000,
367 },
368 .pm_config = {
369 .host_clk_settling_time = 5000,
370 .host_fast_wakeup_support = false
371 },
372 .roam_trigger = {
373 .trigger_pacing = 1,
374 .avg_weight_rssi_beacon = 20,
375 .avg_weight_rssi_data = 10,
376 .avg_weight_snr_beacon = 20,
377 .avg_weight_snr_data = 10,
378 },
379 .scan = {
380 .min_dwell_time_active = 7500,
381 .max_dwell_time_active = 30000,
382 .min_dwell_time_passive = 100000,
383 .max_dwell_time_passive = 100000,
384 .num_probe_reqs = 2,
385 .split_scan_timeout = 50000,
386 },
387 .sched_scan = {
388 /*
389 * Values are in TU/1000 but since sched scan FW command
390 * params are in TUs rounding up may occur.
391 */
392 .base_dwell_time = 7500,
393 .max_dwell_time_delta = 22500,
394 /* based on 250bits per probe @1Mbps */
395 .dwell_time_delta_per_probe = 2000,
396 /* based on 250bits per probe @6Mbps (plus a bit more) */
397 .dwell_time_delta_per_probe_5 = 350,
398 .dwell_time_passive = 100000,
399 .dwell_time_dfs = 150000,
400 .num_probe_reqs = 2,
401 .rssi_threshold = -90,
402 .snr_threshold = 0,
403 },
404 .ht = {
405 .rx_ba_win_size = 10,
406 .tx_ba_win_size = 10,
407 .inactivity_timeout = 10000,
408 .tx_ba_tid_bitmap = CONF_TX_BA_ENABLED_TID_BITMAP,
409 },
410 .mem = {
411 .num_stations = 1,
412 .ssid_profiles = 1,
413 .rx_block_num = 40,
414 .tx_min_block_num = 40,
415 .dynamic_memory = 1,
416 .min_req_tx_blocks = 45,
417 .min_req_rx_blocks = 22,
418 .tx_min = 27,
419 },
420 .fm_coex = {
421 .enable = true,
422 .swallow_period = 5,
423 .n_divider_fref_set_1 = 0xff, /* default */
424 .n_divider_fref_set_2 = 12,
425 .m_divider_fref_set_1 = 148,
426 .m_divider_fref_set_2 = 0xffff, /* default */
427 .coex_pll_stabilization_time = 0xffffffff, /* default */
428 .ldo_stabilization_time = 0xffff, /* default */
429 .fm_disturbed_band_margin = 0xff, /* default */
430 .swallow_clk_diff = 0xff, /* default */
431 },
432 .rx_streaming = {
433 .duration = 150,
434 .queues = 0x1,
435 .interval = 20,
436 .always = 0,
437 },
438 .fwlog = {
439 .mode = WL12XX_FWLOG_ON_DEMAND,
440 .mem_blocks = 2,
441 .severity = 0,
442 .timestamp = WL12XX_FWLOG_TIMESTAMP_DISABLED,
443 .output = WL12XX_FWLOG_OUTPUT_HOST,
444 .threshold = 0,
445 },
446 .rate = {
447 .rate_retry_score = 32000,
448 .per_add = 8192,
449 .per_th1 = 2048,
450 .per_th2 = 4096,
451 .max_per = 8100,
452 .inverse_curiosity_factor = 5,
453 .tx_fail_low_th = 4,
454 .tx_fail_high_th = 10,
455 .per_alpha_shift = 4,
456 .per_add_shift = 13,
457 .per_beta1_shift = 10,
458 .per_beta2_shift = 8,
459 .rate_check_up = 2,
460 .rate_check_down = 12,
461 .rate_retry_policy = {
462 0x00, 0x00, 0x00, 0x00, 0x00,
463 0x00, 0x00, 0x00, 0x00, 0x00,
464 0x00, 0x00, 0x00,
465 },
466 },
467 .hangover = {
468 .recover_time = 0,
469 .hangover_period = 20,
470 .dynamic_mode = 1,
471 .early_termination_mode = 1,
472 .max_period = 20,
473 .min_period = 1,
474 .increase_delta = 1,
475 .decrease_delta = 2,
476 .quiet_time = 4,
477 .increase_time = 1,
478 .window_size = 16,
479 },
480 };
481
482 static struct wl18xx_priv_conf wl18xx_default_priv_conf = {
483 .phy = {
484 .phy_standalone = 0x00,
485 .primary_clock_setting_time = 0x05,
486 .clock_valid_on_wake_up = 0x00,
487 .secondary_clock_setting_time = 0x05,
488 .rdl = 0x01,
489 .auto_detect = 0x00,
490 .dedicated_fem = FEM_NONE,
491 .low_band_component = COMPONENT_2_WAY_SWITCH,
492 .low_band_component_type = 0x05,
493 .high_band_component = COMPONENT_2_WAY_SWITCH,
494 .high_band_component_type = 0x09,
495 .number_of_assembled_ant2_4 = 0x01,
496 .number_of_assembled_ant5 = 0x01,
497 .external_pa_dc2dc = 0x00,
498 .tcxo_ldo_voltage = 0x00,
499 .xtal_itrim_val = 0x04,
500 .srf_state = 0x00,
501 .io_configuration = 0x01,
502 .sdio_configuration = 0x00,
503 .settings = 0x00,
504 .enable_clpc = 0x00,
505 .enable_tx_low_pwr_on_siso_rdl = 0x00,
506 .rx_profile = 0x00,
507 },
508 };
509
510 static const struct wlcore_partition_set wl18xx_ptable[PART_TABLE_LEN] = {
511 [PART_TOP_PRCM_ELP_SOC] = {
512 .mem = { .start = 0x00A02000, .size = 0x00010000 },
513 .reg = { .start = 0x00807000, .size = 0x00005000 },
514 .mem2 = { .start = 0x00800000, .size = 0x0000B000 },
515 .mem3 = { .start = 0x00000000, .size = 0x00000000 },
516 },
517 [PART_DOWN] = {
518 .mem = { .start = 0x00000000, .size = 0x00014000 },
519 .reg = { .start = 0x00810000, .size = 0x0000BFFF },
520 .mem2 = { .start = 0x00000000, .size = 0x00000000 },
521 .mem3 = { .start = 0x00000000, .size = 0x00000000 },
522 },
523 [PART_BOOT] = {
524 .mem = { .start = 0x00700000, .size = 0x0000030c },
525 .reg = { .start = 0x00802000, .size = 0x00014578 },
526 .mem2 = { .start = 0x00B00404, .size = 0x00001000 },
527 .mem3 = { .start = 0x00C00000, .size = 0x00000400 },
528 },
529 [PART_WORK] = {
530 .mem = { .start = 0x00800000, .size = 0x000050FC },
531 .reg = { .start = 0x00B00404, .size = 0x00001000 },
532 .mem2 = { .start = 0x00C00000, .size = 0x00000400 },
533 .mem3 = { .start = 0x00000000, .size = 0x00000000 },
534 },
535 [PART_PHY_INIT] = {
536 /* TODO: use the phy_conf struct size here */
537 .mem = { .start = 0x80926000, .size = 252 },
538 .reg = { .start = 0x00000000, .size = 0x00000000 },
539 .mem2 = { .start = 0x00000000, .size = 0x00000000 },
540 .mem3 = { .start = 0x00000000, .size = 0x00000000 },
541 },
542 };
543
544 static const int wl18xx_rtable[REG_TABLE_LEN] = {
545 [REG_ECPU_CONTROL] = WL18XX_REG_ECPU_CONTROL,
546 [REG_INTERRUPT_NO_CLEAR] = WL18XX_REG_INTERRUPT_NO_CLEAR,
547 [REG_INTERRUPT_ACK] = WL18XX_REG_INTERRUPT_ACK,
548 [REG_COMMAND_MAILBOX_PTR] = WL18XX_REG_COMMAND_MAILBOX_PTR,
549 [REG_EVENT_MAILBOX_PTR] = WL18XX_REG_EVENT_MAILBOX_PTR,
550 [REG_INTERRUPT_TRIG] = WL18XX_REG_INTERRUPT_TRIG_H,
551 [REG_INTERRUPT_MASK] = WL18XX_REG_INTERRUPT_MASK,
552 [REG_PC_ON_RECOVERY] = WL18XX_SCR_PAD4,
553 [REG_CHIP_ID_B] = WL18XX_REG_CHIP_ID_B,
554 [REG_CMD_MBOX_ADDRESS] = WL18XX_CMD_MBOX_ADDRESS,
555
556 /* data access memory addresses, used with partition translation */
557 [REG_SLV_MEM_DATA] = WL18XX_SLV_MEM_DATA,
558 [REG_SLV_REG_DATA] = WL18XX_SLV_REG_DATA,
559
560 /* raw data access memory addresses */
561 [REG_RAW_FW_STATUS_ADDR] = WL18XX_FW_STATUS_ADDR,
562 };
563
564 /* TODO: maybe move to a new header file? */
565 #define WL18XX_FW_NAME "ti-connectivity/wl18xx-fw.bin"
566
567 static int wl18xx_identify_chip(struct wl1271 *wl)
568 {
569 int ret = 0;
570
571 switch (wl->chip.id) {
572 case CHIP_ID_185x_PG10:
573 wl1271_debug(DEBUG_BOOT, "chip id 0x%x (185x PG10)",
574 wl->chip.id);
575 wl->sr_fw_name = WL18XX_FW_NAME;
576 wl->quirks |= WLCORE_QUIRK_NO_ELP |
577 WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN;
578
579 /* TODO: need to blocksize alignment for RX/TX separately? */
580 break;
581 default:
582 wl1271_warning("unsupported chip id: 0x%x", wl->chip.id);
583 ret = -ENODEV;
584 goto out;
585 }
586
587 out:
588 return ret;
589 }
590
591 static void wl18xx_set_clk(struct wl1271 *wl)
592 {
593 struct wl18xx_priv *priv = wl->priv;
594
595 /* write the translated board type to SCR_PAD2 */
596 wl1271_write32(wl, WL18XX_SCR_PAD2,
597 wl18xx_board_type_to_scrpad2[priv->board_type]);
598
599 wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]);
600 wl1271_write32(wl, 0x00A02360, 0xD0078);
601 wl1271_write32(wl, 0x00A0236c, 0x12);
602 wl1271_write32(wl, 0x00A02390, 0x20118);
603 }
604
605 static void wl18xx_boot_soft_reset(struct wl1271 *wl)
606 {
607 /* disable Rx/Tx */
608 wl1271_write32(wl, WL18XX_ENABLE, 0x0);
609
610 /* disable auto calibration on start*/
611 wl1271_write32(wl, WL18XX_SPARE_A2, 0xffff);
612 }
613
614 static int wl18xx_pre_boot(struct wl1271 *wl)
615 {
616 /* TODO: add hw_pg_ver reading */
617
618 wl18xx_set_clk(wl);
619
620 /* Continue the ELP wake up sequence */
621 wl1271_write32(wl, WL18XX_WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
622 udelay(500);
623
624 wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
625
626 /* Disable interrupts */
627 wlcore_write_reg(wl, REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
628
629 wl18xx_boot_soft_reset(wl);
630
631 return 0;
632 }
633
634 static void wl18xx_pre_upload(struct wl1271 *wl)
635 {
636 u32 tmp;
637
638 wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
639
640 /* TODO: check if this is all needed */
641 wl1271_write32(wl, WL18XX_EEPROMLESS_IND, WL18XX_EEPROMLESS_IND);
642
643 tmp = wlcore_read_reg(wl, REG_CHIP_ID_B);
644
645 wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp);
646
647 tmp = wl1271_read32(wl, WL18XX_SCR_PAD2);
648 }
649
650 static void wl18xx_set_mac_and_phy(struct wl1271 *wl)
651 {
652 struct wl18xx_priv *priv = wl->priv;
653 struct wl18xx_conf_phy *phy = &priv->conf.phy;
654 struct wl18xx_mac_and_phy_params params;
655
656 memset(&params, 0, sizeof(params));
657
658 params.phy_standalone = phy->phy_standalone;
659 params.rdl = phy->rdl;
660 params.enable_clpc = phy->enable_clpc;
661 params.enable_tx_low_pwr_on_siso_rdl =
662 phy->enable_tx_low_pwr_on_siso_rdl;
663 params.auto_detect = phy->auto_detect;
664 params.dedicated_fem = phy->dedicated_fem;
665 params.low_band_component = phy->low_band_component;
666 params.low_band_component_type =
667 phy->low_band_component_type;
668 params.high_band_component = phy->high_band_component;
669 params.high_band_component_type =
670 phy->high_band_component_type;
671 params.number_of_assembled_ant2_4 =
672 phy->number_of_assembled_ant2_4;
673 params.number_of_assembled_ant5 =
674 phy->number_of_assembled_ant5;
675 params.external_pa_dc2dc = phy->external_pa_dc2dc;
676 params.tcxo_ldo_voltage = phy->tcxo_ldo_voltage;
677 params.xtal_itrim_val = phy->xtal_itrim_val;
678 params.srf_state = phy->srf_state;
679 params.io_configuration = phy->io_configuration;
680 params.sdio_configuration = phy->sdio_configuration;
681 params.settings = phy->settings;
682 params.rx_profile = phy->rx_profile;
683 params.primary_clock_setting_time =
684 phy->primary_clock_setting_time;
685 params.clock_valid_on_wake_up =
686 phy->clock_valid_on_wake_up;
687 params.secondary_clock_setting_time =
688 phy->secondary_clock_setting_time;
689
690 params.board_type = priv->board_type;
691
692 wlcore_set_partition(wl, &wl->ptable[PART_PHY_INIT]);
693 wl1271_write(wl, WL18XX_PHY_INIT_MEM_ADDR, (u8 *)&params,
694 sizeof(params), false);
695 }
696
697 static void wl18xx_enable_interrupts(struct wl1271 *wl)
698 {
699 wlcore_write_reg(wl, REG_INTERRUPT_MASK, WL1271_ACX_ALL_EVENTS_VECTOR);
700
701 wlcore_enable_interrupts(wl);
702 wlcore_write_reg(wl, REG_INTERRUPT_MASK,
703 WL1271_ACX_INTR_ALL & ~(WL1271_INTR_MASK));
704 }
705
706 static int wl18xx_boot(struct wl1271 *wl)
707 {
708 int ret;
709
710 ret = wl18xx_pre_boot(wl);
711 if (ret < 0)
712 goto out;
713
714 ret = wlcore_boot_upload_nvs(wl);
715 if (ret < 0)
716 goto out;
717
718 wl18xx_pre_upload(wl);
719
720 ret = wlcore_boot_upload_firmware(wl);
721 if (ret < 0)
722 goto out;
723
724 wl18xx_set_mac_and_phy(wl);
725
726 ret = wlcore_boot_run_firmware(wl);
727 if (ret < 0)
728 goto out;
729
730 wl18xx_enable_interrupts(wl);
731
732 out:
733 return ret;
734 }
735
736 static void wl18xx_trigger_cmd(struct wl1271 *wl, int cmd_box_addr,
737 void *buf, size_t len)
738 {
739 struct wl18xx_priv *priv = wl->priv;
740
741 memcpy(priv->cmd_buf, buf, len);
742 memset(priv->cmd_buf + len, 0, WL18XX_CMD_MAX_SIZE - len);
743
744 wl1271_write(wl, cmd_box_addr, priv->cmd_buf, WL18XX_CMD_MAX_SIZE,
745 false);
746 }
747
748 static void wl18xx_ack_event(struct wl1271 *wl)
749 {
750 wlcore_write_reg(wl, REG_INTERRUPT_TRIG, WL18XX_INTR_TRIG_EVENT_ACK);
751 }
752
753 static u32 wl18xx_calc_tx_blocks(struct wl1271 *wl, u32 len, u32 spare_blks)
754 {
755 u32 blk_size = WL18XX_TX_HW_BLOCK_SIZE;
756 return (len + blk_size - 1) / blk_size + spare_blks;
757 }
758
759 static void
760 wl18xx_set_tx_desc_blocks(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
761 u32 blks, u32 spare_blks)
762 {
763 desc->wl18xx_mem.total_mem_blocks = blks;
764 desc->wl18xx_mem.reserved = 0;
765 }
766
767 static void
768 wl18xx_set_tx_desc_data_len(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
769 struct sk_buff *skb)
770 {
771 desc->length = cpu_to_le16(skb->len);
772
773 wl1271_debug(DEBUG_TX, "tx_fill_hdr: hlid: %d "
774 "len: %d life: %d mem: %d", desc->hlid,
775 le16_to_cpu(desc->length),
776 le16_to_cpu(desc->life_time),
777 desc->wl18xx_mem.total_mem_blocks);
778 }
779
780 static enum wl_rx_buf_align
781 wl18xx_get_rx_buf_align(struct wl1271 *wl, u32 rx_desc)
782 {
783 if (rx_desc & RX_BUF_PADDED_PAYLOAD)
784 return WLCORE_RX_BUF_PADDED;
785
786 return WLCORE_RX_BUF_ALIGNED;
787 }
788
789 static u32 wl18xx_get_rx_packet_len(struct wl1271 *wl, void *rx_data,
790 u32 data_len)
791 {
792 struct wl1271_rx_descriptor *desc = rx_data;
793
794 /* invalid packet */
795 if (data_len < sizeof(*desc))
796 return 0;
797
798 return data_len - sizeof(*desc);
799 }
800
801 static void wl18xx_tx_immediate_completion(struct wl1271 *wl)
802 {
803 wl18xx_tx_immediate_complete(wl);
804 }
805
806 static int wl18xx_hw_init(struct wl1271 *wl)
807 {
808 int ret;
809 u32 host_cfg_bitmap = HOST_IF_CFG_RX_FIFO_ENABLE |
810 HOST_IF_CFG_ADD_RX_ALIGNMENT;
811
812 u32 sdio_align_size = 0;
813
814 /* Enable Tx SDIO padding */
815 if (wl->quirks & WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN) {
816 host_cfg_bitmap |= HOST_IF_CFG_TX_PAD_TO_SDIO_BLK;
817 sdio_align_size = WL12XX_BUS_BLOCK_SIZE;
818 }
819
820 /* Enable Rx SDIO padding */
821 if (wl->quirks & WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN) {
822 host_cfg_bitmap |= HOST_IF_CFG_RX_PAD_TO_SDIO_BLK;
823 sdio_align_size = WL12XX_BUS_BLOCK_SIZE;
824 }
825
826 ret = wl18xx_acx_host_if_cfg_bitmap(wl, host_cfg_bitmap,
827 sdio_align_size,
828 WL18XX_TX_HW_BLOCK_SPARE,
829 WL18XX_HOST_IF_LEN_SIZE_FIELD);
830 if (ret < 0)
831 return ret;
832
833 ret = wl18xx_acx_set_checksum_state(wl);
834 if (ret != 0)
835 return ret;
836
837 return ret;
838 }
839
840 static void wl18xx_set_tx_desc_csum(struct wl1271 *wl,
841 struct wl1271_tx_hw_descr *desc,
842 struct sk_buff *skb)
843 {
844 u32 ip_hdr_offset;
845 struct iphdr *ip_hdr;
846
847 if (skb->ip_summed != CHECKSUM_PARTIAL) {
848 desc->wl18xx_checksum_data = 0;
849 return;
850 }
851
852 ip_hdr_offset = skb_network_header(skb) - skb_mac_header(skb);
853 if (WARN_ON(ip_hdr_offset >= (1<<7))) {
854 desc->wl18xx_checksum_data = 0;
855 return;
856 }
857
858 desc->wl18xx_checksum_data = ip_hdr_offset << 1;
859
860 /* FW is interested only in the LSB of the protocol TCP=0 UDP=1 */
861 ip_hdr = (void *)skb_network_header(skb);
862 desc->wl18xx_checksum_data |= (ip_hdr->protocol & 0x01);
863 }
864
865 static void wl18xx_set_rx_csum(struct wl1271 *wl,
866 struct wl1271_rx_descriptor *desc,
867 struct sk_buff *skb)
868 {
869 if (desc->status & WL18XX_RX_CHECKSUM_MASK)
870 skb->ip_summed = CHECKSUM_UNNECESSARY;
871 }
872
873 static u32 wl18xx_sta_get_ap_rate_mask(struct wl1271 *wl,
874 struct wl12xx_vif *wlvif)
875 {
876 u32 hw_rate_set = wlvif->rate_set;
877
878 if (wlvif->channel_type == NL80211_CHAN_HT40MINUS ||
879 wlvif->channel_type == NL80211_CHAN_HT40PLUS) {
880 wl1271_debug(DEBUG_ACX, "using wide channel rate mask");
881 hw_rate_set |= CONF_TX_RATE_USE_WIDE_CHAN;
882
883 /* we don't support MIMO in wide-channel mode */
884 hw_rate_set &= ~CONF_TX_MIMO_RATES;
885 }
886
887 return hw_rate_set;
888 }
889
890 static u32 wl18xx_ap_get_mimo_wide_rate_mask(struct wl1271 *wl,
891 struct wl12xx_vif *wlvif)
892 {
893 if (wlvif->channel_type == NL80211_CHAN_HT40MINUS ||
894 wlvif->channel_type == NL80211_CHAN_HT40PLUS) {
895 wl1271_debug(DEBUG_ACX, "using wide channel rate mask");
896 return CONF_TX_RATE_USE_WIDE_CHAN;
897 } else {
898 wl1271_debug(DEBUG_ACX, "using MIMO rate mask");
899 return CONF_TX_MIMO_RATES;
900 }
901 }
902
903 static void wl18xx_conf_init(struct wl1271 *wl)
904 {
905 struct wl18xx_priv *priv = wl->priv;
906
907 /* apply driver default configuration */
908 memcpy(&wl->conf, &wl18xx_conf, sizeof(wl18xx_conf));
909
910 /* apply default private configuration */
911 memcpy(&priv->conf, &wl18xx_default_priv_conf, sizeof(priv->conf));
912 }
913
914 static struct wlcore_ops wl18xx_ops = {
915 .identify_chip = wl18xx_identify_chip,
916 .boot = wl18xx_boot,
917 .trigger_cmd = wl18xx_trigger_cmd,
918 .ack_event = wl18xx_ack_event,
919 .calc_tx_blocks = wl18xx_calc_tx_blocks,
920 .set_tx_desc_blocks = wl18xx_set_tx_desc_blocks,
921 .set_tx_desc_data_len = wl18xx_set_tx_desc_data_len,
922 .get_rx_buf_align = wl18xx_get_rx_buf_align,
923 .get_rx_packet_len = wl18xx_get_rx_packet_len,
924 .tx_immediate_compl = wl18xx_tx_immediate_completion,
925 .tx_delayed_compl = NULL,
926 .hw_init = wl18xx_hw_init,
927 .set_tx_desc_csum = wl18xx_set_tx_desc_csum,
928 .set_rx_csum = wl18xx_set_rx_csum,
929 .sta_get_ap_rate_mask = wl18xx_sta_get_ap_rate_mask,
930 .ap_get_mimo_wide_rate_mask = wl18xx_ap_get_mimo_wide_rate_mask,
931 };
932
933 /* HT cap appropriate for wide channels */
934 static struct ieee80211_sta_ht_cap wl18xx_ht_cap = {
935 .cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40 |
936 IEEE80211_HT_CAP_SUP_WIDTH_20_40 | IEEE80211_HT_CAP_DSSSCCK40,
937 .ht_supported = true,
938 .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K,
939 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16,
940 .mcs = {
941 .rx_mask = { 0xff, 0, 0, 0, 0, 0, 0, 0, 0, 0, },
942 .rx_highest = cpu_to_le16(150),
943 .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
944 },
945 };
946
947 /* HT cap appropriate for MIMO rates in 20mhz channel */
948 static struct ieee80211_sta_ht_cap wl18xx_mimo_ht_cap = {
949 .cap = IEEE80211_HT_CAP_SGI_20,
950 .ht_supported = true,
951 .ampdu_factor = IEEE80211_HT_MAX_AMPDU_16K,
952 .ampdu_density = IEEE80211_HT_MPDU_DENSITY_16,
953 .mcs = {
954 .rx_mask = { 0xff, 0xff, 0, 0, 0, 0, 0, 0, 0, 0, },
955 .rx_highest = cpu_to_le16(144),
956 .tx_params = IEEE80211_HT_MCS_TX_DEFINED,
957 },
958 };
959
960 int __devinit wl18xx_probe(struct platform_device *pdev)
961 {
962 struct wl1271 *wl;
963 struct ieee80211_hw *hw;
964 struct wl18xx_priv *priv;
965
966 hw = wlcore_alloc_hw(sizeof(*priv));
967 if (IS_ERR(hw)) {
968 wl1271_error("can't allocate hw");
969 return PTR_ERR(hw);
970 }
971
972 wl = hw->priv;
973 priv = wl->priv;
974 wl->ops = &wl18xx_ops;
975 wl->ptable = wl18xx_ptable;
976 wl->rtable = wl18xx_rtable;
977 wl->num_tx_desc = 32;
978 wl->normal_tx_spare = WL18XX_TX_HW_BLOCK_SPARE;
979 wl->gem_tx_spare = WL18XX_TX_HW_GEM_BLOCK_SPARE;
980 wl->band_rate_to_idx = wl18xx_band_rate_to_idx;
981 wl->hw_tx_rate_tbl_size = WL18XX_CONF_HW_RXTX_RATE_MAX;
982 wl->hw_min_ht_rate = WL18XX_CONF_HW_RXTX_RATE_MCS0;
983 wl->fw_status_priv_len = sizeof(struct wl18xx_fw_status_priv);
984 memcpy(&wl->ht_cap, &wl18xx_ht_cap, sizeof(wl18xx_ht_cap));
985 if (ht_mode_param && !strcmp(ht_mode_param, "mimo"))
986 memcpy(&wl->ht_cap, &wl18xx_mimo_ht_cap,
987 sizeof(wl18xx_mimo_ht_cap));
988
989 if (!board_type_param) {
990 board_type_param = kstrdup("dvp_evb", GFP_KERNEL);
991 priv->board_type = BOARD_TYPE_DVP_EVB_18XX;
992 } else {
993 if (!strcmp(board_type_param, "fpga"))
994 priv->board_type = BOARD_TYPE_FPGA_18XX;
995 else if (!strcmp(board_type_param, "hdk"))
996 priv->board_type = BOARD_TYPE_HDK_18XX;
997 else if (!strcmp(board_type_param, "dvp_evb"))
998 priv->board_type = BOARD_TYPE_DVP_EVB_18XX;
999 else {
1000 wl1271_error("invalid board type '%s'",
1001 board_type_param);
1002 wlcore_free_hw(wl);
1003 return -EINVAL;
1004 }
1005 }
1006
1007 wl18xx_conf_init(wl);
1008
1009 return wlcore_probe(wl, pdev);
1010 }
1011
1012 static const struct platform_device_id wl18xx_id_table[] __devinitconst = {
1013 { "wl18xx", 0 },
1014 { } /* Terminating Entry */
1015 };
1016 MODULE_DEVICE_TABLE(platform, wl18xx_id_table);
1017
1018 static struct platform_driver wl18xx_driver = {
1019 .probe = wl18xx_probe,
1020 .remove = __devexit_p(wlcore_remove),
1021 .id_table = wl18xx_id_table,
1022 .driver = {
1023 .name = "wl18xx_driver",
1024 .owner = THIS_MODULE,
1025 }
1026 };
1027
1028 static int __init wl18xx_init(void)
1029 {
1030 return platform_driver_register(&wl18xx_driver);
1031 }
1032 module_init(wl18xx_init);
1033
1034 static void __exit wl18xx_exit(void)
1035 {
1036 platform_driver_unregister(&wl18xx_driver);
1037 }
1038 module_exit(wl18xx_exit);
1039
1040 module_param_named(ht_mode, ht_mode_param, charp, S_IRUSR);
1041 MODULE_PARM_DESC(ht_mode, "Force HT mode: wide or mimo");
1042
1043 module_param_named(board_type, board_type_param, charp, S_IRUSR);
1044 MODULE_PARM_DESC(board_type, "Board type: fpga, hdk or dvp_evb (default)");
1045
1046 MODULE_LICENSE("GPL v2");
1047 MODULE_AUTHOR("Luciano Coelho <coelho@ti.com>");
1048 MODULE_FIRMWARE(WL18XX_FW_NAME);
Linux 2.6 libata-dev (mirror)