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ALSA: wss-lib: move AD1845 frequency setting into wss-lib
[linux-2.6/libata-dev.git] / sound / isa / wss / wss_lib.c
blob13299aebd07727f0a8f6e3b02209a3a697518da9
1 /*
2 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>
3 * Routines for control of CS4231(A)/CS4232/InterWave & compatible chips
4 *
5 * Bugs:
6 * - sometimes record brokes playback with WSS portion of
7 * Yamaha OPL3-SA3 chip
8 * - CS4231 (GUS MAX) - still trouble with occasional noises
9 * - broken initialization?
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 *
25 */
26
27 #include <linux/delay.h>
28 #include <linux/pm.h>
29 #include <linux/init.h>
30 #include <linux/interrupt.h>
31 #include <linux/slab.h>
32 #include <linux/ioport.h>
33 #include <sound/core.h>
34 #include <sound/wss.h>
35 #include <sound/pcm_params.h>
36 #include <sound/tlv.h>
37
38 #include <asm/io.h>
39 #include <asm/dma.h>
40 #include <asm/irq.h>
41
42 MODULE_AUTHOR("Jaroslav Kysela <perex@perex.cz>");
43 MODULE_DESCRIPTION("Routines for control of CS4231(A)/CS4232/InterWave & compatible chips");
44 MODULE_LICENSE("GPL");
45
46 #if 0
47 #define SNDRV_DEBUG_MCE
48 #endif
49
50 /*
51 * Some variables
52 */
53
54 static unsigned char freq_bits[14] = {
55 /* 5510 */ 0x00 | CS4231_XTAL2,
56 /* 6620 */ 0x0E | CS4231_XTAL2,
57 /* 8000 */ 0x00 | CS4231_XTAL1,
58 /* 9600 */ 0x0E | CS4231_XTAL1,
59 /* 11025 */ 0x02 | CS4231_XTAL2,
60 /* 16000 */ 0x02 | CS4231_XTAL1,
61 /* 18900 */ 0x04 | CS4231_XTAL2,
62 /* 22050 */ 0x06 | CS4231_XTAL2,
63 /* 27042 */ 0x04 | CS4231_XTAL1,
64 /* 32000 */ 0x06 | CS4231_XTAL1,
65 /* 33075 */ 0x0C | CS4231_XTAL2,
66 /* 37800 */ 0x08 | CS4231_XTAL2,
67 /* 44100 */ 0x0A | CS4231_XTAL2,
68 /* 48000 */ 0x0C | CS4231_XTAL1
69 };
70
71 static unsigned int rates[14] = {
72 5510, 6620, 8000, 9600, 11025, 16000, 18900, 22050,
73 27042, 32000, 33075, 37800, 44100, 48000
74 };
75
76 static struct snd_pcm_hw_constraint_list hw_constraints_rates = {
77 .count = ARRAY_SIZE(rates),
78 .list = rates,
79 .mask = 0,
80 };
81
82 static int snd_wss_xrate(struct snd_pcm_runtime *runtime)
83 {
84 return snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
85 &hw_constraints_rates);
86 }
87
88 static unsigned char snd_wss_original_image[32] =
89 {
90 0x00, /* 00/00 - lic */
91 0x00, /* 01/01 - ric */
92 0x9f, /* 02/02 - la1ic */
93 0x9f, /* 03/03 - ra1ic */
94 0x9f, /* 04/04 - la2ic */
95 0x9f, /* 05/05 - ra2ic */
96 0xbf, /* 06/06 - loc */
97 0xbf, /* 07/07 - roc */
98 0x20, /* 08/08 - pdfr */
99 CS4231_AUTOCALIB, /* 09/09 - ic */
100 0x00, /* 0a/10 - pc */
101 0x00, /* 0b/11 - ti */
102 CS4231_MODE2, /* 0c/12 - mi */
103 0xfc, /* 0d/13 - lbc */
104 0x00, /* 0e/14 - pbru */
105 0x00, /* 0f/15 - pbrl */
106 0x80, /* 10/16 - afei */
107 0x01, /* 11/17 - afeii */
108 0x9f, /* 12/18 - llic */
109 0x9f, /* 13/19 - rlic */
110 0x00, /* 14/20 - tlb */
111 0x00, /* 15/21 - thb */
112 0x00, /* 16/22 - la3mic/reserved */
113 0x00, /* 17/23 - ra3mic/reserved */
114 0x00, /* 18/24 - afs */
115 0x00, /* 19/25 - lamoc/version */
116 0xcf, /* 1a/26 - mioc */
117 0x00, /* 1b/27 - ramoc/reserved */
118 0x20, /* 1c/28 - cdfr */
119 0x00, /* 1d/29 - res4 */
120 0x00, /* 1e/30 - cbru */
121 0x00, /* 1f/31 - cbrl */
122 };
123
124 static unsigned char snd_opti93x_original_image[32] =
125 {
126 0x00, /* 00/00 - l_mixout_outctrl */
127 0x00, /* 01/01 - r_mixout_outctrl */
128 0x88, /* 02/02 - l_cd_inctrl */
129 0x88, /* 03/03 - r_cd_inctrl */
130 0x88, /* 04/04 - l_a1/fm_inctrl */
131 0x88, /* 05/05 - r_a1/fm_inctrl */
132 0x80, /* 06/06 - l_dac_inctrl */
133 0x80, /* 07/07 - r_dac_inctrl */
134 0x00, /* 08/08 - ply_dataform_reg */
135 0x00, /* 09/09 - if_conf */
136 0x00, /* 0a/10 - pin_ctrl */
137 0x00, /* 0b/11 - err_init_reg */
138 0x0a, /* 0c/12 - id_reg */
139 0x00, /* 0d/13 - reserved */
140 0x00, /* 0e/14 - ply_upcount_reg */
141 0x00, /* 0f/15 - ply_lowcount_reg */
142 0x88, /* 10/16 - reserved/l_a1_inctrl */
143 0x88, /* 11/17 - reserved/r_a1_inctrl */
144 0x88, /* 12/18 - l_line_inctrl */
145 0x88, /* 13/19 - r_line_inctrl */
146 0x88, /* 14/20 - l_mic_inctrl */
147 0x88, /* 15/21 - r_mic_inctrl */
148 0x80, /* 16/22 - l_out_outctrl */
149 0x80, /* 17/23 - r_out_outctrl */
150 0x00, /* 18/24 - reserved */
151 0x00, /* 19/25 - reserved */
152 0x00, /* 1a/26 - reserved */
153 0x00, /* 1b/27 - reserved */
154 0x00, /* 1c/28 - cap_dataform_reg */
155 0x00, /* 1d/29 - reserved */
156 0x00, /* 1e/30 - cap_upcount_reg */
157 0x00 /* 1f/31 - cap_lowcount_reg */
158 };
159
160 /*
161 * Basic I/O functions
162 */
163
164 static inline void wss_outb(struct snd_wss *chip, u8 offset, u8 val)
165 {
166 outb(val, chip->port + offset);
167 }
168
169 static inline u8 wss_inb(struct snd_wss *chip, u8 offset)
170 {
171 return inb(chip->port + offset);
172 }
173
174 static void snd_wss_wait(struct snd_wss *chip)
175 {
176 int timeout;
177
178 for (timeout = 250;
179 timeout > 0 && (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT);
180 timeout--)
181 udelay(100);
182 }
183
184 static void snd_wss_outm(struct snd_wss *chip, unsigned char reg,
185 unsigned char mask, unsigned char value)
186 {
187 unsigned char tmp = (chip->image[reg] & mask) | value;
188
189 snd_wss_wait(chip);
190 #ifdef CONFIG_SND_DEBUG
191 if (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
192 snd_printk("outm: auto calibration time out - reg = 0x%x, value = 0x%x\n", reg, value);
193 #endif
194 chip->image[reg] = tmp;
195 if (!chip->calibrate_mute) {
196 wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg);
197 wmb();
198 wss_outb(chip, CS4231P(REG), tmp);
199 mb();
200 }
201 }
202
203 static void snd_wss_dout(struct snd_wss *chip, unsigned char reg,
204 unsigned char value)
205 {
206 int timeout;
207
208 for (timeout = 250;
209 timeout > 0 && (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT);
210 timeout--)
211 udelay(10);
212 wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg);
213 wss_outb(chip, CS4231P(REG), value);
214 mb();
215 }
216
217 void snd_wss_out(struct snd_wss *chip, unsigned char reg, unsigned char value)
218 {
219 snd_wss_wait(chip);
220 #ifdef CONFIG_SND_DEBUG
221 if (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
222 snd_printk("out: auto calibration time out - reg = 0x%x, value = 0x%x\n", reg, value);
223 #endif
224 wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg);
225 wss_outb(chip, CS4231P(REG), value);
226 chip->image[reg] = value;
227 mb();
228 snd_printdd("codec out - reg 0x%x = 0x%x\n",
229 chip->mce_bit | reg, value);
230 }
231 EXPORT_SYMBOL(snd_wss_out);
232
233 unsigned char snd_wss_in(struct snd_wss *chip, unsigned char reg)
234 {
235 snd_wss_wait(chip);
236 #ifdef CONFIG_SND_DEBUG
237 if (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
238 snd_printk("in: auto calibration time out - reg = 0x%x\n", reg);
239 #endif
240 wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | reg);
241 mb();
242 return wss_inb(chip, CS4231P(REG));
243 }
244 EXPORT_SYMBOL(snd_wss_in);
245
246 void snd_cs4236_ext_out(struct snd_wss *chip, unsigned char reg,
247 unsigned char val)
248 {
249 wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | 0x17);
250 wss_outb(chip, CS4231P(REG),
251 reg | (chip->image[CS4236_EXT_REG] & 0x01));
252 wss_outb(chip, CS4231P(REG), val);
253 chip->eimage[CS4236_REG(reg)] = val;
254 #if 0
255 printk("ext out : reg = 0x%x, val = 0x%x\n", reg, val);
256 #endif
257 }
258 EXPORT_SYMBOL(snd_cs4236_ext_out);
259
260 unsigned char snd_cs4236_ext_in(struct snd_wss *chip, unsigned char reg)
261 {
262 wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | 0x17);
263 wss_outb(chip, CS4231P(REG),
264 reg | (chip->image[CS4236_EXT_REG] & 0x01));
265 #if 1
266 return wss_inb(chip, CS4231P(REG));
267 #else
268 {
269 unsigned char res;
270 res = wss_inb(chip, CS4231P(REG));
271 printk("ext in : reg = 0x%x, val = 0x%x\n", reg, res);
272 return res;
273 }
274 #endif
275 }
276 EXPORT_SYMBOL(snd_cs4236_ext_in);
277
278 #if 0
279
280 static void snd_wss_debug(struct snd_wss *chip)
281 {
282 printk(KERN_DEBUG
283 "CS4231 REGS: INDEX = 0x%02x "
284 " STATUS = 0x%02x\n",
285 wss_inb(chip, CS4231P(REGSEL)),
286 wss_inb(chip, CS4231P(STATUS)));
287 printk(KERN_DEBUG
288 " 0x00: left input = 0x%02x "
289 " 0x10: alt 1 (CFIG 2) = 0x%02x\n",
290 snd_wss_in(chip, 0x00),
291 snd_wss_in(chip, 0x10));
292 printk(KERN_DEBUG
293 " 0x01: right input = 0x%02x "
294 " 0x11: alt 2 (CFIG 3) = 0x%02x\n",
295 snd_wss_in(chip, 0x01),
296 snd_wss_in(chip, 0x11));
297 printk(KERN_DEBUG
298 " 0x02: GF1 left input = 0x%02x "
299 " 0x12: left line in = 0x%02x\n",
300 snd_wss_in(chip, 0x02),
301 snd_wss_in(chip, 0x12));
302 printk(KERN_DEBUG
303 " 0x03: GF1 right input = 0x%02x "
304 " 0x13: right line in = 0x%02x\n",
305 snd_wss_in(chip, 0x03),
306 snd_wss_in(chip, 0x13));
307 printk(KERN_DEBUG
308 " 0x04: CD left input = 0x%02x "
309 " 0x14: timer low = 0x%02x\n",
310 snd_wss_in(chip, 0x04),
311 snd_wss_in(chip, 0x14));
312 printk(KERN_DEBUG
313 " 0x05: CD right input = 0x%02x "
314 " 0x15: timer high = 0x%02x\n",
315 snd_wss_in(chip, 0x05),
316 snd_wss_in(chip, 0x15));
317 printk(KERN_DEBUG
318 " 0x06: left output = 0x%02x "
319 " 0x16: left MIC (PnP) = 0x%02x\n",
320 snd_wss_in(chip, 0x06),
321 snd_wss_in(chip, 0x16));
322 printk(KERN_DEBUG
323 " 0x07: right output = 0x%02x "
324 " 0x17: right MIC (PnP) = 0x%02x\n",
325 snd_wss_in(chip, 0x07),
326 snd_wss_in(chip, 0x17));
327 printk(KERN_DEBUG
328 " 0x08: playback format = 0x%02x "
329 " 0x18: IRQ status = 0x%02x\n",
330 snd_wss_in(chip, 0x08),
331 snd_wss_in(chip, 0x18));
332 printk(KERN_DEBUG
333 " 0x09: iface (CFIG 1) = 0x%02x "
334 " 0x19: left line out = 0x%02x\n",
335 snd_wss_in(chip, 0x09),
336 snd_wss_in(chip, 0x19));
337 printk(KERN_DEBUG
338 " 0x0a: pin control = 0x%02x "
339 " 0x1a: mono control = 0x%02x\n",
340 snd_wss_in(chip, 0x0a),
341 snd_wss_in(chip, 0x1a));
342 printk(KERN_DEBUG
343 " 0x0b: init & status = 0x%02x "
344 " 0x1b: right line out = 0x%02x\n",
345 snd_wss_in(chip, 0x0b),
346 snd_wss_in(chip, 0x1b));
347 printk(KERN_DEBUG
348 " 0x0c: revision & mode = 0x%02x "
349 " 0x1c: record format = 0x%02x\n",
350 snd_wss_in(chip, 0x0c),
351 snd_wss_in(chip, 0x1c));
352 printk(KERN_DEBUG
353 " 0x0d: loopback = 0x%02x "
354 " 0x1d: var freq (PnP) = 0x%02x\n",
355 snd_wss_in(chip, 0x0d),
356 snd_wss_in(chip, 0x1d));
357 printk(KERN_DEBUG
358 " 0x0e: ply upr count = 0x%02x "
359 " 0x1e: ply lwr count = 0x%02x\n",
360 snd_wss_in(chip, 0x0e),
361 snd_wss_in(chip, 0x1e));
362 printk(KERN_DEBUG
363 " 0x0f: rec upr count = 0x%02x "
364 " 0x1f: rec lwr count = 0x%02x\n",
365 snd_wss_in(chip, 0x0f),
366 snd_wss_in(chip, 0x1f));
367 }
368
369 #endif
370
371 /*
372 * CS4231 detection / MCE routines
373 */
374
375 static void snd_wss_busy_wait(struct snd_wss *chip)
376 {
377 int timeout;
378
379 /* huh.. looks like this sequence is proper for CS4231A chip (GUS MAX) */
380 for (timeout = 5; timeout > 0; timeout--)
381 wss_inb(chip, CS4231P(REGSEL));
382 /* end of cleanup sequence */
383 for (timeout = 25000;
384 timeout > 0 && (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT);
385 timeout--)
386 udelay(10);
387 }
388
389 void snd_wss_mce_up(struct snd_wss *chip)
390 {
391 unsigned long flags;
392 int timeout;
393
394 snd_wss_wait(chip);
395 #ifdef CONFIG_SND_DEBUG
396 if (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
397 snd_printk("mce_up - auto calibration time out (0)\n");
398 #endif
399 spin_lock_irqsave(&chip->reg_lock, flags);
400 chip->mce_bit |= CS4231_MCE;
401 timeout = wss_inb(chip, CS4231P(REGSEL));
402 if (timeout == 0x80)
403 snd_printk("mce_up [0x%lx]: serious init problem - codec still busy\n", chip->port);
404 if (!(timeout & CS4231_MCE))
405 wss_outb(chip, CS4231P(REGSEL),
406 chip->mce_bit | (timeout & 0x1f));
407 spin_unlock_irqrestore(&chip->reg_lock, flags);
408 }
409 EXPORT_SYMBOL(snd_wss_mce_up);
410
411 void snd_wss_mce_down(struct snd_wss *chip)
412 {
413 unsigned long flags;
414 unsigned long end_time;
415 int timeout;
416 int hw_mask = WSS_HW_CS4231_MASK | WSS_HW_CS4232_MASK | WSS_HW_AD1848;
417
418 snd_wss_busy_wait(chip);
419
420 #ifdef CONFIG_SND_DEBUG
421 if (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
422 snd_printk("mce_down [0x%lx] - auto calibration time out (0)\n", (long)CS4231P(REGSEL));
423 #endif
424 spin_lock_irqsave(&chip->reg_lock, flags);
425 chip->mce_bit &= ~CS4231_MCE;
426 timeout = wss_inb(chip, CS4231P(REGSEL));
427 wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | (timeout & 0x1f));
428 spin_unlock_irqrestore(&chip->reg_lock, flags);
429 if (timeout == 0x80)
430 snd_printk("mce_down [0x%lx]: serious init problem - codec still busy\n", chip->port);
431 if ((timeout & CS4231_MCE) == 0 || !(chip->hardware & hw_mask))
432 return;
433
434 /*
435 * Wait for (possible -- during init auto-calibration may not be set)
436 * calibration process to start. Needs upto 5 sample periods on AD1848
437 * which at the slowest possible rate of 5.5125 kHz means 907 us.
438 */
439 msleep(1);
440
441 snd_printdd("(1) jiffies = %lu\n", jiffies);
442
443 /* check condition up to 250 ms */
444 end_time = jiffies + msecs_to_jiffies(250);
445 while (snd_wss_in(chip, CS4231_TEST_INIT) &
446 CS4231_CALIB_IN_PROGRESS) {
447
448 if (time_after(jiffies, end_time)) {
449 snd_printk(KERN_ERR "mce_down - "
450 "auto calibration time out (2)\n");
451 return;
452 }
453 msleep(1);
454 }
455
456 snd_printdd("(2) jiffies = %lu\n", jiffies);
457
458 /* check condition up to 100 ms */
459 end_time = jiffies + msecs_to_jiffies(100);
460 while (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT) {
461 if (time_after(jiffies, end_time)) {
462 snd_printk(KERN_ERR "mce_down - auto calibration time out (3)\n");
463 return;
464 }
465 msleep(1);
466 }
467
468 snd_printdd("(3) jiffies = %lu\n", jiffies);
469 snd_printd("mce_down - exit = 0x%x\n", wss_inb(chip, CS4231P(REGSEL)));
470 }
471 EXPORT_SYMBOL(snd_wss_mce_down);
472
473 static unsigned int snd_wss_get_count(unsigned char format, unsigned int size)
474 {
475 switch (format & 0xe0) {
476 case CS4231_LINEAR_16:
477 case CS4231_LINEAR_16_BIG:
478 size >>= 1;
479 break;
480 case CS4231_ADPCM_16:
481 return size >> 2;
482 }
483 if (format & CS4231_STEREO)
484 size >>= 1;
485 return size;
486 }
487
488 static int snd_wss_trigger(struct snd_pcm_substream *substream,
489 int cmd)
490 {
491 struct snd_wss *chip = snd_pcm_substream_chip(substream);
492 int result = 0;
493 unsigned int what;
494 struct snd_pcm_substream *s;
495 int do_start;
496
497 switch (cmd) {
498 case SNDRV_PCM_TRIGGER_START:
499 case SNDRV_PCM_TRIGGER_RESUME:
500 do_start = 1; break;
501 case SNDRV_PCM_TRIGGER_STOP:
502 case SNDRV_PCM_TRIGGER_SUSPEND:
503 do_start = 0; break;
504 default:
505 return -EINVAL;
506 }
507
508 what = 0;
509 snd_pcm_group_for_each_entry(s, substream) {
510 if (s == chip->playback_substream) {
511 what |= CS4231_PLAYBACK_ENABLE;
512 snd_pcm_trigger_done(s, substream);
513 } else if (s == chip->capture_substream) {
514 what |= CS4231_RECORD_ENABLE;
515 snd_pcm_trigger_done(s, substream);
516 }
517 }
518 spin_lock(&chip->reg_lock);
519 if (do_start) {
520 chip->image[CS4231_IFACE_CTRL] |= what;
521 if (chip->trigger)
522 chip->trigger(chip, what, 1);
523 } else {
524 chip->image[CS4231_IFACE_CTRL] &= ~what;
525 if (chip->trigger)
526 chip->trigger(chip, what, 0);
527 }
528 snd_wss_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);
529 spin_unlock(&chip->reg_lock);
530 #if 0
531 snd_wss_debug(chip);
532 #endif
533 return result;
534 }
535
536 /*
537 * CODEC I/O
538 */
539
540 static unsigned char snd_wss_get_rate(unsigned int rate)
541 {
542 int i;
543
544 for (i = 0; i < ARRAY_SIZE(rates); i++)
545 if (rate == rates[i])
546 return freq_bits[i];
547 // snd_BUG();
548 return freq_bits[ARRAY_SIZE(rates) - 1];
549 }
550
551 static unsigned char snd_wss_get_format(struct snd_wss *chip,
552 int format,
553 int channels)
554 {
555 unsigned char rformat;
556
557 rformat = CS4231_LINEAR_8;
558 switch (format) {
559 case SNDRV_PCM_FORMAT_MU_LAW: rformat = CS4231_ULAW_8; break;
560 case SNDRV_PCM_FORMAT_A_LAW: rformat = CS4231_ALAW_8; break;
561 case SNDRV_PCM_FORMAT_S16_LE: rformat = CS4231_LINEAR_16; break;
562 case SNDRV_PCM_FORMAT_S16_BE: rformat = CS4231_LINEAR_16_BIG; break;
563 case SNDRV_PCM_FORMAT_IMA_ADPCM: rformat = CS4231_ADPCM_16; break;
564 }
565 if (channels > 1)
566 rformat |= CS4231_STEREO;
567 #if 0
568 snd_printk("get_format: 0x%x (mode=0x%x)\n", format, mode);
569 #endif
570 return rformat;
571 }
572
573 static void snd_wss_calibrate_mute(struct snd_wss *chip, int mute)
574 {
575 unsigned long flags;
576
577 mute = mute ? 0x80 : 0;
578 spin_lock_irqsave(&chip->reg_lock, flags);
579 if (chip->calibrate_mute == mute) {
580 spin_unlock_irqrestore(&chip->reg_lock, flags);
581 return;
582 }
583 if (!mute) {
584 snd_wss_dout(chip, CS4231_LEFT_INPUT,
585 chip->image[CS4231_LEFT_INPUT]);
586 snd_wss_dout(chip, CS4231_RIGHT_INPUT,
587 chip->image[CS4231_RIGHT_INPUT]);
588 snd_wss_dout(chip, CS4231_LOOPBACK,
589 chip->image[CS4231_LOOPBACK]);
590 }
591 snd_wss_dout(chip, CS4231_AUX1_LEFT_INPUT,
592 mute | chip->image[CS4231_AUX1_LEFT_INPUT]);
593 snd_wss_dout(chip, CS4231_AUX1_RIGHT_INPUT,
594 mute | chip->image[CS4231_AUX1_RIGHT_INPUT]);
595 snd_wss_dout(chip, CS4231_AUX2_LEFT_INPUT,
596 mute | chip->image[CS4231_AUX2_LEFT_INPUT]);
597 snd_wss_dout(chip, CS4231_AUX2_RIGHT_INPUT,
598 mute | chip->image[CS4231_AUX2_RIGHT_INPUT]);
599 snd_wss_dout(chip, CS4231_LEFT_OUTPUT,
600 mute | chip->image[CS4231_LEFT_OUTPUT]);
601 snd_wss_dout(chip, CS4231_RIGHT_OUTPUT,
602 mute | chip->image[CS4231_RIGHT_OUTPUT]);
603 if (!(chip->hardware & WSS_HW_AD1848_MASK)) {
604 snd_wss_dout(chip, CS4231_LEFT_LINE_IN,
605 mute | chip->image[CS4231_LEFT_LINE_IN]);
606 snd_wss_dout(chip, CS4231_RIGHT_LINE_IN,
607 mute | chip->image[CS4231_RIGHT_LINE_IN]);
608 snd_wss_dout(chip, CS4231_MONO_CTRL,
609 mute ? 0xc0 : chip->image[CS4231_MONO_CTRL]);
610 }
611 if (chip->hardware == WSS_HW_INTERWAVE) {
612 snd_wss_dout(chip, CS4231_LEFT_MIC_INPUT,
613 mute | chip->image[CS4231_LEFT_MIC_INPUT]);
614 snd_wss_dout(chip, CS4231_RIGHT_MIC_INPUT,
615 mute | chip->image[CS4231_RIGHT_MIC_INPUT]);
616 snd_wss_dout(chip, CS4231_LINE_LEFT_OUTPUT,
617 mute | chip->image[CS4231_LINE_LEFT_OUTPUT]);
618 snd_wss_dout(chip, CS4231_LINE_RIGHT_OUTPUT,
619 mute | chip->image[CS4231_LINE_RIGHT_OUTPUT]);
620 }
621 chip->calibrate_mute = mute;
622 spin_unlock_irqrestore(&chip->reg_lock, flags);
623 }
624
625 static void snd_wss_playback_format(struct snd_wss *chip,
626 struct snd_pcm_hw_params *params,
627 unsigned char pdfr)
628 {
629 unsigned long flags;
630 int full_calib = 1;
631
632 mutex_lock(&chip->mce_mutex);
633 snd_wss_calibrate_mute(chip, 1);
634 if (chip->hardware == WSS_HW_CS4231A ||
635 (chip->hardware & WSS_HW_CS4232_MASK)) {
636 spin_lock_irqsave(&chip->reg_lock, flags);
637 if ((chip->image[CS4231_PLAYBK_FORMAT] & 0x0f) == (pdfr & 0x0f)) { /* rate is same? */
638 snd_wss_out(chip, CS4231_ALT_FEATURE_1,
639 chip->image[CS4231_ALT_FEATURE_1] | 0x10);
640 chip->image[CS4231_PLAYBK_FORMAT] = pdfr;
641 snd_wss_out(chip, CS4231_PLAYBK_FORMAT,
642 chip->image[CS4231_PLAYBK_FORMAT]);
643 snd_wss_out(chip, CS4231_ALT_FEATURE_1,
644 chip->image[CS4231_ALT_FEATURE_1] &= ~0x10);
645 udelay(100); /* Fixes audible clicks at least on GUS MAX */
646 full_calib = 0;
647 }
648 spin_unlock_irqrestore(&chip->reg_lock, flags);
649 } else if (chip->hardware == WSS_HW_AD1845) {
650 unsigned rate = params_rate(params);
651
652 /*
653 * Program the AD1845 correctly for the playback stream.
654 * Note that we do NOT need to toggle the MCE bit because
655 * the PLAYBACK_ENABLE bit of the Interface Configuration
656 * register is set.
657 *
658 * NOTE: We seem to need to write to the MSB before the LSB
659 * to get the correct sample frequency.
660 */
661 spin_lock_irqsave(&chip->reg_lock, flags);
662 snd_wss_out(chip, CS4231_PLAYBK_FORMAT, (pdfr & 0xf0));
663 snd_wss_out(chip, AD1845_UPR_FREQ_SEL, (rate >> 8) & 0xff);
664 snd_wss_out(chip, AD1845_LWR_FREQ_SEL, rate & 0xff);
665 full_calib = 0;
666 spin_unlock_irqrestore(&chip->reg_lock, flags);
667 }
668 if (full_calib) {
669 snd_wss_mce_up(chip);
670 spin_lock_irqsave(&chip->reg_lock, flags);
671 if (chip->hardware != WSS_HW_INTERWAVE && !chip->single_dma) {
672 if (chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE)
673 pdfr = (pdfr & 0xf0) |
674 (chip->image[CS4231_REC_FORMAT] & 0x0f);
675 } else {
676 chip->image[CS4231_PLAYBK_FORMAT] = pdfr;
677 }
678 snd_wss_out(chip, CS4231_PLAYBK_FORMAT, pdfr);
679 spin_unlock_irqrestore(&chip->reg_lock, flags);
680 if (chip->hardware == WSS_HW_OPL3SA2)
681 udelay(100); /* this seems to help */
682 snd_wss_mce_down(chip);
683 }
684 snd_wss_calibrate_mute(chip, 0);
685 mutex_unlock(&chip->mce_mutex);
686 }
687
688 static void snd_wss_capture_format(struct snd_wss *chip,
689 struct snd_pcm_hw_params *params,
690 unsigned char cdfr)
691 {
692 unsigned long flags;
693 int full_calib = 1;
694
695 mutex_lock(&chip->mce_mutex);
696 snd_wss_calibrate_mute(chip, 1);
697 if (chip->hardware == WSS_HW_CS4231A ||
698 (chip->hardware & WSS_HW_CS4232_MASK)) {
699 spin_lock_irqsave(&chip->reg_lock, flags);
700 if ((chip->image[CS4231_PLAYBK_FORMAT] & 0x0f) == (cdfr & 0x0f) || /* rate is same? */
701 (chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE)) {
702 snd_wss_out(chip, CS4231_ALT_FEATURE_1,
703 chip->image[CS4231_ALT_FEATURE_1] | 0x20);
704 snd_wss_out(chip, CS4231_REC_FORMAT,
705 chip->image[CS4231_REC_FORMAT] = cdfr);
706 snd_wss_out(chip, CS4231_ALT_FEATURE_1,
707 chip->image[CS4231_ALT_FEATURE_1] &= ~0x20);
708 full_calib = 0;
709 }
710 spin_unlock_irqrestore(&chip->reg_lock, flags);
711 } else if (chip->hardware == WSS_HW_AD1845) {
712 unsigned rate = params_rate(params);
713
714 /*
715 * Program the AD1845 correctly for the capture stream.
716 * Note that we do NOT need to toggle the MCE bit because
717 * the PLAYBACK_ENABLE bit of the Interface Configuration
718 * register is set.
719 *
720 * NOTE: We seem to need to write to the MSB before the LSB
721 * to get the correct sample frequency.
722 */
723 spin_lock_irqsave(&chip->reg_lock, flags);
724 snd_wss_out(chip, CS4231_REC_FORMAT, (cdfr & 0xf0));
725 snd_wss_out(chip, AD1845_UPR_FREQ_SEL, (rate >> 8) & 0xff);
726 snd_wss_out(chip, AD1845_LWR_FREQ_SEL, rate & 0xff);
727 full_calib = 0;
728 spin_unlock_irqrestore(&chip->reg_lock, flags);
729 }
730 if (full_calib) {
731 snd_wss_mce_up(chip);
732 spin_lock_irqsave(&chip->reg_lock, flags);
733 if (chip->hardware != WSS_HW_INTERWAVE &&
734 !(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE)) {
735 if (chip->single_dma)
736 snd_wss_out(chip, CS4231_PLAYBK_FORMAT, cdfr);
737 else
738 snd_wss_out(chip, CS4231_PLAYBK_FORMAT,
739 (chip->image[CS4231_PLAYBK_FORMAT] & 0xf0) |
740 (cdfr & 0x0f));
741 spin_unlock_irqrestore(&chip->reg_lock, flags);
742 snd_wss_mce_down(chip);
743 snd_wss_mce_up(chip);
744 spin_lock_irqsave(&chip->reg_lock, flags);
745 }
746 if (chip->hardware & WSS_HW_AD1848_MASK)
747 snd_wss_out(chip, CS4231_PLAYBK_FORMAT, cdfr);
748 else
749 snd_wss_out(chip, CS4231_REC_FORMAT, cdfr);
750 spin_unlock_irqrestore(&chip->reg_lock, flags);
751 snd_wss_mce_down(chip);
752 }
753 snd_wss_calibrate_mute(chip, 0);
754 mutex_unlock(&chip->mce_mutex);
755 }
756
757 /*
758 * Timer interface
759 */
760
761 static unsigned long snd_wss_timer_resolution(struct snd_timer *timer)
762 {
763 struct snd_wss *chip = snd_timer_chip(timer);
764 if (chip->hardware & WSS_HW_CS4236B_MASK)
765 return 14467;
766 else
767 return chip->image[CS4231_PLAYBK_FORMAT] & 1 ? 9969 : 9920;
768 }
769
770 static int snd_wss_timer_start(struct snd_timer *timer)
771 {
772 unsigned long flags;
773 unsigned int ticks;
774 struct snd_wss *chip = snd_timer_chip(timer);
775 spin_lock_irqsave(&chip->reg_lock, flags);
776 ticks = timer->sticks;
777 if ((chip->image[CS4231_ALT_FEATURE_1] & CS4231_TIMER_ENABLE) == 0 ||
778 (unsigned char)(ticks >> 8) != chip->image[CS4231_TIMER_HIGH] ||
779 (unsigned char)ticks != chip->image[CS4231_TIMER_LOW]) {
780 chip->image[CS4231_TIMER_HIGH] = (unsigned char) (ticks >> 8);
781 snd_wss_out(chip, CS4231_TIMER_HIGH,
782 chip->image[CS4231_TIMER_HIGH]);
783 chip->image[CS4231_TIMER_LOW] = (unsigned char) ticks;
784 snd_wss_out(chip, CS4231_TIMER_LOW,
785 chip->image[CS4231_TIMER_LOW]);
786 snd_wss_out(chip, CS4231_ALT_FEATURE_1,
787 chip->image[CS4231_ALT_FEATURE_1] |
788 CS4231_TIMER_ENABLE);
789 }
790 spin_unlock_irqrestore(&chip->reg_lock, flags);
791 return 0;
792 }
793
794 static int snd_wss_timer_stop(struct snd_timer *timer)
795 {
796 unsigned long flags;
797 struct snd_wss *chip = snd_timer_chip(timer);
798 spin_lock_irqsave(&chip->reg_lock, flags);
799 chip->image[CS4231_ALT_FEATURE_1] &= ~CS4231_TIMER_ENABLE;
800 snd_wss_out(chip, CS4231_ALT_FEATURE_1,
801 chip->image[CS4231_ALT_FEATURE_1]);
802 spin_unlock_irqrestore(&chip->reg_lock, flags);
803 return 0;
804 }
805
806 static void snd_wss_init(struct snd_wss *chip)
807 {
808 unsigned long flags;
809
810 snd_wss_mce_down(chip);
811
812 #ifdef SNDRV_DEBUG_MCE
813 snd_printk("init: (1)\n");
814 #endif
815 snd_wss_mce_up(chip);
816 spin_lock_irqsave(&chip->reg_lock, flags);
817 chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE |
818 CS4231_PLAYBACK_PIO |
819 CS4231_RECORD_ENABLE |
820 CS4231_RECORD_PIO |
821 CS4231_CALIB_MODE);
822 chip->image[CS4231_IFACE_CTRL] |= CS4231_AUTOCALIB;
823 snd_wss_out(chip, CS4231_IFACE_CTRL, chip->image[CS4231_IFACE_CTRL]);
824 spin_unlock_irqrestore(&chip->reg_lock, flags);
825 snd_wss_mce_down(chip);
826
827 #ifdef SNDRV_DEBUG_MCE
828 snd_printk("init: (2)\n");
829 #endif
830
831 snd_wss_mce_up(chip);
832 spin_lock_irqsave(&chip->reg_lock, flags);
833 snd_wss_out(chip,
834 CS4231_ALT_FEATURE_1, chip->image[CS4231_ALT_FEATURE_1]);
835 spin_unlock_irqrestore(&chip->reg_lock, flags);
836 snd_wss_mce_down(chip);
837
838 #ifdef SNDRV_DEBUG_MCE
839 snd_printk("init: (3) - afei = 0x%x\n",
840 chip->image[CS4231_ALT_FEATURE_1]);
841 #endif
842
843 spin_lock_irqsave(&chip->reg_lock, flags);
844 snd_wss_out(chip, CS4231_ALT_FEATURE_2,
845 chip->image[CS4231_ALT_FEATURE_2]);
846 spin_unlock_irqrestore(&chip->reg_lock, flags);
847
848 snd_wss_mce_up(chip);
849 spin_lock_irqsave(&chip->reg_lock, flags);
850 snd_wss_out(chip, CS4231_PLAYBK_FORMAT,
851 chip->image[CS4231_PLAYBK_FORMAT]);
852 spin_unlock_irqrestore(&chip->reg_lock, flags);
853 snd_wss_mce_down(chip);
854
855 #ifdef SNDRV_DEBUG_MCE
856 snd_printk("init: (4)\n");
857 #endif
858
859 snd_wss_mce_up(chip);
860 spin_lock_irqsave(&chip->reg_lock, flags);
861 if (!(chip->hardware & WSS_HW_AD1848_MASK))
862 snd_wss_out(chip, CS4231_REC_FORMAT,
863 chip->image[CS4231_REC_FORMAT]);
864 spin_unlock_irqrestore(&chip->reg_lock, flags);
865 snd_wss_mce_down(chip);
866
867 #ifdef SNDRV_DEBUG_MCE
868 snd_printk("init: (5)\n");
869 #endif
870 }
871
872 static int snd_wss_open(struct snd_wss *chip, unsigned int mode)
873 {
874 unsigned long flags;
875
876 mutex_lock(&chip->open_mutex);
877 if ((chip->mode & mode) ||
878 ((chip->mode & WSS_MODE_OPEN) && chip->single_dma)) {
879 mutex_unlock(&chip->open_mutex);
880 return -EAGAIN;
881 }
882 if (chip->mode & WSS_MODE_OPEN) {
883 chip->mode |= mode;
884 mutex_unlock(&chip->open_mutex);
885 return 0;
886 }
887 /* ok. now enable and ack CODEC IRQ */
888 spin_lock_irqsave(&chip->reg_lock, flags);
889 if (!(chip->hardware & WSS_HW_AD1848_MASK)) {
890 snd_wss_out(chip, CS4231_IRQ_STATUS,
891 CS4231_PLAYBACK_IRQ |
892 CS4231_RECORD_IRQ |
893 CS4231_TIMER_IRQ);
894 snd_wss_out(chip, CS4231_IRQ_STATUS, 0);
895 }
896 wss_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
897 wss_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
898 chip->image[CS4231_PIN_CTRL] |= CS4231_IRQ_ENABLE;
899 snd_wss_out(chip, CS4231_PIN_CTRL, chip->image[CS4231_PIN_CTRL]);
900 if (!(chip->hardware & WSS_HW_AD1848_MASK)) {
901 snd_wss_out(chip, CS4231_IRQ_STATUS,
902 CS4231_PLAYBACK_IRQ |
903 CS4231_RECORD_IRQ |
904 CS4231_TIMER_IRQ);
905 snd_wss_out(chip, CS4231_IRQ_STATUS, 0);
906 }
907 spin_unlock_irqrestore(&chip->reg_lock, flags);
908
909 chip->mode = mode;
910 mutex_unlock(&chip->open_mutex);
911 return 0;
912 }
913
914 static void snd_wss_close(struct snd_wss *chip, unsigned int mode)
915 {
916 unsigned long flags;
917
918 mutex_lock(&chip->open_mutex);
919 chip->mode &= ~mode;
920 if (chip->mode & WSS_MODE_OPEN) {
921 mutex_unlock(&chip->open_mutex);
922 return;
923 }
924 snd_wss_calibrate_mute(chip, 1);
925
926 /* disable IRQ */
927 spin_lock_irqsave(&chip->reg_lock, flags);
928 if (!(chip->hardware & WSS_HW_AD1848_MASK))
929 snd_wss_out(chip, CS4231_IRQ_STATUS, 0);
930 wss_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
931 wss_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
932 chip->image[CS4231_PIN_CTRL] &= ~CS4231_IRQ_ENABLE;
933 snd_wss_out(chip, CS4231_PIN_CTRL, chip->image[CS4231_PIN_CTRL]);
934
935 /* now disable record & playback */
936
937 if (chip->image[CS4231_IFACE_CTRL] & (CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
938 CS4231_RECORD_ENABLE | CS4231_RECORD_PIO)) {
939 spin_unlock_irqrestore(&chip->reg_lock, flags);
940 snd_wss_mce_up(chip);
941 spin_lock_irqsave(&chip->reg_lock, flags);
942 chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO |
943 CS4231_RECORD_ENABLE | CS4231_RECORD_PIO);
944 snd_wss_out(chip, CS4231_IFACE_CTRL,
945 chip->image[CS4231_IFACE_CTRL]);
946 spin_unlock_irqrestore(&chip->reg_lock, flags);
947 snd_wss_mce_down(chip);
948 spin_lock_irqsave(&chip->reg_lock, flags);
949 }
950
951 /* clear IRQ again */
952 if (!(chip->hardware & WSS_HW_AD1848_MASK))
953 snd_wss_out(chip, CS4231_IRQ_STATUS, 0);
954 wss_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
955 wss_outb(chip, CS4231P(STATUS), 0); /* clear IRQ */
956 spin_unlock_irqrestore(&chip->reg_lock, flags);
957
958 snd_wss_calibrate_mute(chip, 0);
959
960 chip->mode = 0;
961 mutex_unlock(&chip->open_mutex);
962 }
963
964 /*
965 * timer open/close
966 */
967
968 static int snd_wss_timer_open(struct snd_timer *timer)
969 {
970 struct snd_wss *chip = snd_timer_chip(timer);
971 snd_wss_open(chip, WSS_MODE_TIMER);
972 return 0;
973 }
974
975 static int snd_wss_timer_close(struct snd_timer *timer)
976 {
977 struct snd_wss *chip = snd_timer_chip(timer);
978 snd_wss_close(chip, WSS_MODE_TIMER);
979 return 0;
980 }
981
982 static struct snd_timer_hardware snd_wss_timer_table =
983 {
984 .flags = SNDRV_TIMER_HW_AUTO,
985 .resolution = 9945,
986 .ticks = 65535,
987 .open = snd_wss_timer_open,
988 .close = snd_wss_timer_close,
989 .c_resolution = snd_wss_timer_resolution,
990 .start = snd_wss_timer_start,
991 .stop = snd_wss_timer_stop,
992 };
993
994 /*
995 * ok.. exported functions..
996 */
997
998 static int snd_wss_playback_hw_params(struct snd_pcm_substream *substream,
999 struct snd_pcm_hw_params *hw_params)
1000 {
1001 struct snd_wss *chip = snd_pcm_substream_chip(substream);
1002 unsigned char new_pdfr;
1003 int err;
1004
1005 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
1006 return err;
1007 new_pdfr = snd_wss_get_format(chip, params_format(hw_params),
1008 params_channels(hw_params)) |
1009 snd_wss_get_rate(params_rate(hw_params));
1010 chip->set_playback_format(chip, hw_params, new_pdfr);
1011 return 0;
1012 }
1013
1014 static int snd_wss_playback_hw_free(struct snd_pcm_substream *substream)
1015 {
1016 return snd_pcm_lib_free_pages(substream);
1017 }
1018
1019 static int snd_wss_playback_prepare(struct snd_pcm_substream *substream)
1020 {
1021 struct snd_wss *chip = snd_pcm_substream_chip(substream);
1022 struct snd_pcm_runtime *runtime = substream->runtime;
1023 unsigned long flags;
1024 unsigned int size = snd_pcm_lib_buffer_bytes(substream);
1025 unsigned int count = snd_pcm_lib_period_bytes(substream);
1026
1027 spin_lock_irqsave(&chip->reg_lock, flags);
1028 chip->p_dma_size = size;
1029 chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_PLAYBACK_ENABLE | CS4231_PLAYBACK_PIO);
1030 snd_dma_program(chip->dma1, runtime->dma_addr, size, DMA_MODE_WRITE | DMA_AUTOINIT);
1031 count = snd_wss_get_count(chip->image[CS4231_PLAYBK_FORMAT], count) - 1;
1032 snd_wss_out(chip, CS4231_PLY_LWR_CNT, (unsigned char) count);
1033 snd_wss_out(chip, CS4231_PLY_UPR_CNT, (unsigned char) (count >> 8));
1034 spin_unlock_irqrestore(&chip->reg_lock, flags);
1035 #if 0
1036 snd_wss_debug(chip);
1037 #endif
1038 return 0;
1039 }
1040
1041 static int snd_wss_capture_hw_params(struct snd_pcm_substream *substream,
1042 struct snd_pcm_hw_params *hw_params)
1043 {
1044 struct snd_wss *chip = snd_pcm_substream_chip(substream);
1045 unsigned char new_cdfr;
1046 int err;
1047
1048 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
1049 return err;
1050 new_cdfr = snd_wss_get_format(chip, params_format(hw_params),
1051 params_channels(hw_params)) |
1052 snd_wss_get_rate(params_rate(hw_params));
1053 chip->set_capture_format(chip, hw_params, new_cdfr);
1054 return 0;
1055 }
1056
1057 static int snd_wss_capture_hw_free(struct snd_pcm_substream *substream)
1058 {
1059 return snd_pcm_lib_free_pages(substream);
1060 }
1061
1062 static int snd_wss_capture_prepare(struct snd_pcm_substream *substream)
1063 {
1064 struct snd_wss *chip = snd_pcm_substream_chip(substream);
1065 struct snd_pcm_runtime *runtime = substream->runtime;
1066 unsigned long flags;
1067 unsigned int size = snd_pcm_lib_buffer_bytes(substream);
1068 unsigned int count = snd_pcm_lib_period_bytes(substream);
1069
1070 spin_lock_irqsave(&chip->reg_lock, flags);
1071 chip->c_dma_size = size;
1072 chip->image[CS4231_IFACE_CTRL] &= ~(CS4231_RECORD_ENABLE | CS4231_RECORD_PIO);
1073 snd_dma_program(chip->dma2, runtime->dma_addr, size, DMA_MODE_READ | DMA_AUTOINIT);
1074 if (chip->hardware & WSS_HW_AD1848_MASK)
1075 count = snd_wss_get_count(chip->image[CS4231_PLAYBK_FORMAT],
1076 count);
1077 else
1078 count = snd_wss_get_count(chip->image[CS4231_REC_FORMAT],
1079 count);
1080 count--;
1081 if (chip->single_dma && chip->hardware != WSS_HW_INTERWAVE) {
1082 snd_wss_out(chip, CS4231_PLY_LWR_CNT, (unsigned char) count);
1083 snd_wss_out(chip, CS4231_PLY_UPR_CNT,
1084 (unsigned char) (count >> 8));
1085 } else {
1086 snd_wss_out(chip, CS4231_REC_LWR_CNT, (unsigned char) count);
1087 snd_wss_out(chip, CS4231_REC_UPR_CNT,
1088 (unsigned char) (count >> 8));
1089 }
1090 spin_unlock_irqrestore(&chip->reg_lock, flags);
1091 return 0;
1092 }
1093
1094 void snd_wss_overrange(struct snd_wss *chip)
1095 {
1096 unsigned long flags;
1097 unsigned char res;
1098
1099 spin_lock_irqsave(&chip->reg_lock, flags);
1100 res = snd_wss_in(chip, CS4231_TEST_INIT);
1101 spin_unlock_irqrestore(&chip->reg_lock, flags);
1102 if (res & (0x08 | 0x02)) /* detect overrange only above 0dB; may be user selectable? */
1103 chip->capture_substream->runtime->overrange++;
1104 }
1105 EXPORT_SYMBOL(snd_wss_overrange);
1106
1107 irqreturn_t snd_wss_interrupt(int irq, void *dev_id)
1108 {
1109 struct snd_wss *chip = dev_id;
1110 unsigned char status;
1111
1112 if (chip->hardware & WSS_HW_AD1848_MASK)
1113 /* pretend it was the only possible irq for AD1848 */
1114 status = CS4231_PLAYBACK_IRQ;
1115 else
1116 status = snd_wss_in(chip, CS4231_IRQ_STATUS);
1117 if (status & CS4231_TIMER_IRQ) {
1118 if (chip->timer)
1119 snd_timer_interrupt(chip->timer, chip->timer->sticks);
1120 }
1121 if (chip->single_dma && chip->hardware != WSS_HW_INTERWAVE) {
1122 if (status & CS4231_PLAYBACK_IRQ) {
1123 if (chip->mode & WSS_MODE_PLAY) {
1124 if (chip->playback_substream)
1125 snd_pcm_period_elapsed(chip->playback_substream);
1126 }
1127 if (chip->mode & WSS_MODE_RECORD) {
1128 if (chip->capture_substream) {
1129 snd_wss_overrange(chip);
1130 snd_pcm_period_elapsed(chip->capture_substream);
1131 }
1132 }
1133 }
1134 } else {
1135 if (status & CS4231_PLAYBACK_IRQ) {
1136 if (chip->playback_substream)
1137 snd_pcm_period_elapsed(chip->playback_substream);
1138 }
1139 if (status & CS4231_RECORD_IRQ) {
1140 if (chip->capture_substream) {
1141 snd_wss_overrange(chip);
1142 snd_pcm_period_elapsed(chip->capture_substream);
1143 }
1144 }
1145 }
1146
1147 spin_lock(&chip->reg_lock);
1148 status = ~CS4231_ALL_IRQS | ~status;
1149 if (chip->hardware & WSS_HW_AD1848_MASK)
1150 wss_outb(chip, CS4231P(STATUS), 0);
1151 else
1152 snd_wss_outm(chip, CS4231_IRQ_STATUS, status, 0);
1153 spin_unlock(&chip->reg_lock);
1154 return IRQ_HANDLED;
1155 }
1156 EXPORT_SYMBOL(snd_wss_interrupt);
1157
1158 static snd_pcm_uframes_t snd_wss_playback_pointer(struct snd_pcm_substream *substream)
1159 {
1160 struct snd_wss *chip = snd_pcm_substream_chip(substream);
1161 size_t ptr;
1162
1163 if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_PLAYBACK_ENABLE))
1164 return 0;
1165 ptr = snd_dma_pointer(chip->dma1, chip->p_dma_size);
1166 return bytes_to_frames(substream->runtime, ptr);
1167 }
1168
1169 static snd_pcm_uframes_t snd_wss_capture_pointer(struct snd_pcm_substream *substream)
1170 {
1171 struct snd_wss *chip = snd_pcm_substream_chip(substream);
1172 size_t ptr;
1173
1174 if (!(chip->image[CS4231_IFACE_CTRL] & CS4231_RECORD_ENABLE))
1175 return 0;
1176 ptr = snd_dma_pointer(chip->dma2, chip->c_dma_size);
1177 return bytes_to_frames(substream->runtime, ptr);
1178 }
1179
1180 /*
1181
1182 */
1183
1184 static int snd_ad1848_probe(struct snd_wss *chip)
1185 {
1186 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1187 unsigned long flags;
1188 unsigned char r;
1189 unsigned short hardware = 0;
1190 int err = 0;
1191 int i;
1192
1193 while (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT) {
1194 if (time_after(jiffies, timeout))
1195 return -ENODEV;
1196 cond_resched();
1197 }
1198 spin_lock_irqsave(&chip->reg_lock, flags);
1199
1200 /* set CS423x MODE 1 */
1201 snd_wss_dout(chip, CS4231_MISC_INFO, 0);
1202
1203 snd_wss_dout(chip, CS4231_RIGHT_INPUT, 0x45); /* 0x55 & ~0x10 */
1204 r = snd_wss_in(chip, CS4231_RIGHT_INPUT);
1205 if (r != 0x45) {
1206 /* RMGE always high on AD1847 */
1207 if ((r & ~CS4231_ENABLE_MIC_GAIN) != 0x45) {
1208 err = -ENODEV;
1209 goto out;
1210 }
1211 hardware = WSS_HW_AD1847;
1212 } else {
1213 snd_wss_dout(chip, CS4231_LEFT_INPUT, 0xaa);
1214 r = snd_wss_in(chip, CS4231_LEFT_INPUT);
1215 /* L/RMGE always low on AT2320 */
1216 if ((r | CS4231_ENABLE_MIC_GAIN) != 0xaa) {
1217 err = -ENODEV;
1218 goto out;
1219 }
1220 }
1221
1222 /* clear pending IRQ */
1223 wss_inb(chip, CS4231P(STATUS));
1224 wss_outb(chip, CS4231P(STATUS), 0);
1225 mb();
1226
1227 if ((chip->hardware & WSS_HW_TYPE_MASK) != WSS_HW_DETECT)
1228 goto out;
1229
1230 if (hardware) {
1231 chip->hardware = hardware;
1232 goto out;
1233 }
1234
1235 r = snd_wss_in(chip, CS4231_MISC_INFO);
1236
1237 /* set CS423x MODE 2 */
1238 snd_wss_dout(chip, CS4231_MISC_INFO, CS4231_MODE2);
1239 for (i = 0; i < 16; i++) {
1240 if (snd_wss_in(chip, i) != snd_wss_in(chip, 16 + i)) {
1241 /* we have more than 16 registers: check ID */
1242 if ((r & 0xf) != 0xa)
1243 goto out_mode;
1244 /*
1245 * on CMI8330, CS4231_VERSION is volume control and
1246 * can be set to 0
1247 */
1248 snd_wss_dout(chip, CS4231_VERSION, 0);
1249 r = snd_wss_in(chip, CS4231_VERSION) & 0xe7;
1250 if (!r)
1251 chip->hardware = WSS_HW_CMI8330;
1252 goto out_mode;
1253 }
1254 }
1255 if (r & 0x80)
1256 chip->hardware = WSS_HW_CS4248;
1257 else
1258 chip->hardware = WSS_HW_AD1848;
1259 out_mode:
1260 snd_wss_dout(chip, CS4231_MISC_INFO, 0);
1261 out:
1262 spin_unlock_irqrestore(&chip->reg_lock, flags);
1263 return err;
1264 }
1265
1266 static int snd_wss_probe(struct snd_wss *chip)
1267 {
1268 unsigned long flags;
1269 int i, id, rev, regnum;
1270 unsigned char *ptr;
1271 unsigned int hw;
1272
1273 id = snd_ad1848_probe(chip);
1274 if (id < 0)
1275 return id;
1276
1277 hw = chip->hardware;
1278 if ((hw & WSS_HW_TYPE_MASK) == WSS_HW_DETECT) {
1279 for (i = 0; i < 50; i++) {
1280 mb();
1281 if (wss_inb(chip, CS4231P(REGSEL)) & CS4231_INIT)
1282 msleep(2);
1283 else {
1284 spin_lock_irqsave(&chip->reg_lock, flags);
1285 snd_wss_out(chip, CS4231_MISC_INFO,
1286 CS4231_MODE2);
1287 id = snd_wss_in(chip, CS4231_MISC_INFO) & 0x0f;
1288 spin_unlock_irqrestore(&chip->reg_lock, flags);
1289 if (id == 0x0a)
1290 break; /* this is valid value */
1291 }
1292 }
1293 snd_printdd("wss: port = 0x%lx, id = 0x%x\n", chip->port, id);
1294 if (id != 0x0a)
1295 return -ENODEV; /* no valid device found */
1296
1297 rev = snd_wss_in(chip, CS4231_VERSION) & 0xe7;
1298 snd_printdd("CS4231: VERSION (I25) = 0x%x\n", rev);
1299 if (rev == 0x80) {
1300 unsigned char tmp = snd_wss_in(chip, 23);
1301 snd_wss_out(chip, 23, ~tmp);
1302 if (snd_wss_in(chip, 23) != tmp)
1303 chip->hardware = WSS_HW_AD1845;
1304 else
1305 chip->hardware = WSS_HW_CS4231;
1306 } else if (rev == 0xa0) {
1307 chip->hardware = WSS_HW_CS4231A;
1308 } else if (rev == 0xa2) {
1309 chip->hardware = WSS_HW_CS4232;
1310 } else if (rev == 0xb2) {
1311 chip->hardware = WSS_HW_CS4232A;
1312 } else if (rev == 0x83) {
1313 chip->hardware = WSS_HW_CS4236;
1314 } else if (rev == 0x03) {
1315 chip->hardware = WSS_HW_CS4236B;
1316 } else {
1317 snd_printk("unknown CS chip with version 0x%x\n", rev);
1318 return -ENODEV; /* unknown CS4231 chip? */
1319 }
1320 }
1321 spin_lock_irqsave(&chip->reg_lock, flags);
1322 wss_inb(chip, CS4231P(STATUS)); /* clear any pendings IRQ */
1323 wss_outb(chip, CS4231P(STATUS), 0);
1324 mb();
1325 spin_unlock_irqrestore(&chip->reg_lock, flags);
1326
1327 if (!(chip->hardware & WSS_HW_AD1848_MASK))
1328 chip->image[CS4231_MISC_INFO] = CS4231_MODE2;
1329 switch (chip->hardware) {
1330 case WSS_HW_INTERWAVE:
1331 chip->image[CS4231_MISC_INFO] = CS4231_IW_MODE3;
1332 break;
1333 case WSS_HW_CS4235:
1334 case WSS_HW_CS4236B:
1335 case WSS_HW_CS4237B:
1336 case WSS_HW_CS4238B:
1337 case WSS_HW_CS4239:
1338 if (hw == WSS_HW_DETECT3)
1339 chip->image[CS4231_MISC_INFO] = CS4231_4236_MODE3;
1340 else
1341 chip->hardware = WSS_HW_CS4236;
1342 break;
1343 }
1344
1345 chip->image[CS4231_IFACE_CTRL] =
1346 (chip->image[CS4231_IFACE_CTRL] & ~CS4231_SINGLE_DMA) |
1347 (chip->single_dma ? CS4231_SINGLE_DMA : 0);
1348 if (chip->hardware != WSS_HW_OPTI93X) {
1349 chip->image[CS4231_ALT_FEATURE_1] = 0x80;
1350 chip->image[CS4231_ALT_FEATURE_2] =
1351 chip->hardware == WSS_HW_INTERWAVE ? 0xc2 : 0x01;
1352 }
1353 /* enable fine grained frequency selection */
1354 if (chip->hardware == WSS_HW_AD1845)
1355 chip->image[AD1845_PWR_DOWN] = 8;
1356
1357 ptr = (unsigned char *) &chip->image;
1358 regnum = (chip->hardware & WSS_HW_AD1848_MASK) ? 16 : 32;
1359 snd_wss_mce_down(chip);
1360 spin_lock_irqsave(&chip->reg_lock, flags);
1361 for (i = 0; i < regnum; i++) /* ok.. fill all registers */
1362 snd_wss_out(chip, i, *ptr++);
1363 spin_unlock_irqrestore(&chip->reg_lock, flags);
1364 snd_wss_mce_up(chip);
1365 snd_wss_mce_down(chip);
1366
1367 mdelay(2);
1368
1369 /* ok.. try check hardware version for CS4236+ chips */
1370 if ((hw & WSS_HW_TYPE_MASK) == WSS_HW_DETECT) {
1371 if (chip->hardware == WSS_HW_CS4236B) {
1372 rev = snd_cs4236_ext_in(chip, CS4236_VERSION);
1373 snd_cs4236_ext_out(chip, CS4236_VERSION, 0xff);
1374 id = snd_cs4236_ext_in(chip, CS4236_VERSION);
1375 snd_cs4236_ext_out(chip, CS4236_VERSION, rev);
1376 snd_printdd("CS4231: ext version; rev = 0x%x, id = 0x%x\n", rev, id);
1377 if ((id & 0x1f) == 0x1d) { /* CS4235 */
1378 chip->hardware = WSS_HW_CS4235;
1379 switch (id >> 5) {
1380 case 4:
1381 case 5:
1382 case 6:
1383 break;
1384 default:
1385 snd_printk("unknown CS4235 chip (enhanced version = 0x%x)\n", id);
1386 }
1387 } else if ((id & 0x1f) == 0x0b) { /* CS4236/B */
1388 switch (id >> 5) {
1389 case 4:
1390 case 5:
1391 case 6:
1392 case 7:
1393 chip->hardware = WSS_HW_CS4236B;
1394 break;
1395 default:
1396 snd_printk("unknown CS4236 chip (enhanced version = 0x%x)\n", id);
1397 }
1398 } else if ((id & 0x1f) == 0x08) { /* CS4237B */
1399 chip->hardware = WSS_HW_CS4237B;
1400 switch (id >> 5) {
1401 case 4:
1402 case 5:
1403 case 6:
1404 case 7:
1405 break;
1406 default:
1407 snd_printk("unknown CS4237B chip (enhanced version = 0x%x)\n", id);
1408 }
1409 } else if ((id & 0x1f) == 0x09) { /* CS4238B */
1410 chip->hardware = WSS_HW_CS4238B;
1411 switch (id >> 5) {
1412 case 5:
1413 case 6:
1414 case 7:
1415 break;
1416 default:
1417 snd_printk("unknown CS4238B chip (enhanced version = 0x%x)\n", id);
1418 }
1419 } else if ((id & 0x1f) == 0x1e) { /* CS4239 */
1420 chip->hardware = WSS_HW_CS4239;
1421 switch (id >> 5) {
1422 case 4:
1423 case 5:
1424 case 6:
1425 break;
1426 default:
1427 snd_printk("unknown CS4239 chip (enhanced version = 0x%x)\n", id);
1428 }
1429 } else {
1430 snd_printk("unknown CS4236/CS423xB chip (enhanced version = 0x%x)\n", id);
1431 }
1432 }
1433 }
1434 return 0; /* all things are ok.. */
1435 }
1436
1437 /*
1438
1439 */
1440
1441 static struct snd_pcm_hardware snd_wss_playback =
1442 {
1443 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1444 SNDRV_PCM_INFO_MMAP_VALID |
1445 SNDRV_PCM_INFO_RESUME |
1446 SNDRV_PCM_INFO_SYNC_START),
1447 .formats = (SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW | SNDRV_PCM_FMTBIT_IMA_ADPCM |
1448 SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE),
1449 .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
1450 .rate_min = 5510,
1451 .rate_max = 48000,
1452 .channels_min = 1,
1453 .channels_max = 2,
1454 .buffer_bytes_max = (128*1024),
1455 .period_bytes_min = 64,
1456 .period_bytes_max = (128*1024),
1457 .periods_min = 1,
1458 .periods_max = 1024,
1459 .fifo_size = 0,
1460 };
1461
1462 static struct snd_pcm_hardware snd_wss_capture =
1463 {
1464 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
1465 SNDRV_PCM_INFO_MMAP_VALID |
1466 SNDRV_PCM_INFO_RESUME |
1467 SNDRV_PCM_INFO_SYNC_START),
1468 .formats = (SNDRV_PCM_FMTBIT_MU_LAW | SNDRV_PCM_FMTBIT_A_LAW | SNDRV_PCM_FMTBIT_IMA_ADPCM |
1469 SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE),
1470 .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
1471 .rate_min = 5510,
1472 .rate_max = 48000,
1473 .channels_min = 1,
1474 .channels_max = 2,
1475 .buffer_bytes_max = (128*1024),
1476 .period_bytes_min = 64,
1477 .period_bytes_max = (128*1024),
1478 .periods_min = 1,
1479 .periods_max = 1024,
1480 .fifo_size = 0,
1481 };
1482
1483 /*
1484
1485 */
1486
1487 static int snd_wss_playback_open(struct snd_pcm_substream *substream)
1488 {
1489 struct snd_wss *chip = snd_pcm_substream_chip(substream);
1490 struct snd_pcm_runtime *runtime = substream->runtime;
1491 int err;
1492
1493 runtime->hw = snd_wss_playback;
1494
1495 /* hardware limitation of older chipsets */
1496 if (chip->hardware & WSS_HW_AD1848_MASK)
1497 runtime->hw.formats &= ~(SNDRV_PCM_FMTBIT_IMA_ADPCM |
1498 SNDRV_PCM_FMTBIT_S16_BE);
1499
1500 /* hardware bug in InterWave chipset */
1501 if (chip->hardware == WSS_HW_INTERWAVE && chip->dma1 > 3)
1502 runtime->hw.formats &= ~SNDRV_PCM_FMTBIT_MU_LAW;
1503
1504 /* hardware limitation of cheap chips */
1505 if (chip->hardware == WSS_HW_CS4235 ||
1506 chip->hardware == WSS_HW_CS4239)
1507 runtime->hw.formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE;
1508
1509 snd_pcm_limit_isa_dma_size(chip->dma1, &runtime->hw.buffer_bytes_max);
1510 snd_pcm_limit_isa_dma_size(chip->dma1, &runtime->hw.period_bytes_max);
1511
1512 if (chip->claim_dma) {
1513 if ((err = chip->claim_dma(chip, chip->dma_private_data, chip->dma1)) < 0)
1514 return err;
1515 }
1516
1517 err = snd_wss_open(chip, WSS_MODE_PLAY);
1518 if (err < 0) {
1519 if (chip->release_dma)
1520 chip->release_dma(chip, chip->dma_private_data, chip->dma1);
1521 snd_free_pages(runtime->dma_area, runtime->dma_bytes);
1522 return err;
1523 }
1524 chip->playback_substream = substream;
1525 snd_pcm_set_sync(substream);
1526 chip->rate_constraint(runtime);
1527 return 0;
1528 }
1529
1530 static int snd_wss_capture_open(struct snd_pcm_substream *substream)
1531 {
1532 struct snd_wss *chip = snd_pcm_substream_chip(substream);
1533 struct snd_pcm_runtime *runtime = substream->runtime;
1534 int err;
1535
1536 runtime->hw = snd_wss_capture;
1537
1538 /* hardware limitation of older chipsets */
1539 if (chip->hardware & WSS_HW_AD1848_MASK)
1540 runtime->hw.formats &= ~(SNDRV_PCM_FMTBIT_IMA_ADPCM |
1541 SNDRV_PCM_FMTBIT_S16_BE);
1542
1543 /* hardware limitation of cheap chips */
1544 if (chip->hardware == WSS_HW_CS4235 ||
1545 chip->hardware == WSS_HW_CS4239 ||
1546 chip->hardware == WSS_HW_OPTI93X)
1547 runtime->hw.formats = SNDRV_PCM_FMTBIT_U8 |
1548 SNDRV_PCM_FMTBIT_S16_LE;
1549
1550 snd_pcm_limit_isa_dma_size(chip->dma2, &runtime->hw.buffer_bytes_max);
1551 snd_pcm_limit_isa_dma_size(chip->dma2, &runtime->hw.period_bytes_max);
1552
1553 if (chip->claim_dma) {
1554 if ((err = chip->claim_dma(chip, chip->dma_private_data, chip->dma2)) < 0)
1555 return err;
1556 }
1557
1558 err = snd_wss_open(chip, WSS_MODE_RECORD);
1559 if (err < 0) {
1560 if (chip->release_dma)
1561 chip->release_dma(chip, chip->dma_private_data, chip->dma2);
1562 snd_free_pages(runtime->dma_area, runtime->dma_bytes);
1563 return err;
1564 }
1565 chip->capture_substream = substream;
1566 snd_pcm_set_sync(substream);
1567 chip->rate_constraint(runtime);
1568 return 0;
1569 }
1570
1571 static int snd_wss_playback_close(struct snd_pcm_substream *substream)
1572 {
1573 struct snd_wss *chip = snd_pcm_substream_chip(substream);
1574
1575 chip->playback_substream = NULL;
1576 snd_wss_close(chip, WSS_MODE_PLAY);
1577 return 0;
1578 }
1579
1580 static int snd_wss_capture_close(struct snd_pcm_substream *substream)
1581 {
1582 struct snd_wss *chip = snd_pcm_substream_chip(substream);
1583
1584 chip->capture_substream = NULL;
1585 snd_wss_close(chip, WSS_MODE_RECORD);
1586 return 0;
1587 }
1588
1589 static void snd_wss_thinkpad_twiddle(struct snd_wss *chip, int on)
1590 {
1591 int tmp;
1592
1593 if (!chip->thinkpad_flag)
1594 return;
1595
1596 outb(0x1c, AD1848_THINKPAD_CTL_PORT1);
1597 tmp = inb(AD1848_THINKPAD_CTL_PORT2);
1598
1599 if (on)
1600 /* turn it on */
1601 tmp |= AD1848_THINKPAD_CS4248_ENABLE_BIT;
1602 else
1603 /* turn it off */
1604 tmp &= ~AD1848_THINKPAD_CS4248_ENABLE_BIT;
1605
1606 outb(tmp, AD1848_THINKPAD_CTL_PORT2);
1607 }
1608
1609 #ifdef CONFIG_PM
1610
1611 /* lowlevel suspend callback for CS4231 */
1612 static void snd_wss_suspend(struct snd_wss *chip)
1613 {
1614 int reg;
1615 unsigned long flags;
1616
1617 snd_pcm_suspend_all(chip->pcm);
1618 spin_lock_irqsave(&chip->reg_lock, flags);
1619 for (reg = 0; reg < 32; reg++)
1620 chip->image[reg] = snd_wss_in(chip, reg);
1621 spin_unlock_irqrestore(&chip->reg_lock, flags);
1622 if (chip->thinkpad_flag)
1623 snd_wss_thinkpad_twiddle(chip, 0);
1624 }
1625
1626 /* lowlevel resume callback for CS4231 */
1627 static void snd_wss_resume(struct snd_wss *chip)
1628 {
1629 int reg;
1630 unsigned long flags;
1631 /* int timeout; */
1632
1633 if (chip->thinkpad_flag)
1634 snd_wss_thinkpad_twiddle(chip, 1);
1635 snd_wss_mce_up(chip);
1636 spin_lock_irqsave(&chip->reg_lock, flags);
1637 for (reg = 0; reg < 32; reg++) {
1638 switch (reg) {
1639 case CS4231_VERSION:
1640 break;
1641 default:
1642 snd_wss_out(chip, reg, chip->image[reg]);
1643 break;
1644 }
1645 }
1646 spin_unlock_irqrestore(&chip->reg_lock, flags);
1647 #if 1
1648 snd_wss_mce_down(chip);
1649 #else
1650 /* The following is a workaround to avoid freeze after resume on TP600E.
1651 This is the first half of copy of snd_wss_mce_down(), but doesn't
1652 include rescheduling. -- iwai
1653 */
1654 snd_wss_busy_wait(chip);
1655 spin_lock_irqsave(&chip->reg_lock, flags);
1656 chip->mce_bit &= ~CS4231_MCE;
1657 timeout = wss_inb(chip, CS4231P(REGSEL));
1658 wss_outb(chip, CS4231P(REGSEL), chip->mce_bit | (timeout & 0x1f));
1659 spin_unlock_irqrestore(&chip->reg_lock, flags);
1660 if (timeout == 0x80)
1661 snd_printk("down [0x%lx]: serious init problem - codec still busy\n", chip->port);
1662 if ((timeout & CS4231_MCE) == 0 ||
1663 !(chip->hardware & (WSS_HW_CS4231_MASK | WSS_HW_CS4232_MASK))) {
1664 return;
1665 }
1666 snd_wss_busy_wait(chip);
1667 #endif
1668 }
1669 #endif /* CONFIG_PM */
1670
1671 static int snd_wss_free(struct snd_wss *chip)
1672 {
1673 release_and_free_resource(chip->res_port);
1674 release_and_free_resource(chip->res_cport);
1675 if (chip->irq >= 0) {
1676 disable_irq(chip->irq);
1677 if (!(chip->hwshare & WSS_HWSHARE_IRQ))
1678 free_irq(chip->irq, (void *) chip);
1679 }
1680 if (!(chip->hwshare & WSS_HWSHARE_DMA1) && chip->dma1 >= 0) {
1681 snd_dma_disable(chip->dma1);
1682 free_dma(chip->dma1);
1683 }
1684 if (!(chip->hwshare & WSS_HWSHARE_DMA2) &&
1685 chip->dma2 >= 0 && chip->dma2 != chip->dma1) {
1686 snd_dma_disable(chip->dma2);
1687 free_dma(chip->dma2);
1688 }
1689 if (chip->timer)
1690 snd_device_free(chip->card, chip->timer);
1691 kfree(chip);
1692 return 0;
1693 }
1694
1695 static int snd_wss_dev_free(struct snd_device *device)
1696 {
1697 struct snd_wss *chip = device->device_data;
1698 return snd_wss_free(chip);
1699 }
1700
1701 const char *snd_wss_chip_id(struct snd_wss *chip)
1702 {
1703 switch (chip->hardware) {
1704 case WSS_HW_CS4231:
1705 return "CS4231";
1706 case WSS_HW_CS4231A:
1707 return "CS4231A";
1708 case WSS_HW_CS4232:
1709 return "CS4232";
1710 case WSS_HW_CS4232A:
1711 return "CS4232A";
1712 case WSS_HW_CS4235:
1713 return "CS4235";
1714 case WSS_HW_CS4236:
1715 return "CS4236";
1716 case WSS_HW_CS4236B:
1717 return "CS4236B";
1718 case WSS_HW_CS4237B:
1719 return "CS4237B";
1720 case WSS_HW_CS4238B:
1721 return "CS4238B";
1722 case WSS_HW_CS4239:
1723 return "CS4239";
1724 case WSS_HW_INTERWAVE:
1725 return "AMD InterWave";
1726 case WSS_HW_OPL3SA2:
1727 return chip->card->shortname;
1728 case WSS_HW_AD1845:
1729 return "AD1845";
1730 case WSS_HW_OPTI93X:
1731 return "OPTi 93x";
1732 case WSS_HW_AD1847:
1733 return "AD1847";
1734 case WSS_HW_AD1848:
1735 return "AD1848";
1736 case WSS_HW_CS4248:
1737 return "CS4248";
1738 case WSS_HW_CMI8330:
1739 return "CMI8330/C3D";
1740 default:
1741 return "???";
1742 }
1743 }
1744 EXPORT_SYMBOL(snd_wss_chip_id);
1745
1746 static int snd_wss_new(struct snd_card *card,
1747 unsigned short hardware,
1748 unsigned short hwshare,
1749 struct snd_wss **rchip)
1750 {
1751 struct snd_wss *chip;
1752
1753 *rchip = NULL;
1754 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1755 if (chip == NULL)
1756 return -ENOMEM;
1757 chip->hardware = hardware;
1758 chip->hwshare = hwshare;
1759
1760 spin_lock_init(&chip->reg_lock);
1761 mutex_init(&chip->mce_mutex);
1762 mutex_init(&chip->open_mutex);
1763 chip->card = card;
1764 chip->rate_constraint = snd_wss_xrate;
1765 chip->set_playback_format = snd_wss_playback_format;
1766 chip->set_capture_format = snd_wss_capture_format;
1767 if (chip->hardware == WSS_HW_OPTI93X)
1768 memcpy(&chip->image, &snd_opti93x_original_image,
1769 sizeof(snd_opti93x_original_image));
1770 else
1771 memcpy(&chip->image, &snd_wss_original_image,
1772 sizeof(snd_wss_original_image));
1773 if (chip->hardware & WSS_HW_AD1848_MASK) {
1774 chip->image[CS4231_PIN_CTRL] = 0;
1775 chip->image[CS4231_TEST_INIT] = 0;
1776 }
1777
1778 *rchip = chip;
1779 return 0;
1780 }
1781
1782 int snd_wss_create(struct snd_card *card,
1783 unsigned long port,
1784 unsigned long cport,
1785 int irq, int dma1, int dma2,
1786 unsigned short hardware,
1787 unsigned short hwshare,
1788 struct snd_wss **rchip)
1789 {
1790 static struct snd_device_ops ops = {
1791 .dev_free = snd_wss_dev_free,
1792 };
1793 struct snd_wss *chip;
1794 int err;
1795
1796 err = snd_wss_new(card, hardware, hwshare, &chip);
1797 if (err < 0)
1798 return err;
1799
1800 chip->irq = -1;
1801 chip->dma1 = -1;
1802 chip->dma2 = -1;
1803
1804 chip->res_port = request_region(port, 4, "WSS");
1805 if (!chip->res_port) {
1806 snd_printk(KERN_ERR "wss: can't grab port 0x%lx\n", port);
1807 snd_wss_free(chip);
1808 return -EBUSY;
1809 }
1810 chip->port = port;
1811 if ((long)cport >= 0) {
1812 chip->res_cport = request_region(cport, 8, "CS4232 Control");
1813 if (!chip->res_cport) {
1814 snd_printk(KERN_ERR
1815 "wss: can't grab control port 0x%lx\n", cport);
1816 snd_wss_free(chip);
1817 return -ENODEV;
1818 }
1819 }
1820 chip->cport = cport;
1821 if (!(hwshare & WSS_HWSHARE_IRQ))
1822 if (request_irq(irq, snd_wss_interrupt, IRQF_DISABLED,
1823 "WSS", (void *) chip)) {
1824 snd_printk(KERN_ERR "wss: can't grab IRQ %d\n", irq);
1825 snd_wss_free(chip);
1826 return -EBUSY;
1827 }
1828 chip->irq = irq;
1829 if (!(hwshare & WSS_HWSHARE_DMA1) && request_dma(dma1, "WSS - 1")) {
1830 snd_printk(KERN_ERR "wss: can't grab DMA1 %d\n", dma1);
1831 snd_wss_free(chip);
1832 return -EBUSY;
1833 }
1834 chip->dma1 = dma1;
1835 if (!(hwshare & WSS_HWSHARE_DMA2) && dma1 != dma2 &&
1836 dma2 >= 0 && request_dma(dma2, "WSS - 2")) {
1837 snd_printk(KERN_ERR "wss: can't grab DMA2 %d\n", dma2);
1838 snd_wss_free(chip);
1839 return -EBUSY;
1840 }
1841 if (dma1 == dma2 || dma2 < 0) {
1842 chip->single_dma = 1;
1843 chip->dma2 = chip->dma1;
1844 } else
1845 chip->dma2 = dma2;
1846
1847 if (hardware == WSS_HW_THINKPAD) {
1848 chip->thinkpad_flag = 1;
1849 chip->hardware = WSS_HW_DETECT; /* reset */
1850 snd_wss_thinkpad_twiddle(chip, 1);
1851 }
1852
1853 /* global setup */
1854 if (snd_wss_probe(chip) < 0) {
1855 snd_wss_free(chip);
1856 return -ENODEV;
1857 }
1858 snd_wss_init(chip);
1859
1860 #if 0
1861 if (chip->hardware & WSS_HW_CS4232_MASK) {
1862 if (chip->res_cport == NULL)
1863 snd_printk("CS4232 control port features are not accessible\n");
1864 }
1865 #endif
1866
1867 /* Register device */
1868 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1869 if (err < 0) {
1870 snd_wss_free(chip);
1871 return err;
1872 }
1873
1874 #ifdef CONFIG_PM
1875 /* Power Management */
1876 chip->suspend = snd_wss_suspend;
1877 chip->resume = snd_wss_resume;
1878 #endif
1879
1880 *rchip = chip;
1881 return 0;
1882 }
1883 EXPORT_SYMBOL(snd_wss_create);
1884
1885 static struct snd_pcm_ops snd_wss_playback_ops = {
1886 .open = snd_wss_playback_open,
1887 .close = snd_wss_playback_close,
1888 .ioctl = snd_pcm_lib_ioctl,
1889 .hw_params = snd_wss_playback_hw_params,
1890 .hw_free = snd_wss_playback_hw_free,
1891 .prepare = snd_wss_playback_prepare,
1892 .trigger = snd_wss_trigger,
1893 .pointer = snd_wss_playback_pointer,
1894 };
1895
1896 static struct snd_pcm_ops snd_wss_capture_ops = {
1897 .open = snd_wss_capture_open,
1898 .close = snd_wss_capture_close,
1899 .ioctl = snd_pcm_lib_ioctl,
1900 .hw_params = snd_wss_capture_hw_params,
1901 .hw_free = snd_wss_capture_hw_free,
1902 .prepare = snd_wss_capture_prepare,
1903 .trigger = snd_wss_trigger,
1904 .pointer = snd_wss_capture_pointer,
1905 };
1906
1907 int snd_wss_pcm(struct snd_wss *chip, int device, struct snd_pcm **rpcm)
1908 {
1909 struct snd_pcm *pcm;
1910 int err;
1911
1912 err = snd_pcm_new(chip->card, "WSS", device, 1, 1, &pcm);
1913 if (err < 0)
1914 return err;
1915
1916 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_wss_playback_ops);
1917 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_wss_capture_ops);
1918
1919 /* global setup */
1920 pcm->private_data = chip;
1921 pcm->info_flags = 0;
1922 if (chip->single_dma)
1923 pcm->info_flags |= SNDRV_PCM_INFO_HALF_DUPLEX;
1924 if (chip->hardware != WSS_HW_INTERWAVE)
1925 pcm->info_flags |= SNDRV_PCM_INFO_JOINT_DUPLEX;
1926 strcpy(pcm->name, snd_wss_chip_id(chip));
1927
1928 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1929 snd_dma_isa_data(),
1930 64*1024, chip->dma1 > 3 || chip->dma2 > 3 ? 128*1024 : 64*1024);
1931
1932 chip->pcm = pcm;
1933 if (rpcm)
1934 *rpcm = pcm;
1935 return 0;
1936 }
1937 EXPORT_SYMBOL(snd_wss_pcm);
1938
1939 static void snd_wss_timer_free(struct snd_timer *timer)
1940 {
1941 struct snd_wss *chip = timer->private_data;
1942 chip->timer = NULL;
1943 }
1944
1945 int snd_wss_timer(struct snd_wss *chip, int device, struct snd_timer **rtimer)
1946 {
1947 struct snd_timer *timer;
1948 struct snd_timer_id tid;
1949 int err;
1950
1951 /* Timer initialization */
1952 tid.dev_class = SNDRV_TIMER_CLASS_CARD;
1953 tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;
1954 tid.card = chip->card->number;
1955 tid.device = device;
1956 tid.subdevice = 0;
1957 if ((err = snd_timer_new(chip->card, "CS4231", &tid, &timer)) < 0)
1958 return err;
1959 strcpy(timer->name, snd_wss_chip_id(chip));
1960 timer->private_data = chip;
1961 timer->private_free = snd_wss_timer_free;
1962 timer->hw = snd_wss_timer_table;
1963 chip->timer = timer;
1964 if (rtimer)
1965 *rtimer = timer;
1966 return 0;
1967 }
1968 EXPORT_SYMBOL(snd_wss_timer);
1969
1970 /*
1971 * MIXER part
1972 */
1973
1974 static int snd_wss_info_mux(struct snd_kcontrol *kcontrol,
1975 struct snd_ctl_elem_info *uinfo)
1976 {
1977 static char *texts[4] = {
1978 "Line", "Aux", "Mic", "Mix"
1979 };
1980 static char *opl3sa_texts[4] = {
1981 "Line", "CD", "Mic", "Mix"
1982 };
1983 static char *gusmax_texts[4] = {
1984 "Line", "Synth", "Mic", "Mix"
1985 };
1986 char **ptexts = texts;
1987 struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
1988
1989 if (snd_BUG_ON(!chip->card))
1990 return -EINVAL;
1991 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1992 uinfo->count = 2;
1993 uinfo->value.enumerated.items = 4;
1994 if (uinfo->value.enumerated.item > 3)
1995 uinfo->value.enumerated.item = 3;
1996 if (!strcmp(chip->card->driver, "GUS MAX"))
1997 ptexts = gusmax_texts;
1998 switch (chip->hardware) {
1999 case WSS_HW_INTERWAVE:
2000 ptexts = gusmax_texts;
2001 break;
2002 case WSS_HW_OPL3SA2:
2003 ptexts = opl3sa_texts;
2004 break;
2005 }
2006 strcpy(uinfo->value.enumerated.name, ptexts[uinfo->value.enumerated.item]);
2007 return 0;
2008 }
2009
2010 static int snd_wss_get_mux(struct snd_kcontrol *kcontrol,
2011 struct snd_ctl_elem_value *ucontrol)
2012 {
2013 struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
2014 unsigned long flags;
2015
2016 spin_lock_irqsave(&chip->reg_lock, flags);
2017 ucontrol->value.enumerated.item[0] = (chip->image[CS4231_LEFT_INPUT] & CS4231_MIXS_ALL) >> 6;
2018 ucontrol->value.enumerated.item[1] = (chip->image[CS4231_RIGHT_INPUT] & CS4231_MIXS_ALL) >> 6;
2019 spin_unlock_irqrestore(&chip->reg_lock, flags);
2020 return 0;
2021 }
2022
2023 static int snd_wss_put_mux(struct snd_kcontrol *kcontrol,
2024 struct snd_ctl_elem_value *ucontrol)
2025 {
2026 struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
2027 unsigned long flags;
2028 unsigned short left, right;
2029 int change;
2030
2031 if (ucontrol->value.enumerated.item[0] > 3 ||
2032 ucontrol->value.enumerated.item[1] > 3)
2033 return -EINVAL;
2034 left = ucontrol->value.enumerated.item[0] << 6;
2035 right = ucontrol->value.enumerated.item[1] << 6;
2036 spin_lock_irqsave(&chip->reg_lock, flags);
2037 left = (chip->image[CS4231_LEFT_INPUT] & ~CS4231_MIXS_ALL) | left;
2038 right = (chip->image[CS4231_RIGHT_INPUT] & ~CS4231_MIXS_ALL) | right;
2039 change = left != chip->image[CS4231_LEFT_INPUT] ||
2040 right != chip->image[CS4231_RIGHT_INPUT];
2041 snd_wss_out(chip, CS4231_LEFT_INPUT, left);
2042 snd_wss_out(chip, CS4231_RIGHT_INPUT, right);
2043 spin_unlock_irqrestore(&chip->reg_lock, flags);
2044 return change;
2045 }
2046
2047 int snd_wss_info_single(struct snd_kcontrol *kcontrol,
2048 struct snd_ctl_elem_info *uinfo)
2049 {
2050 int mask = (kcontrol->private_value >> 16) & 0xff;
2051
2052 uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2053 uinfo->count = 1;
2054 uinfo->value.integer.min = 0;
2055 uinfo->value.integer.max = mask;
2056 return 0;
2057 }
2058 EXPORT_SYMBOL(snd_wss_info_single);
2059
2060 int snd_wss_get_single(struct snd_kcontrol *kcontrol,
2061 struct snd_ctl_elem_value *ucontrol)
2062 {
2063 struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
2064 unsigned long flags;
2065 int reg = kcontrol->private_value & 0xff;
2066 int shift = (kcontrol->private_value >> 8) & 0xff;
2067 int mask = (kcontrol->private_value >> 16) & 0xff;
2068 int invert = (kcontrol->private_value >> 24) & 0xff;
2069
2070 spin_lock_irqsave(&chip->reg_lock, flags);
2071 ucontrol->value.integer.value[0] = (chip->image[reg] >> shift) & mask;
2072 spin_unlock_irqrestore(&chip->reg_lock, flags);
2073 if (invert)
2074 ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
2075 return 0;
2076 }
2077 EXPORT_SYMBOL(snd_wss_get_single);
2078
2079 int snd_wss_put_single(struct snd_kcontrol *kcontrol,
2080 struct snd_ctl_elem_value *ucontrol)
2081 {
2082 struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
2083 unsigned long flags;
2084 int reg = kcontrol->private_value & 0xff;
2085 int shift = (kcontrol->private_value >> 8) & 0xff;
2086 int mask = (kcontrol->private_value >> 16) & 0xff;
2087 int invert = (kcontrol->private_value >> 24) & 0xff;
2088 int change;
2089 unsigned short val;
2090
2091 val = (ucontrol->value.integer.value[0] & mask);
2092 if (invert)
2093 val = mask - val;
2094 val <<= shift;
2095 spin_lock_irqsave(&chip->reg_lock, flags);
2096 val = (chip->image[reg] & ~(mask << shift)) | val;
2097 change = val != chip->image[reg];
2098 snd_wss_out(chip, reg, val);
2099 spin_unlock_irqrestore(&chip->reg_lock, flags);
2100 return change;
2101 }
2102 EXPORT_SYMBOL(snd_wss_put_single);
2103
2104 int snd_wss_info_double(struct snd_kcontrol *kcontrol,
2105 struct snd_ctl_elem_info *uinfo)
2106 {
2107 int mask = (kcontrol->private_value >> 24) & 0xff;
2108
2109 uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2110 uinfo->count = 2;
2111 uinfo->value.integer.min = 0;
2112 uinfo->value.integer.max = mask;
2113 return 0;
2114 }
2115 EXPORT_SYMBOL(snd_wss_info_double);
2116
2117 int snd_wss_get_double(struct snd_kcontrol *kcontrol,
2118 struct snd_ctl_elem_value *ucontrol)
2119 {
2120 struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
2121 unsigned long flags;
2122 int left_reg = kcontrol->private_value & 0xff;
2123 int right_reg = (kcontrol->private_value >> 8) & 0xff;
2124 int shift_left = (kcontrol->private_value >> 16) & 0x07;
2125 int shift_right = (kcontrol->private_value >> 19) & 0x07;
2126 int mask = (kcontrol->private_value >> 24) & 0xff;
2127 int invert = (kcontrol->private_value >> 22) & 1;
2128
2129 spin_lock_irqsave(&chip->reg_lock, flags);
2130 ucontrol->value.integer.value[0] = (chip->image[left_reg] >> shift_left) & mask;
2131 ucontrol->value.integer.value[1] = (chip->image[right_reg] >> shift_right) & mask;
2132 spin_unlock_irqrestore(&chip->reg_lock, flags);
2133 if (invert) {
2134 ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
2135 ucontrol->value.integer.value[1] = mask - ucontrol->value.integer.value[1];
2136 }
2137 return 0;
2138 }
2139 EXPORT_SYMBOL(snd_wss_get_double);
2140
2141 int snd_wss_put_double(struct snd_kcontrol *kcontrol,
2142 struct snd_ctl_elem_value *ucontrol)
2143 {
2144 struct snd_wss *chip = snd_kcontrol_chip(kcontrol);
2145 unsigned long flags;
2146 int left_reg = kcontrol->private_value & 0xff;
2147 int right_reg = (kcontrol->private_value >> 8) & 0xff;
2148 int shift_left = (kcontrol->private_value >> 16) & 0x07;
2149 int shift_right = (kcontrol->private_value >> 19) & 0x07;
2150 int mask = (kcontrol->private_value >> 24) & 0xff;
2151 int invert = (kcontrol->private_value >> 22) & 1;
2152 int change;
2153 unsigned short val1, val2;
2154
2155 val1 = ucontrol->value.integer.value[0] & mask;
2156 val2 = ucontrol->value.integer.value[1] & mask;
2157 if (invert) {
2158 val1 = mask - val1;
2159 val2 = mask - val2;
2160 }
2161 val1 <<= shift_left;
2162 val2 <<= shift_right;
2163 spin_lock_irqsave(&chip->reg_lock, flags);
2164 if (left_reg != right_reg) {
2165 val1 = (chip->image[left_reg] & ~(mask << shift_left)) | val1;
2166 val2 = (chip->image[right_reg] & ~(mask << shift_right)) | val2;
2167 change = val1 != chip->image[left_reg] ||
2168 val2 != chip->image[right_reg];
2169 snd_wss_out(chip, left_reg, val1);
2170 snd_wss_out(chip, right_reg, val2);
2171 } else {
2172 mask = (mask << shift_left) | (mask << shift_right);
2173 val1 = (chip->image[left_reg] & ~mask) | val1 | val2;
2174 change = val1 != chip->image[left_reg];
2175 snd_wss_out(chip, left_reg, val1);
2176 }
2177 spin_unlock_irqrestore(&chip->reg_lock, flags);
2178 return change;
2179 }
2180 EXPORT_SYMBOL(snd_wss_put_double);
2181
2182 static const DECLARE_TLV_DB_SCALE(db_scale_6bit, -9450, 150, 0);
2183 static const DECLARE_TLV_DB_SCALE(db_scale_5bit_12db_max, -3450, 150, 0);
2184 static const DECLARE_TLV_DB_SCALE(db_scale_rec_gain, 0, 150, 0);
2185
2186 static struct snd_kcontrol_new snd_ad1848_controls[] = {
2187 WSS_DOUBLE("PCM Playback Switch", 0, CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT,
2188 7, 7, 1, 1),
2189 WSS_DOUBLE_TLV("PCM Playback Volume", 0,
2190 CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 0, 0, 63, 1,
2191 db_scale_6bit),
2192 WSS_DOUBLE("Aux Playback Switch", 0,
2193 CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 7, 7, 1, 1),
2194 WSS_DOUBLE_TLV("Aux Playback Volume", 0,
2195 CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 0, 0, 31, 1,
2196 db_scale_5bit_12db_max),
2197 WSS_DOUBLE("Aux Playback Switch", 1,
2198 CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 7, 7, 1, 1),
2199 WSS_DOUBLE_TLV("Aux Playback Volume", 1,
2200 CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 0, 0, 31, 1,
2201 db_scale_5bit_12db_max),
2202 WSS_DOUBLE_TLV("Capture Volume", 0, CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT,
2203 0, 0, 15, 0, db_scale_rec_gain),
2204 {
2205 .name = "Capture Source",
2206 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2207 .info = snd_wss_info_mux,
2208 .get = snd_wss_get_mux,
2209 .put = snd_wss_put_mux,
2210 },
2211 WSS_SINGLE("Loopback Capture Switch", 0, CS4231_LOOPBACK, 0, 1, 0),
2212 WSS_SINGLE_TLV("Loopback Capture Volume", 0, CS4231_LOOPBACK, 1, 63, 0,
2213 db_scale_6bit),
2214 };
2215
2216 static struct snd_kcontrol_new snd_wss_controls[] = {
2217 WSS_DOUBLE("PCM Playback Switch", 0,
2218 CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 7, 7, 1, 1),
2219 WSS_DOUBLE("PCM Playback Volume", 0,
2220 CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 0, 0, 63, 1),
2221 WSS_DOUBLE("Line Playback Switch", 0,
2222 CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 7, 7, 1, 1),
2223 WSS_DOUBLE("Line Playback Volume", 0,
2224 CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 0, 0, 31, 1),
2225 WSS_DOUBLE("Aux Playback Switch", 0,
2226 CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 7, 7, 1, 1),
2227 WSS_DOUBLE("Aux Playback Volume", 0,
2228 CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 0, 0, 31, 1),
2229 WSS_DOUBLE("Aux Playback Switch", 1,
2230 CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 7, 7, 1, 1),
2231 WSS_DOUBLE("Aux Playback Volume", 1,
2232 CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 0, 0, 31, 1),
2233 WSS_SINGLE("Mono Playback Switch", 0,
2234 CS4231_MONO_CTRL, 7, 1, 1),
2235 WSS_SINGLE("Mono Playback Volume", 0,
2236 CS4231_MONO_CTRL, 0, 15, 1),
2237 WSS_SINGLE("Mono Output Playback Switch", 0,
2238 CS4231_MONO_CTRL, 6, 1, 1),
2239 WSS_SINGLE("Mono Output Playback Bypass", 0,
2240 CS4231_MONO_CTRL, 5, 1, 0),
2241 WSS_DOUBLE("Capture Volume", 0,
2242 CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 0, 0, 15, 0),
2243 {
2244 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2245 .name = "Capture Source",
2246 .info = snd_wss_info_mux,
2247 .get = snd_wss_get_mux,
2248 .put = snd_wss_put_mux,
2249 },
2250 WSS_DOUBLE("Mic Boost", 0,
2251 CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 5, 5, 1, 0),
2252 WSS_SINGLE("Loopback Capture Switch", 0,
2253 CS4231_LOOPBACK, 0, 1, 0),
2254 WSS_SINGLE("Loopback Capture Volume", 0,
2255 CS4231_LOOPBACK, 2, 63, 1)
2256 };
2257
2258 static struct snd_kcontrol_new snd_opti93x_controls[] = {
2259 WSS_DOUBLE("Master Playback Switch", 0,
2260 OPTi93X_OUT_LEFT, OPTi93X_OUT_RIGHT, 7, 7, 1, 1),
2261 WSS_DOUBLE("Master Playback Volume", 0,
2262 OPTi93X_OUT_LEFT, OPTi93X_OUT_RIGHT, 1, 1, 31, 1),
2263 WSS_DOUBLE("PCM Playback Switch", 0,
2264 CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 7, 7, 1, 1),
2265 WSS_DOUBLE("PCM Playback Volume", 0,
2266 CS4231_LEFT_OUTPUT, CS4231_RIGHT_OUTPUT, 0, 0, 31, 1),
2267 WSS_DOUBLE("FM Playback Switch", 0,
2268 CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 7, 7, 1, 1),
2269 WSS_DOUBLE("FM Playback Volume", 0,
2270 CS4231_AUX2_LEFT_INPUT, CS4231_AUX2_RIGHT_INPUT, 1, 1, 15, 1),
2271 WSS_DOUBLE("Line Playback Switch", 0,
2272 CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 7, 7, 1, 1),
2273 WSS_DOUBLE("Line Playback Volume", 0,
2274 CS4231_LEFT_LINE_IN, CS4231_RIGHT_LINE_IN, 0, 0, 15, 1),
2275 WSS_DOUBLE("Mic Playback Switch", 0,
2276 OPTi93X_MIC_LEFT_INPUT, OPTi93X_MIC_RIGHT_INPUT, 7, 7, 1, 1),
2277 WSS_DOUBLE("Mic Playback Volume", 0,
2278 OPTi93X_MIC_LEFT_INPUT, OPTi93X_MIC_RIGHT_INPUT, 1, 1, 15, 1),
2279 WSS_DOUBLE("Mic Boost", 0,
2280 CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 5, 5, 1, 0),
2281 WSS_DOUBLE("CD Playback Switch", 0,
2282 CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 7, 7, 1, 1),
2283 WSS_DOUBLE("CD Playback Volume", 0,
2284 CS4231_AUX1_LEFT_INPUT, CS4231_AUX1_RIGHT_INPUT, 1, 1, 15, 1),
2285 WSS_DOUBLE("Aux Playback Switch", 0,
2286 OPTi931_AUX_LEFT_INPUT, OPTi931_AUX_RIGHT_INPUT, 7, 7, 1, 1),
2287 WSS_DOUBLE("Aux Playback Volume", 0,
2288 OPTi931_AUX_LEFT_INPUT, OPTi931_AUX_RIGHT_INPUT, 1, 1, 15, 1),
2289 WSS_DOUBLE("Capture Volume", 0,
2290 CS4231_LEFT_INPUT, CS4231_RIGHT_INPUT, 0, 0, 15, 0),
2291 {
2292 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2293 .name = "Capture Source",
2294 .info = snd_wss_info_mux,
2295 .get = snd_wss_get_mux,
2296 .put = snd_wss_put_mux,
2297 }
2298 };
2299
2300 int snd_wss_mixer(struct snd_wss *chip)
2301 {
2302 struct snd_card *card;
2303 unsigned int idx;
2304 int err;
2305
2306 if (snd_BUG_ON(!chip || !chip->pcm))
2307 return -EINVAL;
2308
2309 card = chip->card;
2310
2311 strcpy(card->mixername, chip->pcm->name);
2312
2313 if (chip->hardware == WSS_HW_OPTI93X)
2314 for (idx = 0; idx < ARRAY_SIZE(snd_opti93x_controls); idx++) {
2315 err = snd_ctl_add(card,
2316 snd_ctl_new1(&snd_opti93x_controls[idx],
2317 chip));
2318 if (err < 0)
2319 return err;
2320 }
2321 else if (chip->hardware & WSS_HW_AD1848_MASK)
2322 for (idx = 0; idx < ARRAY_SIZE(snd_ad1848_controls); idx++) {
2323 err = snd_ctl_add(card,
2324 snd_ctl_new1(&snd_ad1848_controls[idx],
2325 chip));
2326 if (err < 0)
2327 return err;
2328 }
2329 else
2330 for (idx = 0; idx < ARRAY_SIZE(snd_wss_controls); idx++) {
2331 err = snd_ctl_add(card,
2332 snd_ctl_new1(&snd_wss_controls[idx],
2333 chip));
2334 if (err < 0)
2335 return err;
2336 }
2337 return 0;
2338 }
2339 EXPORT_SYMBOL(snd_wss_mixer);
2340
2341 const struct snd_pcm_ops *snd_wss_get_pcm_ops(int direction)
2342 {
2343 return direction == SNDRV_PCM_STREAM_PLAYBACK ?
2344 &snd_wss_playback_ops : &snd_wss_capture_ops;
2345 }
2346 EXPORT_SYMBOL(snd_wss_get_pcm_ops);
2347
2348 /*
2349 * INIT part
2350 */
2351
2352 static int __init alsa_wss_init(void)
2353 {
2354 return 0;
2355 }
2356
2357 static void __exit alsa_wss_exit(void)
2358 {
2359 }
2360
2361 module_init(alsa_wss_init);
2362 module_exit(alsa_wss_exit);
Linux 2.6 libata-dev (mirror)