2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include "radeon_drm.h"
31 #include "atom-bits.h"
33 /* from radeon_encoder.c */
35 radeon_get_encoder_id(struct drm_device
*dev
, uint32_t supported_device
,
37 extern void radeon_link_encoder_connector(struct drm_device
*dev
);
39 radeon_add_atom_encoder(struct drm_device
*dev
, uint32_t encoder_id
,
40 uint32_t supported_device
);
42 /* from radeon_connector.c */
44 radeon_add_atom_connector(struct drm_device
*dev
,
45 uint32_t connector_id
,
46 uint32_t supported_device
,
48 struct radeon_i2c_bus_rec
*i2c_bus
,
49 bool linkb
, uint32_t igp_lane_info
,
50 uint16_t connector_object_id
,
51 struct radeon_hpd
*hpd
);
53 /* from radeon_legacy_encoder.c */
55 radeon_add_legacy_encoder(struct drm_device
*dev
, uint32_t encoder_id
,
56 uint32_t supported_device
);
58 union atom_supported_devices
{
59 struct _ATOM_SUPPORTED_DEVICES_INFO info
;
60 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2
;
61 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1
;
64 static inline struct radeon_i2c_bus_rec
radeon_lookup_i2c_gpio(struct radeon_device
*rdev
,
67 struct atom_context
*ctx
= rdev
->mode_info
.atom_context
;
68 ATOM_GPIO_I2C_ASSIGMENT
*gpio
;
69 struct radeon_i2c_bus_rec i2c
;
70 int index
= GetIndexIntoMasterTable(DATA
, GPIO_I2C_Info
);
71 struct _ATOM_GPIO_I2C_INFO
*i2c_info
;
75 memset(&i2c
, 0, sizeof(struct radeon_i2c_bus_rec
));
78 atom_parse_data_header(ctx
, index
, NULL
, NULL
, NULL
, &data_offset
);
80 i2c_info
= (struct _ATOM_GPIO_I2C_INFO
*)(ctx
->bios
+ data_offset
);
83 for (i
= 0; i
< ATOM_MAX_SUPPORTED_DEVICE
; i
++) {
84 gpio
= &i2c_info
->asGPIO_Info
[i
];
86 if (gpio
->sucI2cId
.ucAccess
== id
) {
87 i2c
.mask_clk_reg
= le16_to_cpu(gpio
->usClkMaskRegisterIndex
) * 4;
88 i2c
.mask_data_reg
= le16_to_cpu(gpio
->usDataMaskRegisterIndex
) * 4;
89 i2c
.en_clk_reg
= le16_to_cpu(gpio
->usClkEnRegisterIndex
) * 4;
90 i2c
.en_data_reg
= le16_to_cpu(gpio
->usDataEnRegisterIndex
) * 4;
91 i2c
.y_clk_reg
= le16_to_cpu(gpio
->usClkY_RegisterIndex
) * 4;
92 i2c
.y_data_reg
= le16_to_cpu(gpio
->usDataY_RegisterIndex
) * 4;
93 i2c
.a_clk_reg
= le16_to_cpu(gpio
->usClkA_RegisterIndex
) * 4;
94 i2c
.a_data_reg
= le16_to_cpu(gpio
->usDataA_RegisterIndex
) * 4;
95 i2c
.mask_clk_mask
= (1 << gpio
->ucClkMaskShift
);
96 i2c
.mask_data_mask
= (1 << gpio
->ucDataMaskShift
);
97 i2c
.en_clk_mask
= (1 << gpio
->ucClkEnShift
);
98 i2c
.en_data_mask
= (1 << gpio
->ucDataEnShift
);
99 i2c
.y_clk_mask
= (1 << gpio
->ucClkY_Shift
);
100 i2c
.y_data_mask
= (1 << gpio
->ucDataY_Shift
);
101 i2c
.a_clk_mask
= (1 << gpio
->ucClkA_Shift
);
102 i2c
.a_data_mask
= (1 << gpio
->ucDataA_Shift
);
104 if (gpio
->sucI2cId
.sbfAccess
.bfHW_Capable
)
105 i2c
.hw_capable
= true;
107 i2c
.hw_capable
= false;
109 if (gpio
->sucI2cId
.ucAccess
== 0xa0)
114 i2c
.i2c_id
= gpio
->sucI2cId
.ucAccess
;
124 static inline struct radeon_gpio_rec
radeon_lookup_gpio(struct radeon_device
*rdev
,
127 struct atom_context
*ctx
= rdev
->mode_info
.atom_context
;
128 struct radeon_gpio_rec gpio
;
129 int index
= GetIndexIntoMasterTable(DATA
, GPIO_Pin_LUT
);
130 struct _ATOM_GPIO_PIN_LUT
*gpio_info
;
131 ATOM_GPIO_PIN_ASSIGNMENT
*pin
;
132 u16 data_offset
, size
;
135 memset(&gpio
, 0, sizeof(struct radeon_gpio_rec
));
138 atom_parse_data_header(ctx
, index
, &size
, NULL
, NULL
, &data_offset
);
140 gpio_info
= (struct _ATOM_GPIO_PIN_LUT
*)(ctx
->bios
+ data_offset
);
142 num_indices
= (size
- sizeof(ATOM_COMMON_TABLE_HEADER
)) / sizeof(ATOM_GPIO_PIN_ASSIGNMENT
);
144 for (i
= 0; i
< num_indices
; i
++) {
145 pin
= &gpio_info
->asGPIO_Pin
[i
];
146 if (id
== pin
->ucGPIO_ID
) {
147 gpio
.id
= pin
->ucGPIO_ID
;
148 gpio
.reg
= pin
->usGpioPin_AIndex
* 4;
149 gpio
.mask
= (1 << pin
->ucGpioPinBitShift
);
158 static struct radeon_hpd
radeon_atom_get_hpd_info_from_gpio(struct radeon_device
*rdev
,
159 struct radeon_gpio_rec
*gpio
)
161 struct radeon_hpd hpd
;
163 if (gpio
->reg
== AVIVO_DC_GPIO_HPD_A
) {
166 hpd
.hpd
= RADEON_HPD_1
;
169 hpd
.hpd
= RADEON_HPD_2
;
172 hpd
.hpd
= RADEON_HPD_3
;
175 hpd
.hpd
= RADEON_HPD_4
;
178 hpd
.hpd
= RADEON_HPD_5
;
181 hpd
.hpd
= RADEON_HPD_6
;
184 hpd
.hpd
= RADEON_HPD_NONE
;
188 hpd
.hpd
= RADEON_HPD_NONE
;
192 static bool radeon_atom_apply_quirks(struct drm_device
*dev
,
193 uint32_t supported_device
,
195 struct radeon_i2c_bus_rec
*i2c_bus
,
197 struct radeon_hpd
*hpd
)
200 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
201 if ((dev
->pdev
->device
== 0x791e) &&
202 (dev
->pdev
->subsystem_vendor
== 0x1043) &&
203 (dev
->pdev
->subsystem_device
== 0x826d)) {
204 if ((*connector_type
== DRM_MODE_CONNECTOR_HDMIA
) &&
205 (supported_device
== ATOM_DEVICE_DFP3_SUPPORT
))
206 *connector_type
= DRM_MODE_CONNECTOR_DVID
;
209 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
210 if ((dev
->pdev
->device
== 0x7941) &&
211 (dev
->pdev
->subsystem_vendor
== 0x147b) &&
212 (dev
->pdev
->subsystem_device
== 0x2412)) {
213 if (*connector_type
== DRM_MODE_CONNECTOR_DVII
)
217 /* Falcon NW laptop lists vga ddc line for LVDS */
218 if ((dev
->pdev
->device
== 0x5653) &&
219 (dev
->pdev
->subsystem_vendor
== 0x1462) &&
220 (dev
->pdev
->subsystem_device
== 0x0291)) {
221 if (*connector_type
== DRM_MODE_CONNECTOR_LVDS
) {
222 i2c_bus
->valid
= false;
227 /* HIS X1300 is DVI+VGA, not DVI+DVI */
228 if ((dev
->pdev
->device
== 0x7146) &&
229 (dev
->pdev
->subsystem_vendor
== 0x17af) &&
230 (dev
->pdev
->subsystem_device
== 0x2058)) {
231 if (supported_device
== ATOM_DEVICE_DFP1_SUPPORT
)
235 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
236 if ((dev
->pdev
->device
== 0x7142) &&
237 (dev
->pdev
->subsystem_vendor
== 0x1458) &&
238 (dev
->pdev
->subsystem_device
== 0x2134)) {
239 if (supported_device
== ATOM_DEVICE_DFP1_SUPPORT
)
245 if ((dev
->pdev
->device
== 0x71C5) &&
246 (dev
->pdev
->subsystem_vendor
== 0x106b) &&
247 (dev
->pdev
->subsystem_device
== 0x0080)) {
248 if ((supported_device
== ATOM_DEVICE_CRT1_SUPPORT
) ||
249 (supported_device
== ATOM_DEVICE_DFP2_SUPPORT
))
253 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
254 if ((dev
->pdev
->device
== 0x9598) &&
255 (dev
->pdev
->subsystem_vendor
== 0x1043) &&
256 (dev
->pdev
->subsystem_device
== 0x01da)) {
257 if (*connector_type
== DRM_MODE_CONNECTOR_HDMIA
) {
258 *connector_type
= DRM_MODE_CONNECTOR_DVII
;
262 /* ASUS HD 3450 board lists the DVI port as HDMI */
263 if ((dev
->pdev
->device
== 0x95C5) &&
264 (dev
->pdev
->subsystem_vendor
== 0x1043) &&
265 (dev
->pdev
->subsystem_device
== 0x01e2)) {
266 if (*connector_type
== DRM_MODE_CONNECTOR_HDMIA
) {
267 *connector_type
= DRM_MODE_CONNECTOR_DVII
;
271 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
272 * HDMI + VGA reporting as HDMI
274 if (*connector_type
== DRM_MODE_CONNECTOR_HDMIA
) {
275 if (supported_device
& (ATOM_DEVICE_CRT_SUPPORT
)) {
276 *connector_type
= DRM_MODE_CONNECTOR_VGA
;
281 /* Acer laptop reports DVI-D as DVI-I */
282 if ((dev
->pdev
->device
== 0x95c4) &&
283 (dev
->pdev
->subsystem_vendor
== 0x1025) &&
284 (dev
->pdev
->subsystem_device
== 0x013c)) {
285 if ((*connector_type
== DRM_MODE_CONNECTOR_DVII
) &&
286 (supported_device
== ATOM_DEVICE_DFP1_SUPPORT
))
287 *connector_type
= DRM_MODE_CONNECTOR_DVID
;
293 const int supported_devices_connector_convert
[] = {
294 DRM_MODE_CONNECTOR_Unknown
,
295 DRM_MODE_CONNECTOR_VGA
,
296 DRM_MODE_CONNECTOR_DVII
,
297 DRM_MODE_CONNECTOR_DVID
,
298 DRM_MODE_CONNECTOR_DVIA
,
299 DRM_MODE_CONNECTOR_SVIDEO
,
300 DRM_MODE_CONNECTOR_Composite
,
301 DRM_MODE_CONNECTOR_LVDS
,
302 DRM_MODE_CONNECTOR_Unknown
,
303 DRM_MODE_CONNECTOR_Unknown
,
304 DRM_MODE_CONNECTOR_HDMIA
,
305 DRM_MODE_CONNECTOR_HDMIB
,
306 DRM_MODE_CONNECTOR_Unknown
,
307 DRM_MODE_CONNECTOR_Unknown
,
308 DRM_MODE_CONNECTOR_9PinDIN
,
309 DRM_MODE_CONNECTOR_DisplayPort
312 const uint16_t supported_devices_connector_object_id_convert
[] = {
313 CONNECTOR_OBJECT_ID_NONE
,
314 CONNECTOR_OBJECT_ID_VGA
,
315 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I
, /* not all boards support DL */
316 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D
, /* not all boards support DL */
317 CONNECTOR_OBJECT_ID_VGA
, /* technically DVI-A */
318 CONNECTOR_OBJECT_ID_COMPOSITE
,
319 CONNECTOR_OBJECT_ID_SVIDEO
,
320 CONNECTOR_OBJECT_ID_LVDS
,
321 CONNECTOR_OBJECT_ID_9PIN_DIN
,
322 CONNECTOR_OBJECT_ID_9PIN_DIN
,
323 CONNECTOR_OBJECT_ID_DISPLAYPORT
,
324 CONNECTOR_OBJECT_ID_HDMI_TYPE_A
,
325 CONNECTOR_OBJECT_ID_HDMI_TYPE_B
,
326 CONNECTOR_OBJECT_ID_SVIDEO
329 const int object_connector_convert
[] = {
330 DRM_MODE_CONNECTOR_Unknown
,
331 DRM_MODE_CONNECTOR_DVII
,
332 DRM_MODE_CONNECTOR_DVII
,
333 DRM_MODE_CONNECTOR_DVID
,
334 DRM_MODE_CONNECTOR_DVID
,
335 DRM_MODE_CONNECTOR_VGA
,
336 DRM_MODE_CONNECTOR_Composite
,
337 DRM_MODE_CONNECTOR_SVIDEO
,
338 DRM_MODE_CONNECTOR_Unknown
,
339 DRM_MODE_CONNECTOR_Unknown
,
340 DRM_MODE_CONNECTOR_9PinDIN
,
341 DRM_MODE_CONNECTOR_Unknown
,
342 DRM_MODE_CONNECTOR_HDMIA
,
343 DRM_MODE_CONNECTOR_HDMIB
,
344 DRM_MODE_CONNECTOR_LVDS
,
345 DRM_MODE_CONNECTOR_9PinDIN
,
346 DRM_MODE_CONNECTOR_Unknown
,
347 DRM_MODE_CONNECTOR_Unknown
,
348 DRM_MODE_CONNECTOR_Unknown
,
349 DRM_MODE_CONNECTOR_DisplayPort
,
350 DRM_MODE_CONNECTOR_eDP
,
351 DRM_MODE_CONNECTOR_Unknown
354 bool radeon_get_atom_connector_info_from_object_table(struct drm_device
*dev
)
356 struct radeon_device
*rdev
= dev
->dev_private
;
357 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
358 struct atom_context
*ctx
= mode_info
->atom_context
;
359 int index
= GetIndexIntoMasterTable(DATA
, Object_Header
);
360 u16 size
, data_offset
;
362 ATOM_CONNECTOR_OBJECT_TABLE
*con_obj
;
363 ATOM_DISPLAY_OBJECT_PATH_TABLE
*path_obj
;
364 ATOM_OBJECT_HEADER
*obj_header
;
365 int i
, j
, path_size
, device_support
;
367 u16 igp_lane_info
, conn_id
, connector_object_id
;
369 struct radeon_i2c_bus_rec ddc_bus
;
370 struct radeon_gpio_rec gpio
;
371 struct radeon_hpd hpd
;
373 atom_parse_data_header(ctx
, index
, &size
, &frev
, &crev
, &data_offset
);
375 if (data_offset
== 0)
381 obj_header
= (ATOM_OBJECT_HEADER
*) (ctx
->bios
+ data_offset
);
382 path_obj
= (ATOM_DISPLAY_OBJECT_PATH_TABLE
*)
383 (ctx
->bios
+ data_offset
+
384 le16_to_cpu(obj_header
->usDisplayPathTableOffset
));
385 con_obj
= (ATOM_CONNECTOR_OBJECT_TABLE
*)
386 (ctx
->bios
+ data_offset
+
387 le16_to_cpu(obj_header
->usConnectorObjectTableOffset
));
388 device_support
= le16_to_cpu(obj_header
->usDeviceSupport
);
391 for (i
= 0; i
< path_obj
->ucNumOfDispPath
; i
++) {
392 uint8_t *addr
= (uint8_t *) path_obj
->asDispPath
;
393 ATOM_DISPLAY_OBJECT_PATH
*path
;
395 path
= (ATOM_DISPLAY_OBJECT_PATH
*) addr
;
396 path_size
+= le16_to_cpu(path
->usSize
);
398 if (device_support
& le16_to_cpu(path
->usDeviceTag
)) {
399 uint8_t con_obj_id
, con_obj_num
, con_obj_type
;
402 (le16_to_cpu(path
->usConnObjectId
) & OBJECT_ID_MASK
)
405 (le16_to_cpu(path
->usConnObjectId
) & ENUM_ID_MASK
)
408 (le16_to_cpu(path
->usConnObjectId
) &
409 OBJECT_TYPE_MASK
) >> OBJECT_TYPE_SHIFT
;
411 /* TODO CV support */
412 if (le16_to_cpu(path
->usDeviceTag
) ==
413 ATOM_DEVICE_CV_SUPPORT
)
417 if ((rdev
->flags
& RADEON_IS_IGP
) &&
419 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR
)) {
420 uint16_t igp_offset
= 0;
421 ATOM_INTEGRATED_SYSTEM_INFO_V2
*igp_obj
;
424 GetIndexIntoMasterTable(DATA
,
425 IntegratedSystemInfo
);
427 atom_parse_data_header(ctx
, index
, &size
, &frev
,
432 (ATOM_INTEGRATED_SYSTEM_INFO_V2
433 *) (ctx
->bios
+ igp_offset
);
436 uint32_t slot_config
, ct
;
438 if (con_obj_num
== 1)
447 ct
= (slot_config
>> 16) & 0xff;
449 object_connector_convert
451 connector_object_id
= ct
;
453 slot_config
& 0xffff;
461 object_connector_convert
[con_obj_id
];
462 connector_object_id
= con_obj_id
;
465 if (connector_type
== DRM_MODE_CONNECTOR_Unknown
)
468 for (j
= 0; j
< ((le16_to_cpu(path
->usSize
) - 8) / 2);
470 uint8_t enc_obj_id
, enc_obj_num
, enc_obj_type
;
473 (le16_to_cpu(path
->usGraphicObjIds
[j
]) &
474 OBJECT_ID_MASK
) >> OBJECT_ID_SHIFT
;
476 (le16_to_cpu(path
->usGraphicObjIds
[j
]) &
477 ENUM_ID_MASK
) >> ENUM_ID_SHIFT
;
479 (le16_to_cpu(path
->usGraphicObjIds
[j
]) &
480 OBJECT_TYPE_MASK
) >> OBJECT_TYPE_SHIFT
;
482 /* FIXME: add support for router objects */
483 if (enc_obj_type
== GRAPH_OBJECT_TYPE_ENCODER
) {
484 if (enc_obj_num
== 2)
489 radeon_add_atom_encoder(dev
,
498 /* look up gpio for ddc, hpd */
499 if ((le16_to_cpu(path
->usDeviceTag
) &
500 (ATOM_DEVICE_TV_SUPPORT
| ATOM_DEVICE_CV_SUPPORT
)) == 0) {
501 for (j
= 0; j
< con_obj
->ucNumberOfObjects
; j
++) {
502 if (le16_to_cpu(path
->usConnObjectId
) ==
503 le16_to_cpu(con_obj
->asObjects
[j
].
505 ATOM_COMMON_RECORD_HEADER
507 (ATOM_COMMON_RECORD_HEADER
509 (ctx
->bios
+ data_offset
+
510 le16_to_cpu(con_obj
->
513 ATOM_I2C_RECORD
*i2c_record
;
514 ATOM_HPD_INT_RECORD
*hpd_record
;
515 ATOM_I2C_ID_CONFIG_ACCESS
*i2c_config
;
516 hpd
.hpd
= RADEON_HPD_NONE
;
518 while (record
->ucRecordType
> 0
521 ATOM_MAX_OBJECT_RECORD_NUMBER
) {
522 switch (record
->ucRecordType
) {
523 case ATOM_I2C_RECORD_TYPE
:
528 (ATOM_I2C_ID_CONFIG_ACCESS
*)
529 &i2c_record
->sucI2cId
;
530 ddc_bus
= radeon_lookup_i2c_gpio(rdev
,
534 case ATOM_HPD_INT_RECORD_TYPE
:
536 (ATOM_HPD_INT_RECORD
*)
538 gpio
= radeon_lookup_gpio(rdev
,
539 hpd_record
->ucHPDIntGPIOID
);
540 hpd
= radeon_atom_get_hpd_info_from_gpio(rdev
, &gpio
);
541 hpd
.plugged_state
= hpd_record
->ucPlugged_PinState
;
545 (ATOM_COMMON_RECORD_HEADER
555 hpd
.hpd
= RADEON_HPD_NONE
;
556 ddc_bus
.valid
= false;
559 conn_id
= le16_to_cpu(path
->usConnObjectId
);
561 if (!radeon_atom_apply_quirks
562 (dev
, le16_to_cpu(path
->usDeviceTag
), &connector_type
,
563 &ddc_bus
, &conn_id
, &hpd
))
566 radeon_add_atom_connector(dev
,
570 connector_type
, &ddc_bus
,
571 linkb
, igp_lane_info
,
578 radeon_link_encoder_connector(dev
);
583 static uint16_t atombios_get_connector_object_id(struct drm_device
*dev
,
587 struct radeon_device
*rdev
= dev
->dev_private
;
589 if (rdev
->flags
& RADEON_IS_IGP
) {
590 return supported_devices_connector_object_id_convert
592 } else if (((connector_type
== DRM_MODE_CONNECTOR_DVII
) ||
593 (connector_type
== DRM_MODE_CONNECTOR_DVID
)) &&
594 (devices
& ATOM_DEVICE_DFP2_SUPPORT
)) {
595 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
596 struct atom_context
*ctx
= mode_info
->atom_context
;
597 int index
= GetIndexIntoMasterTable(DATA
, XTMDS_Info
);
598 uint16_t size
, data_offset
;
600 ATOM_XTMDS_INFO
*xtmds
;
602 atom_parse_data_header(ctx
, index
, &size
, &frev
, &crev
, &data_offset
);
603 xtmds
= (ATOM_XTMDS_INFO
*)(ctx
->bios
+ data_offset
);
605 if (xtmds
->ucSupportedLink
& ATOM_XTMDS_SUPPORTED_DUALLINK
) {
606 if (connector_type
== DRM_MODE_CONNECTOR_DVII
)
607 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I
;
609 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D
;
611 if (connector_type
== DRM_MODE_CONNECTOR_DVII
)
612 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I
;
614 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D
;
617 return supported_devices_connector_object_id_convert
622 struct bios_connector
{
627 struct radeon_i2c_bus_rec ddc_bus
;
628 struct radeon_hpd hpd
;
631 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
635 struct radeon_device
*rdev
= dev
->dev_private
;
636 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
637 struct atom_context
*ctx
= mode_info
->atom_context
;
638 int index
= GetIndexIntoMasterTable(DATA
, SupportedDevicesInfo
);
639 uint16_t size
, data_offset
;
641 uint16_t device_support
;
643 union atom_supported_devices
*supported_devices
;
644 int i
, j
, max_device
;
645 struct bios_connector bios_connectors
[ATOM_MAX_SUPPORTED_DEVICE
];
647 atom_parse_data_header(ctx
, index
, &size
, &frev
, &crev
, &data_offset
);
650 (union atom_supported_devices
*)(ctx
->bios
+ data_offset
);
652 device_support
= le16_to_cpu(supported_devices
->info
.usDeviceSupport
);
655 max_device
= ATOM_MAX_SUPPORTED_DEVICE
;
657 max_device
= ATOM_MAX_SUPPORTED_DEVICE_INFO
;
659 for (i
= 0; i
< max_device
; i
++) {
660 ATOM_CONNECTOR_INFO_I2C ci
=
661 supported_devices
->info
.asConnInfo
[i
];
663 bios_connectors
[i
].valid
= false;
665 if (!(device_support
& (1 << i
))) {
669 if (i
== ATOM_DEVICE_CV_INDEX
) {
670 DRM_DEBUG("Skipping Component Video\n");
674 bios_connectors
[i
].connector_type
=
675 supported_devices_connector_convert
[ci
.sucConnectorInfo
.
679 if (bios_connectors
[i
].connector_type
==
680 DRM_MODE_CONNECTOR_Unknown
)
683 dac
= ci
.sucConnectorInfo
.sbfAccess
.bfAssociatedDAC
;
685 bios_connectors
[i
].line_mux
=
686 ci
.sucI2cId
.ucAccess
;
688 /* give tv unique connector ids */
689 if (i
== ATOM_DEVICE_TV1_INDEX
) {
690 bios_connectors
[i
].ddc_bus
.valid
= false;
691 bios_connectors
[i
].line_mux
= 50;
692 } else if (i
== ATOM_DEVICE_TV2_INDEX
) {
693 bios_connectors
[i
].ddc_bus
.valid
= false;
694 bios_connectors
[i
].line_mux
= 51;
695 } else if (i
== ATOM_DEVICE_CV_INDEX
) {
696 bios_connectors
[i
].ddc_bus
.valid
= false;
697 bios_connectors
[i
].line_mux
= 52;
699 bios_connectors
[i
].ddc_bus
=
700 radeon_lookup_i2c_gpio(rdev
,
701 bios_connectors
[i
].line_mux
);
703 if ((crev
> 1) && (frev
> 1)) {
704 u8 isb
= supported_devices
->info_2d1
.asIntSrcInfo
[i
].ucIntSrcBitmap
;
707 bios_connectors
[i
].hpd
.hpd
= RADEON_HPD_1
;
710 bios_connectors
[i
].hpd
.hpd
= RADEON_HPD_2
;
713 bios_connectors
[i
].hpd
.hpd
= RADEON_HPD_NONE
;
717 if (i
== ATOM_DEVICE_DFP1_INDEX
)
718 bios_connectors
[i
].hpd
.hpd
= RADEON_HPD_1
;
719 else if (i
== ATOM_DEVICE_DFP2_INDEX
)
720 bios_connectors
[i
].hpd
.hpd
= RADEON_HPD_2
;
722 bios_connectors
[i
].hpd
.hpd
= RADEON_HPD_NONE
;
725 /* Always set the connector type to VGA for CRT1/CRT2. if they are
726 * shared with a DVI port, we'll pick up the DVI connector when we
727 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
729 if (i
== ATOM_DEVICE_CRT1_INDEX
|| i
== ATOM_DEVICE_CRT2_INDEX
)
730 bios_connectors
[i
].connector_type
=
731 DRM_MODE_CONNECTOR_VGA
;
733 if (!radeon_atom_apply_quirks
734 (dev
, (1 << i
), &bios_connectors
[i
].connector_type
,
735 &bios_connectors
[i
].ddc_bus
, &bios_connectors
[i
].line_mux
,
736 &bios_connectors
[i
].hpd
))
739 bios_connectors
[i
].valid
= true;
740 bios_connectors
[i
].devices
= (1 << i
);
742 if (ASIC_IS_AVIVO(rdev
) || radeon_r4xx_atom
)
743 radeon_add_atom_encoder(dev
,
744 radeon_get_encoder_id(dev
,
749 radeon_add_legacy_encoder(dev
,
750 radeon_get_encoder_id(dev
,
756 /* combine shared connectors */
757 for (i
= 0; i
< max_device
; i
++) {
758 if (bios_connectors
[i
].valid
) {
759 for (j
= 0; j
< max_device
; j
++) {
760 if (bios_connectors
[j
].valid
&& (i
!= j
)) {
761 if (bios_connectors
[i
].line_mux
==
762 bios_connectors
[j
].line_mux
) {
763 /* make sure not to combine LVDS */
764 if (bios_connectors
[i
].devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
765 bios_connectors
[i
].line_mux
= 53;
766 bios_connectors
[i
].ddc_bus
.valid
= false;
769 if (bios_connectors
[j
].devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
770 bios_connectors
[j
].line_mux
= 53;
771 bios_connectors
[j
].ddc_bus
.valid
= false;
774 /* combine analog and digital for DVI-I */
775 if (((bios_connectors
[i
].devices
& (ATOM_DEVICE_DFP_SUPPORT
)) &&
776 (bios_connectors
[j
].devices
& (ATOM_DEVICE_CRT_SUPPORT
))) ||
777 ((bios_connectors
[j
].devices
& (ATOM_DEVICE_DFP_SUPPORT
)) &&
778 (bios_connectors
[i
].devices
& (ATOM_DEVICE_CRT_SUPPORT
)))) {
779 bios_connectors
[i
].devices
|=
780 bios_connectors
[j
].devices
;
781 bios_connectors
[i
].connector_type
=
782 DRM_MODE_CONNECTOR_DVII
;
783 if (bios_connectors
[j
].devices
& (ATOM_DEVICE_DFP_SUPPORT
))
784 bios_connectors
[i
].hpd
=
785 bios_connectors
[j
].hpd
;
786 bios_connectors
[j
].valid
= false;
794 /* add the connectors */
795 for (i
= 0; i
< max_device
; i
++) {
796 if (bios_connectors
[i
].valid
) {
797 uint16_t connector_object_id
=
798 atombios_get_connector_object_id(dev
,
799 bios_connectors
[i
].connector_type
,
800 bios_connectors
[i
].devices
);
801 radeon_add_atom_connector(dev
,
802 bios_connectors
[i
].line_mux
,
803 bios_connectors
[i
].devices
,
806 &bios_connectors
[i
].ddc_bus
,
809 &bios_connectors
[i
].hpd
);
813 radeon_link_encoder_connector(dev
);
818 union firmware_info
{
819 ATOM_FIRMWARE_INFO info
;
820 ATOM_FIRMWARE_INFO_V1_2 info_12
;
821 ATOM_FIRMWARE_INFO_V1_3 info_13
;
822 ATOM_FIRMWARE_INFO_V1_4 info_14
;
825 bool radeon_atom_get_clock_info(struct drm_device
*dev
)
827 struct radeon_device
*rdev
= dev
->dev_private
;
828 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
829 int index
= GetIndexIntoMasterTable(DATA
, FirmwareInfo
);
830 union firmware_info
*firmware_info
;
832 struct radeon_pll
*p1pll
= &rdev
->clock
.p1pll
;
833 struct radeon_pll
*p2pll
= &rdev
->clock
.p2pll
;
834 struct radeon_pll
*spll
= &rdev
->clock
.spll
;
835 struct radeon_pll
*mpll
= &rdev
->clock
.mpll
;
836 uint16_t data_offset
;
838 atom_parse_data_header(mode_info
->atom_context
, index
, NULL
, &frev
,
839 &crev
, &data_offset
);
842 (union firmware_info
*)(mode_info
->atom_context
->bios
+
847 p1pll
->reference_freq
=
848 le16_to_cpu(firmware_info
->info
.usReferenceClock
);
849 p1pll
->reference_div
= 0;
853 le16_to_cpu(firmware_info
->info
.usMinPixelClockPLL_Output
);
856 le32_to_cpu(firmware_info
->info_12
.ulMinPixelClockPLL_Output
);
858 le32_to_cpu(firmware_info
->info
.ulMaxPixelClockPLL_Output
);
860 if (p1pll
->pll_out_min
== 0) {
861 if (ASIC_IS_AVIVO(rdev
))
862 p1pll
->pll_out_min
= 64800;
864 p1pll
->pll_out_min
= 20000;
865 } else if (p1pll
->pll_out_min
> 64800) {
866 /* Limiting the pll output range is a good thing generally as
867 * it limits the number of possible pll combinations for a given
868 * frequency presumably to the ones that work best on each card.
869 * However, certain duallink DVI monitors seem to like
870 * pll combinations that would be limited by this at least on
871 * pre-DCE 3.0 r6xx hardware. This might need to be adjusted per
875 p1pll
->pll_out_min
= 64800;
879 le16_to_cpu(firmware_info
->info
.usMinPixelClockPLL_Input
);
881 le16_to_cpu(firmware_info
->info
.usMaxPixelClockPLL_Input
);
886 spll
->reference_freq
=
887 le16_to_cpu(firmware_info
->info
.usReferenceClock
);
888 spll
->reference_div
= 0;
891 le16_to_cpu(firmware_info
->info
.usMinEngineClockPLL_Output
);
893 le32_to_cpu(firmware_info
->info
.ulMaxEngineClockPLL_Output
);
896 if (spll
->pll_out_min
== 0) {
897 if (ASIC_IS_AVIVO(rdev
))
898 spll
->pll_out_min
= 64800;
900 spll
->pll_out_min
= 20000;
904 le16_to_cpu(firmware_info
->info
.usMinEngineClockPLL_Input
);
906 le16_to_cpu(firmware_info
->info
.usMaxEngineClockPLL_Input
);
909 mpll
->reference_freq
=
910 le16_to_cpu(firmware_info
->info
.usReferenceClock
);
911 mpll
->reference_div
= 0;
914 le16_to_cpu(firmware_info
->info
.usMinMemoryClockPLL_Output
);
916 le32_to_cpu(firmware_info
->info
.ulMaxMemoryClockPLL_Output
);
919 if (mpll
->pll_out_min
== 0) {
920 if (ASIC_IS_AVIVO(rdev
))
921 mpll
->pll_out_min
= 64800;
923 mpll
->pll_out_min
= 20000;
927 le16_to_cpu(firmware_info
->info
.usMinMemoryClockPLL_Input
);
929 le16_to_cpu(firmware_info
->info
.usMaxMemoryClockPLL_Input
);
931 rdev
->clock
.default_sclk
=
932 le32_to_cpu(firmware_info
->info
.ulDefaultEngineClock
);
933 rdev
->clock
.default_mclk
=
934 le32_to_cpu(firmware_info
->info
.ulDefaultMemoryClock
);
941 bool radeon_atombios_get_tmds_info(struct radeon_encoder
*encoder
,
942 struct radeon_encoder_int_tmds
*tmds
)
944 struct drm_device
*dev
= encoder
->base
.dev
;
945 struct radeon_device
*rdev
= dev
->dev_private
;
946 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
947 int index
= GetIndexIntoMasterTable(DATA
, TMDS_Info
);
948 uint16_t data_offset
;
949 struct _ATOM_TMDS_INFO
*tmds_info
;
954 atom_parse_data_header(mode_info
->atom_context
, index
, NULL
, &frev
,
955 &crev
, &data_offset
);
958 (struct _ATOM_TMDS_INFO
*)(mode_info
->atom_context
->bios
+
962 maxfreq
= le16_to_cpu(tmds_info
->usMaxFrequency
);
963 for (i
= 0; i
< 4; i
++) {
964 tmds
->tmds_pll
[i
].freq
=
965 le16_to_cpu(tmds_info
->asMiscInfo
[i
].usFrequency
);
966 tmds
->tmds_pll
[i
].value
=
967 tmds_info
->asMiscInfo
[i
].ucPLL_ChargePump
& 0x3f;
968 tmds
->tmds_pll
[i
].value
|=
969 (tmds_info
->asMiscInfo
[i
].
970 ucPLL_VCO_Gain
& 0x3f) << 6;
971 tmds
->tmds_pll
[i
].value
|=
972 (tmds_info
->asMiscInfo
[i
].
973 ucPLL_DutyCycle
& 0xf) << 12;
974 tmds
->tmds_pll
[i
].value
|=
975 (tmds_info
->asMiscInfo
[i
].
976 ucPLL_VoltageSwing
& 0xf) << 16;
978 DRM_DEBUG("TMDS PLL From ATOMBIOS %u %x\n",
979 tmds
->tmds_pll
[i
].freq
,
980 tmds
->tmds_pll
[i
].value
);
982 if (maxfreq
== tmds
->tmds_pll
[i
].freq
) {
983 tmds
->tmds_pll
[i
].freq
= 0xffffffff;
992 static struct radeon_atom_ss
*radeon_atombios_get_ss_info(struct
997 struct drm_device
*dev
= encoder
->base
.dev
;
998 struct radeon_device
*rdev
= dev
->dev_private
;
999 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1000 int index
= GetIndexIntoMasterTable(DATA
, PPLL_SS_Info
);
1001 uint16_t data_offset
;
1002 struct _ATOM_SPREAD_SPECTRUM_INFO
*ss_info
;
1004 struct radeon_atom_ss
*ss
= NULL
;
1007 if (id
> ATOM_MAX_SS_ENTRY
)
1010 atom_parse_data_header(mode_info
->atom_context
, index
, NULL
, &frev
,
1011 &crev
, &data_offset
);
1014 (struct _ATOM_SPREAD_SPECTRUM_INFO
*)(mode_info
->atom_context
->bios
+ data_offset
);
1018 kzalloc(sizeof(struct radeon_atom_ss
), GFP_KERNEL
);
1023 for (i
= 0; i
< ATOM_MAX_SS_ENTRY
; i
++) {
1024 if (ss_info
->asSS_Info
[i
].ucSS_Id
== id
) {
1026 le16_to_cpu(ss_info
->asSS_Info
[i
].usSpreadSpectrumPercentage
);
1027 ss
->type
= ss_info
->asSS_Info
[i
].ucSpreadSpectrumType
;
1028 ss
->step
= ss_info
->asSS_Info
[i
].ucSS_Step
;
1029 ss
->delay
= ss_info
->asSS_Info
[i
].ucSS_Delay
;
1030 ss
->range
= ss_info
->asSS_Info
[i
].ucSS_Range
;
1031 ss
->refdiv
= ss_info
->asSS_Info
[i
].ucRecommendedRef_Div
;
1040 struct _ATOM_LVDS_INFO info
;
1041 struct _ATOM_LVDS_INFO_V12 info_12
;
1044 struct radeon_encoder_atom_dig
*radeon_atombios_get_lvds_info(struct
1048 struct drm_device
*dev
= encoder
->base
.dev
;
1049 struct radeon_device
*rdev
= dev
->dev_private
;
1050 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1051 int index
= GetIndexIntoMasterTable(DATA
, LVDS_Info
);
1052 uint16_t data_offset
, misc
;
1053 union lvds_info
*lvds_info
;
1055 struct radeon_encoder_atom_dig
*lvds
= NULL
;
1057 atom_parse_data_header(mode_info
->atom_context
, index
, NULL
, &frev
,
1058 &crev
, &data_offset
);
1061 (union lvds_info
*)(mode_info
->atom_context
->bios
+ data_offset
);
1065 kzalloc(sizeof(struct radeon_encoder_atom_dig
), GFP_KERNEL
);
1070 lvds
->native_mode
.clock
=
1071 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usPixClk
) * 10;
1072 lvds
->native_mode
.hdisplay
=
1073 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usHActive
);
1074 lvds
->native_mode
.vdisplay
=
1075 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usVActive
);
1076 lvds
->native_mode
.htotal
= lvds
->native_mode
.hdisplay
+
1077 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usHBlanking_Time
);
1078 lvds
->native_mode
.hsync_start
= lvds
->native_mode
.hdisplay
+
1079 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usHSyncOffset
);
1080 lvds
->native_mode
.hsync_end
= lvds
->native_mode
.hsync_start
+
1081 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usHSyncWidth
);
1082 lvds
->native_mode
.vtotal
= lvds
->native_mode
.vdisplay
+
1083 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usVBlanking_Time
);
1084 lvds
->native_mode
.vsync_start
= lvds
->native_mode
.vdisplay
+
1085 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usVSyncWidth
);
1086 lvds
->native_mode
.vsync_end
= lvds
->native_mode
.vsync_start
+
1087 le16_to_cpu(lvds_info
->info
.sLCDTiming
.usVSyncWidth
);
1088 lvds
->panel_pwr_delay
=
1089 le16_to_cpu(lvds_info
->info
.usOffDelayInMs
);
1090 lvds
->lvds_misc
= lvds_info
->info
.ucLVDS_Misc
;
1092 misc
= le16_to_cpu(lvds_info
->info
.sLCDTiming
.susModeMiscInfo
.usAccess
);
1093 if (misc
& ATOM_VSYNC_POLARITY
)
1094 lvds
->native_mode
.flags
|= DRM_MODE_FLAG_NVSYNC
;
1095 if (misc
& ATOM_HSYNC_POLARITY
)
1096 lvds
->native_mode
.flags
|= DRM_MODE_FLAG_NHSYNC
;
1097 if (misc
& ATOM_COMPOSITESYNC
)
1098 lvds
->native_mode
.flags
|= DRM_MODE_FLAG_CSYNC
;
1099 if (misc
& ATOM_INTERLACE
)
1100 lvds
->native_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
1101 if (misc
& ATOM_DOUBLE_CLOCK_MODE
)
1102 lvds
->native_mode
.flags
|= DRM_MODE_FLAG_DBLSCAN
;
1104 /* set crtc values */
1105 drm_mode_set_crtcinfo(&lvds
->native_mode
, CRTC_INTERLACE_HALVE_V
);
1107 lvds
->ss
= radeon_atombios_get_ss_info(encoder
, lvds_info
->info
.ucSS_Id
);
1109 encoder
->native_mode
= lvds
->native_mode
;
1114 struct radeon_encoder_primary_dac
*
1115 radeon_atombios_get_primary_dac_info(struct radeon_encoder
*encoder
)
1117 struct drm_device
*dev
= encoder
->base
.dev
;
1118 struct radeon_device
*rdev
= dev
->dev_private
;
1119 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1120 int index
= GetIndexIntoMasterTable(DATA
, CompassionateData
);
1121 uint16_t data_offset
;
1122 struct _COMPASSIONATE_DATA
*dac_info
;
1125 struct radeon_encoder_primary_dac
*p_dac
= NULL
;
1127 atom_parse_data_header(mode_info
->atom_context
, index
, NULL
, &frev
, &crev
, &data_offset
);
1129 dac_info
= (struct _COMPASSIONATE_DATA
*)(mode_info
->atom_context
->bios
+ data_offset
);
1132 p_dac
= kzalloc(sizeof(struct radeon_encoder_primary_dac
), GFP_KERNEL
);
1137 bg
= dac_info
->ucDAC1_BG_Adjustment
;
1138 dac
= dac_info
->ucDAC1_DAC_Adjustment
;
1139 p_dac
->ps2_pdac_adj
= (bg
<< 8) | (dac
);
1145 bool radeon_atom_get_tv_timings(struct radeon_device
*rdev
, int index
,
1146 struct drm_display_mode
*mode
)
1148 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1149 ATOM_ANALOG_TV_INFO
*tv_info
;
1150 ATOM_ANALOG_TV_INFO_V1_2
*tv_info_v1_2
;
1151 ATOM_DTD_FORMAT
*dtd_timings
;
1152 int data_index
= GetIndexIntoMasterTable(DATA
, AnalogTV_Info
);
1154 u16 data_offset
, misc
;
1156 atom_parse_data_header(mode_info
->atom_context
, data_index
, NULL
, &frev
, &crev
, &data_offset
);
1160 tv_info
= (ATOM_ANALOG_TV_INFO
*)(mode_info
->atom_context
->bios
+ data_offset
);
1161 if (index
> MAX_SUPPORTED_TV_TIMING
)
1164 mode
->crtc_htotal
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_H_Total
);
1165 mode
->crtc_hdisplay
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_H_Disp
);
1166 mode
->crtc_hsync_start
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_H_SyncStart
);
1167 mode
->crtc_hsync_end
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_H_SyncStart
) +
1168 le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_H_SyncWidth
);
1170 mode
->crtc_vtotal
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_V_Total
);
1171 mode
->crtc_vdisplay
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_V_Disp
);
1172 mode
->crtc_vsync_start
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_V_SyncStart
);
1173 mode
->crtc_vsync_end
= le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_V_SyncStart
) +
1174 le16_to_cpu(tv_info
->aModeTimings
[index
].usCRTC_V_SyncWidth
);
1177 misc
= le16_to_cpu(tv_info
->aModeTimings
[index
].susModeMiscInfo
.usAccess
);
1178 if (misc
& ATOM_VSYNC_POLARITY
)
1179 mode
->flags
|= DRM_MODE_FLAG_NVSYNC
;
1180 if (misc
& ATOM_HSYNC_POLARITY
)
1181 mode
->flags
|= DRM_MODE_FLAG_NHSYNC
;
1182 if (misc
& ATOM_COMPOSITESYNC
)
1183 mode
->flags
|= DRM_MODE_FLAG_CSYNC
;
1184 if (misc
& ATOM_INTERLACE
)
1185 mode
->flags
|= DRM_MODE_FLAG_INTERLACE
;
1186 if (misc
& ATOM_DOUBLE_CLOCK_MODE
)
1187 mode
->flags
|= DRM_MODE_FLAG_DBLSCAN
;
1189 mode
->clock
= le16_to_cpu(tv_info
->aModeTimings
[index
].usPixelClock
) * 10;
1192 /* PAL timings appear to have wrong values for totals */
1193 mode
->crtc_htotal
-= 1;
1194 mode
->crtc_vtotal
-= 1;
1198 tv_info_v1_2
= (ATOM_ANALOG_TV_INFO_V1_2
*)(mode_info
->atom_context
->bios
+ data_offset
);
1199 if (index
> MAX_SUPPORTED_TV_TIMING_V1_2
)
1202 dtd_timings
= &tv_info_v1_2
->aModeTimings
[index
];
1203 mode
->crtc_htotal
= le16_to_cpu(dtd_timings
->usHActive
) +
1204 le16_to_cpu(dtd_timings
->usHBlanking_Time
);
1205 mode
->crtc_hdisplay
= le16_to_cpu(dtd_timings
->usHActive
);
1206 mode
->crtc_hsync_start
= le16_to_cpu(dtd_timings
->usHActive
) +
1207 le16_to_cpu(dtd_timings
->usHSyncOffset
);
1208 mode
->crtc_hsync_end
= mode
->crtc_hsync_start
+
1209 le16_to_cpu(dtd_timings
->usHSyncWidth
);
1211 mode
->crtc_vtotal
= le16_to_cpu(dtd_timings
->usVActive
) +
1212 le16_to_cpu(dtd_timings
->usVBlanking_Time
);
1213 mode
->crtc_vdisplay
= le16_to_cpu(dtd_timings
->usVActive
);
1214 mode
->crtc_vsync_start
= le16_to_cpu(dtd_timings
->usVActive
) +
1215 le16_to_cpu(dtd_timings
->usVSyncOffset
);
1216 mode
->crtc_vsync_end
= mode
->crtc_vsync_start
+
1217 le16_to_cpu(dtd_timings
->usVSyncWidth
);
1220 misc
= le16_to_cpu(dtd_timings
->susModeMiscInfo
.usAccess
);
1221 if (misc
& ATOM_VSYNC_POLARITY
)
1222 mode
->flags
|= DRM_MODE_FLAG_NVSYNC
;
1223 if (misc
& ATOM_HSYNC_POLARITY
)
1224 mode
->flags
|= DRM_MODE_FLAG_NHSYNC
;
1225 if (misc
& ATOM_COMPOSITESYNC
)
1226 mode
->flags
|= DRM_MODE_FLAG_CSYNC
;
1227 if (misc
& ATOM_INTERLACE
)
1228 mode
->flags
|= DRM_MODE_FLAG_INTERLACE
;
1229 if (misc
& ATOM_DOUBLE_CLOCK_MODE
)
1230 mode
->flags
|= DRM_MODE_FLAG_DBLSCAN
;
1232 mode
->clock
= le16_to_cpu(dtd_timings
->usPixClk
) * 10;
1239 radeon_atombios_get_tv_info(struct radeon_device
*rdev
)
1241 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1242 int index
= GetIndexIntoMasterTable(DATA
, AnalogTV_Info
);
1243 uint16_t data_offset
;
1245 struct _ATOM_ANALOG_TV_INFO
*tv_info
;
1246 enum radeon_tv_std tv_std
= TV_STD_NTSC
;
1248 atom_parse_data_header(mode_info
->atom_context
, index
, NULL
, &frev
, &crev
, &data_offset
);
1250 tv_info
= (struct _ATOM_ANALOG_TV_INFO
*)(mode_info
->atom_context
->bios
+ data_offset
);
1252 switch (tv_info
->ucTV_BootUpDefaultStandard
) {
1254 tv_std
= TV_STD_NTSC
;
1255 DRM_INFO("Default TV standard: NTSC\n");
1258 tv_std
= TV_STD_NTSC_J
;
1259 DRM_INFO("Default TV standard: NTSC-J\n");
1262 tv_std
= TV_STD_PAL
;
1263 DRM_INFO("Default TV standard: PAL\n");
1266 tv_std
= TV_STD_PAL_M
;
1267 DRM_INFO("Default TV standard: PAL-M\n");
1270 tv_std
= TV_STD_PAL_N
;
1271 DRM_INFO("Default TV standard: PAL-N\n");
1274 tv_std
= TV_STD_PAL_CN
;
1275 DRM_INFO("Default TV standard: PAL-CN\n");
1278 tv_std
= TV_STD_PAL_60
;
1279 DRM_INFO("Default TV standard: PAL-60\n");
1282 tv_std
= TV_STD_SECAM
;
1283 DRM_INFO("Default TV standard: SECAM\n");
1286 tv_std
= TV_STD_NTSC
;
1287 DRM_INFO("Unknown TV standard; defaulting to NTSC\n");
1293 struct radeon_encoder_tv_dac
*
1294 radeon_atombios_get_tv_dac_info(struct radeon_encoder
*encoder
)
1296 struct drm_device
*dev
= encoder
->base
.dev
;
1297 struct radeon_device
*rdev
= dev
->dev_private
;
1298 struct radeon_mode_info
*mode_info
= &rdev
->mode_info
;
1299 int index
= GetIndexIntoMasterTable(DATA
, CompassionateData
);
1300 uint16_t data_offset
;
1301 struct _COMPASSIONATE_DATA
*dac_info
;
1304 struct radeon_encoder_tv_dac
*tv_dac
= NULL
;
1306 atom_parse_data_header(mode_info
->atom_context
, index
, NULL
, &frev
, &crev
, &data_offset
);
1308 dac_info
= (struct _COMPASSIONATE_DATA
*)(mode_info
->atom_context
->bios
+ data_offset
);
1311 tv_dac
= kzalloc(sizeof(struct radeon_encoder_tv_dac
), GFP_KERNEL
);
1316 bg
= dac_info
->ucDAC2_CRT2_BG_Adjustment
;
1317 dac
= dac_info
->ucDAC2_CRT2_DAC_Adjustment
;
1318 tv_dac
->ps2_tvdac_adj
= (bg
<< 16) | (dac
<< 20);
1320 bg
= dac_info
->ucDAC2_PAL_BG_Adjustment
;
1321 dac
= dac_info
->ucDAC2_PAL_DAC_Adjustment
;
1322 tv_dac
->pal_tvdac_adj
= (bg
<< 16) | (dac
<< 20);
1324 bg
= dac_info
->ucDAC2_NTSC_BG_Adjustment
;
1325 dac
= dac_info
->ucDAC2_NTSC_DAC_Adjustment
;
1326 tv_dac
->ntsc_tvdac_adj
= (bg
<< 16) | (dac
<< 20);
1328 tv_dac
->tv_std
= radeon_atombios_get_tv_info(rdev
);
1333 void radeon_atom_set_clock_gating(struct radeon_device
*rdev
, int enable
)
1335 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args
;
1336 int index
= GetIndexIntoMasterTable(COMMAND
, DynamicClockGating
);
1338 args
.ucEnable
= enable
;
1340 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1343 void radeon_atom_static_pwrmgt_setup(struct radeon_device
*rdev
, int enable
)
1345 ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION args
;
1346 int index
= GetIndexIntoMasterTable(COMMAND
, EnableASIC_StaticPwrMgt
);
1348 args
.ucEnable
= enable
;
1350 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1353 uint32_t radeon_atom_get_engine_clock(struct radeon_device
*rdev
)
1355 GET_ENGINE_CLOCK_PS_ALLOCATION args
;
1356 int index
= GetIndexIntoMasterTable(COMMAND
, GetEngineClock
);
1358 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1359 return args
.ulReturnEngineClock
;
1362 uint32_t radeon_atom_get_memory_clock(struct radeon_device
*rdev
)
1364 GET_MEMORY_CLOCK_PS_ALLOCATION args
;
1365 int index
= GetIndexIntoMasterTable(COMMAND
, GetMemoryClock
);
1367 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1368 return args
.ulReturnMemoryClock
;
1371 void radeon_atom_set_engine_clock(struct radeon_device
*rdev
,
1374 SET_ENGINE_CLOCK_PS_ALLOCATION args
;
1375 int index
= GetIndexIntoMasterTable(COMMAND
, SetEngineClock
);
1377 args
.ulTargetEngineClock
= eng_clock
; /* 10 khz */
1379 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1382 void radeon_atom_set_memory_clock(struct radeon_device
*rdev
,
1385 SET_MEMORY_CLOCK_PS_ALLOCATION args
;
1386 int index
= GetIndexIntoMasterTable(COMMAND
, SetMemoryClock
);
1388 if (rdev
->flags
& RADEON_IS_IGP
)
1391 args
.ulTargetMemoryClock
= mem_clock
; /* 10 khz */
1393 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1396 void radeon_atom_initialize_bios_scratch_regs(struct drm_device
*dev
)
1398 struct radeon_device
*rdev
= dev
->dev_private
;
1399 uint32_t bios_2_scratch
, bios_6_scratch
;
1401 if (rdev
->family
>= CHIP_R600
) {
1402 bios_2_scratch
= RREG32(R600_BIOS_2_SCRATCH
);
1403 bios_6_scratch
= RREG32(R600_BIOS_6_SCRATCH
);
1405 bios_2_scratch
= RREG32(RADEON_BIOS_2_SCRATCH
);
1406 bios_6_scratch
= RREG32(RADEON_BIOS_6_SCRATCH
);
1409 /* let the bios control the backlight */
1410 bios_2_scratch
&= ~ATOM_S2_VRI_BRIGHT_ENABLE
;
1412 /* tell the bios not to handle mode switching */
1413 bios_6_scratch
|= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH
| ATOM_S6_ACC_MODE
);
1415 if (rdev
->family
>= CHIP_R600
) {
1416 WREG32(R600_BIOS_2_SCRATCH
, bios_2_scratch
);
1417 WREG32(R600_BIOS_6_SCRATCH
, bios_6_scratch
);
1419 WREG32(RADEON_BIOS_2_SCRATCH
, bios_2_scratch
);
1420 WREG32(RADEON_BIOS_6_SCRATCH
, bios_6_scratch
);
1425 void radeon_save_bios_scratch_regs(struct radeon_device
*rdev
)
1427 uint32_t scratch_reg
;
1430 if (rdev
->family
>= CHIP_R600
)
1431 scratch_reg
= R600_BIOS_0_SCRATCH
;
1433 scratch_reg
= RADEON_BIOS_0_SCRATCH
;
1435 for (i
= 0; i
< RADEON_BIOS_NUM_SCRATCH
; i
++)
1436 rdev
->bios_scratch
[i
] = RREG32(scratch_reg
+ (i
* 4));
1439 void radeon_restore_bios_scratch_regs(struct radeon_device
*rdev
)
1441 uint32_t scratch_reg
;
1444 if (rdev
->family
>= CHIP_R600
)
1445 scratch_reg
= R600_BIOS_0_SCRATCH
;
1447 scratch_reg
= RADEON_BIOS_0_SCRATCH
;
1449 for (i
= 0; i
< RADEON_BIOS_NUM_SCRATCH
; i
++)
1450 WREG32(scratch_reg
+ (i
* 4), rdev
->bios_scratch
[i
]);
1453 void radeon_atom_output_lock(struct drm_encoder
*encoder
, bool lock
)
1455 struct drm_device
*dev
= encoder
->dev
;
1456 struct radeon_device
*rdev
= dev
->dev_private
;
1457 uint32_t bios_6_scratch
;
1459 if (rdev
->family
>= CHIP_R600
)
1460 bios_6_scratch
= RREG32(R600_BIOS_6_SCRATCH
);
1462 bios_6_scratch
= RREG32(RADEON_BIOS_6_SCRATCH
);
1465 bios_6_scratch
|= ATOM_S6_CRITICAL_STATE
;
1467 bios_6_scratch
&= ~ATOM_S6_CRITICAL_STATE
;
1469 if (rdev
->family
>= CHIP_R600
)
1470 WREG32(R600_BIOS_6_SCRATCH
, bios_6_scratch
);
1472 WREG32(RADEON_BIOS_6_SCRATCH
, bios_6_scratch
);
1475 /* at some point we may want to break this out into individual functions */
1477 radeon_atombios_connected_scratch_regs(struct drm_connector
*connector
,
1478 struct drm_encoder
*encoder
,
1481 struct drm_device
*dev
= connector
->dev
;
1482 struct radeon_device
*rdev
= dev
->dev_private
;
1483 struct radeon_connector
*radeon_connector
=
1484 to_radeon_connector(connector
);
1485 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1486 uint32_t bios_0_scratch
, bios_3_scratch
, bios_6_scratch
;
1488 if (rdev
->family
>= CHIP_R600
) {
1489 bios_0_scratch
= RREG32(R600_BIOS_0_SCRATCH
);
1490 bios_3_scratch
= RREG32(R600_BIOS_3_SCRATCH
);
1491 bios_6_scratch
= RREG32(R600_BIOS_6_SCRATCH
);
1493 bios_0_scratch
= RREG32(RADEON_BIOS_0_SCRATCH
);
1494 bios_3_scratch
= RREG32(RADEON_BIOS_3_SCRATCH
);
1495 bios_6_scratch
= RREG32(RADEON_BIOS_6_SCRATCH
);
1498 if ((radeon_encoder
->devices
& ATOM_DEVICE_TV1_SUPPORT
) &&
1499 (radeon_connector
->devices
& ATOM_DEVICE_TV1_SUPPORT
)) {
1501 DRM_DEBUG("TV1 connected\n");
1502 bios_3_scratch
|= ATOM_S3_TV1_ACTIVE
;
1503 bios_6_scratch
|= ATOM_S6_ACC_REQ_TV1
;
1505 DRM_DEBUG("TV1 disconnected\n");
1506 bios_0_scratch
&= ~ATOM_S0_TV1_MASK
;
1507 bios_3_scratch
&= ~ATOM_S3_TV1_ACTIVE
;
1508 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_TV1
;
1511 if ((radeon_encoder
->devices
& ATOM_DEVICE_CV_SUPPORT
) &&
1512 (radeon_connector
->devices
& ATOM_DEVICE_CV_SUPPORT
)) {
1514 DRM_DEBUG("CV connected\n");
1515 bios_3_scratch
|= ATOM_S3_CV_ACTIVE
;
1516 bios_6_scratch
|= ATOM_S6_ACC_REQ_CV
;
1518 DRM_DEBUG("CV disconnected\n");
1519 bios_0_scratch
&= ~ATOM_S0_CV_MASK
;
1520 bios_3_scratch
&= ~ATOM_S3_CV_ACTIVE
;
1521 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_CV
;
1524 if ((radeon_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
) &&
1525 (radeon_connector
->devices
& ATOM_DEVICE_LCD1_SUPPORT
)) {
1527 DRM_DEBUG("LCD1 connected\n");
1528 bios_0_scratch
|= ATOM_S0_LCD1
;
1529 bios_3_scratch
|= ATOM_S3_LCD1_ACTIVE
;
1530 bios_6_scratch
|= ATOM_S6_ACC_REQ_LCD1
;
1532 DRM_DEBUG("LCD1 disconnected\n");
1533 bios_0_scratch
&= ~ATOM_S0_LCD1
;
1534 bios_3_scratch
&= ~ATOM_S3_LCD1_ACTIVE
;
1535 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_LCD1
;
1538 if ((radeon_encoder
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) &&
1539 (radeon_connector
->devices
& ATOM_DEVICE_CRT1_SUPPORT
)) {
1541 DRM_DEBUG("CRT1 connected\n");
1542 bios_0_scratch
|= ATOM_S0_CRT1_COLOR
;
1543 bios_3_scratch
|= ATOM_S3_CRT1_ACTIVE
;
1544 bios_6_scratch
|= ATOM_S6_ACC_REQ_CRT1
;
1546 DRM_DEBUG("CRT1 disconnected\n");
1547 bios_0_scratch
&= ~ATOM_S0_CRT1_MASK
;
1548 bios_3_scratch
&= ~ATOM_S3_CRT1_ACTIVE
;
1549 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_CRT1
;
1552 if ((radeon_encoder
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) &&
1553 (radeon_connector
->devices
& ATOM_DEVICE_CRT2_SUPPORT
)) {
1555 DRM_DEBUG("CRT2 connected\n");
1556 bios_0_scratch
|= ATOM_S0_CRT2_COLOR
;
1557 bios_3_scratch
|= ATOM_S3_CRT2_ACTIVE
;
1558 bios_6_scratch
|= ATOM_S6_ACC_REQ_CRT2
;
1560 DRM_DEBUG("CRT2 disconnected\n");
1561 bios_0_scratch
&= ~ATOM_S0_CRT2_MASK
;
1562 bios_3_scratch
&= ~ATOM_S3_CRT2_ACTIVE
;
1563 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_CRT2
;
1566 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP1_SUPPORT
) &&
1567 (radeon_connector
->devices
& ATOM_DEVICE_DFP1_SUPPORT
)) {
1569 DRM_DEBUG("DFP1 connected\n");
1570 bios_0_scratch
|= ATOM_S0_DFP1
;
1571 bios_3_scratch
|= ATOM_S3_DFP1_ACTIVE
;
1572 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP1
;
1574 DRM_DEBUG("DFP1 disconnected\n");
1575 bios_0_scratch
&= ~ATOM_S0_DFP1
;
1576 bios_3_scratch
&= ~ATOM_S3_DFP1_ACTIVE
;
1577 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP1
;
1580 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP2_SUPPORT
) &&
1581 (radeon_connector
->devices
& ATOM_DEVICE_DFP2_SUPPORT
)) {
1583 DRM_DEBUG("DFP2 connected\n");
1584 bios_0_scratch
|= ATOM_S0_DFP2
;
1585 bios_3_scratch
|= ATOM_S3_DFP2_ACTIVE
;
1586 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP2
;
1588 DRM_DEBUG("DFP2 disconnected\n");
1589 bios_0_scratch
&= ~ATOM_S0_DFP2
;
1590 bios_3_scratch
&= ~ATOM_S3_DFP2_ACTIVE
;
1591 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP2
;
1594 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP3_SUPPORT
) &&
1595 (radeon_connector
->devices
& ATOM_DEVICE_DFP3_SUPPORT
)) {
1597 DRM_DEBUG("DFP3 connected\n");
1598 bios_0_scratch
|= ATOM_S0_DFP3
;
1599 bios_3_scratch
|= ATOM_S3_DFP3_ACTIVE
;
1600 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP3
;
1602 DRM_DEBUG("DFP3 disconnected\n");
1603 bios_0_scratch
&= ~ATOM_S0_DFP3
;
1604 bios_3_scratch
&= ~ATOM_S3_DFP3_ACTIVE
;
1605 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP3
;
1608 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP4_SUPPORT
) &&
1609 (radeon_connector
->devices
& ATOM_DEVICE_DFP4_SUPPORT
)) {
1611 DRM_DEBUG("DFP4 connected\n");
1612 bios_0_scratch
|= ATOM_S0_DFP4
;
1613 bios_3_scratch
|= ATOM_S3_DFP4_ACTIVE
;
1614 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP4
;
1616 DRM_DEBUG("DFP4 disconnected\n");
1617 bios_0_scratch
&= ~ATOM_S0_DFP4
;
1618 bios_3_scratch
&= ~ATOM_S3_DFP4_ACTIVE
;
1619 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP4
;
1622 if ((radeon_encoder
->devices
& ATOM_DEVICE_DFP5_SUPPORT
) &&
1623 (radeon_connector
->devices
& ATOM_DEVICE_DFP5_SUPPORT
)) {
1625 DRM_DEBUG("DFP5 connected\n");
1626 bios_0_scratch
|= ATOM_S0_DFP5
;
1627 bios_3_scratch
|= ATOM_S3_DFP5_ACTIVE
;
1628 bios_6_scratch
|= ATOM_S6_ACC_REQ_DFP5
;
1630 DRM_DEBUG("DFP5 disconnected\n");
1631 bios_0_scratch
&= ~ATOM_S0_DFP5
;
1632 bios_3_scratch
&= ~ATOM_S3_DFP5_ACTIVE
;
1633 bios_6_scratch
&= ~ATOM_S6_ACC_REQ_DFP5
;
1637 if (rdev
->family
>= CHIP_R600
) {
1638 WREG32(R600_BIOS_0_SCRATCH
, bios_0_scratch
);
1639 WREG32(R600_BIOS_3_SCRATCH
, bios_3_scratch
);
1640 WREG32(R600_BIOS_6_SCRATCH
, bios_6_scratch
);
1642 WREG32(RADEON_BIOS_0_SCRATCH
, bios_0_scratch
);
1643 WREG32(RADEON_BIOS_3_SCRATCH
, bios_3_scratch
);
1644 WREG32(RADEON_BIOS_6_SCRATCH
, bios_6_scratch
);
1649 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder
*encoder
, int crtc
)
1651 struct drm_device
*dev
= encoder
->dev
;
1652 struct radeon_device
*rdev
= dev
->dev_private
;
1653 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1654 uint32_t bios_3_scratch
;
1656 if (rdev
->family
>= CHIP_R600
)
1657 bios_3_scratch
= RREG32(R600_BIOS_3_SCRATCH
);
1659 bios_3_scratch
= RREG32(RADEON_BIOS_3_SCRATCH
);
1661 if (radeon_encoder
->devices
& ATOM_DEVICE_TV1_SUPPORT
) {
1662 bios_3_scratch
&= ~ATOM_S3_TV1_CRTC_ACTIVE
;
1663 bios_3_scratch
|= (crtc
<< 18);
1665 if (radeon_encoder
->devices
& ATOM_DEVICE_CV_SUPPORT
) {
1666 bios_3_scratch
&= ~ATOM_S3_CV_CRTC_ACTIVE
;
1667 bios_3_scratch
|= (crtc
<< 24);
1669 if (radeon_encoder
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) {
1670 bios_3_scratch
&= ~ATOM_S3_CRT1_CRTC_ACTIVE
;
1671 bios_3_scratch
|= (crtc
<< 16);
1673 if (radeon_encoder
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) {
1674 bios_3_scratch
&= ~ATOM_S3_CRT2_CRTC_ACTIVE
;
1675 bios_3_scratch
|= (crtc
<< 20);
1677 if (radeon_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
) {
1678 bios_3_scratch
&= ~ATOM_S3_LCD1_CRTC_ACTIVE
;
1679 bios_3_scratch
|= (crtc
<< 17);
1681 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP1_SUPPORT
) {
1682 bios_3_scratch
&= ~ATOM_S3_DFP1_CRTC_ACTIVE
;
1683 bios_3_scratch
|= (crtc
<< 19);
1685 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP2_SUPPORT
) {
1686 bios_3_scratch
&= ~ATOM_S3_DFP2_CRTC_ACTIVE
;
1687 bios_3_scratch
|= (crtc
<< 23);
1689 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP3_SUPPORT
) {
1690 bios_3_scratch
&= ~ATOM_S3_DFP3_CRTC_ACTIVE
;
1691 bios_3_scratch
|= (crtc
<< 25);
1694 if (rdev
->family
>= CHIP_R600
)
1695 WREG32(R600_BIOS_3_SCRATCH
, bios_3_scratch
);
1697 WREG32(RADEON_BIOS_3_SCRATCH
, bios_3_scratch
);
1701 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder
*encoder
, bool on
)
1703 struct drm_device
*dev
= encoder
->dev
;
1704 struct radeon_device
*rdev
= dev
->dev_private
;
1705 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1706 uint32_t bios_2_scratch
;
1708 if (rdev
->family
>= CHIP_R600
)
1709 bios_2_scratch
= RREG32(R600_BIOS_2_SCRATCH
);
1711 bios_2_scratch
= RREG32(RADEON_BIOS_2_SCRATCH
);
1713 if (radeon_encoder
->devices
& ATOM_DEVICE_TV1_SUPPORT
) {
1715 bios_2_scratch
&= ~ATOM_S2_TV1_DPMS_STATE
;
1717 bios_2_scratch
|= ATOM_S2_TV1_DPMS_STATE
;
1719 if (radeon_encoder
->devices
& ATOM_DEVICE_CV_SUPPORT
) {
1721 bios_2_scratch
&= ~ATOM_S2_CV_DPMS_STATE
;
1723 bios_2_scratch
|= ATOM_S2_CV_DPMS_STATE
;
1725 if (radeon_encoder
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) {
1727 bios_2_scratch
&= ~ATOM_S2_CRT1_DPMS_STATE
;
1729 bios_2_scratch
|= ATOM_S2_CRT1_DPMS_STATE
;
1731 if (radeon_encoder
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) {
1733 bios_2_scratch
&= ~ATOM_S2_CRT2_DPMS_STATE
;
1735 bios_2_scratch
|= ATOM_S2_CRT2_DPMS_STATE
;
1737 if (radeon_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
) {
1739 bios_2_scratch
&= ~ATOM_S2_LCD1_DPMS_STATE
;
1741 bios_2_scratch
|= ATOM_S2_LCD1_DPMS_STATE
;
1743 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP1_SUPPORT
) {
1745 bios_2_scratch
&= ~ATOM_S2_DFP1_DPMS_STATE
;
1747 bios_2_scratch
|= ATOM_S2_DFP1_DPMS_STATE
;
1749 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP2_SUPPORT
) {
1751 bios_2_scratch
&= ~ATOM_S2_DFP2_DPMS_STATE
;
1753 bios_2_scratch
|= ATOM_S2_DFP2_DPMS_STATE
;
1755 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP3_SUPPORT
) {
1757 bios_2_scratch
&= ~ATOM_S2_DFP3_DPMS_STATE
;
1759 bios_2_scratch
|= ATOM_S2_DFP3_DPMS_STATE
;
1761 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP4_SUPPORT
) {
1763 bios_2_scratch
&= ~ATOM_S2_DFP4_DPMS_STATE
;
1765 bios_2_scratch
|= ATOM_S2_DFP4_DPMS_STATE
;
1767 if (radeon_encoder
->devices
& ATOM_DEVICE_DFP5_SUPPORT
) {
1769 bios_2_scratch
&= ~ATOM_S2_DFP5_DPMS_STATE
;
1771 bios_2_scratch
|= ATOM_S2_DFP5_DPMS_STATE
;
1774 if (rdev
->family
>= CHIP_R600
)
1775 WREG32(R600_BIOS_2_SCRATCH
, bios_2_scratch
);
1777 WREG32(RADEON_BIOS_2_SCRATCH
, bios_2_scratch
);