1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2005-2008 Solarflare Communications Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
11 /* Common definitions for all Efx net driver code */
13 #ifndef EFX_NET_DRIVER_H
14 #define EFX_NET_DRIVER_H
16 #include <linux/version.h>
17 #include <linux/netdevice.h>
18 #include <linux/etherdevice.h>
19 #include <linux/ethtool.h>
20 #include <linux/if_vlan.h>
21 #include <linux/timer.h>
22 #include <linux/mii.h>
23 #include <linux/list.h>
24 #include <linux/pci.h>
25 #include <linux/device.h>
26 #include <linux/highmem.h>
27 #include <linux/workqueue.h>
28 #include <linux/inet_lro.h>
29 #include <linux/i2c.h>
34 #define EFX_MAX_LRO_DESCRIPTORS 8
35 #define EFX_MAX_LRO_AGGR MAX_SKB_FRAGS
37 /**************************************************************************
41 **************************************************************************/
42 #ifndef EFX_DRIVER_NAME
43 #define EFX_DRIVER_NAME "sfc"
45 #define EFX_DRIVER_VERSION "2.2"
47 #ifdef EFX_ENABLE_DEBUG
48 #define EFX_BUG_ON_PARANOID(x) BUG_ON(x)
49 #define EFX_WARN_ON_PARANOID(x) WARN_ON(x)
51 #define EFX_BUG_ON_PARANOID(x) do {} while (0)
52 #define EFX_WARN_ON_PARANOID(x) do {} while (0)
55 /* Un-rate-limited logging */
56 #define EFX_ERR(efx, fmt, args...) \
57 dev_err(&((efx)->pci_dev->dev), "ERR: %s " fmt, efx_dev_name(efx), ##args)
59 #define EFX_INFO(efx, fmt, args...) \
60 dev_info(&((efx)->pci_dev->dev), "INFO: %s " fmt, efx_dev_name(efx), ##args)
62 #ifdef EFX_ENABLE_DEBUG
63 #define EFX_LOG(efx, fmt, args...) \
64 dev_info(&((efx)->pci_dev->dev), "DBG: %s " fmt, efx_dev_name(efx), ##args)
66 #define EFX_LOG(efx, fmt, args...) \
67 dev_dbg(&((efx)->pci_dev->dev), "DBG: %s " fmt, efx_dev_name(efx), ##args)
70 #define EFX_TRACE(efx, fmt, args...) do {} while (0)
72 #define EFX_REGDUMP(efx, fmt, args...) do {} while (0)
74 /* Rate-limited logging */
75 #define EFX_ERR_RL(efx, fmt, args...) \
76 do {if (net_ratelimit()) EFX_ERR(efx, fmt, ##args); } while (0)
78 #define EFX_INFO_RL(efx, fmt, args...) \
79 do {if (net_ratelimit()) EFX_INFO(efx, fmt, ##args); } while (0)
81 #define EFX_LOG_RL(efx, fmt, args...) \
82 do {if (net_ratelimit()) EFX_LOG(efx, fmt, ##args); } while (0)
84 /**************************************************************************
88 **************************************************************************/
90 #define EFX_MAX_CHANNELS 32
91 #define EFX_MAX_RX_QUEUES EFX_MAX_CHANNELS
93 #define EFX_TX_QUEUE_OFFLOAD_CSUM 0
94 #define EFX_TX_QUEUE_NO_CSUM 1
95 #define EFX_TX_QUEUE_COUNT 2
98 * struct efx_special_buffer - An Efx special buffer
99 * @addr: CPU base address of the buffer
100 * @dma_addr: DMA base address of the buffer
101 * @len: Buffer length, in bytes
102 * @index: Buffer index within controller;s buffer table
103 * @entries: Number of buffer table entries
105 * Special buffers are used for the event queues and the TX and RX
106 * descriptor queues for each channel. They are *not* used for the
107 * actual transmit and receive buffers.
109 * Note that for Falcon, TX and RX descriptor queues live in host memory.
110 * Allocation and freeing procedures must take this into account.
112 struct efx_special_buffer
{
121 * struct efx_tx_buffer - An Efx TX buffer
122 * @skb: The associated socket buffer.
123 * Set only on the final fragment of a packet; %NULL for all other
124 * fragments. When this fragment completes, then we can free this
126 * @tsoh: The associated TSO header structure, or %NULL if this
127 * buffer is not a TSO header.
128 * @dma_addr: DMA address of the fragment.
129 * @len: Length of this fragment.
130 * This field is zero when the queue slot is empty.
131 * @continuation: True if this fragment is not the end of a packet.
132 * @unmap_single: True if pci_unmap_single should be used.
133 * @unmap_len: Length of this fragment to unmap
135 struct efx_tx_buffer
{
136 const struct sk_buff
*skb
;
137 struct efx_tso_header
*tsoh
;
142 unsigned short unmap_len
;
146 * struct efx_tx_queue - An Efx TX queue
148 * This is a ring buffer of TX fragments.
149 * Since the TX completion path always executes on the same
150 * CPU and the xmit path can operate on different CPUs,
151 * performance is increased by ensuring that the completion
152 * path and the xmit path operate on different cache lines.
153 * This is particularly important if the xmit path is always
154 * executing on one CPU which is different from the completion
155 * path. There is also a cache line for members which are
156 * read but not written on the fast path.
158 * @efx: The associated Efx NIC
159 * @queue: DMA queue number
160 * @channel: The associated channel
161 * @buffer: The software buffer ring
162 * @txd: The hardware descriptor ring
163 * @flushed: Used when handling queue flushing
164 * @read_count: Current read pointer.
165 * This is the number of buffers that have been removed from both rings.
166 * @stopped: Stopped count.
167 * Set if this TX queue is currently stopping its port.
168 * @insert_count: Current insert pointer
169 * This is the number of buffers that have been added to the
171 * @write_count: Current write pointer
172 * This is the number of buffers that have been added to the
174 * @old_read_count: The value of read_count when last checked.
175 * This is here for performance reasons. The xmit path will
176 * only get the up-to-date value of read_count if this
177 * variable indicates that the queue is full. This is to
178 * avoid cache-line ping-pong between the xmit path and the
180 * @tso_headers_free: A list of TSO headers allocated for this TX queue
181 * that are not in use, and so available for new TSO sends. The list
182 * is protected by the TX queue lock.
183 * @tso_bursts: Number of times TSO xmit invoked by kernel
184 * @tso_long_headers: Number of packets with headers too long for standard
186 * @tso_packets: Number of packets via the TSO xmit path
188 struct efx_tx_queue
{
189 /* Members which don't change on the fast path */
190 struct efx_nic
*efx ____cacheline_aligned_in_smp
;
192 struct efx_channel
*channel
;
194 struct efx_tx_buffer
*buffer
;
195 struct efx_special_buffer txd
;
198 /* Members used mainly on the completion path */
199 unsigned int read_count ____cacheline_aligned_in_smp
;
202 /* Members used only on the xmit path */
203 unsigned int insert_count ____cacheline_aligned_in_smp
;
204 unsigned int write_count
;
205 unsigned int old_read_count
;
206 struct efx_tso_header
*tso_headers_free
;
207 unsigned int tso_bursts
;
208 unsigned int tso_long_headers
;
209 unsigned int tso_packets
;
213 * struct efx_rx_buffer - An Efx RX data buffer
214 * @dma_addr: DMA base address of the buffer
215 * @skb: The associated socket buffer, if any.
216 * If both this and page are %NULL, the buffer slot is currently free.
217 * @page: The associated page buffer, if any.
218 * If both this and skb are %NULL, the buffer slot is currently free.
219 * @data: Pointer to ethernet header
220 * @len: Buffer length, in bytes.
221 * @unmap_addr: DMA address to unmap
223 struct efx_rx_buffer
{
229 dma_addr_t unmap_addr
;
233 * struct efx_rx_queue - An Efx RX queue
234 * @efx: The associated Efx NIC
235 * @queue: DMA queue number
236 * @channel: The associated channel
237 * @buffer: The software buffer ring
238 * @rxd: The hardware descriptor ring
239 * @added_count: Number of buffers added to the receive queue.
240 * @notified_count: Number of buffers given to NIC (<= @added_count).
241 * @removed_count: Number of buffers removed from the receive queue.
242 * @add_lock: Receive queue descriptor add spin lock.
243 * This lock must be held in order to add buffers to the RX
244 * descriptor ring (rxd and buffer) and to update added_count (but
245 * not removed_count).
246 * @max_fill: RX descriptor maximum fill level (<= ring size)
247 * @fast_fill_trigger: RX descriptor fill level that will trigger a fast fill
249 * @fast_fill_limit: The level to which a fast fill will fill
250 * (@fast_fill_trigger <= @fast_fill_limit <= @max_fill)
251 * @min_fill: RX descriptor minimum non-zero fill level.
252 * This records the minimum fill level observed when a ring
253 * refill was triggered.
254 * @min_overfill: RX descriptor minimum overflow fill level.
255 * This records the minimum fill level at which RX queue
256 * overflow was observed. It should never be set.
257 * @alloc_page_count: RX allocation strategy counter.
258 * @alloc_skb_count: RX allocation strategy counter.
259 * @work: Descriptor push work thread
260 * @buf_page: Page for next RX buffer.
261 * We can use a single page for multiple RX buffers. This tracks
262 * the remaining space in the allocation.
263 * @buf_dma_addr: Page's DMA address.
264 * @buf_data: Page's host address.
265 * @flushed: Use when handling queue flushing
267 struct efx_rx_queue
{
270 struct efx_channel
*channel
;
271 struct efx_rx_buffer
*buffer
;
272 struct efx_special_buffer rxd
;
278 unsigned int max_fill
;
279 unsigned int fast_fill_trigger
;
280 unsigned int fast_fill_limit
;
281 unsigned int min_fill
;
282 unsigned int min_overfill
;
283 unsigned int alloc_page_count
;
284 unsigned int alloc_skb_count
;
285 struct delayed_work work
;
286 unsigned int slow_fill_count
;
288 struct page
*buf_page
;
289 dma_addr_t buf_dma_addr
;
295 * struct efx_buffer - An Efx general-purpose buffer
296 * @addr: host base address of the buffer
297 * @dma_addr: DMA base address of the buffer
298 * @len: Buffer length, in bytes
300 * Falcon uses these buffers for its interrupt status registers and
310 /* Flags for channel->used_flags */
311 #define EFX_USED_BY_RX 1
312 #define EFX_USED_BY_TX 2
313 #define EFX_USED_BY_RX_TX (EFX_USED_BY_RX | EFX_USED_BY_TX)
315 enum efx_rx_alloc_method
{
316 RX_ALLOC_METHOD_AUTO
= 0,
317 RX_ALLOC_METHOD_SKB
= 1,
318 RX_ALLOC_METHOD_PAGE
= 2,
322 * struct efx_channel - An Efx channel
324 * A channel comprises an event queue, at least one TX queue, at least
325 * one RX queue, and an associated tasklet for processing the event
328 * @efx: Associated Efx NIC
329 * @channel: Channel instance number
330 * @name: Name for channel and IRQ
331 * @used_flags: Channel is used by net driver
332 * @enabled: Channel enabled indicator
333 * @irq: IRQ number (MSI and MSI-X only)
334 * @irq_moderation: IRQ moderation value (in us)
335 * @napi_dev: Net device used with NAPI
336 * @napi_str: NAPI control structure
337 * @reset_work: Scheduled reset work thread
338 * @work_pending: Is work pending via NAPI?
339 * @eventq: Event queue buffer
340 * @eventq_read_ptr: Event queue read pointer
341 * @last_eventq_read_ptr: Last event queue read pointer value.
342 * @eventq_magic: Event queue magic value for driver-generated test events
343 * @lro_mgr: LRO state
344 * @rx_alloc_level: Watermark based heuristic counter for pushing descriptors
345 * and diagnostic counters
346 * @rx_alloc_push_pages: RX allocation method currently in use for pushing
348 * @rx_alloc_pop_pages: RX allocation method currently in use for popping
350 * @n_rx_tobe_disc: Count of RX_TOBE_DISC errors
351 * @n_rx_ip_frag_err: Count of RX IP fragment errors
352 * @n_rx_ip_hdr_chksum_err: Count of RX IP header checksum errors
353 * @n_rx_tcp_udp_chksum_err: Count of RX TCP and UDP checksum errors
354 * @n_rx_frm_trunc: Count of RX_FRM_TRUNC errors
355 * @n_rx_overlength: Count of RX_OVERLENGTH errors
356 * @n_skbuff_leaks: Count of skbuffs leaked due to RX overrun
361 char name
[IFNAMSIZ
+ 6];
365 unsigned int irq_moderation
;
366 struct net_device
*napi_dev
;
367 struct napi_struct napi_str
;
369 struct efx_special_buffer eventq
;
370 unsigned int eventq_read_ptr
;
371 unsigned int last_eventq_read_ptr
;
372 unsigned int eventq_magic
;
374 struct net_lro_mgr lro_mgr
;
376 int rx_alloc_push_pages
;
377 int rx_alloc_pop_pages
;
379 unsigned n_rx_tobe_disc
;
380 unsigned n_rx_ip_frag_err
;
381 unsigned n_rx_ip_hdr_chksum_err
;
382 unsigned n_rx_tcp_udp_chksum_err
;
383 unsigned n_rx_frm_trunc
;
384 unsigned n_rx_overlength
;
385 unsigned n_skbuff_leaks
;
387 /* Used to pipeline received packets in order to optimise memory
388 * access with prefetches.
390 struct efx_rx_buffer
*rx_pkt
;
396 * struct efx_blinker - S/W LED blinking context
397 * @led_num: LED ID (board-specific meaning)
398 * @state: Current state - on or off
399 * @resubmit: Timer resubmission flag
400 * @timer: Control timer for blinking
406 struct timer_list timer
;
411 * struct efx_board - board information
412 * @type: Board model type
413 * @major: Major rev. ('A', 'B' ...)
414 * @minor: Minor rev. (0, 1, ...)
415 * @init: Initialisation function
416 * @init_leds: Sets up board LEDs
417 * @set_fault_led: Turns the fault LED on or off
418 * @blink: Starts/stops blinking
419 * @monitor: Board-specific health check function
420 * @fini: Cleanup function
421 * @blinker: used to blink LEDs in software
422 * @hwmon_client: I2C client for hardware monitor
423 * @ioexp_client: I2C client for power/port control
429 int (*init
) (struct efx_nic
*nic
);
430 /* As the LEDs are typically attached to the PHY, LEDs
431 * have a separate init callback that happens later than
433 int (*init_leds
)(struct efx_nic
*efx
);
434 int (*monitor
) (struct efx_nic
*nic
);
435 void (*set_fault_led
) (struct efx_nic
*efx
, bool state
);
436 void (*blink
) (struct efx_nic
*efx
, bool start
);
437 void (*fini
) (struct efx_nic
*nic
);
438 struct efx_blinker blinker
;
439 struct i2c_client
*hwmon_client
, *ioexp_client
;
442 #define STRING_TABLE_LOOKUP(val, member) \
443 member ## _names[val]
446 /* Be careful if altering to correct macro below */
447 EFX_INT_MODE_MSIX
= 0,
448 EFX_INT_MODE_MSI
= 1,
449 EFX_INT_MODE_LEGACY
= 2,
450 EFX_INT_MODE_MAX
/* Insert any new items before this */
452 #define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI)
456 PHY_TYPE_CX4_RTMR
= 1,
457 PHY_TYPE_1G_ALASKA
= 2,
458 PHY_TYPE_10XPRESS
= 3,
461 PHY_TYPE_MAX
/* Insert any new items before this */
464 #define PHY_ADDR_INVALID 0xff
466 #define EFX_IS10G(efx) ((efx)->link_speed == 10000)
477 * Alignment of page-allocated RX buffers
479 * Controls the number of bytes inserted at the start of an RX buffer.
480 * This is the equivalent of NET_IP_ALIGN [which controls the alignment
481 * of the skb->head for hardware DMA].
483 #ifdef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
484 #define EFX_PAGE_IP_ALIGN 0
486 #define EFX_PAGE_IP_ALIGN NET_IP_ALIGN
490 * Alignment of the skb->head which wraps a page-allocated RX buffer
492 * The skb allocated to wrap an rx_buffer can have this alignment. Since
493 * the data is memcpy'd from the rx_buf, it does not need to be equal to
496 #define EFX_PAGE_SKB_ALIGN 2
498 /* Forward declaration */
501 /* Pseudo bit-mask flow control field */
508 /* Supported MAC bit-mask */
515 * struct efx_mac_operations - Efx MAC operations table
516 * @reconfigure: Reconfigure MAC. Serialised by the mac_lock
517 * @update_stats: Update statistics
518 * @check_hw: Check hardware. Serialised by the mac_lock
520 struct efx_mac_operations
{
521 void (*reconfigure
) (struct efx_nic
*efx
);
522 void (*update_stats
) (struct efx_nic
*efx
);
523 int (*check_hw
) (struct efx_nic
*efx
);
527 * struct efx_phy_operations - Efx PHY operations table
528 * @init: Initialise PHY
529 * @fini: Shut down PHY
530 * @reconfigure: Reconfigure PHY (e.g. for new link parameters)
531 * @clear_interrupt: Clear down interrupt
533 * @check_hw: Check hardware
534 * @get_settings: Get ethtool settings. Serialised by the mac_lock.
535 * @set_settings: Set ethtool settings. Serialised by the mac_lock.
536 * @mmds: MMD presence mask
537 * @loopbacks: Supported loopback modes mask
539 struct efx_phy_operations
{
540 enum efx_mac_type macs
;
541 int (*init
) (struct efx_nic
*efx
);
542 void (*fini
) (struct efx_nic
*efx
);
543 void (*reconfigure
) (struct efx_nic
*efx
);
544 void (*clear_interrupt
) (struct efx_nic
*efx
);
545 int (*check_hw
) (struct efx_nic
*efx
);
546 int (*test
) (struct efx_nic
*efx
);
547 void (*get_settings
) (struct efx_nic
*efx
,
548 struct ethtool_cmd
*ecmd
);
549 int (*set_settings
) (struct efx_nic
*efx
,
550 struct ethtool_cmd
*ecmd
);
556 * @enum efx_phy_mode - PHY operating mode flags
557 * @PHY_MODE_NORMAL: on and should pass traffic
558 * @PHY_MODE_TX_DISABLED: on with TX disabled
559 * @PHY_MODE_LOW_POWER: set to low power through MDIO
560 * @PHY_MODE_OFF: switched off through external control
561 * @PHY_MODE_SPECIAL: on but will not pass traffic
565 PHY_MODE_TX_DISABLED
= 1,
566 PHY_MODE_LOW_POWER
= 2,
568 PHY_MODE_SPECIAL
= 8,
571 static inline bool efx_phy_mode_disabled(enum efx_phy_mode mode
)
573 return !!(mode
& ~PHY_MODE_TX_DISABLED
);
577 * Efx extended statistics
579 * Not all statistics are provided by all supported MACs. The purpose
580 * is this structure is to contain the raw statistics provided by each
583 struct efx_mac_stats
{
587 unsigned long tx_packets
;
588 unsigned long tx_bad
;
589 unsigned long tx_pause
;
590 unsigned long tx_control
;
591 unsigned long tx_unicast
;
592 unsigned long tx_multicast
;
593 unsigned long tx_broadcast
;
594 unsigned long tx_lt64
;
596 unsigned long tx_65_to_127
;
597 unsigned long tx_128_to_255
;
598 unsigned long tx_256_to_511
;
599 unsigned long tx_512_to_1023
;
600 unsigned long tx_1024_to_15xx
;
601 unsigned long tx_15xx_to_jumbo
;
602 unsigned long tx_gtjumbo
;
603 unsigned long tx_collision
;
604 unsigned long tx_single_collision
;
605 unsigned long tx_multiple_collision
;
606 unsigned long tx_excessive_collision
;
607 unsigned long tx_deferred
;
608 unsigned long tx_late_collision
;
609 unsigned long tx_excessive_deferred
;
610 unsigned long tx_non_tcpudp
;
611 unsigned long tx_mac_src_error
;
612 unsigned long tx_ip_src_error
;
616 unsigned long rx_packets
;
617 unsigned long rx_good
;
618 unsigned long rx_bad
;
619 unsigned long rx_pause
;
620 unsigned long rx_control
;
621 unsigned long rx_unicast
;
622 unsigned long rx_multicast
;
623 unsigned long rx_broadcast
;
624 unsigned long rx_lt64
;
626 unsigned long rx_65_to_127
;
627 unsigned long rx_128_to_255
;
628 unsigned long rx_256_to_511
;
629 unsigned long rx_512_to_1023
;
630 unsigned long rx_1024_to_15xx
;
631 unsigned long rx_15xx_to_jumbo
;
632 unsigned long rx_gtjumbo
;
633 unsigned long rx_bad_lt64
;
634 unsigned long rx_bad_64_to_15xx
;
635 unsigned long rx_bad_15xx_to_jumbo
;
636 unsigned long rx_bad_gtjumbo
;
637 unsigned long rx_overflow
;
638 unsigned long rx_missed
;
639 unsigned long rx_false_carrier
;
640 unsigned long rx_symbol_error
;
641 unsigned long rx_align_error
;
642 unsigned long rx_length_error
;
643 unsigned long rx_internal_error
;
644 unsigned long rx_good_lt64
;
647 /* Number of bits used in a multicast filter hash address */
648 #define EFX_MCAST_HASH_BITS 8
650 /* Number of (single-bit) entries in a multicast filter hash */
651 #define EFX_MCAST_HASH_ENTRIES (1 << EFX_MCAST_HASH_BITS)
653 /* An Efx multicast filter hash */
654 union efx_multicast_hash
{
655 u8 byte
[EFX_MCAST_HASH_ENTRIES
/ 8];
656 efx_oword_t oword
[EFX_MCAST_HASH_ENTRIES
/ sizeof(efx_oword_t
) / 8];
660 * struct efx_nic - an Efx NIC
661 * @name: Device name (net device name or bus id before net device registered)
662 * @pci_dev: The PCI device
663 * @type: Controller type attributes
664 * @legacy_irq: IRQ number
665 * @workqueue: Workqueue for port reconfigures and the HW monitor.
666 * Work items do not hold and must not acquire RTNL.
667 * @reset_work: Scheduled reset workitem
668 * @monitor_work: Hardware monitor workitem
669 * @membase_phys: Memory BAR value as physical address
670 * @membase: Memory BAR value
671 * @biu_lock: BIU (bus interface unit) lock
672 * @interrupt_mode: Interrupt mode
673 * @i2c_adap: I2C adapter
674 * @board_info: Board-level information
675 * @state: Device state flag. Serialised by the rtnl_lock.
676 * @reset_pending: Pending reset method (normally RESET_TYPE_NONE)
677 * @tx_queue: TX DMA queues
678 * @rx_queue: RX DMA queues
680 * @n_rx_queues: Number of RX queues
681 * @n_channels: Number of channels in use
682 * @rx_buffer_len: RX buffer length
683 * @rx_buffer_order: Order (log2) of number of pages for each RX buffer
684 * @irq_status: Interrupt status buffer
685 * @last_irq_cpu: Last CPU to handle interrupt.
686 * This register is written with the SMP processor ID whenever an
687 * interrupt is handled. It is used by falcon_test_interrupt()
688 * to verify that an interrupt has occurred.
689 * @spi_flash: SPI flash device
690 * This field will be %NULL if no flash device is present.
691 * @spi_eeprom: SPI EEPROM device
692 * This field will be %NULL if no EEPROM device is present.
693 * @spi_lock: SPI bus lock
694 * @n_rx_nodesc_drop_cnt: RX no descriptor drop count
695 * @nic_data: Hardware dependant state
696 * @mac_lock: MAC access lock. Protects @port_enabled, @phy_mode,
697 * @port_inhibited, efx_monitor() and efx_reconfigure_port()
698 * @port_enabled: Port enabled indicator.
699 * Serialises efx_stop_all(), efx_start_all() and efx_monitor() and
700 * efx_reconfigure_work with kernel interfaces. Safe to read under any
701 * one of the rtnl_lock, mac_lock, or netif_tx_lock, but all three must
702 * be held to modify it.
703 * @port_inhibited: If set, the netif_carrier is always off. Hold the mac_lock
704 * @port_initialized: Port initialized?
705 * @net_dev: Operating system network device. Consider holding the rtnl lock
706 * @rx_checksum_enabled: RX checksumming enabled
707 * @netif_stop_count: Port stop count
708 * @netif_stop_lock: Port stop lock
709 * @mac_stats: MAC statistics. These include all statistics the MACs
710 * can provide. Generic code converts these into a standard
711 * &struct net_device_stats.
712 * @stats_buffer: DMA buffer for statistics
713 * @stats_lock: Statistics update lock. Serialises statistics fetches
714 * @stats_enabled: Temporarily disable statistics fetches.
715 * Serialised by @stats_lock
716 * @mac_op: MAC interface
717 * @mac_address: Permanent MAC address
718 * @phy_type: PHY type
719 * @phy_lock: PHY access lock
720 * @phy_op: PHY interface
721 * @phy_data: PHY private data (including PHY-specific stats)
722 * @mii: PHY interface
723 * @phy_mode: PHY operating mode. Serialised by @mac_lock.
724 * @mac_up: MAC link state
725 * @link_up: Link status
726 * @link_fd: Link is full duplex
727 * @link_speed: Link speed (Mbps)
728 * @n_link_state_changes: Number of times the link has changed state
729 * @promiscuous: Promiscuous flag. Protected by netif_tx_lock.
730 * @multicast_hash: Multicast hash table
731 * @flow_control: Flow control flags - separate RX/TX so can't use link_options
732 * @reconfigure_work: work item for dealing with PHY events
733 * @loopback_mode: Loopback status
734 * @loopback_modes: Supported loopback mode bitmask
735 * @loopback_selftest: Offline self-test private state
737 * The @priv field of the corresponding &struct net_device points to
742 struct pci_dev
*pci_dev
;
743 const struct efx_nic_type
*type
;
745 struct workqueue_struct
*workqueue
;
746 struct work_struct reset_work
;
747 struct delayed_work monitor_work
;
748 resource_size_t membase_phys
;
749 void __iomem
*membase
;
751 enum efx_int_mode interrupt_mode
;
753 struct i2c_adapter i2c_adap
;
754 struct efx_board board_info
;
756 enum nic_state state
;
757 enum reset_type reset_pending
;
759 struct efx_tx_queue tx_queue
[EFX_TX_QUEUE_COUNT
];
760 struct efx_rx_queue rx_queue
[EFX_MAX_RX_QUEUES
];
761 struct efx_channel channel
[EFX_MAX_CHANNELS
];
765 unsigned int rx_buffer_len
;
766 unsigned int rx_buffer_order
;
768 struct efx_buffer irq_status
;
769 volatile signed int last_irq_cpu
;
771 struct efx_spi_device
*spi_flash
;
772 struct efx_spi_device
*spi_eeprom
;
773 struct mutex spi_lock
;
775 unsigned n_rx_nodesc_drop_cnt
;
777 struct falcon_nic_data
*nic_data
;
779 struct mutex mac_lock
;
783 bool port_initialized
;
784 struct net_device
*net_dev
;
785 bool rx_checksum_enabled
;
787 atomic_t netif_stop_count
;
788 spinlock_t netif_stop_lock
;
790 struct efx_mac_stats mac_stats
;
791 struct efx_buffer stats_buffer
;
792 spinlock_t stats_lock
;
795 struct efx_mac_operations
*mac_op
;
796 unsigned char mac_address
[ETH_ALEN
];
798 enum phy_type phy_type
;
800 struct efx_phy_operations
*phy_op
;
802 struct mii_if_info mii
;
803 enum efx_phy_mode phy_mode
;
808 unsigned int link_speed
;
809 unsigned int n_link_state_changes
;
812 union efx_multicast_hash multicast_hash
;
813 enum efx_fc_type flow_control
;
814 struct work_struct reconfigure_work
;
817 enum efx_loopback_mode loopback_mode
;
818 unsigned int loopback_modes
;
820 void *loopback_selftest
;
823 static inline int efx_dev_registered(struct efx_nic
*efx
)
825 return efx
->net_dev
->reg_state
== NETREG_REGISTERED
;
828 /* Net device name, for inclusion in log messages if it has been registered.
829 * Use efx->name not efx->net_dev->name so that races with (un)registration
832 static inline const char *efx_dev_name(struct efx_nic
*efx
)
834 return efx_dev_registered(efx
) ? efx
->name
: "";
838 * struct efx_nic_type - Efx device type definition
839 * @mem_bar: Memory BAR number
840 * @mem_map_size: Memory BAR mapped size
841 * @txd_ptr_tbl_base: TX descriptor ring base address
842 * @rxd_ptr_tbl_base: RX descriptor ring base address
843 * @buf_tbl_base: Buffer table base address
844 * @evq_ptr_tbl_base: Event queue pointer table base address
845 * @evq_rptr_tbl_base: Event queue read-pointer table base address
846 * @txd_ring_mask: TX descriptor ring size - 1 (must be a power of two - 1)
847 * @rxd_ring_mask: RX descriptor ring size - 1 (must be a power of two - 1)
848 * @evq_size: Event queue size (must be a power of two)
849 * @max_dma_mask: Maximum possible DMA mask
850 * @tx_dma_mask: TX DMA mask
851 * @bug5391_mask: Address mask for bug 5391 workaround
852 * @rx_xoff_thresh: RX FIFO XOFF watermark (bytes)
853 * @rx_xon_thresh: RX FIFO XON watermark (bytes)
854 * @rx_buffer_padding: Padding added to each RX buffer
855 * @max_interrupt_mode: Highest capability interrupt mode supported
856 * from &enum efx_init_mode.
857 * @phys_addr_channels: Number of channels with physically addressed
860 struct efx_nic_type
{
861 unsigned int mem_bar
;
862 unsigned int mem_map_size
;
863 unsigned int txd_ptr_tbl_base
;
864 unsigned int rxd_ptr_tbl_base
;
865 unsigned int buf_tbl_base
;
866 unsigned int evq_ptr_tbl_base
;
867 unsigned int evq_rptr_tbl_base
;
869 unsigned int txd_ring_mask
;
870 unsigned int rxd_ring_mask
;
871 unsigned int evq_size
;
873 unsigned int tx_dma_mask
;
874 unsigned bug5391_mask
;
878 unsigned int rx_buffer_padding
;
879 unsigned int max_interrupt_mode
;
880 unsigned int phys_addr_channels
;
883 /**************************************************************************
885 * Prototypes and inline functions
887 *************************************************************************/
889 /* Iterate over all used channels */
890 #define efx_for_each_channel(_channel, _efx) \
891 for (_channel = &_efx->channel[0]; \
892 _channel < &_efx->channel[EFX_MAX_CHANNELS]; \
894 if (!_channel->used_flags) \
898 /* Iterate over all used TX queues */
899 #define efx_for_each_tx_queue(_tx_queue, _efx) \
900 for (_tx_queue = &_efx->tx_queue[0]; \
901 _tx_queue < &_efx->tx_queue[EFX_TX_QUEUE_COUNT]; \
904 /* Iterate over all TX queues belonging to a channel */
905 #define efx_for_each_channel_tx_queue(_tx_queue, _channel) \
906 for (_tx_queue = &_channel->efx->tx_queue[0]; \
907 _tx_queue < &_channel->efx->tx_queue[EFX_TX_QUEUE_COUNT]; \
909 if (_tx_queue->channel != _channel) \
913 /* Iterate over all used RX queues */
914 #define efx_for_each_rx_queue(_rx_queue, _efx) \
915 for (_rx_queue = &_efx->rx_queue[0]; \
916 _rx_queue < &_efx->rx_queue[_efx->n_rx_queues]; \
919 /* Iterate over all RX queues belonging to a channel */
920 #define efx_for_each_channel_rx_queue(_rx_queue, _channel) \
921 for (_rx_queue = &_channel->efx->rx_queue[_channel->channel]; \
924 if (_rx_queue->channel != _channel) \
928 /* Returns a pointer to the specified receive buffer in the RX
931 static inline struct efx_rx_buffer
*efx_rx_buffer(struct efx_rx_queue
*rx_queue
,
934 return (&rx_queue
->buffer
[index
]);
937 /* Set bit in a little-endian bitfield */
938 static inline void set_bit_le(unsigned nr
, unsigned char *addr
)
940 addr
[nr
/ 8] |= (1 << (nr
% 8));
943 /* Clear bit in a little-endian bitfield */
944 static inline void clear_bit_le(unsigned nr
, unsigned char *addr
)
946 addr
[nr
/ 8] &= ~(1 << (nr
% 8));
951 * EFX_MAX_FRAME_LEN - calculate maximum frame length
953 * This calculates the maximum frame length that will be used for a
954 * given MTU. The frame length will be equal to the MTU plus a
955 * constant amount of header space and padding. This is the quantity
956 * that the net driver will program into the MAC as the maximum frame
959 * The 10G MAC used in Falcon requires 8-byte alignment on the frame
960 * length, so we round up to the nearest 8.
962 #define EFX_MAX_FRAME_LEN(mtu) \
963 ((((mtu) + ETH_HLEN + VLAN_HLEN + 4/* FCS */) + 7) & ~7)
966 #endif /* EFX_NET_DRIVER_H */