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ath9k: Initialize channel change time
[linux-2.6/libata-dev.git] / drivers / net / wireless / ath9k / main.c
blob7264c4c36a5f589624e33687ecfeb48b303f8670
1 /*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/nl80211.h>
18 #include "ath9k.h"
19
20 #define ATH_PCI_VERSION "0.1"
21
22 static char *dev_info = "ath9k";
23
24 MODULE_AUTHOR("Atheros Communications");
25 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
26 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
27 MODULE_LICENSE("Dual BSD/GPL");
28
29 /* We use the hw_value as an index into our private channel structure */
30
31 #define CHAN2G(_freq, _idx) { \
32 .center_freq = (_freq), \
33 .hw_value = (_idx), \
34 .max_power = 30, \
35 }
36
37 #define CHAN5G(_freq, _idx) { \
38 .band = IEEE80211_BAND_5GHZ, \
39 .center_freq = (_freq), \
40 .hw_value = (_idx), \
41 .max_power = 30, \
42 }
43
44 /* Some 2 GHz radios are actually tunable on 2312-2732
45 * on 5 MHz steps, we support the channels which we know
46 * we have calibration data for all cards though to make
47 * this static */
48 static struct ieee80211_channel ath9k_2ghz_chantable[] = {
49 CHAN2G(2412, 0), /* Channel 1 */
50 CHAN2G(2417, 1), /* Channel 2 */
51 CHAN2G(2422, 2), /* Channel 3 */
52 CHAN2G(2427, 3), /* Channel 4 */
53 CHAN2G(2432, 4), /* Channel 5 */
54 CHAN2G(2437, 5), /* Channel 6 */
55 CHAN2G(2442, 6), /* Channel 7 */
56 CHAN2G(2447, 7), /* Channel 8 */
57 CHAN2G(2452, 8), /* Channel 9 */
58 CHAN2G(2457, 9), /* Channel 10 */
59 CHAN2G(2462, 10), /* Channel 11 */
60 CHAN2G(2467, 11), /* Channel 12 */
61 CHAN2G(2472, 12), /* Channel 13 */
62 CHAN2G(2484, 13), /* Channel 14 */
63 };
64
65 /* Some 5 GHz radios are actually tunable on XXXX-YYYY
66 * on 5 MHz steps, we support the channels which we know
67 * we have calibration data for all cards though to make
68 * this static */
69 static struct ieee80211_channel ath9k_5ghz_chantable[] = {
70 /* _We_ call this UNII 1 */
71 CHAN5G(5180, 14), /* Channel 36 */
72 CHAN5G(5200, 15), /* Channel 40 */
73 CHAN5G(5220, 16), /* Channel 44 */
74 CHAN5G(5240, 17), /* Channel 48 */
75 /* _We_ call this UNII 2 */
76 CHAN5G(5260, 18), /* Channel 52 */
77 CHAN5G(5280, 19), /* Channel 56 */
78 CHAN5G(5300, 20), /* Channel 60 */
79 CHAN5G(5320, 21), /* Channel 64 */
80 /* _We_ call this "Middle band" */
81 CHAN5G(5500, 22), /* Channel 100 */
82 CHAN5G(5520, 23), /* Channel 104 */
83 CHAN5G(5540, 24), /* Channel 108 */
84 CHAN5G(5560, 25), /* Channel 112 */
85 CHAN5G(5580, 26), /* Channel 116 */
86 CHAN5G(5600, 27), /* Channel 120 */
87 CHAN5G(5620, 28), /* Channel 124 */
88 CHAN5G(5640, 29), /* Channel 128 */
89 CHAN5G(5660, 30), /* Channel 132 */
90 CHAN5G(5680, 31), /* Channel 136 */
91 CHAN5G(5700, 32), /* Channel 140 */
92 /* _We_ call this UNII 3 */
93 CHAN5G(5745, 33), /* Channel 149 */
94 CHAN5G(5765, 34), /* Channel 153 */
95 CHAN5G(5785, 35), /* Channel 157 */
96 CHAN5G(5805, 36), /* Channel 161 */
97 CHAN5G(5825, 37), /* Channel 165 */
98 };
99
100 static void ath_cache_conf_rate(struct ath_softc *sc,
101 struct ieee80211_conf *conf)
102 {
103 switch (conf->channel->band) {
104 case IEEE80211_BAND_2GHZ:
105 if (conf_is_ht20(conf))
106 sc->cur_rate_table =
107 sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
108 else if (conf_is_ht40_minus(conf))
109 sc->cur_rate_table =
110 sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
111 else if (conf_is_ht40_plus(conf))
112 sc->cur_rate_table =
113 sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
114 else
115 sc->cur_rate_table =
116 sc->hw_rate_table[ATH9K_MODE_11G];
117 break;
118 case IEEE80211_BAND_5GHZ:
119 if (conf_is_ht20(conf))
120 sc->cur_rate_table =
121 sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
122 else if (conf_is_ht40_minus(conf))
123 sc->cur_rate_table =
124 sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
125 else if (conf_is_ht40_plus(conf))
126 sc->cur_rate_table =
127 sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
128 else
129 sc->cur_rate_table =
130 sc->hw_rate_table[ATH9K_MODE_11A];
131 break;
132 default:
133 BUG_ON(1);
134 break;
135 }
136 }
137
138 static void ath_update_txpow(struct ath_softc *sc)
139 {
140 struct ath_hw *ah = sc->sc_ah;
141 u32 txpow;
142
143 if (sc->curtxpow != sc->config.txpowlimit) {
144 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
145 /* read back in case value is clamped */
146 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
147 sc->curtxpow = txpow;
148 }
149 }
150
151 static u8 parse_mpdudensity(u8 mpdudensity)
152 {
153 /*
154 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
155 * 0 for no restriction
156 * 1 for 1/4 us
157 * 2 for 1/2 us
158 * 3 for 1 us
159 * 4 for 2 us
160 * 5 for 4 us
161 * 6 for 8 us
162 * 7 for 16 us
163 */
164 switch (mpdudensity) {
165 case 0:
166 return 0;
167 case 1:
168 case 2:
169 case 3:
170 /* Our lower layer calculations limit our precision to
171 1 microsecond */
172 return 1;
173 case 4:
174 return 2;
175 case 5:
176 return 4;
177 case 6:
178 return 8;
179 case 7:
180 return 16;
181 default:
182 return 0;
183 }
184 }
185
186 static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
187 {
188 struct ath_rate_table *rate_table = NULL;
189 struct ieee80211_supported_band *sband;
190 struct ieee80211_rate *rate;
191 int i, maxrates;
192
193 switch (band) {
194 case IEEE80211_BAND_2GHZ:
195 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
196 break;
197 case IEEE80211_BAND_5GHZ:
198 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
199 break;
200 default:
201 break;
202 }
203
204 if (rate_table == NULL)
205 return;
206
207 sband = &sc->sbands[band];
208 rate = sc->rates[band];
209
210 if (rate_table->rate_cnt > ATH_RATE_MAX)
211 maxrates = ATH_RATE_MAX;
212 else
213 maxrates = rate_table->rate_cnt;
214
215 for (i = 0; i < maxrates; i++) {
216 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
217 rate[i].hw_value = rate_table->info[i].ratecode;
218 if (rate_table->info[i].short_preamble) {
219 rate[i].hw_value_short = rate_table->info[i].ratecode |
220 rate_table->info[i].short_preamble;
221 rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
222 }
223 sband->n_bitrates++;
224
225 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
226 rate[i].bitrate / 10, rate[i].hw_value);
227 }
228 }
229
230 /*
231 * Set/change channels. If the channel is really being changed, it's done
232 * by reseting the chip. To accomplish this we must first cleanup any pending
233 * DMA, then restart stuff.
234 */
235 static int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan)
236 {
237 struct ath_hw *ah = sc->sc_ah;
238 bool fastcc = true, stopped;
239 struct ieee80211_hw *hw = sc->hw;
240 struct ieee80211_channel *channel = hw->conf.channel;
241 int r;
242
243 if (sc->sc_flags & SC_OP_INVALID)
244 return -EIO;
245
246 ath9k_ps_wakeup(sc);
247
248 /*
249 * This is only performed if the channel settings have
250 * actually changed.
251 *
252 * To switch channels clear any pending DMA operations;
253 * wait long enough for the RX fifo to drain, reset the
254 * hardware at the new frequency, and then re-enable
255 * the relevant bits of the h/w.
256 */
257 ath9k_hw_set_interrupts(ah, 0);
258 ath_drain_all_txq(sc, false);
259 stopped = ath_stoprecv(sc);
260
261 /* XXX: do not flush receive queue here. We don't want
262 * to flush data frames already in queue because of
263 * changing channel. */
264
265 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
266 fastcc = false;
267
268 DPRINTF(sc, ATH_DBG_CONFIG,
269 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
270 sc->sc_ah->curchan->channel,
271 channel->center_freq, sc->tx_chan_width);
272
273 spin_lock_bh(&sc->sc_resetlock);
274
275 r = ath9k_hw_reset(ah, hchan, fastcc);
276 if (r) {
277 DPRINTF(sc, ATH_DBG_FATAL,
278 "Unable to reset channel (%u Mhz) "
279 "reset status %u\n",
280 channel->center_freq, r);
281 spin_unlock_bh(&sc->sc_resetlock);
282 return r;
283 }
284 spin_unlock_bh(&sc->sc_resetlock);
285
286 sc->sc_flags &= ~SC_OP_CHAINMASK_UPDATE;
287 sc->sc_flags &= ~SC_OP_FULL_RESET;
288
289 if (ath_startrecv(sc) != 0) {
290 DPRINTF(sc, ATH_DBG_FATAL,
291 "Unable to restart recv logic\n");
292 return -EIO;
293 }
294
295 ath_cache_conf_rate(sc, &hw->conf);
296 ath_update_txpow(sc);
297 ath9k_hw_set_interrupts(ah, sc->imask);
298 ath9k_ps_restore(sc);
299 return 0;
300 }
301
302 /*
303 * This routine performs the periodic noise floor calibration function
304 * that is used to adjust and optimize the chip performance. This
305 * takes environmental changes (location, temperature) into account.
306 * When the task is complete, it reschedules itself depending on the
307 * appropriate interval that was calculated.
308 */
309 static void ath_ani_calibrate(unsigned long data)
310 {
311 struct ath_softc *sc;
312 struct ath_hw *ah;
313 bool longcal = false;
314 bool shortcal = false;
315 bool aniflag = false;
316 unsigned int timestamp = jiffies_to_msecs(jiffies);
317 u32 cal_interval;
318
319 sc = (struct ath_softc *)data;
320 ah = sc->sc_ah;
321
322 /*
323 * don't calibrate when we're scanning.
324 * we are most likely not on our home channel.
325 */
326 if (sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC)
327 return;
328
329 /* Long calibration runs independently of short calibration. */
330 if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
331 longcal = true;
332 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
333 sc->ani.longcal_timer = timestamp;
334 }
335
336 /* Short calibration applies only while caldone is false */
337 if (!sc->ani.caldone) {
338 if ((timestamp - sc->ani.shortcal_timer) >=
339 ATH_SHORT_CALINTERVAL) {
340 shortcal = true;
341 DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
342 sc->ani.shortcal_timer = timestamp;
343 sc->ani.resetcal_timer = timestamp;
344 }
345 } else {
346 if ((timestamp - sc->ani.resetcal_timer) >=
347 ATH_RESTART_CALINTERVAL) {
348 sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
349 if (sc->ani.caldone)
350 sc->ani.resetcal_timer = timestamp;
351 }
352 }
353
354 /* Verify whether we must check ANI */
355 if ((timestamp - sc->ani.checkani_timer) >=
356 ATH_ANI_POLLINTERVAL) {
357 aniflag = true;
358 sc->ani.checkani_timer = timestamp;
359 }
360
361 /* Skip all processing if there's nothing to do. */
362 if (longcal || shortcal || aniflag) {
363 /* Call ANI routine if necessary */
364 if (aniflag)
365 ath9k_hw_ani_monitor(ah, &sc->nodestats,
366 ah->curchan);
367
368 /* Perform calibration if necessary */
369 if (longcal || shortcal) {
370 bool iscaldone = false;
371
372 if (ath9k_hw_calibrate(ah, ah->curchan,
373 sc->rx_chainmask, longcal,
374 &iscaldone)) {
375 if (longcal)
376 sc->ani.noise_floor =
377 ath9k_hw_getchan_noise(ah,
378 ah->curchan);
379
380 DPRINTF(sc, ATH_DBG_ANI,
381 "calibrate chan %u/%x nf: %d\n",
382 ah->curchan->channel,
383 ah->curchan->channelFlags,
384 sc->ani.noise_floor);
385 } else {
386 DPRINTF(sc, ATH_DBG_ANY,
387 "calibrate chan %u/%x failed\n",
388 ah->curchan->channel,
389 ah->curchan->channelFlags);
390 }
391 sc->ani.caldone = iscaldone;
392 }
393 }
394
395 /*
396 * Set timer interval based on previous results.
397 * The interval must be the shortest necessary to satisfy ANI,
398 * short calibration and long calibration.
399 */
400 cal_interval = ATH_LONG_CALINTERVAL;
401 if (sc->sc_ah->config.enable_ani)
402 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
403 if (!sc->ani.caldone)
404 cal_interval = min(cal_interval, (u32)ATH_SHORT_CALINTERVAL);
405
406 mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
407 }
408
409 /*
410 * Update tx/rx chainmask. For legacy association,
411 * hard code chainmask to 1x1, for 11n association, use
412 * the chainmask configuration, for bt coexistence, use
413 * the chainmask configuration even in legacy mode.
414 */
415 static void ath_update_chainmask(struct ath_softc *sc, int is_ht)
416 {
417 sc->sc_flags |= SC_OP_CHAINMASK_UPDATE;
418 if (is_ht ||
419 (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) {
420 sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
421 sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
422 } else {
423 sc->tx_chainmask = 1;
424 sc->rx_chainmask = 1;
425 }
426
427 DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
428 sc->tx_chainmask, sc->rx_chainmask);
429 }
430
431 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
432 {
433 struct ath_node *an;
434
435 an = (struct ath_node *)sta->drv_priv;
436
437 if (sc->sc_flags & SC_OP_TXAGGR)
438 ath_tx_node_init(sc, an);
439
440 an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
441 sta->ht_cap.ampdu_factor);
442 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
443 }
444
445 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
446 {
447 struct ath_node *an = (struct ath_node *)sta->drv_priv;
448
449 if (sc->sc_flags & SC_OP_TXAGGR)
450 ath_tx_node_cleanup(sc, an);
451 }
452
453 static void ath9k_tasklet(unsigned long data)
454 {
455 struct ath_softc *sc = (struct ath_softc *)data;
456 u32 status = sc->intrstatus;
457
458 if (status & ATH9K_INT_FATAL) {
459 /* need a chip reset */
460 ath_reset(sc, false);
461 return;
462 } else {
463
464 if (status &
465 (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
466 spin_lock_bh(&sc->rx.rxflushlock);
467 ath_rx_tasklet(sc, 0);
468 spin_unlock_bh(&sc->rx.rxflushlock);
469 }
470 /* XXX: optimize this */
471 if (status & ATH9K_INT_TX)
472 ath_tx_tasklet(sc);
473 }
474
475 /* re-enable hardware interrupt */
476 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
477 }
478
479 irqreturn_t ath_isr(int irq, void *dev)
480 {
481 struct ath_softc *sc = dev;
482 struct ath_hw *ah = sc->sc_ah;
483 enum ath9k_int status;
484 bool sched = false;
485
486 do {
487 if (sc->sc_flags & SC_OP_INVALID) {
488 /*
489 * The hardware is not ready/present, don't
490 * touch anything. Note this can happen early
491 * on if the IRQ is shared.
492 */
493 return IRQ_NONE;
494 }
495 if (!ath9k_hw_intrpend(ah)) { /* shared irq, not for us */
496 return IRQ_NONE;
497 }
498
499 /*
500 * Figure out the reason(s) for the interrupt. Note
501 * that the hal returns a pseudo-ISR that may include
502 * bits we haven't explicitly enabled so we mask the
503 * value to insure we only process bits we requested.
504 */
505 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
506
507 status &= sc->imask; /* discard unasked-for bits */
508
509 /*
510 * If there are no status bits set, then this interrupt was not
511 * for me (should have been caught above).
512 */
513 if (!status)
514 return IRQ_NONE;
515
516 sc->intrstatus = status;
517
518 if (status & ATH9K_INT_FATAL) {
519 /* need a chip reset */
520 sched = true;
521 } else if (status & ATH9K_INT_RXORN) {
522 /* need a chip reset */
523 sched = true;
524 } else {
525 if (status & ATH9K_INT_SWBA) {
526 /* schedule a tasklet for beacon handling */
527 tasklet_schedule(&sc->bcon_tasklet);
528 }
529 if (status & ATH9K_INT_RXEOL) {
530 /*
531 * NB: the hardware should re-read the link when
532 * RXE bit is written, but it doesn't work
533 * at least on older hardware revs.
534 */
535 sched = true;
536 }
537
538 if (status & ATH9K_INT_TXURN)
539 /* bump tx trigger level */
540 ath9k_hw_updatetxtriglevel(ah, true);
541 /* XXX: optimize this */
542 if (status & ATH9K_INT_RX)
543 sched = true;
544 if (status & ATH9K_INT_TX)
545 sched = true;
546 if (status & ATH9K_INT_BMISS)
547 sched = true;
548 /* carrier sense timeout */
549 if (status & ATH9K_INT_CST)
550 sched = true;
551 if (status & ATH9K_INT_MIB) {
552 /*
553 * Disable interrupts until we service the MIB
554 * interrupt; otherwise it will continue to
555 * fire.
556 */
557 ath9k_hw_set_interrupts(ah, 0);
558 /*
559 * Let the hal handle the event. We assume
560 * it will clear whatever condition caused
561 * the interrupt.
562 */
563 ath9k_hw_procmibevent(ah, &sc->nodestats);
564 ath9k_hw_set_interrupts(ah, sc->imask);
565 }
566 if (status & ATH9K_INT_TIM_TIMER) {
567 if (!(ah->caps.hw_caps &
568 ATH9K_HW_CAP_AUTOSLEEP)) {
569 /* Clear RxAbort bit so that we can
570 * receive frames */
571 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
572 ath9k_hw_setrxabort(ah, 0);
573 sched = true;
574 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
575 }
576 }
577 if (status & ATH9K_INT_TSFOOR) {
578 /* FIXME: Handle this interrupt for power save */
579 sched = true;
580 }
581 }
582 } while (0);
583
584 ath_debug_stat_interrupt(sc, status);
585
586 if (sched) {
587 /* turn off every interrupt except SWBA */
588 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
589 tasklet_schedule(&sc->intr_tq);
590 }
591
592 return IRQ_HANDLED;
593 }
594
595 static u32 ath_get_extchanmode(struct ath_softc *sc,
596 struct ieee80211_channel *chan,
597 enum nl80211_channel_type channel_type)
598 {
599 u32 chanmode = 0;
600
601 switch (chan->band) {
602 case IEEE80211_BAND_2GHZ:
603 switch(channel_type) {
604 case NL80211_CHAN_NO_HT:
605 case NL80211_CHAN_HT20:
606 chanmode = CHANNEL_G_HT20;
607 break;
608 case NL80211_CHAN_HT40PLUS:
609 chanmode = CHANNEL_G_HT40PLUS;
610 break;
611 case NL80211_CHAN_HT40MINUS:
612 chanmode = CHANNEL_G_HT40MINUS;
613 break;
614 }
615 break;
616 case IEEE80211_BAND_5GHZ:
617 switch(channel_type) {
618 case NL80211_CHAN_NO_HT:
619 case NL80211_CHAN_HT20:
620 chanmode = CHANNEL_A_HT20;
621 break;
622 case NL80211_CHAN_HT40PLUS:
623 chanmode = CHANNEL_A_HT40PLUS;
624 break;
625 case NL80211_CHAN_HT40MINUS:
626 chanmode = CHANNEL_A_HT40MINUS;
627 break;
628 }
629 break;
630 default:
631 break;
632 }
633
634 return chanmode;
635 }
636
637 static int ath_keyset(struct ath_softc *sc, u16 keyix,
638 struct ath9k_keyval *hk, const u8 mac[ETH_ALEN])
639 {
640 bool status;
641
642 status = ath9k_hw_set_keycache_entry(sc->sc_ah,
643 keyix, hk, mac, false);
644
645 return status != false;
646 }
647
648 static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
649 struct ath9k_keyval *hk,
650 const u8 *addr)
651 {
652 const u8 *key_rxmic;
653 const u8 *key_txmic;
654
655 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
656 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
657
658 if (addr == NULL) {
659 /* Group key installation */
660 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
661 return ath_keyset(sc, keyix, hk, addr);
662 }
663 if (!sc->splitmic) {
664 /*
665 * data key goes at first index,
666 * the hal handles the MIC keys at index+64.
667 */
668 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
669 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
670 return ath_keyset(sc, keyix, hk, addr);
671 }
672 /*
673 * TX key goes at first index, RX key at +32.
674 * The hal handles the MIC keys at index+64.
675 */
676 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
677 if (!ath_keyset(sc, keyix, hk, NULL)) {
678 /* Txmic entry failed. No need to proceed further */
679 DPRINTF(sc, ATH_DBG_KEYCACHE,
680 "Setting TX MIC Key Failed\n");
681 return 0;
682 }
683
684 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
685 /* XXX delete tx key on failure? */
686 return ath_keyset(sc, keyix + 32, hk, addr);
687 }
688
689 static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
690 {
691 int i;
692
693 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
694 if (test_bit(i, sc->keymap) ||
695 test_bit(i + 64, sc->keymap))
696 continue; /* At least one part of TKIP key allocated */
697 if (sc->splitmic &&
698 (test_bit(i + 32, sc->keymap) ||
699 test_bit(i + 64 + 32, sc->keymap)))
700 continue; /* At least one part of TKIP key allocated */
701
702 /* Found a free slot for a TKIP key */
703 return i;
704 }
705 return -1;
706 }
707
708 static int ath_reserve_key_cache_slot(struct ath_softc *sc)
709 {
710 int i;
711
712 /* First, try to find slots that would not be available for TKIP. */
713 if (sc->splitmic) {
714 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
715 if (!test_bit(i, sc->keymap) &&
716 (test_bit(i + 32, sc->keymap) ||
717 test_bit(i + 64, sc->keymap) ||
718 test_bit(i + 64 + 32, sc->keymap)))
719 return i;
720 if (!test_bit(i + 32, sc->keymap) &&
721 (test_bit(i, sc->keymap) ||
722 test_bit(i + 64, sc->keymap) ||
723 test_bit(i + 64 + 32, sc->keymap)))
724 return i + 32;
725 if (!test_bit(i + 64, sc->keymap) &&
726 (test_bit(i , sc->keymap) ||
727 test_bit(i + 32, sc->keymap) ||
728 test_bit(i + 64 + 32, sc->keymap)))
729 return i + 64;
730 if (!test_bit(i + 64 + 32, sc->keymap) &&
731 (test_bit(i, sc->keymap) ||
732 test_bit(i + 32, sc->keymap) ||
733 test_bit(i + 64, sc->keymap)))
734 return i + 64 + 32;
735 }
736 } else {
737 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
738 if (!test_bit(i, sc->keymap) &&
739 test_bit(i + 64, sc->keymap))
740 return i;
741 if (test_bit(i, sc->keymap) &&
742 !test_bit(i + 64, sc->keymap))
743 return i + 64;
744 }
745 }
746
747 /* No partially used TKIP slots, pick any available slot */
748 for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
749 /* Do not allow slots that could be needed for TKIP group keys
750 * to be used. This limitation could be removed if we know that
751 * TKIP will not be used. */
752 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
753 continue;
754 if (sc->splitmic) {
755 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
756 continue;
757 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
758 continue;
759 }
760
761 if (!test_bit(i, sc->keymap))
762 return i; /* Found a free slot for a key */
763 }
764
765 /* No free slot found */
766 return -1;
767 }
768
769 static int ath_key_config(struct ath_softc *sc,
770 struct ieee80211_sta *sta,
771 struct ieee80211_key_conf *key)
772 {
773 struct ath9k_keyval hk;
774 const u8 *mac = NULL;
775 int ret = 0;
776 int idx;
777
778 memset(&hk, 0, sizeof(hk));
779
780 switch (key->alg) {
781 case ALG_WEP:
782 hk.kv_type = ATH9K_CIPHER_WEP;
783 break;
784 case ALG_TKIP:
785 hk.kv_type = ATH9K_CIPHER_TKIP;
786 break;
787 case ALG_CCMP:
788 hk.kv_type = ATH9K_CIPHER_AES_CCM;
789 break;
790 default:
791 return -EOPNOTSUPP;
792 }
793
794 hk.kv_len = key->keylen;
795 memcpy(hk.kv_val, key->key, key->keylen);
796
797 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
798 /* For now, use the default keys for broadcast keys. This may
799 * need to change with virtual interfaces. */
800 idx = key->keyidx;
801 } else if (key->keyidx) {
802 struct ieee80211_vif *vif;
803
804 if (WARN_ON(!sta))
805 return -EOPNOTSUPP;
806 mac = sta->addr;
807
808 vif = sc->vifs[0];
809 if (vif->type != NL80211_IFTYPE_AP) {
810 /* Only keyidx 0 should be used with unicast key, but
811 * allow this for client mode for now. */
812 idx = key->keyidx;
813 } else
814 return -EIO;
815 } else {
816 if (WARN_ON(!sta))
817 return -EOPNOTSUPP;
818 mac = sta->addr;
819
820 if (key->alg == ALG_TKIP)
821 idx = ath_reserve_key_cache_slot_tkip(sc);
822 else
823 idx = ath_reserve_key_cache_slot(sc);
824 if (idx < 0)
825 return -ENOSPC; /* no free key cache entries */
826 }
827
828 if (key->alg == ALG_TKIP)
829 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac);
830 else
831 ret = ath_keyset(sc, idx, &hk, mac);
832
833 if (!ret)
834 return -EIO;
835
836 set_bit(idx, sc->keymap);
837 if (key->alg == ALG_TKIP) {
838 set_bit(idx + 64, sc->keymap);
839 if (sc->splitmic) {
840 set_bit(idx + 32, sc->keymap);
841 set_bit(idx + 64 + 32, sc->keymap);
842 }
843 }
844
845 return idx;
846 }
847
848 static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
849 {
850 ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
851 if (key->hw_key_idx < IEEE80211_WEP_NKID)
852 return;
853
854 clear_bit(key->hw_key_idx, sc->keymap);
855 if (key->alg != ALG_TKIP)
856 return;
857
858 clear_bit(key->hw_key_idx + 64, sc->keymap);
859 if (sc->splitmic) {
860 clear_bit(key->hw_key_idx + 32, sc->keymap);
861 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
862 }
863 }
864
865 static void setup_ht_cap(struct ath_softc *sc,
866 struct ieee80211_sta_ht_cap *ht_info)
867 {
868 #define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3 /* 2 ^ 16 */
869 #define ATH9K_HT_CAP_MPDUDENSITY_8 0x6 /* 8 usec */
870
871 ht_info->ht_supported = true;
872 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
873 IEEE80211_HT_CAP_SM_PS |
874 IEEE80211_HT_CAP_SGI_40 |
875 IEEE80211_HT_CAP_DSSSCCK40;
876
877 ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
878 ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
879
880 /* set up supported mcs set */
881 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
882
883 switch(sc->rx_chainmask) {
884 case 1:
885 ht_info->mcs.rx_mask[0] = 0xff;
886 break;
887 case 3:
888 case 5:
889 case 7:
890 default:
891 ht_info->mcs.rx_mask[0] = 0xff;
892 ht_info->mcs.rx_mask[1] = 0xff;
893 break;
894 }
895
896 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
897 }
898
899 static void ath9k_bss_assoc_info(struct ath_softc *sc,
900 struct ieee80211_vif *vif,
901 struct ieee80211_bss_conf *bss_conf)
902 {
903 struct ath_vif *avp = (void *)vif->drv_priv;
904
905 if (bss_conf->assoc) {
906 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
907 bss_conf->aid, sc->curbssid);
908
909 /* New association, store aid */
910 if (avp->av_opmode == NL80211_IFTYPE_STATION) {
911 sc->curaid = bss_conf->aid;
912 ath9k_hw_write_associd(sc);
913 }
914
915 /* Configure the beacon */
916 ath_beacon_config(sc, 0);
917 sc->sc_flags |= SC_OP_BEACONS;
918
919 /* Reset rssi stats */
920 sc->nodestats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
921 sc->nodestats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
922 sc->nodestats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
923 sc->nodestats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
924
925 /* Start ANI */
926 mod_timer(&sc->ani.timer,
927 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
928
929 } else {
930 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISSOC\n");
931 sc->curaid = 0;
932 }
933 }
934
935 /********************************/
936 /* LED functions */
937 /********************************/
938
939 static void ath_led_blink_work(struct work_struct *work)
940 {
941 struct ath_softc *sc = container_of(work, struct ath_softc,
942 ath_led_blink_work.work);
943
944 if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
945 return;
946 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
947 (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
948
949 queue_delayed_work(sc->hw->workqueue, &sc->ath_led_blink_work,
950 (sc->sc_flags & SC_OP_LED_ON) ?
951 msecs_to_jiffies(sc->led_off_duration) :
952 msecs_to_jiffies(sc->led_on_duration));
953
954 sc->led_on_duration =
955 max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25);
956 sc->led_off_duration =
957 max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10);
958 sc->led_on_cnt = sc->led_off_cnt = 0;
959 if (sc->sc_flags & SC_OP_LED_ON)
960 sc->sc_flags &= ~SC_OP_LED_ON;
961 else
962 sc->sc_flags |= SC_OP_LED_ON;
963 }
964
965 static void ath_led_brightness(struct led_classdev *led_cdev,
966 enum led_brightness brightness)
967 {
968 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
969 struct ath_softc *sc = led->sc;
970
971 switch (brightness) {
972 case LED_OFF:
973 if (led->led_type == ATH_LED_ASSOC ||
974 led->led_type == ATH_LED_RADIO) {
975 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
976 (led->led_type == ATH_LED_RADIO));
977 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
978 if (led->led_type == ATH_LED_RADIO)
979 sc->sc_flags &= ~SC_OP_LED_ON;
980 } else {
981 sc->led_off_cnt++;
982 }
983 break;
984 case LED_FULL:
985 if (led->led_type == ATH_LED_ASSOC) {
986 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
987 queue_delayed_work(sc->hw->workqueue,
988 &sc->ath_led_blink_work, 0);
989 } else if (led->led_type == ATH_LED_RADIO) {
990 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
991 sc->sc_flags |= SC_OP_LED_ON;
992 } else {
993 sc->led_on_cnt++;
994 }
995 break;
996 default:
997 break;
998 }
999 }
1000
1001 static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
1002 char *trigger)
1003 {
1004 int ret;
1005
1006 led->sc = sc;
1007 led->led_cdev.name = led->name;
1008 led->led_cdev.default_trigger = trigger;
1009 led->led_cdev.brightness_set = ath_led_brightness;
1010
1011 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1012 if (ret)
1013 DPRINTF(sc, ATH_DBG_FATAL,
1014 "Failed to register led:%s", led->name);
1015 else
1016 led->registered = 1;
1017 return ret;
1018 }
1019
1020 static void ath_unregister_led(struct ath_led *led)
1021 {
1022 if (led->registered) {
1023 led_classdev_unregister(&led->led_cdev);
1024 led->registered = 0;
1025 }
1026 }
1027
1028 static void ath_deinit_leds(struct ath_softc *sc)
1029 {
1030 cancel_delayed_work_sync(&sc->ath_led_blink_work);
1031 ath_unregister_led(&sc->assoc_led);
1032 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1033 ath_unregister_led(&sc->tx_led);
1034 ath_unregister_led(&sc->rx_led);
1035 ath_unregister_led(&sc->radio_led);
1036 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1037 }
1038
1039 static void ath_init_leds(struct ath_softc *sc)
1040 {
1041 char *trigger;
1042 int ret;
1043
1044 /* Configure gpio 1 for output */
1045 ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1046 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1047 /* LED off, active low */
1048 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1049
1050 INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1051
1052 trigger = ieee80211_get_radio_led_name(sc->hw);
1053 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1054 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
1055 ret = ath_register_led(sc, &sc->radio_led, trigger);
1056 sc->radio_led.led_type = ATH_LED_RADIO;
1057 if (ret)
1058 goto fail;
1059
1060 trigger = ieee80211_get_assoc_led_name(sc->hw);
1061 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1062 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
1063 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1064 sc->assoc_led.led_type = ATH_LED_ASSOC;
1065 if (ret)
1066 goto fail;
1067
1068 trigger = ieee80211_get_tx_led_name(sc->hw);
1069 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1070 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
1071 ret = ath_register_led(sc, &sc->tx_led, trigger);
1072 sc->tx_led.led_type = ATH_LED_TX;
1073 if (ret)
1074 goto fail;
1075
1076 trigger = ieee80211_get_rx_led_name(sc->hw);
1077 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1078 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
1079 ret = ath_register_led(sc, &sc->rx_led, trigger);
1080 sc->rx_led.led_type = ATH_LED_RX;
1081 if (ret)
1082 goto fail;
1083
1084 return;
1085
1086 fail:
1087 ath_deinit_leds(sc);
1088 }
1089
1090 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1091
1092 /*******************/
1093 /* Rfkill */
1094 /*******************/
1095
1096 static void ath_radio_enable(struct ath_softc *sc)
1097 {
1098 struct ath_hw *ah = sc->sc_ah;
1099 struct ieee80211_channel *channel = sc->hw->conf.channel;
1100 int r;
1101
1102 ath9k_ps_wakeup(sc);
1103 spin_lock_bh(&sc->sc_resetlock);
1104
1105 r = ath9k_hw_reset(ah, ah->curchan, false);
1106
1107 if (r) {
1108 DPRINTF(sc, ATH_DBG_FATAL,
1109 "Unable to reset channel %u (%uMhz) ",
1110 "reset status %u\n",
1111 channel->center_freq, r);
1112 }
1113 spin_unlock_bh(&sc->sc_resetlock);
1114
1115 ath_update_txpow(sc);
1116 if (ath_startrecv(sc) != 0) {
1117 DPRINTF(sc, ATH_DBG_FATAL,
1118 "Unable to restart recv logic\n");
1119 return;
1120 }
1121
1122 if (sc->sc_flags & SC_OP_BEACONS)
1123 ath_beacon_config(sc, ATH_IF_ID_ANY); /* restart beacons */
1124
1125 /* Re-Enable interrupts */
1126 ath9k_hw_set_interrupts(ah, sc->imask);
1127
1128 /* Enable LED */
1129 ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1130 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1131 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1132
1133 ieee80211_wake_queues(sc->hw);
1134 ath9k_ps_restore(sc);
1135 }
1136
1137 static void ath_radio_disable(struct ath_softc *sc)
1138 {
1139 struct ath_hw *ah = sc->sc_ah;
1140 struct ieee80211_channel *channel = sc->hw->conf.channel;
1141 int r;
1142
1143 ath9k_ps_wakeup(sc);
1144 ieee80211_stop_queues(sc->hw);
1145
1146 /* Disable LED */
1147 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1148 ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1149
1150 /* Disable interrupts */
1151 ath9k_hw_set_interrupts(ah, 0);
1152
1153 ath_drain_all_txq(sc, false); /* clear pending tx frames */
1154 ath_stoprecv(sc); /* turn off frame recv */
1155 ath_flushrecv(sc); /* flush recv queue */
1156
1157 spin_lock_bh(&sc->sc_resetlock);
1158 r = ath9k_hw_reset(ah, ah->curchan, false);
1159 if (r) {
1160 DPRINTF(sc, ATH_DBG_FATAL,
1161 "Unable to reset channel %u (%uMhz) "
1162 "reset status %u\n",
1163 channel->center_freq, r);
1164 }
1165 spin_unlock_bh(&sc->sc_resetlock);
1166
1167 ath9k_hw_phy_disable(ah);
1168 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1169 ath9k_ps_restore(sc);
1170 }
1171
1172 static bool ath_is_rfkill_set(struct ath_softc *sc)
1173 {
1174 struct ath_hw *ah = sc->sc_ah;
1175
1176 return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1177 ah->rfkill_polarity;
1178 }
1179
1180 /* h/w rfkill poll function */
1181 static void ath_rfkill_poll(struct work_struct *work)
1182 {
1183 struct ath_softc *sc = container_of(work, struct ath_softc,
1184 rf_kill.rfkill_poll.work);
1185 bool radio_on;
1186
1187 if (sc->sc_flags & SC_OP_INVALID)
1188 return;
1189
1190 radio_on = !ath_is_rfkill_set(sc);
1191
1192 /*
1193 * enable/disable radio only when there is a
1194 * state change in RF switch
1195 */
1196 if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
1197 enum rfkill_state state;
1198
1199 if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
1200 state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
1201 : RFKILL_STATE_HARD_BLOCKED;
1202 } else if (radio_on) {
1203 ath_radio_enable(sc);
1204 state = RFKILL_STATE_UNBLOCKED;
1205 } else {
1206 ath_radio_disable(sc);
1207 state = RFKILL_STATE_HARD_BLOCKED;
1208 }
1209
1210 if (state == RFKILL_STATE_HARD_BLOCKED)
1211 sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
1212 else
1213 sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
1214
1215 rfkill_force_state(sc->rf_kill.rfkill, state);
1216 }
1217
1218 queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
1219 msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
1220 }
1221
1222 /* s/w rfkill handler */
1223 static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
1224 {
1225 struct ath_softc *sc = data;
1226
1227 switch (state) {
1228 case RFKILL_STATE_SOFT_BLOCKED:
1229 if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
1230 SC_OP_RFKILL_SW_BLOCKED)))
1231 ath_radio_disable(sc);
1232 sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
1233 return 0;
1234 case RFKILL_STATE_UNBLOCKED:
1235 if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
1236 sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
1237 if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
1238 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
1239 "radio as it is disabled by h/w\n");
1240 return -EPERM;
1241 }
1242 ath_radio_enable(sc);
1243 }
1244 return 0;
1245 default:
1246 return -EINVAL;
1247 }
1248 }
1249
1250 /* Init s/w rfkill */
1251 static int ath_init_sw_rfkill(struct ath_softc *sc)
1252 {
1253 sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
1254 RFKILL_TYPE_WLAN);
1255 if (!sc->rf_kill.rfkill) {
1256 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
1257 return -ENOMEM;
1258 }
1259
1260 snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
1261 "ath9k-%s::rfkill", wiphy_name(sc->hw->wiphy));
1262 sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
1263 sc->rf_kill.rfkill->data = sc;
1264 sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
1265 sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
1266 sc->rf_kill.rfkill->user_claim_unsupported = 1;
1267
1268 return 0;
1269 }
1270
1271 /* Deinitialize rfkill */
1272 static void ath_deinit_rfkill(struct ath_softc *sc)
1273 {
1274 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1275 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1276
1277 if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
1278 rfkill_unregister(sc->rf_kill.rfkill);
1279 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
1280 sc->rf_kill.rfkill = NULL;
1281 }
1282 }
1283
1284 static int ath_start_rfkill_poll(struct ath_softc *sc)
1285 {
1286 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1287 queue_delayed_work(sc->hw->workqueue,
1288 &sc->rf_kill.rfkill_poll, 0);
1289
1290 if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1291 if (rfkill_register(sc->rf_kill.rfkill)) {
1292 DPRINTF(sc, ATH_DBG_FATAL,
1293 "Unable to register rfkill\n");
1294 rfkill_free(sc->rf_kill.rfkill);
1295
1296 /* Deinitialize the device */
1297 ath_cleanup(sc);
1298 return -EIO;
1299 } else {
1300 sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1301 }
1302 }
1303
1304 return 0;
1305 }
1306 #endif /* CONFIG_RFKILL */
1307
1308 void ath_cleanup(struct ath_softc *sc)
1309 {
1310 ath_detach(sc);
1311 free_irq(sc->irq, sc);
1312 ath_bus_cleanup(sc);
1313 ieee80211_free_hw(sc->hw);
1314 }
1315
1316 void ath_detach(struct ath_softc *sc)
1317 {
1318 struct ieee80211_hw *hw = sc->hw;
1319 int i = 0;
1320
1321 ath9k_ps_wakeup(sc);
1322
1323 DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
1324
1325 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1326 ath_deinit_rfkill(sc);
1327 #endif
1328 ath_deinit_leds(sc);
1329
1330 ieee80211_unregister_hw(hw);
1331 ath_rx_cleanup(sc);
1332 ath_tx_cleanup(sc);
1333
1334 tasklet_kill(&sc->intr_tq);
1335 tasklet_kill(&sc->bcon_tasklet);
1336
1337 if (!(sc->sc_flags & SC_OP_INVALID))
1338 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
1339
1340 /* cleanup tx queues */
1341 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1342 if (ATH_TXQ_SETUP(sc, i))
1343 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1344
1345 ath9k_hw_detach(sc->sc_ah);
1346 ath9k_exit_debug(sc);
1347 ath9k_ps_restore(sc);
1348 }
1349
1350 static int ath_init(u16 devid, struct ath_softc *sc)
1351 {
1352 struct ath_hw *ah = NULL;
1353 int status;
1354 int error = 0, i;
1355 int csz = 0;
1356
1357 /* XXX: hardware will not be ready until ath_open() being called */
1358 sc->sc_flags |= SC_OP_INVALID;
1359
1360 if (ath9k_init_debug(sc) < 0)
1361 printk(KERN_ERR "Unable to create debugfs files\n");
1362
1363 spin_lock_init(&sc->sc_resetlock);
1364 mutex_init(&sc->mutex);
1365 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1366 tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
1367 (unsigned long)sc);
1368
1369 /*
1370 * Cache line size is used to size and align various
1371 * structures used to communicate with the hardware.
1372 */
1373 ath_read_cachesize(sc, &csz);
1374 /* XXX assert csz is non-zero */
1375 sc->cachelsz = csz << 2; /* convert to bytes */
1376
1377 ah = ath9k_hw_attach(devid, sc, &status);
1378 if (ah == NULL) {
1379 DPRINTF(sc, ATH_DBG_FATAL,
1380 "Unable to attach hardware; HAL status %d\n", status);
1381 error = -ENXIO;
1382 goto bad;
1383 }
1384 sc->sc_ah = ah;
1385
1386 /* Get the hardware key cache size. */
1387 sc->keymax = ah->caps.keycache_size;
1388 if (sc->keymax > ATH_KEYMAX) {
1389 DPRINTF(sc, ATH_DBG_KEYCACHE,
1390 "Warning, using only %u entries in %u key cache\n",
1391 ATH_KEYMAX, sc->keymax);
1392 sc->keymax = ATH_KEYMAX;
1393 }
1394
1395 /*
1396 * Reset the key cache since some parts do not
1397 * reset the contents on initial power up.
1398 */
1399 for (i = 0; i < sc->keymax; i++)
1400 ath9k_hw_keyreset(ah, (u16) i);
1401
1402 if (ath9k_regd_init(sc->sc_ah))
1403 goto bad;
1404
1405 /* default to MONITOR mode */
1406 sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
1407
1408 /* Setup rate tables */
1409
1410 ath_rate_attach(sc);
1411 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1412 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1413
1414 /*
1415 * Allocate hardware transmit queues: one queue for
1416 * beacon frames and one data queue for each QoS
1417 * priority. Note that the hal handles reseting
1418 * these queues at the needed time.
1419 */
1420 sc->beacon.beaconq = ath_beaconq_setup(ah);
1421 if (sc->beacon.beaconq == -1) {
1422 DPRINTF(sc, ATH_DBG_FATAL,
1423 "Unable to setup a beacon xmit queue\n");
1424 error = -EIO;
1425 goto bad2;
1426 }
1427 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1428 if (sc->beacon.cabq == NULL) {
1429 DPRINTF(sc, ATH_DBG_FATAL,
1430 "Unable to setup CAB xmit queue\n");
1431 error = -EIO;
1432 goto bad2;
1433 }
1434
1435 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
1436 ath_cabq_update(sc);
1437
1438 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1439 sc->tx.hwq_map[i] = -1;
1440
1441 /* Setup data queues */
1442 /* NB: ensure BK queue is the lowest priority h/w queue */
1443 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1444 DPRINTF(sc, ATH_DBG_FATAL,
1445 "Unable to setup xmit queue for BK traffic\n");
1446 error = -EIO;
1447 goto bad2;
1448 }
1449
1450 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1451 DPRINTF(sc, ATH_DBG_FATAL,
1452 "Unable to setup xmit queue for BE traffic\n");
1453 error = -EIO;
1454 goto bad2;
1455 }
1456 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1457 DPRINTF(sc, ATH_DBG_FATAL,
1458 "Unable to setup xmit queue for VI traffic\n");
1459 error = -EIO;
1460 goto bad2;
1461 }
1462 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1463 DPRINTF(sc, ATH_DBG_FATAL,
1464 "Unable to setup xmit queue for VO traffic\n");
1465 error = -EIO;
1466 goto bad2;
1467 }
1468
1469 /* Initializes the noise floor to a reasonable default value.
1470 * Later on this will be updated during ANI processing. */
1471
1472 sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1473 setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
1474
1475 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1476 ATH9K_CIPHER_TKIP, NULL)) {
1477 /*
1478 * Whether we should enable h/w TKIP MIC.
1479 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1480 * report WMM capable, so it's always safe to turn on
1481 * TKIP MIC in this case.
1482 */
1483 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1484 0, 1, NULL);
1485 }
1486
1487 /*
1488 * Check whether the separate key cache entries
1489 * are required to handle both tx+rx MIC keys.
1490 * With split mic keys the number of stations is limited
1491 * to 27 otherwise 59.
1492 */
1493 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1494 ATH9K_CIPHER_TKIP, NULL)
1495 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1496 ATH9K_CIPHER_MIC, NULL)
1497 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1498 0, NULL))
1499 sc->splitmic = 1;
1500
1501 /* turn on mcast key search if possible */
1502 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1503 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1504 1, NULL);
1505
1506 sc->config.txpowlimit = ATH_TXPOWER_MAX;
1507
1508 /* 11n Capabilities */
1509 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1510 sc->sc_flags |= SC_OP_TXAGGR;
1511 sc->sc_flags |= SC_OP_RXAGGR;
1512 }
1513
1514 sc->tx_chainmask = ah->caps.tx_chainmask;
1515 sc->rx_chainmask = ah->caps.rx_chainmask;
1516
1517 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1518 sc->rx.defant = ath9k_hw_getdefantenna(ah);
1519
1520 if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) {
1521 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
1522 ATH_SET_VIF_BSSID_MASK(sc->bssidmask);
1523 ath9k_hw_setbssidmask(sc);
1524 }
1525
1526 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
1527
1528 /* initialize beacon slots */
1529 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)
1530 sc->beacon.bslot[i] = ATH_IF_ID_ANY;
1531
1532 /* save MISC configurations */
1533 sc->config.swBeaconProcess = 1;
1534
1535 /* setup channels and rates */
1536
1537 sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
1538 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1539 sc->rates[IEEE80211_BAND_2GHZ];
1540 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1541 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1542 ARRAY_SIZE(ath9k_2ghz_chantable);
1543
1544 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
1545 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
1546 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1547 sc->rates[IEEE80211_BAND_5GHZ];
1548 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1549 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1550 ARRAY_SIZE(ath9k_5ghz_chantable);
1551 }
1552
1553 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)
1554 ath9k_hw_btcoex_enable(sc->sc_ah);
1555
1556 return 0;
1557 bad2:
1558 /* cleanup tx queues */
1559 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1560 if (ATH_TXQ_SETUP(sc, i))
1561 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1562 bad:
1563 if (ah)
1564 ath9k_hw_detach(ah);
1565 ath9k_exit_debug(sc);
1566
1567 return error;
1568 }
1569
1570 int ath_attach(u16 devid, struct ath_softc *sc)
1571 {
1572 struct ieee80211_hw *hw = sc->hw;
1573 const struct ieee80211_regdomain *regd;
1574 int error = 0, i;
1575
1576 DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
1577
1578 error = ath_init(devid, sc);
1579 if (error != 0)
1580 return error;
1581
1582 /* get mac address from hardware and set in mac80211 */
1583
1584 SET_IEEE80211_PERM_ADDR(hw, sc->sc_ah->macaddr);
1585
1586 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1587 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1588 IEEE80211_HW_SIGNAL_DBM |
1589 IEEE80211_HW_AMPDU_AGGREGATION |
1590 IEEE80211_HW_SUPPORTS_PS |
1591 IEEE80211_HW_PS_NULLFUNC_STACK;
1592
1593 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah))
1594 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1595
1596 hw->wiphy->interface_modes =
1597 BIT(NL80211_IFTYPE_AP) |
1598 BIT(NL80211_IFTYPE_STATION) |
1599 BIT(NL80211_IFTYPE_ADHOC);
1600
1601 hw->wiphy->reg_notifier = ath9k_reg_notifier;
1602 hw->wiphy->strict_regulatory = true;
1603
1604 hw->queues = 4;
1605 hw->max_rates = 4;
1606 hw->channel_change_time = 5000;
1607 hw->max_rate_tries = ATH_11N_TXMAXTRY;
1608 hw->sta_data_size = sizeof(struct ath_node);
1609 hw->vif_data_size = sizeof(struct ath_vif);
1610
1611 hw->rate_control_algorithm = "ath9k_rate_control";
1612
1613 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1614 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1615 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1616 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1617 }
1618
1619 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &sc->sbands[IEEE80211_BAND_2GHZ];
1620 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1621 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1622 &sc->sbands[IEEE80211_BAND_5GHZ];
1623
1624 /* initialize tx/rx engine */
1625 error = ath_tx_init(sc, ATH_TXBUF);
1626 if (error != 0)
1627 goto error_attach;
1628
1629 error = ath_rx_init(sc, ATH_RXBUF);
1630 if (error != 0)
1631 goto error_attach;
1632
1633 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1634 /* Initialze h/w Rfkill */
1635 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1636 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
1637
1638 /* Initialize s/w rfkill */
1639 error = ath_init_sw_rfkill(sc);
1640 if (error)
1641 goto error_attach;
1642 #endif
1643
1644 if (ath9k_is_world_regd(sc->sc_ah)) {
1645 /* Anything applied here (prior to wiphy registration) gets
1646 * saved on the wiphy orig_* parameters */
1647 regd = ath9k_world_regdomain(sc->sc_ah);
1648 hw->wiphy->custom_regulatory = true;
1649 hw->wiphy->strict_regulatory = false;
1650 } else {
1651 /* This gets applied in the case of the absense of CRDA,
1652 * it's our own custom world regulatory domain, similar to
1653 * cfg80211's but we enable passive scanning */
1654 regd = ath9k_default_world_regdomain();
1655 }
1656 wiphy_apply_custom_regulatory(hw->wiphy, regd);
1657 ath9k_reg_apply_radar_flags(hw->wiphy);
1658 ath9k_reg_apply_world_flags(hw->wiphy, REGDOM_SET_BY_INIT);
1659
1660 error = ieee80211_register_hw(hw);
1661
1662 if (!ath9k_is_world_regd(sc->sc_ah))
1663 regulatory_hint(hw->wiphy, sc->sc_ah->regulatory.alpha2);
1664
1665 /* Initialize LED control */
1666 ath_init_leds(sc);
1667
1668
1669 return 0;
1670
1671 error_attach:
1672 /* cleanup tx queues */
1673 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1674 if (ATH_TXQ_SETUP(sc, i))
1675 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1676
1677 ath9k_hw_detach(sc->sc_ah);
1678 ath9k_exit_debug(sc);
1679
1680 return error;
1681 }
1682
1683 int ath_reset(struct ath_softc *sc, bool retry_tx)
1684 {
1685 struct ath_hw *ah = sc->sc_ah;
1686 struct ieee80211_hw *hw = sc->hw;
1687 int r;
1688
1689 ath9k_hw_set_interrupts(ah, 0);
1690 ath_drain_all_txq(sc, retry_tx);
1691 ath_stoprecv(sc);
1692 ath_flushrecv(sc);
1693
1694 spin_lock_bh(&sc->sc_resetlock);
1695 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
1696 if (r)
1697 DPRINTF(sc, ATH_DBG_FATAL,
1698 "Unable to reset hardware; reset status %u\n", r);
1699 spin_unlock_bh(&sc->sc_resetlock);
1700
1701 if (ath_startrecv(sc) != 0)
1702 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
1703
1704 /*
1705 * We may be doing a reset in response to a request
1706 * that changes the channel so update any state that
1707 * might change as a result.
1708 */
1709 ath_cache_conf_rate(sc, &hw->conf);
1710
1711 ath_update_txpow(sc);
1712
1713 if (sc->sc_flags & SC_OP_BEACONS)
1714 ath_beacon_config(sc, ATH_IF_ID_ANY); /* restart beacons */
1715
1716 ath9k_hw_set_interrupts(ah, sc->imask);
1717
1718 if (retry_tx) {
1719 int i;
1720 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1721 if (ATH_TXQ_SETUP(sc, i)) {
1722 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1723 ath_txq_schedule(sc, &sc->tx.txq[i]);
1724 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
1725 }
1726 }
1727 }
1728
1729 return r;
1730 }
1731
1732 /*
1733 * This function will allocate both the DMA descriptor structure, and the
1734 * buffers it contains. These are used to contain the descriptors used
1735 * by the system.
1736 */
1737 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1738 struct list_head *head, const char *name,
1739 int nbuf, int ndesc)
1740 {
1741 #define DS2PHYS(_dd, _ds) \
1742 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1743 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1744 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1745
1746 struct ath_desc *ds;
1747 struct ath_buf *bf;
1748 int i, bsize, error;
1749
1750 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1751 name, nbuf, ndesc);
1752
1753 /* ath_desc must be a multiple of DWORDs */
1754 if ((sizeof(struct ath_desc) % 4) != 0) {
1755 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
1756 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1757 error = -ENOMEM;
1758 goto fail;
1759 }
1760
1761 dd->dd_name = name;
1762 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1763
1764 /*
1765 * Need additional DMA memory because we can't use
1766 * descriptors that cross the 4K page boundary. Assume
1767 * one skipped descriptor per 4K page.
1768 */
1769 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1770 u32 ndesc_skipped =
1771 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1772 u32 dma_len;
1773
1774 while (ndesc_skipped) {
1775 dma_len = ndesc_skipped * sizeof(struct ath_desc);
1776 dd->dd_desc_len += dma_len;
1777
1778 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1779 };
1780 }
1781
1782 /* allocate descriptors */
1783 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
1784 &dd->dd_desc_paddr, GFP_ATOMIC);
1785 if (dd->dd_desc == NULL) {
1786 error = -ENOMEM;
1787 goto fail;
1788 }
1789 ds = dd->dd_desc;
1790 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1791 dd->dd_name, ds, (u32) dd->dd_desc_len,
1792 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1793
1794 /* allocate buffers */
1795 bsize = sizeof(struct ath_buf) * nbuf;
1796 bf = kmalloc(bsize, GFP_KERNEL);
1797 if (bf == NULL) {
1798 error = -ENOMEM;
1799 goto fail2;
1800 }
1801 memset(bf, 0, bsize);
1802 dd->dd_bufptr = bf;
1803
1804 INIT_LIST_HEAD(head);
1805 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1806 bf->bf_desc = ds;
1807 bf->bf_daddr = DS2PHYS(dd, ds);
1808
1809 if (!(sc->sc_ah->caps.hw_caps &
1810 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1811 /*
1812 * Skip descriptor addresses which can cause 4KB
1813 * boundary crossing (addr + length) with a 32 dword
1814 * descriptor fetch.
1815 */
1816 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1817 ASSERT((caddr_t) bf->bf_desc <
1818 ((caddr_t) dd->dd_desc +
1819 dd->dd_desc_len));
1820
1821 ds += ndesc;
1822 bf->bf_desc = ds;
1823 bf->bf_daddr = DS2PHYS(dd, ds);
1824 }
1825 }
1826 list_add_tail(&bf->list, head);
1827 }
1828 return 0;
1829 fail2:
1830 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1831 dd->dd_desc_paddr);
1832 fail:
1833 memset(dd, 0, sizeof(*dd));
1834 return error;
1835 #undef ATH_DESC_4KB_BOUND_CHECK
1836 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1837 #undef DS2PHYS
1838 }
1839
1840 void ath_descdma_cleanup(struct ath_softc *sc,
1841 struct ath_descdma *dd,
1842 struct list_head *head)
1843 {
1844 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1845 dd->dd_desc_paddr);
1846
1847 INIT_LIST_HEAD(head);
1848 kfree(dd->dd_bufptr);
1849 memset(dd, 0, sizeof(*dd));
1850 }
1851
1852 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1853 {
1854 int qnum;
1855
1856 switch (queue) {
1857 case 0:
1858 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
1859 break;
1860 case 1:
1861 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
1862 break;
1863 case 2:
1864 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1865 break;
1866 case 3:
1867 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
1868 break;
1869 default:
1870 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1871 break;
1872 }
1873
1874 return qnum;
1875 }
1876
1877 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1878 {
1879 int qnum;
1880
1881 switch (queue) {
1882 case ATH9K_WME_AC_VO:
1883 qnum = 0;
1884 break;
1885 case ATH9K_WME_AC_VI:
1886 qnum = 1;
1887 break;
1888 case ATH9K_WME_AC_BE:
1889 qnum = 2;
1890 break;
1891 case ATH9K_WME_AC_BK:
1892 qnum = 3;
1893 break;
1894 default:
1895 qnum = -1;
1896 break;
1897 }
1898
1899 return qnum;
1900 }
1901
1902 /* XXX: Remove me once we don't depend on ath9k_channel for all
1903 * this redundant data */
1904 static void ath9k_update_ichannel(struct ath_softc *sc,
1905 struct ath9k_channel *ichan)
1906 {
1907 struct ieee80211_hw *hw = sc->hw;
1908 struct ieee80211_channel *chan = hw->conf.channel;
1909 struct ieee80211_conf *conf = &hw->conf;
1910
1911 ichan->channel = chan->center_freq;
1912 ichan->chan = chan;
1913
1914 if (chan->band == IEEE80211_BAND_2GHZ) {
1915 ichan->chanmode = CHANNEL_G;
1916 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM;
1917 } else {
1918 ichan->chanmode = CHANNEL_A;
1919 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1920 }
1921
1922 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1923
1924 if (conf_is_ht(conf)) {
1925 if (conf_is_ht40(conf))
1926 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
1927
1928 ichan->chanmode = ath_get_extchanmode(sc, chan,
1929 conf->channel_type);
1930 }
1931 }
1932
1933 /**********************/
1934 /* mac80211 callbacks */
1935 /**********************/
1936
1937 static int ath9k_start(struct ieee80211_hw *hw)
1938 {
1939 struct ath_softc *sc = hw->priv;
1940 struct ieee80211_channel *curchan = hw->conf.channel;
1941 struct ath9k_channel *init_channel;
1942 int r, pos;
1943
1944 DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1945 "initial channel: %d MHz\n", curchan->center_freq);
1946
1947 mutex_lock(&sc->mutex);
1948
1949 /* setup initial channel */
1950
1951 pos = curchan->hw_value;
1952
1953 init_channel = &sc->sc_ah->channels[pos];
1954 ath9k_update_ichannel(sc, init_channel);
1955
1956 /* Reset SERDES registers */
1957 ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1958
1959 /*
1960 * The basic interface to setting the hardware in a good
1961 * state is ``reset''. On return the hardware is known to
1962 * be powered up and with interrupts disabled. This must
1963 * be followed by initialization of the appropriate bits
1964 * and then setup of the interrupt mask.
1965 */
1966 spin_lock_bh(&sc->sc_resetlock);
1967 r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
1968 if (r) {
1969 DPRINTF(sc, ATH_DBG_FATAL,
1970 "Unable to reset hardware; reset status %u "
1971 "(freq %u MHz)\n", r,
1972 curchan->center_freq);
1973 spin_unlock_bh(&sc->sc_resetlock);
1974 goto mutex_unlock;
1975 }
1976 spin_unlock_bh(&sc->sc_resetlock);
1977
1978 /*
1979 * This is needed only to setup initial state
1980 * but it's best done after a reset.
1981 */
1982 ath_update_txpow(sc);
1983
1984 /*
1985 * Setup the hardware after reset:
1986 * The receive engine is set going.
1987 * Frame transmit is handled entirely
1988 * in the frame output path; there's nothing to do
1989 * here except setup the interrupt mask.
1990 */
1991 if (ath_startrecv(sc) != 0) {
1992 DPRINTF(sc, ATH_DBG_FATAL,
1993 "Unable to start recv logic\n");
1994 r = -EIO;
1995 goto mutex_unlock;
1996 }
1997
1998 /* Setup our intr mask. */
1999 sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
2000 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
2001 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
2002
2003 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
2004 sc->imask |= ATH9K_INT_GTT;
2005
2006 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
2007 sc->imask |= ATH9K_INT_CST;
2008
2009 ath_cache_conf_rate(sc, &hw->conf);
2010
2011 sc->sc_flags &= ~SC_OP_INVALID;
2012
2013 /* Disable BMISS interrupt when we're not associated */
2014 sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
2015 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
2016
2017 ieee80211_wake_queues(sc->hw);
2018
2019 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2020 r = ath_start_rfkill_poll(sc);
2021 #endif
2022
2023 mutex_unlock:
2024 mutex_unlock(&sc->mutex);
2025
2026 return r;
2027 }
2028
2029 static int ath9k_tx(struct ieee80211_hw *hw,
2030 struct sk_buff *skb)
2031 {
2032 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2033 struct ath_softc *sc = hw->priv;
2034 struct ath_tx_control txctl;
2035 int hdrlen, padsize;
2036
2037 memset(&txctl, 0, sizeof(struct ath_tx_control));
2038
2039 /*
2040 * As a temporary workaround, assign seq# here; this will likely need
2041 * to be cleaned up to work better with Beacon transmission and virtual
2042 * BSSes.
2043 */
2044 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2045 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2046 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2047 sc->tx.seq_no += 0x10;
2048 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2049 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
2050 }
2051
2052 /* Add the padding after the header if this is not already done */
2053 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2054 if (hdrlen & 3) {
2055 padsize = hdrlen % 4;
2056 if (skb_headroom(skb) < padsize)
2057 return -1;
2058 skb_push(skb, padsize);
2059 memmove(skb->data, skb->data + padsize, hdrlen);
2060 }
2061
2062 /* Check if a tx queue is available */
2063
2064 txctl.txq = ath_test_get_txq(sc, skb);
2065 if (!txctl.txq)
2066 goto exit;
2067
2068 DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
2069
2070 if (ath_tx_start(sc, skb, &txctl) != 0) {
2071 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
2072 goto exit;
2073 }
2074
2075 return 0;
2076 exit:
2077 dev_kfree_skb_any(skb);
2078 return 0;
2079 }
2080
2081 static void ath9k_stop(struct ieee80211_hw *hw)
2082 {
2083 struct ath_softc *sc = hw->priv;
2084
2085 if (sc->sc_flags & SC_OP_INVALID) {
2086 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
2087 return;
2088 }
2089
2090 mutex_lock(&sc->mutex);
2091
2092 ieee80211_stop_queues(sc->hw);
2093
2094 /* make sure h/w will not generate any interrupt
2095 * before setting the invalid flag. */
2096 ath9k_hw_set_interrupts(sc->sc_ah, 0);
2097
2098 if (!(sc->sc_flags & SC_OP_INVALID)) {
2099 ath_drain_all_txq(sc, false);
2100 ath_stoprecv(sc);
2101 ath9k_hw_phy_disable(sc->sc_ah);
2102 } else
2103 sc->rx.rxlink = NULL;
2104
2105 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2106 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2107 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2108 #endif
2109 /* disable HAL and put h/w to sleep */
2110 ath9k_hw_disable(sc->sc_ah);
2111 ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2112
2113 sc->sc_flags |= SC_OP_INVALID;
2114
2115 mutex_unlock(&sc->mutex);
2116
2117 DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
2118 }
2119
2120 static int ath9k_add_interface(struct ieee80211_hw *hw,
2121 struct ieee80211_if_init_conf *conf)
2122 {
2123 struct ath_softc *sc = hw->priv;
2124 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2125 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2126
2127 /* Support only vif for now */
2128
2129 if (sc->nvifs)
2130 return -ENOBUFS;
2131
2132 mutex_lock(&sc->mutex);
2133
2134 switch (conf->type) {
2135 case NL80211_IFTYPE_STATION:
2136 ic_opmode = NL80211_IFTYPE_STATION;
2137 break;
2138 case NL80211_IFTYPE_ADHOC:
2139 ic_opmode = NL80211_IFTYPE_ADHOC;
2140 break;
2141 case NL80211_IFTYPE_AP:
2142 ic_opmode = NL80211_IFTYPE_AP;
2143 break;
2144 default:
2145 DPRINTF(sc, ATH_DBG_FATAL,
2146 "Interface type %d not yet supported\n", conf->type);
2147 return -EOPNOTSUPP;
2148 }
2149
2150 DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode);
2151
2152 /* Set the VIF opmode */
2153 avp->av_opmode = ic_opmode;
2154 avp->av_bslot = -1;
2155
2156 if (ic_opmode == NL80211_IFTYPE_AP)
2157 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2158
2159 sc->vifs[0] = conf->vif;
2160 sc->nvifs++;
2161
2162 /* Set the device opmode */
2163 sc->sc_ah->opmode = ic_opmode;
2164
2165 /*
2166 * Enable MIB interrupts when there are hardware phy counters.
2167 * Note we only do this (at the moment) for station mode.
2168 */
2169 if ((conf->type == NL80211_IFTYPE_STATION) ||
2170 (conf->type == NL80211_IFTYPE_ADHOC)) {
2171 if (ath9k_hw_phycounters(sc->sc_ah))
2172 sc->imask |= ATH9K_INT_MIB;
2173 sc->imask |= ATH9K_INT_TSFOOR;
2174 }
2175
2176 /*
2177 * Some hardware processes the TIM IE and fires an
2178 * interrupt when the TIM bit is set. For hardware
2179 * that does, if not overridden by configuration,
2180 * enable the TIM interrupt when operating as station.
2181 */
2182 if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) &&
2183 (conf->type == NL80211_IFTYPE_STATION) &&
2184 !sc->config.swBeaconProcess)
2185 sc->imask |= ATH9K_INT_TIM;
2186
2187 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
2188
2189 if (conf->type == NL80211_IFTYPE_AP) {
2190 /* TODO: is this a suitable place to start ANI for AP mode? */
2191 /* Start ANI */
2192 mod_timer(&sc->ani.timer,
2193 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
2194 }
2195
2196 mutex_unlock(&sc->mutex);
2197
2198 return 0;
2199 }
2200
2201 static void ath9k_remove_interface(struct ieee80211_hw *hw,
2202 struct ieee80211_if_init_conf *conf)
2203 {
2204 struct ath_softc *sc = hw->priv;
2205 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2206
2207 DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
2208
2209 mutex_lock(&sc->mutex);
2210
2211 /* Stop ANI */
2212 del_timer_sync(&sc->ani.timer);
2213
2214 /* Reclaim beacon resources */
2215 if (sc->sc_ah->opmode == NL80211_IFTYPE_AP ||
2216 sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) {
2217 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2218 ath_beacon_return(sc, avp);
2219 }
2220
2221 sc->sc_flags &= ~SC_OP_BEACONS;
2222
2223 sc->vifs[0] = NULL;
2224 sc->nvifs--;
2225
2226 mutex_unlock(&sc->mutex);
2227 }
2228
2229 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2230 {
2231 struct ath_softc *sc = hw->priv;
2232 struct ieee80211_conf *conf = &hw->conf;
2233
2234 mutex_lock(&sc->mutex);
2235
2236 if (changed & IEEE80211_CONF_CHANGE_PS) {
2237 if (conf->flags & IEEE80211_CONF_PS) {
2238 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2239 sc->imask |= ATH9K_INT_TIM_TIMER;
2240 ath9k_hw_set_interrupts(sc->sc_ah,
2241 sc->imask);
2242 }
2243 ath9k_hw_setrxabort(sc->sc_ah, 1);
2244 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
2245 } else {
2246 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
2247 ath9k_hw_setrxabort(sc->sc_ah, 0);
2248 sc->sc_flags &= ~SC_OP_WAIT_FOR_BEACON;
2249 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2250 sc->imask &= ~ATH9K_INT_TIM_TIMER;
2251 ath9k_hw_set_interrupts(sc->sc_ah,
2252 sc->imask);
2253 }
2254 }
2255 }
2256
2257 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2258 struct ieee80211_channel *curchan = hw->conf.channel;
2259 int pos = curchan->hw_value;
2260
2261 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2262 curchan->center_freq);
2263
2264 /* XXX: remove me eventualy */
2265 ath9k_update_ichannel(sc, &sc->sc_ah->channels[pos]);
2266
2267 ath_update_chainmask(sc, conf_is_ht(conf));
2268
2269 if (ath_set_channel(sc, &sc->sc_ah->channels[pos]) < 0) {
2270 DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
2271 mutex_unlock(&sc->mutex);
2272 return -EINVAL;
2273 }
2274 }
2275
2276 if (changed & IEEE80211_CONF_CHANGE_POWER)
2277 sc->config.txpowlimit = 2 * conf->power_level;
2278
2279 mutex_unlock(&sc->mutex);
2280
2281 return 0;
2282 }
2283
2284 static int ath9k_config_interface(struct ieee80211_hw *hw,
2285 struct ieee80211_vif *vif,
2286 struct ieee80211_if_conf *conf)
2287 {
2288 struct ath_softc *sc = hw->priv;
2289 struct ath_hw *ah = sc->sc_ah;
2290 struct ath_vif *avp = (void *)vif->drv_priv;
2291 u32 rfilt = 0;
2292 int error, i;
2293
2294 /* TODO: Need to decide which hw opmode to use for multi-interface
2295 * cases */
2296 if (vif->type == NL80211_IFTYPE_AP &&
2297 ah->opmode != NL80211_IFTYPE_AP) {
2298 ah->opmode = NL80211_IFTYPE_STATION;
2299 ath9k_hw_setopmode(ah);
2300 memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN);
2301 sc->curaid = 0;
2302 ath9k_hw_write_associd(sc);
2303 /* Request full reset to get hw opmode changed properly */
2304 sc->sc_flags |= SC_OP_FULL_RESET;
2305 }
2306
2307 if ((conf->changed & IEEE80211_IFCC_BSSID) &&
2308 !is_zero_ether_addr(conf->bssid)) {
2309 switch (vif->type) {
2310 case NL80211_IFTYPE_STATION:
2311 case NL80211_IFTYPE_ADHOC:
2312 /* Set BSSID */
2313 memcpy(sc->curbssid, conf->bssid, ETH_ALEN);
2314 sc->curaid = 0;
2315 ath9k_hw_write_associd(sc);
2316
2317 /* Set aggregation protection mode parameters */
2318 sc->config.ath_aggr_prot = 0;
2319
2320 DPRINTF(sc, ATH_DBG_CONFIG,
2321 "RX filter 0x%x bssid %pM aid 0x%x\n",
2322 rfilt, sc->curbssid, sc->curaid);
2323
2324 /* need to reconfigure the beacon */
2325 sc->sc_flags &= ~SC_OP_BEACONS ;
2326
2327 break;
2328 default:
2329 break;
2330 }
2331 }
2332
2333 if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2334 (vif->type == NL80211_IFTYPE_AP)) {
2335 if ((conf->changed & IEEE80211_IFCC_BEACON) ||
2336 (conf->changed & IEEE80211_IFCC_BEACON_ENABLED &&
2337 conf->enable_beacon)) {
2338 /*
2339 * Allocate and setup the beacon frame.
2340 *
2341 * Stop any previous beacon DMA. This may be
2342 * necessary, for example, when an ibss merge
2343 * causes reconfiguration; we may be called
2344 * with beacon transmission active.
2345 */
2346 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2347
2348 error = ath_beacon_alloc(sc, 0);
2349 if (error != 0)
2350 return error;
2351
2352 ath_beacon_sync(sc, 0);
2353 }
2354 }
2355
2356 /* Check for WLAN_CAPABILITY_PRIVACY ? */
2357 if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2358 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2359 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2360 ath9k_hw_keysetmac(sc->sc_ah,
2361 (u16)i,
2362 sc->curbssid);
2363 }
2364
2365 /* Only legacy IBSS for now */
2366 if (vif->type == NL80211_IFTYPE_ADHOC)
2367 ath_update_chainmask(sc, 0);
2368
2369 return 0;
2370 }
2371
2372 #define SUPPORTED_FILTERS \
2373 (FIF_PROMISC_IN_BSS | \
2374 FIF_ALLMULTI | \
2375 FIF_CONTROL | \
2376 FIF_OTHER_BSS | \
2377 FIF_BCN_PRBRESP_PROMISC | \
2378 FIF_FCSFAIL)
2379
2380 /* FIXME: sc->sc_full_reset ? */
2381 static void ath9k_configure_filter(struct ieee80211_hw *hw,
2382 unsigned int changed_flags,
2383 unsigned int *total_flags,
2384 int mc_count,
2385 struct dev_mc_list *mclist)
2386 {
2387 struct ath_softc *sc = hw->priv;
2388 u32 rfilt;
2389
2390 changed_flags &= SUPPORTED_FILTERS;
2391 *total_flags &= SUPPORTED_FILTERS;
2392
2393 sc->rx.rxfilter = *total_flags;
2394 rfilt = ath_calcrxfilter(sc);
2395 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2396
2397 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
2398 if (*total_flags & FIF_BCN_PRBRESP_PROMISC) {
2399 memcpy(sc->curbssid, ath_bcast_mac, ETH_ALEN);
2400 sc->curaid = 0;
2401 ath9k_hw_write_associd(sc);
2402 }
2403 }
2404
2405 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
2406 }
2407
2408 static void ath9k_sta_notify(struct ieee80211_hw *hw,
2409 struct ieee80211_vif *vif,
2410 enum sta_notify_cmd cmd,
2411 struct ieee80211_sta *sta)
2412 {
2413 struct ath_softc *sc = hw->priv;
2414
2415 switch (cmd) {
2416 case STA_NOTIFY_ADD:
2417 ath_node_attach(sc, sta);
2418 break;
2419 case STA_NOTIFY_REMOVE:
2420 ath_node_detach(sc, sta);
2421 break;
2422 default:
2423 break;
2424 }
2425 }
2426
2427 static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2428 const struct ieee80211_tx_queue_params *params)
2429 {
2430 struct ath_softc *sc = hw->priv;
2431 struct ath9k_tx_queue_info qi;
2432 int ret = 0, qnum;
2433
2434 if (queue >= WME_NUM_AC)
2435 return 0;
2436
2437 mutex_lock(&sc->mutex);
2438
2439 qi.tqi_aifs = params->aifs;
2440 qi.tqi_cwmin = params->cw_min;
2441 qi.tqi_cwmax = params->cw_max;
2442 qi.tqi_burstTime = params->txop;
2443 qnum = ath_get_hal_qnum(queue, sc);
2444
2445 DPRINTF(sc, ATH_DBG_CONFIG,
2446 "Configure tx [queue/halq] [%d/%d], "
2447 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2448 queue, qnum, params->aifs, params->cw_min,
2449 params->cw_max, params->txop);
2450
2451 ret = ath_txq_update(sc, qnum, &qi);
2452 if (ret)
2453 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
2454
2455 mutex_unlock(&sc->mutex);
2456
2457 return ret;
2458 }
2459
2460 static int ath9k_set_key(struct ieee80211_hw *hw,
2461 enum set_key_cmd cmd,
2462 struct ieee80211_vif *vif,
2463 struct ieee80211_sta *sta,
2464 struct ieee80211_key_conf *key)
2465 {
2466 struct ath_softc *sc = hw->priv;
2467 int ret = 0;
2468
2469 mutex_lock(&sc->mutex);
2470 ath9k_ps_wakeup(sc);
2471 DPRINTF(sc, ATH_DBG_KEYCACHE, "Set HW Key\n");
2472
2473 switch (cmd) {
2474 case SET_KEY:
2475 ret = ath_key_config(sc, sta, key);
2476 if (ret >= 0) {
2477 key->hw_key_idx = ret;
2478 /* push IV and Michael MIC generation to stack */
2479 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2480 if (key->alg == ALG_TKIP)
2481 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2482 if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2483 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
2484 ret = 0;
2485 }
2486 break;
2487 case DISABLE_KEY:
2488 ath_key_delete(sc, key);
2489 break;
2490 default:
2491 ret = -EINVAL;
2492 }
2493
2494 ath9k_ps_restore(sc);
2495 mutex_unlock(&sc->mutex);
2496
2497 return ret;
2498 }
2499
2500 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2501 struct ieee80211_vif *vif,
2502 struct ieee80211_bss_conf *bss_conf,
2503 u32 changed)
2504 {
2505 struct ath_softc *sc = hw->priv;
2506
2507 mutex_lock(&sc->mutex);
2508
2509 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2510 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2511 bss_conf->use_short_preamble);
2512 if (bss_conf->use_short_preamble)
2513 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2514 else
2515 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2516 }
2517
2518 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2519 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2520 bss_conf->use_cts_prot);
2521 if (bss_conf->use_cts_prot &&
2522 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2523 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2524 else
2525 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2526 }
2527
2528 if (changed & BSS_CHANGED_ASSOC) {
2529 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
2530 bss_conf->assoc);
2531 ath9k_bss_assoc_info(sc, vif, bss_conf);
2532 }
2533
2534 mutex_unlock(&sc->mutex);
2535 }
2536
2537 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2538 {
2539 u64 tsf;
2540 struct ath_softc *sc = hw->priv;
2541
2542 mutex_lock(&sc->mutex);
2543 tsf = ath9k_hw_gettsf64(sc->sc_ah);
2544 mutex_unlock(&sc->mutex);
2545
2546 return tsf;
2547 }
2548
2549 static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2550 {
2551 struct ath_softc *sc = hw->priv;
2552
2553 mutex_lock(&sc->mutex);
2554 ath9k_hw_settsf64(sc->sc_ah, tsf);
2555 mutex_unlock(&sc->mutex);
2556 }
2557
2558 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2559 {
2560 struct ath_softc *sc = hw->priv;
2561
2562 mutex_lock(&sc->mutex);
2563 ath9k_hw_reset_tsf(sc->sc_ah);
2564 mutex_unlock(&sc->mutex);
2565 }
2566
2567 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2568 enum ieee80211_ampdu_mlme_action action,
2569 struct ieee80211_sta *sta,
2570 u16 tid, u16 *ssn)
2571 {
2572 struct ath_softc *sc = hw->priv;
2573 int ret = 0;
2574
2575 switch (action) {
2576 case IEEE80211_AMPDU_RX_START:
2577 if (!(sc->sc_flags & SC_OP_RXAGGR))
2578 ret = -ENOTSUPP;
2579 break;
2580 case IEEE80211_AMPDU_RX_STOP:
2581 break;
2582 case IEEE80211_AMPDU_TX_START:
2583 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2584 if (ret < 0)
2585 DPRINTF(sc, ATH_DBG_FATAL,
2586 "Unable to start TX aggregation\n");
2587 else
2588 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2589 break;
2590 case IEEE80211_AMPDU_TX_STOP:
2591 ret = ath_tx_aggr_stop(sc, sta, tid);
2592 if (ret < 0)
2593 DPRINTF(sc, ATH_DBG_FATAL,
2594 "Unable to stop TX aggregation\n");
2595
2596 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2597 break;
2598 case IEEE80211_AMPDU_TX_RESUME:
2599 ath_tx_aggr_resume(sc, sta, tid);
2600 break;
2601 default:
2602 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
2603 }
2604
2605 return ret;
2606 }
2607
2608 struct ieee80211_ops ath9k_ops = {
2609 .tx = ath9k_tx,
2610 .start = ath9k_start,
2611 .stop = ath9k_stop,
2612 .add_interface = ath9k_add_interface,
2613 .remove_interface = ath9k_remove_interface,
2614 .config = ath9k_config,
2615 .config_interface = ath9k_config_interface,
2616 .configure_filter = ath9k_configure_filter,
2617 .sta_notify = ath9k_sta_notify,
2618 .conf_tx = ath9k_conf_tx,
2619 .bss_info_changed = ath9k_bss_info_changed,
2620 .set_key = ath9k_set_key,
2621 .get_tsf = ath9k_get_tsf,
2622 .set_tsf = ath9k_set_tsf,
2623 .reset_tsf = ath9k_reset_tsf,
2624 .ampdu_action = ath9k_ampdu_action,
2625 };
2626
2627 static struct {
2628 u32 version;
2629 const char * name;
2630 } ath_mac_bb_names[] = {
2631 { AR_SREV_VERSION_5416_PCI, "5416" },
2632 { AR_SREV_VERSION_5416_PCIE, "5418" },
2633 { AR_SREV_VERSION_9100, "9100" },
2634 { AR_SREV_VERSION_9160, "9160" },
2635 { AR_SREV_VERSION_9280, "9280" },
2636 { AR_SREV_VERSION_9285, "9285" }
2637 };
2638
2639 static struct {
2640 u16 version;
2641 const char * name;
2642 } ath_rf_names[] = {
2643 { 0, "5133" },
2644 { AR_RAD5133_SREV_MAJOR, "5133" },
2645 { AR_RAD5122_SREV_MAJOR, "5122" },
2646 { AR_RAD2133_SREV_MAJOR, "2133" },
2647 { AR_RAD2122_SREV_MAJOR, "2122" }
2648 };
2649
2650 /*
2651 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2652 */
2653 const char *
2654 ath_mac_bb_name(u32 mac_bb_version)
2655 {
2656 int i;
2657
2658 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2659 if (ath_mac_bb_names[i].version == mac_bb_version) {
2660 return ath_mac_bb_names[i].name;
2661 }
2662 }
2663
2664 return "????";
2665 }
2666
2667 /*
2668 * Return the RF name. "????" is returned if the RF is unknown.
2669 */
2670 const char *
2671 ath_rf_name(u16 rf_version)
2672 {
2673 int i;
2674
2675 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2676 if (ath_rf_names[i].version == rf_version) {
2677 return ath_rf_names[i].name;
2678 }
2679 }
2680
2681 return "????";
2682 }
2683
2684 static int __init ath9k_init(void)
2685 {
2686 int error;
2687
2688 /* Register rate control algorithm */
2689 error = ath_rate_control_register();
2690 if (error != 0) {
2691 printk(KERN_ERR
2692 "ath9k: Unable to register rate control "
2693 "algorithm: %d\n",
2694 error);
2695 goto err_out;
2696 }
2697
2698 error = ath_pci_init();
2699 if (error < 0) {
2700 printk(KERN_ERR
2701 "ath9k: No PCI devices found, driver not installed.\n");
2702 error = -ENODEV;
2703 goto err_rate_unregister;
2704 }
2705
2706 error = ath_ahb_init();
2707 if (error < 0) {
2708 error = -ENODEV;
2709 goto err_pci_exit;
2710 }
2711
2712 return 0;
2713
2714 err_pci_exit:
2715 ath_pci_exit();
2716
2717 err_rate_unregister:
2718 ath_rate_control_unregister();
2719 err_out:
2720 return error;
2721 }
2722 module_init(ath9k_init);
2723
2724 static void __exit ath9k_exit(void)
2725 {
2726 ath_ahb_exit();
2727 ath_pci_exit();
2728 ath_rate_control_unregister();
2729 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
2730 }
2731 module_exit(ath9k_exit);
Linux 2.6 libata-dev (mirror)