1 /* $Id: irq.c,v 1.114 2002/01/11 08:45:38 davem Exp $
2 * irq.c: UltraSparc IRQ handling/init/registry.
4 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
6 * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz)
9 #include <linux/config.h>
10 #include <linux/module.h>
11 #include <linux/sched.h>
12 #include <linux/ptrace.h>
13 #include <linux/errno.h>
14 #include <linux/kernel_stat.h>
15 #include <linux/signal.h>
17 #include <linux/interrupt.h>
18 #include <linux/slab.h>
19 #include <linux/random.h>
20 #include <linux/init.h>
21 #include <linux/delay.h>
22 #include <linux/proc_fs.h>
23 #include <linux/seq_file.h>
25 #include <asm/ptrace.h>
26 #include <asm/processor.h>
27 #include <asm/atomic.h>
28 #include <asm/system.h>
32 #include <asm/iommu.h>
34 #include <asm/oplib.h>
35 #include <asm/timer.h>
37 #include <asm/starfire.h>
38 #include <asm/uaccess.h>
39 #include <asm/cache.h>
40 #include <asm/cpudata.h>
41 #include <asm/auxio.h>
45 static void distribute_irqs(void);
48 /* UPA nodes send interrupt packet to UltraSparc with first data reg
49 * value low 5 (7 on Starfire) bits holding the IRQ identifier being
50 * delivered. We must translate this into a non-vector IRQ so we can
51 * set the softint on this cpu.
53 * To make processing these packets efficient and race free we use
54 * an array of irq buckets below. The interrupt vector handler in
55 * entry.S feeds incoming packets into per-cpu pil-indexed lists.
56 * The IVEC handler does not need to act atomically, the PIL dispatch
57 * code uses CAS to get an atomic snapshot of the list and clear it
61 struct ino_bucket ivector_table
[NUM_IVECS
] __attribute__ ((aligned (SMP_CACHE_BYTES
)));
63 /* This has to be in the main kernel image, it cannot be
64 * turned into per-cpu data. The reason is that the main
65 * kernel image is locked into the TLB and this structure
66 * is accessed from the vectored interrupt trap handler. If
67 * access to this structure takes a TLB miss it could cause
68 * the 5-level sparc v9 trap stack to overflow.
70 struct irq_work_struct
{
71 unsigned int irq_worklists
[16];
73 struct irq_work_struct __irq_work
[NR_CPUS
];
74 #define irq_work(__cpu, __pil) &(__irq_work[(__cpu)].irq_worklists[(__pil)])
76 static struct irqaction
*irq_action
[NR_IRQS
+1];
78 /* This only synchronizes entities which modify IRQ handler
79 * state and some selected user-level spots that want to
80 * read things in the table. IRQ handler processing orders
81 * its' accesses such that no locking is needed.
83 static DEFINE_SPINLOCK(irq_action_lock
);
85 static void register_irq_proc (unsigned int irq
);
88 * Upper 2b of irqaction->flags holds the ino.
89 * irqaction->mask holds the smp affinity information.
91 #define put_ino_in_irqaction(action, irq) \
92 action->flags &= 0xffffffffffffUL; \
93 if (__bucket(irq) == &pil0_dummy_bucket) \
94 action->flags |= 0xdeadUL << 48; \
96 action->flags |= __irq_ino(irq) << 48;
97 #define get_ino_in_irqaction(action) (action->flags >> 48)
99 #define put_smpaff_in_irqaction(action, smpaff) (action)->mask = (smpaff)
100 #define get_smpaff_in_irqaction(action) ((action)->mask)
102 int show_interrupts(struct seq_file
*p
, void *v
)
105 int i
= *(loff_t
*) v
;
106 struct irqaction
*action
;
111 spin_lock_irqsave(&irq_action_lock
, flags
);
113 if (!(action
= *(i
+ irq_action
)))
115 seq_printf(p
, "%3d: ", i
);
117 seq_printf(p
, "%10u ", kstat_irqs(i
));
119 for (j
= 0; j
< NR_CPUS
; j
++) {
122 seq_printf(p
, "%10u ",
123 kstat_cpu(j
).irqs
[i
]);
126 seq_printf(p
, " %s:%lx", action
->name
,
127 get_ino_in_irqaction(action
));
128 for (action
= action
->next
; action
; action
= action
->next
) {
129 seq_printf(p
, ", %s:%lx", action
->name
,
130 get_ino_in_irqaction(action
));
135 spin_unlock_irqrestore(&irq_action_lock
, flags
);
140 /* Now these are always passed a true fully specified sun4u INO. */
141 void enable_irq(unsigned int irq
)
143 struct ino_bucket
*bucket
= __bucket(irq
);
153 if (tlb_type
== hypervisor
) {
154 /* XXX SUN4V: implement me... XXX */
156 if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
) {
159 __asm__ ("rdpr %%ver, %0" : "=r" (ver
));
160 if ((ver
>> 32) == __JALAPENO_ID
||
161 (ver
>> 32) == __SERRANO_ID
) {
162 /* We set it to our JBUS ID. */
163 __asm__
__volatile__("ldxa [%%g0] %1, %0"
165 : "i" (ASI_JBUS_CONFIG
));
166 tid
= ((tid
& (0x1fUL
<<17)) << 9);
167 tid
&= IMAP_TID_JBUS
;
169 /* We set it to our Safari AID. */
170 __asm__
__volatile__("ldxa [%%g0] %1, %0"
172 : "i"(ASI_SAFARI_CONFIG
));
173 tid
= ((tid
& (0x3ffUL
<<17)) << 9);
174 tid
&= IMAP_AID_SAFARI
;
176 } else if (this_is_starfire
== 0) {
177 /* We set it to our UPA MID. */
178 __asm__
__volatile__("ldxa [%%g0] %1, %0"
180 : "i" (ASI_UPA_CONFIG
));
181 tid
= ((tid
& UPA_CONFIG_MID
) << 9);
184 tid
= (starfire_translate(imap
,
185 smp_processor_id()) << 26);
189 /* NOTE NOTE NOTE, IGN and INO are read-only, IGN is a product
190 * of this SYSIO's preconfigured IGN in the SYSIO Control
191 * Register, the hardware just mirrors that value here.
192 * However for Graphics and UPA Slave devices the full
193 * IMAP_INR field can be set by the programmer here.
195 * Things like FFB can now be handled via the new IRQ
198 upa_writel(tid
| IMAP_VALID
, imap
);
204 /* This now gets passed true ino's as well. */
205 void disable_irq(unsigned int irq
)
207 struct ino_bucket
*bucket
= __bucket(irq
);
214 /* NOTE: We do not want to futz with the IRQ clear registers
215 * and move the state to IDLE, the SCSI code does call
216 * disable_irq() to assure atomicity in the queue cmd
217 * SCSI adapter driver code. Thus we'd lose interrupts.
219 tmp
= upa_readl(imap
);
221 upa_writel(tmp
, imap
);
225 /* The timer is the one "weird" interrupt which is generated by
226 * the CPU %tick register and not by some normal vectored interrupt
227 * source. To handle this special case, we use this dummy INO bucket.
229 static struct irq_desc pil0_dummy_desc
;
230 static struct ino_bucket pil0_dummy_bucket
= {
231 .irq_info
= &pil0_dummy_desc
,
234 static void build_irq_error(const char *msg
, unsigned int ino
, int pil
, int inofixup
,
235 unsigned long iclr
, unsigned long imap
,
236 struct ino_bucket
*bucket
)
238 prom_printf("IRQ: INO %04x (%d:%016lx:%016lx) --> "
239 "(%d:%d:%016lx:%016lx), halting...\n",
240 ino
, bucket
->pil
, bucket
->iclr
, bucket
->imap
,
241 pil
, inofixup
, iclr
, imap
);
245 unsigned int build_irq(int pil
, int inofixup
, unsigned long iclr
, unsigned long imap
)
247 struct ino_bucket
*bucket
;
251 if (iclr
!= 0UL || imap
!= 0UL) {
252 prom_printf("Invalid dummy bucket for PIL0 (%lx:%lx)\n",
256 return __irq(&pil0_dummy_bucket
);
259 /* RULE: Both must be specified in all other cases. */
260 if (iclr
== 0UL || imap
== 0UL) {
261 prom_printf("Invalid build_irq %d %d %016lx %016lx\n",
262 pil
, inofixup
, iclr
, imap
);
266 ino
= (upa_readl(imap
) & (IMAP_IGN
| IMAP_INO
)) + inofixup
;
267 if (ino
> NUM_IVECS
) {
268 prom_printf("Invalid INO %04x (%d:%d:%016lx:%016lx)\n",
269 ino
, pil
, inofixup
, iclr
, imap
);
273 bucket
= &ivector_table
[ino
];
274 if (bucket
->flags
& IBF_ACTIVE
)
275 build_irq_error("IRQ: Trying to build active INO bucket.\n",
276 ino
, pil
, inofixup
, iclr
, imap
, bucket
);
278 if (bucket
->irq_info
) {
279 if (bucket
->imap
!= imap
|| bucket
->iclr
!= iclr
)
280 build_irq_error("IRQ: Trying to reinit INO bucket.\n",
281 ino
, pil
, inofixup
, iclr
, imap
, bucket
);
286 bucket
->irq_info
= kmalloc(sizeof(struct irq_desc
), GFP_ATOMIC
);
287 if (!bucket
->irq_info
) {
288 prom_printf("IRQ: Error, kmalloc(irq_desc) failed.\n");
291 memset(bucket
->irq_info
, 0, sizeof(struct irq_desc
));
293 /* Ok, looks good, set it up. Don't touch the irq_chain or
302 return __irq(bucket
);
305 static void atomic_bucket_insert(struct ino_bucket
*bucket
)
307 unsigned long pstate
;
310 __asm__
__volatile__("rdpr %%pstate, %0" : "=r" (pstate
));
311 __asm__
__volatile__("wrpr %0, %1, %%pstate"
312 : : "r" (pstate
), "i" (PSTATE_IE
));
313 ent
= irq_work(smp_processor_id(), bucket
->pil
);
314 bucket
->irq_chain
= *ent
;
315 *ent
= __irq(bucket
);
316 __asm__
__volatile__("wrpr %0, 0x0, %%pstate" : : "r" (pstate
));
319 static int check_irq_sharing(int pil
, unsigned long irqflags
)
321 struct irqaction
*action
, *tmp
;
323 action
= *(irq_action
+ pil
);
325 if ((action
->flags
& SA_SHIRQ
) && (irqflags
& SA_SHIRQ
)) {
326 for (tmp
= action
; tmp
->next
; tmp
= tmp
->next
)
335 static void append_irq_action(int pil
, struct irqaction
*action
)
337 struct irqaction
**pp
= irq_action
+ pil
;
344 static struct irqaction
*get_action_slot(struct ino_bucket
*bucket
)
346 struct irq_desc
*desc
= bucket
->irq_info
;
350 if (bucket
->flags
& IBF_PCI
)
351 max_irq
= MAX_IRQ_DESC_ACTION
;
352 for (i
= 0; i
< max_irq
; i
++) {
353 struct irqaction
*p
= &desc
->action
[i
];
356 if (desc
->action_active_mask
& mask
)
359 desc
->action_active_mask
|= mask
;
365 int request_irq(unsigned int irq
, irqreturn_t (*handler
)(int, void *, struct pt_regs
*),
366 unsigned long irqflags
, const char *name
, void *dev_id
)
368 struct irqaction
*action
;
369 struct ino_bucket
*bucket
= __bucket(irq
);
373 if (unlikely(!handler
))
376 if (unlikely(!bucket
->irq_info
))
379 if ((bucket
!= &pil0_dummy_bucket
) && (irqflags
& SA_SAMPLE_RANDOM
)) {
381 * This function might sleep, we want to call it first,
382 * outside of the atomic block. In SA_STATIC_ALLOC case,
383 * random driver's kmalloc will fail, but it is safe.
384 * If already initialized, random driver will not reinit.
385 * Yes, this might clear the entropy pool if the wrong
386 * driver is attempted to be loaded, without actually
387 * installing a new handler, but is this really a problem,
388 * only the sysadmin is able to do this.
390 rand_initialize_irq(irq
);
393 spin_lock_irqsave(&irq_action_lock
, flags
);
395 if (check_irq_sharing(bucket
->pil
, irqflags
)) {
396 spin_unlock_irqrestore(&irq_action_lock
, flags
);
400 action
= get_action_slot(bucket
);
402 spin_unlock_irqrestore(&irq_action_lock
, flags
);
406 bucket
->flags
|= IBF_ACTIVE
;
408 if (bucket
!= &pil0_dummy_bucket
) {
409 pending
= bucket
->pending
;
414 action
->handler
= handler
;
415 action
->flags
= irqflags
;
418 action
->dev_id
= dev_id
;
419 put_ino_in_irqaction(action
, irq
);
420 put_smpaff_in_irqaction(action
, CPU_MASK_NONE
);
422 append_irq_action(bucket
->pil
, action
);
426 /* We ate the IVEC already, this makes sure it does not get lost. */
428 atomic_bucket_insert(bucket
);
429 set_softint(1 << bucket
->pil
);
432 spin_unlock_irqrestore(&irq_action_lock
, flags
);
434 if (bucket
!= &pil0_dummy_bucket
)
435 register_irq_proc(__irq_ino(irq
));
443 EXPORT_SYMBOL(request_irq
);
445 static struct irqaction
*unlink_irq_action(unsigned int irq
, void *dev_id
)
447 struct ino_bucket
*bucket
= __bucket(irq
);
448 struct irqaction
*action
, **pp
;
450 pp
= irq_action
+ bucket
->pil
;
452 if (unlikely(!action
))
455 if (unlikely(!action
->handler
)) {
456 printk("Freeing free IRQ %d\n", bucket
->pil
);
460 while (action
&& action
->dev_id
!= dev_id
) {
471 void free_irq(unsigned int irq
, void *dev_id
)
473 struct irqaction
*action
;
474 struct ino_bucket
*bucket
;
477 spin_lock_irqsave(&irq_action_lock
, flags
);
479 action
= unlink_irq_action(irq
, dev_id
);
481 spin_unlock_irqrestore(&irq_action_lock
, flags
);
483 if (unlikely(!action
))
486 synchronize_irq(irq
);
488 spin_lock_irqsave(&irq_action_lock
, flags
);
490 bucket
= __bucket(irq
);
491 if (bucket
!= &pil0_dummy_bucket
) {
492 struct irq_desc
*desc
= bucket
->irq_info
;
493 unsigned long imap
= bucket
->imap
;
496 for (i
= 0; i
< MAX_IRQ_DESC_ACTION
; i
++) {
497 struct irqaction
*p
= &desc
->action
[i
];
500 desc
->action_active_mask
&= ~(1 << i
);
505 if (!desc
->action_active_mask
) {
506 /* This unique interrupt source is now inactive. */
507 bucket
->flags
&= ~IBF_ACTIVE
;
509 /* See if any other buckets share this bucket's IMAP
510 * and are still active.
512 for (ent
= 0; ent
< NUM_IVECS
; ent
++) {
513 struct ino_bucket
*bp
= &ivector_table
[ent
];
516 (bp
->flags
& IBF_ACTIVE
) != 0)
520 /* Only disable when no other sub-irq levels of
521 * the same IMAP are active.
523 if (ent
== NUM_IVECS
)
528 spin_unlock_irqrestore(&irq_action_lock
, flags
);
531 EXPORT_SYMBOL(free_irq
);
534 void synchronize_irq(unsigned int irq
)
536 struct ino_bucket
*bucket
= __bucket(irq
);
539 /* The following is how I wish I could implement this.
540 * Unfortunately the ICLR registers are read-only, you can
541 * only write ICLR_foo values to them. To get the current
542 * IRQ status you would need to get at the IRQ diag registers
543 * in the PCI/SBUS controller and the layout of those vary
544 * from one controller to the next, sigh... -DaveM
546 unsigned long iclr
= bucket
->iclr
;
549 u32 tmp
= upa_readl(iclr
);
551 if (tmp
== ICLR_TRANSMIT
||
552 tmp
== ICLR_PENDING
) {
559 /* So we have to do this with a INPROGRESS bit just like x86. */
560 while (bucket
->flags
& IBF_INPROGRESS
)
564 #endif /* CONFIG_SMP */
566 static void process_bucket(int irq
, struct ino_bucket
*bp
, struct pt_regs
*regs
)
568 struct irq_desc
*desc
= bp
->irq_info
;
569 unsigned char flags
= bp
->flags
;
573 bp
->flags
|= IBF_INPROGRESS
;
575 if (unlikely(!(flags
& IBF_ACTIVE
))) {
580 if (desc
->pre_handler
)
581 desc
->pre_handler(bp
,
582 desc
->pre_handler_arg1
,
583 desc
->pre_handler_arg2
);
585 action_mask
= desc
->action_active_mask
;
587 for (i
= 0; i
< MAX_IRQ_DESC_ACTION
; i
++) {
588 struct irqaction
*p
= &desc
->action
[i
];
591 if (!(action_mask
& mask
))
594 action_mask
&= ~mask
;
596 if (p
->handler(__irq(bp
), p
->dev_id
, regs
) == IRQ_HANDLED
)
603 upa_writel(ICLR_IDLE
, bp
->iclr
);
604 /* Test and add entropy */
605 if (random
& SA_SAMPLE_RANDOM
)
606 add_interrupt_randomness(irq
);
609 bp
->flags
&= ~IBF_INPROGRESS
;
612 void handler_irq(int irq
, struct pt_regs
*regs
)
614 struct ino_bucket
*bp
;
615 int cpu
= smp_processor_id();
619 * Check for TICK_INT on level 14 softint.
622 unsigned long clr_mask
= 1 << irq
;
623 unsigned long tick_mask
= tick_ops
->softint_mask
;
625 if ((irq
== 14) && (get_softint() & tick_mask
)) {
627 clr_mask
= tick_mask
;
629 clear_softint(clr_mask
);
632 clear_softint(1 << irq
);
636 kstat_this_cpu
.irqs
[irq
]++;
641 __bucket(xchg32(irq_work(cpu
, irq
), 0)) :
644 bp
= __bucket(xchg32(irq_work(cpu
, irq
), 0));
647 struct ino_bucket
*nbp
= __bucket(bp
->irq_chain
);
650 process_bucket(irq
, bp
, regs
);
656 #ifdef CONFIG_BLK_DEV_FD
657 extern irqreturn_t
floppy_interrupt(int, void *, struct pt_regs
*);;
659 /* XXX No easy way to include asm/floppy.h XXX */
660 extern unsigned char *pdma_vaddr
;
661 extern unsigned long pdma_size
;
662 extern volatile int doing_pdma
;
663 extern unsigned long fdc_status
;
665 irqreturn_t
sparc_floppy_irq(int irq
, void *dev_cookie
, struct pt_regs
*regs
)
667 if (likely(doing_pdma
)) {
668 void __iomem
*stat
= (void __iomem
*) fdc_status
;
669 unsigned char *vaddr
= pdma_vaddr
;
670 unsigned long size
= pdma_size
;
675 if (unlikely(!(val
& 0x80))) {
680 if (unlikely(!(val
& 0x20))) {
688 *vaddr
++ = readb(stat
+ 1);
690 unsigned char data
= *vaddr
++;
693 writeb(data
, stat
+ 1);
701 /* Send Terminal Count pulse to floppy controller. */
702 val
= readb(auxio_register
);
703 val
|= AUXIO_AUX1_FTCNT
;
704 writeb(val
, auxio_register
);
705 val
&= ~AUXIO_AUX1_FTCNT
;
706 writeb(val
, auxio_register
);
712 return floppy_interrupt(irq
, dev_cookie
, regs
);
714 EXPORT_SYMBOL(sparc_floppy_irq
);
717 /* We really don't need these at all on the Sparc. We only have
718 * stubs here because they are exported to modules.
720 unsigned long probe_irq_on(void)
725 EXPORT_SYMBOL(probe_irq_on
);
727 int probe_irq_off(unsigned long mask
)
732 EXPORT_SYMBOL(probe_irq_off
);
735 static int retarget_one_irq(struct irqaction
*p
, int goal_cpu
)
737 struct ino_bucket
*bucket
= get_ino_in_irqaction(p
) + ivector_table
;
738 unsigned long imap
= bucket
->imap
;
741 while (!cpu_online(goal_cpu
)) {
742 if (++goal_cpu
>= NR_CPUS
)
746 if (tlb_type
== cheetah
|| tlb_type
== cheetah_plus
) {
747 tid
= goal_cpu
<< 26;
748 tid
&= IMAP_AID_SAFARI
;
749 } else if (this_is_starfire
== 0) {
750 tid
= goal_cpu
<< 26;
753 tid
= (starfire_translate(imap
, goal_cpu
) << 26);
756 upa_writel(tid
| IMAP_VALID
, imap
);
759 if (++goal_cpu
>= NR_CPUS
)
761 } while (!cpu_online(goal_cpu
));
766 /* Called from request_irq. */
767 static void distribute_irqs(void)
772 spin_lock_irqsave(&irq_action_lock
, flags
);
776 * Skip the timer at [0], and very rare error/power intrs at [15].
777 * Also level [12], it causes problems on Ex000 systems.
779 for (level
= 1; level
< NR_IRQS
; level
++) {
780 struct irqaction
*p
= irq_action
[level
];
786 cpu
= retarget_one_irq(p
, cpu
);
790 spin_unlock_irqrestore(&irq_action_lock
, flags
);
801 static struct sun5_timer
*prom_timers
;
802 static u64 prom_limit0
, prom_limit1
;
804 static void map_prom_timers(void)
806 unsigned int addr
[3];
809 /* PROM timer node hangs out in the top level of device siblings... */
810 tnode
= prom_finddevice("/counter-timer");
812 /* Assume if node is not present, PROM uses different tick mechanism
813 * which we should not care about.
815 if (tnode
== 0 || tnode
== -1) {
816 prom_timers
= (struct sun5_timer
*) 0;
820 /* If PROM is really using this, it must be mapped by him. */
821 err
= prom_getproperty(tnode
, "address", (char *)addr
, sizeof(addr
));
823 prom_printf("PROM does not have timer mapped, trying to continue.\n");
824 prom_timers
= (struct sun5_timer
*) 0;
827 prom_timers
= (struct sun5_timer
*) ((unsigned long)addr
[0]);
830 static void kill_prom_timer(void)
835 /* Save them away for later. */
836 prom_limit0
= prom_timers
->limit0
;
837 prom_limit1
= prom_timers
->limit1
;
839 /* Just as in sun4c/sun4m PROM uses timer which ticks at IRQ 14.
840 * We turn both off here just to be paranoid.
842 prom_timers
->limit0
= 0;
843 prom_timers
->limit1
= 0;
845 /* Wheee, eat the interrupt packet too... */
846 __asm__
__volatile__(
848 " ldxa [%%g0] %0, %%g1\n"
849 " ldxa [%%g2] %1, %%g1\n"
850 " stxa %%g0, [%%g0] %0\n"
853 : "i" (ASI_INTR_RECEIVE
), "i" (ASI_INTR_R
)
857 void init_irqwork_curcpu(void)
859 int cpu
= hard_smp_processor_id();
861 memset(__irq_work
+ cpu
, 0, sizeof(struct irq_work_struct
));
864 static void __cpuinit
init_one_mondo(unsigned long *pa_ptr
, unsigned long type
)
866 register unsigned long func
__asm__("%o5");
867 register unsigned long arg0
__asm__("%o0");
868 register unsigned long arg1
__asm__("%o1");
869 register unsigned long arg2
__asm__("%o2");
870 unsigned long page
= get_zeroed_page(GFP_ATOMIC
);
873 prom_printf("SUN4V: Error, cannot allocate mondo queue.\n");
877 *pa_ptr
= __pa(page
);
879 func
= HV_FAST_CPU_QCONF
;
882 arg2
= 128; /* XXX Implied by Niagara queue offsets. XXX */
883 __asm__
__volatile__("ta %8"
884 : "=&r" (func
), "=&r" (arg0
),
885 "=&r" (arg1
), "=&r" (arg2
)
886 : "0" (func
), "1" (arg0
),
887 "2" (arg1
), "3" (arg2
),
890 if (func
!= HV_EOK
) {
891 prom_printf("SUN4V: cpu_qconf(%lu) failed with error %lu\n",
897 static void __cpuinit
init_one_kbuf(unsigned long *pa_ptr
)
899 unsigned long page
= get_zeroed_page(GFP_ATOMIC
);
902 prom_printf("SUN4V: Error, cannot allocate kbuf page.\n");
906 *pa_ptr
= __pa(page
);
909 static void __cpuinit
init_cpu_send_mondo_info(struct trap_per_cpu
*tb
)
914 BUILD_BUG_ON((NR_CPUS
* sizeof(u16
)) > (PAGE_SIZE
- 64));
916 page
= get_zeroed_page(GFP_ATOMIC
);
918 prom_printf("SUN4V: Error, cannot allocate cpu mondo page.\n");
922 tb
->cpu_mondo_block_pa
= __pa(page
);
923 tb
->cpu_list_pa
= __pa(page
+ 64);
927 /* Allocate and init the mondo and error queues for this cpu. */
928 void __cpuinit
sun4v_init_mondo_queues(void)
930 int cpu
= hard_smp_processor_id();
931 struct trap_per_cpu
*tb
= &trap_block
[cpu
];
933 init_one_mondo(&tb
->cpu_mondo_pa
, HV_CPU_QUEUE_CPU_MONDO
);
934 init_one_mondo(&tb
->dev_mondo_pa
, HV_CPU_QUEUE_DEVICE_MONDO
);
936 init_one_mondo(&tb
->resum_mondo_pa
, HV_CPU_QUEUE_RES_ERROR
);
937 init_one_kbuf(&tb
->resum_kernel_buf_pa
);
939 init_one_mondo(&tb
->nonresum_mondo_pa
, HV_CPU_QUEUE_NONRES_ERROR
);
940 init_one_kbuf(&tb
->nonresum_kernel_buf_pa
);
942 init_cpu_send_mondo_info(tb
);
945 /* Only invoked on boot processor. */
946 void __init
init_IRQ(void)
950 memset(&ivector_table
[0], 0, sizeof(ivector_table
));
952 if (tlb_type
== hypervisor
)
953 sun4v_init_mondo_queues();
955 /* We need to clear any IRQ's pending in the soft interrupt
956 * registers, a spurious one could be left around from the
957 * PROM timer which we just disabled.
959 clear_softint(get_softint());
961 /* Now that ivector table is initialized, it is safe
962 * to receive IRQ vector traps. We will normally take
963 * one or two right now, in case some device PROM used
964 * to boot us wants to speak to us. We just ignore them.
966 __asm__
__volatile__("rdpr %%pstate, %%g1\n\t"
967 "or %%g1, %0, %%g1\n\t"
968 "wrpr %%g1, 0x0, %%pstate"
974 static struct proc_dir_entry
* root_irq_dir
;
975 static struct proc_dir_entry
* irq_dir
[NUM_IVECS
];
979 static int irq_affinity_read_proc (char *page
, char **start
, off_t off
,
980 int count
, int *eof
, void *data
)
982 struct ino_bucket
*bp
= ivector_table
+ (long)data
;
983 struct irq_desc
*desc
= bp
->irq_info
;
984 struct irqaction
*ap
= desc
->action
;
988 mask
= get_smpaff_in_irqaction(ap
);
989 if (cpus_empty(mask
))
990 mask
= cpu_online_map
;
992 len
= cpumask_scnprintf(page
, count
, mask
);
995 len
+= sprintf(page
+ len
, "\n");
999 static inline void set_intr_affinity(int irq
, cpumask_t hw_aff
)
1001 struct ino_bucket
*bp
= ivector_table
+ irq
;
1002 struct irq_desc
*desc
= bp
->irq_info
;
1003 struct irqaction
*ap
= desc
->action
;
1005 /* Users specify affinity in terms of hw cpu ids.
1006 * As soon as we do this, handler_irq() might see and take action.
1008 put_smpaff_in_irqaction(ap
, hw_aff
);
1010 /* Migration is simply done by the next cpu to service this
1015 static int irq_affinity_write_proc (struct file
*file
, const char __user
*buffer
,
1016 unsigned long count
, void *data
)
1018 int irq
= (long) data
, full_count
= count
, err
;
1019 cpumask_t new_value
;
1021 err
= cpumask_parse(buffer
, count
, new_value
);
1024 * Do not allow disabling IRQs completely - it's a too easy
1025 * way to make the system unusable accidentally :-) At least
1026 * one online CPU still has to be targeted.
1028 cpus_and(new_value
, new_value
, cpu_online_map
);
1029 if (cpus_empty(new_value
))
1032 set_intr_affinity(irq
, new_value
);
1039 #define MAX_NAMELEN 10
1041 static void register_irq_proc (unsigned int irq
)
1043 char name
[MAX_NAMELEN
];
1045 if (!root_irq_dir
|| irq_dir
[irq
])
1048 memset(name
, 0, MAX_NAMELEN
);
1049 sprintf(name
, "%x", irq
);
1051 /* create /proc/irq/1234 */
1052 irq_dir
[irq
] = proc_mkdir(name
, root_irq_dir
);
1055 /* XXX SMP affinity not supported on starfire yet. */
1056 if (this_is_starfire
== 0) {
1057 struct proc_dir_entry
*entry
;
1059 /* create /proc/irq/1234/smp_affinity */
1060 entry
= create_proc_entry("smp_affinity", 0600, irq_dir
[irq
]);
1064 entry
->data
= (void *)(long)irq
;
1065 entry
->read_proc
= irq_affinity_read_proc
;
1066 entry
->write_proc
= irq_affinity_write_proc
;
1072 void init_irq_proc (void)
1074 /* create /proc/irq */
1075 root_irq_dir
= proc_mkdir("irq", NULL
);