drivers/idle/intel_idle.c

   1 /*
   2  * intel_idle.c - native hardware idle loop for modern Intel processors
   3  *
   4  * Copyright (c) 2010, Intel Corporation.
   5  * Len Brown <len.brown@intel.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms and conditions of the GNU General Public License,
   9  * version 2, as published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program; if not, write to the Free Software Foundation, Inc.,
  18  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  19  */
  20
  21 /*
  22  * intel_idle is a cpuidle driver that loads on specific Intel processors
  23  * in lieu of the legacy ACPI processor_idle driver.  The intent is to
  24  * make Linux more efficient on these processors, as intel_idle knows
  25  * more than ACPI, as well as make Linux more immune to ACPI BIOS bugs.
  26  */
  27
  28 /*
  29  * Design Assumptions
  30  *
  31  * All CPUs have same idle states as boot CPU
  32  *
  33  * Chipset BM_STS (bus master status) bit is a NOP
  34  *      for preventing entry into deep C-stats
  35  */
  36
  37 /*
  38  * Known limitations
  39  *
  40  * The driver currently initializes for_each_online_cpu() upon modprobe.
  41  * It it unaware of subsequent processors hot-added to the system.
  42  * This means that if you boot with maxcpus=n and later online
  43  * processors above n, those processors will use C1 only.
  44  *
  45  * ACPI has a .suspend hack to turn off deep c-statees during suspend
  46  * to avoid complications with the lapic timer workaround.
  47  * Have not seen issues with suspend, but may need same workaround here.
  48  *
  49  * There is currently no kernel-based automatic probing/loading mechanism
  50  * if the driver is built as a module.
  51  */
  52
  53 /* un-comment DEBUG to enable pr_debug() statements */
  54 #define DEBUG
  55
  56 #include <linux/kernel.h>
  57 #include <linux/cpuidle.h>
  58 #include <linux/clockchips.h>
  59 #include <trace/events/power.h>
  60 #include <linux/sched.h>
  61 #include <linux/notifier.h>
  62 #include <linux/cpu.h>
  63 #include <linux/module.h>
  64 #include <asm/cpu_device_id.h>
  65 #include <asm/mwait.h>
  66 #include <asm/msr.h>
  67
  68 #define INTEL_IDLE_VERSION "0.4"
  69 #define PREFIX "intel_idle: "
  70
  71 static struct cpuidle_driver intel_idle_driver = {
  72         .name = "intel_idle",
  73         .owner = THIS_MODULE,
  74         .en_core_tk_irqen = 1,
  75 };
  76 /* intel_idle.max_cstate=0 disables driver */
  77 static int max_cstate = MWAIT_MAX_NUM_CSTATES - 1;
  78
  79 static unsigned int mwait_substates;
  80
  81 #define LAPIC_TIMER_ALWAYS_RELIABLE 0xFFFFFFFF
  82 /* Reliable LAPIC Timer States, bit 1 for C1 etc.  */
  83 static unsigned int lapic_timer_reliable_states = (1 << 1);      /* Default to only C1 */
  84
  85 struct idle_cpu {
  86         struct cpuidle_state *state_table;
  87
  88         /*
  89          * Hardware C-state auto-demotion may not always be optimal.
  90          * Indicate which enable bits to clear here.
  91          */
  92         unsigned long auto_demotion_disable_flags;
  93 };
  94
  95 static const struct idle_cpu *icpu;
  96 static struct cpuidle_device __percpu *intel_idle_cpuidle_devices;
  97 static int intel_idle(struct cpuidle_device *dev,
  98                         struct cpuidle_driver *drv, int index);
  99 static int intel_idle_cpu_init(int cpu);
 100
 101 static struct cpuidle_state *cpuidle_state_table;
 102
 103 /*
 104  * Set this flag for states where the HW flushes the TLB for us
 105  * and so we don't need cross-calls to keep it consistent.
 106  * If this flag is set, SW flushes the TLB, so even if the
 107  * HW doesn't do the flushing, this flag is safe to use.
 108  */
 109 #define CPUIDLE_FLAG_TLB_FLUSHED        0x10000
 110
 111 /*
 112  * States are indexed by the cstate number,
 113  * which is also the index into the MWAIT hint array.
 114  * Thus C0 is a dummy.
 115  */
 116 static struct cpuidle_state nehalem_cstates[MWAIT_MAX_NUM_CSTATES] = {
 117         { /* MWAIT C0 */ },
 118         { /* MWAIT C1 */
 119                 .name = "C1-NHM",
 120                 .desc = "MWAIT 0x00",
 121                 .flags = CPUIDLE_FLAG_TIME_VALID,
 122                 .exit_latency = 3,
 123                 .target_residency = 6,
 124                 .enter = &intel_idle },
 125         { /* MWAIT C2 */
 126                 .name = "C3-NHM",
 127                 .desc = "MWAIT 0x10",
 128                 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 129                 .exit_latency = 20,
 130                 .target_residency = 80,
 131                 .enter = &intel_idle },
 132         { /* MWAIT C3 */
 133                 .name = "C6-NHM",
 134                 .desc = "MWAIT 0x20",
 135                 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 136                 .exit_latency = 200,
 137                 .target_residency = 800,
 138                 .enter = &intel_idle },
 139 };
 140
 141 static struct cpuidle_state snb_cstates[MWAIT_MAX_NUM_CSTATES] = {
 142         { /* MWAIT C0 */ },
 143         { /* MWAIT C1 */
 144                 .name = "C1-SNB",
 145                 .desc = "MWAIT 0x00",
 146                 .flags = CPUIDLE_FLAG_TIME_VALID,
 147                 .exit_latency = 1,
 148                 .target_residency = 1,
 149                 .enter = &intel_idle },
 150         { /* MWAIT C2 */
 151                 .name = "C3-SNB",
 152                 .desc = "MWAIT 0x10",
 153                 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 154                 .exit_latency = 80,
 155                 .target_residency = 211,
 156                 .enter = &intel_idle },
 157         { /* MWAIT C3 */
 158                 .name = "C6-SNB",
 159                 .desc = "MWAIT 0x20",
 160                 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 161                 .exit_latency = 104,
 162                 .target_residency = 345,
 163                 .enter = &intel_idle },
 164         { /* MWAIT C4 */
 165                 .name = "C7-SNB",
 166                 .desc = "MWAIT 0x30",
 167                 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 168                 .exit_latency = 109,
 169                 .target_residency = 345,
 170                 .enter = &intel_idle },
 171 };
 172
 173 static struct cpuidle_state ivb_cstates[MWAIT_MAX_NUM_CSTATES] = {
 174         { /* MWAIT C0 */ },
 175         { /* MWAIT C1 */
 176                 .name = "C1-IVB",
 177                 .desc = "MWAIT 0x00",
 178                 .flags = CPUIDLE_FLAG_TIME_VALID,
 179                 .exit_latency = 1,
 180                 .target_residency = 1,
 181                 .enter = &intel_idle },
 182         { /* MWAIT C2 */
 183                 .name = "C3-IVB",
 184                 .desc = "MWAIT 0x10",
 185                 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 186                 .exit_latency = 59,
 187                 .target_residency = 156,
 188                 .enter = &intel_idle },
 189         { /* MWAIT C3 */
 190                 .name = "C6-IVB",
 191                 .desc = "MWAIT 0x20",
 192                 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 193                 .exit_latency = 80,
 194                 .target_residency = 300,
 195                 .enter = &intel_idle },
 196         { /* MWAIT C4 */
 197                 .name = "C7-IVB",
 198                 .desc = "MWAIT 0x30",
 199                 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 200                 .exit_latency = 87,
 201                 .target_residency = 300,
 202                 .enter = &intel_idle },
 203 };
 204
 205 static struct cpuidle_state atom_cstates[MWAIT_MAX_NUM_CSTATES] = {
 206         { /* MWAIT C0 */ },
 207         { /* MWAIT C1 */
 208                 .name = "C1-ATM",
 209                 .desc = "MWAIT 0x00",
 210                 .flags = CPUIDLE_FLAG_TIME_VALID,
 211                 .exit_latency = 1,
 212                 .target_residency = 4,
 213                 .enter = &intel_idle },
 214         { /* MWAIT C2 */
 215                 .name = "C2-ATM",
 216                 .desc = "MWAIT 0x10",
 217                 .flags = CPUIDLE_FLAG_TIME_VALID,
 218                 .exit_latency = 20,
 219                 .target_residency = 80,
 220                 .enter = &intel_idle },
 221         { /* MWAIT C3 */ },
 222         { /* MWAIT C4 */
 223                 .name = "C4-ATM",
 224                 .desc = "MWAIT 0x30",
 225                 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 226                 .exit_latency = 100,
 227                 .target_residency = 400,
 228                 .enter = &intel_idle },
 229         { /* MWAIT C5 */ },
 230         { /* MWAIT C6 */
 231                 .name = "C6-ATM",
 232                 .desc = "MWAIT 0x52",
 233                 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED,
 234                 .exit_latency = 140,
 235                 .target_residency = 560,
 236                 .enter = &intel_idle },
 237 };
 238
 239 static long get_driver_data(int cstate)
 240 {
 241         int driver_data;
 242         switch (cstate) {
 243
 244         case 1: /* MWAIT C1 */
 245                 driver_data = 0x00;
 246                 break;
 247         case 2: /* MWAIT C2 */
 248                 driver_data = 0x10;
 249                 break;
 250         case 3: /* MWAIT C3 */
 251                 driver_data = 0x20;
 252                 break;
 253         case 4: /* MWAIT C4 */
 254                 driver_data = 0x30;
 255                 break;
 256         case 5: /* MWAIT C5 */
 257                 driver_data = 0x40;
 258                 break;
 259         case 6: /* MWAIT C6 */
 260                 driver_data = 0x52;
 261                 break;
 262         default:
 263                 driver_data = 0x00;
 264         }
 265         return driver_data;
 266 }
 267
 268 /**
 269  * intel_idle
 270  * @dev: cpuidle_device
 271  * @drv: cpuidle driver
 272  * @index: index of cpuidle state
 273  *
 274  * Must be called under local_irq_disable().
 275  */
 276 static int intel_idle(struct cpuidle_device *dev,
 277                 struct cpuidle_driver *drv, int index)
 278 {
 279         unsigned long ecx = 1; /* break on interrupt flag */
 280         struct cpuidle_state *state = &drv->states[index];
 281         struct cpuidle_state_usage *state_usage = &dev->states_usage[index];
 282         unsigned long eax = (unsigned long)cpuidle_get_statedata(state_usage);
 283         unsigned int cstate;
 284         int cpu = smp_processor_id();
 285
 286         cstate = (((eax) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK) + 1;
 287
 288         /*
 289          * leave_mm() to avoid costly and often unnecessary wakeups
 290          * for flushing the user TLB's associated with the active mm.
 291          */
 292         if (state->flags & CPUIDLE_FLAG_TLB_FLUSHED)
 293                 leave_mm(cpu);
 294
 295         if (!(lapic_timer_reliable_states & (1 << (cstate))))
 296                 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
 297
 298         stop_critical_timings();
 299         if (!need_resched()) {
 300
 301                 __monitor((void *)&current_thread_info()->flags, 0, 0);
 302                 smp_mb();
 303                 if (!need_resched())
 304                         __mwait(eax, ecx);
 305         }
 306
 307         start_critical_timings();
 308
 309         if (!(lapic_timer_reliable_states & (1 << (cstate))))
 310                 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
 311
 312         return index;
 313 }
 314
 315 static void __setup_broadcast_timer(void *arg)
 316 {
 317         unsigned long reason = (unsigned long)arg;
 318         int cpu = smp_processor_id();
 319
 320         reason = reason ?
 321                 CLOCK_EVT_NOTIFY_BROADCAST_ON : CLOCK_EVT_NOTIFY_BROADCAST_OFF;
 322
 323         clockevents_notify(reason, &cpu);
 324 }
 325
 326 static int cpu_hotplug_notify(struct notifier_block *n,
 327                               unsigned long action, void *hcpu)
 328 {
 329         int hotcpu = (unsigned long)hcpu;
 330         struct cpuidle_device *dev;
 331
 332         switch (action & 0xf) {
 333         case CPU_ONLINE:
 334
 335                 if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE)
 336                         smp_call_function_single(hotcpu, __setup_broadcast_timer,
 337                                                  (void *)true, 1);
 338
 339                 /*
 340                  * Some systems can hotplug a cpu at runtime after
 341                  * the kernel has booted, we have to initialize the
 342                  * driver in this case
 343                  */
 344                 dev = per_cpu_ptr(intel_idle_cpuidle_devices, hotcpu);
 345                 if (!dev->registered)
 346                         intel_idle_cpu_init(hotcpu);
 347
 348                 break;
 349         }
 350         return NOTIFY_OK;
 351 }
 352
 353 static struct notifier_block cpu_hotplug_notifier = {
 354         .notifier_call = cpu_hotplug_notify,
 355 };
 356
 357 static void auto_demotion_disable(void *dummy)
 358 {
 359         unsigned long long msr_bits;
 360
 361         rdmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits);
 362         msr_bits &= ~(icpu->auto_demotion_disable_flags);
 363         wrmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits);
 364 }
 365
 366 static const struct idle_cpu idle_cpu_nehalem = {
 367         .state_table = nehalem_cstates,
 368         .auto_demotion_disable_flags = NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE,
 369 };
 370
 371 static const struct idle_cpu idle_cpu_atom = {
 372         .state_table = atom_cstates,
 373 };
 374
 375 static const struct idle_cpu idle_cpu_lincroft = {
 376         .state_table = atom_cstates,
 377         .auto_demotion_disable_flags = ATM_LNC_C6_AUTO_DEMOTE,
 378 };
 379
 380 static const struct idle_cpu idle_cpu_snb = {
 381         .state_table = snb_cstates,
 382 };
 383
 384 static const struct idle_cpu idle_cpu_ivb = {
 385         .state_table = ivb_cstates,
 386 };
 387
 388 #define ICPU(model, cpu) \
 389         { X86_VENDOR_INTEL, 6, model, X86_FEATURE_MWAIT, (unsigned long)&cpu }
 390
 391 static const struct x86_cpu_id intel_idle_ids[] = {
 392         ICPU(0x1a, idle_cpu_nehalem),
 393         ICPU(0x1e, idle_cpu_nehalem),
 394         ICPU(0x1f, idle_cpu_nehalem),
 395         ICPU(0x25, idle_cpu_nehalem),
 396         ICPU(0x2c, idle_cpu_nehalem),
 397         ICPU(0x2e, idle_cpu_nehalem),
 398         ICPU(0x1c, idle_cpu_atom),
 399         ICPU(0x26, idle_cpu_lincroft),
 400         ICPU(0x2f, idle_cpu_nehalem),
 401         ICPU(0x2a, idle_cpu_snb),
 402         ICPU(0x2d, idle_cpu_snb),
 403         ICPU(0x3a, idle_cpu_ivb),
 404         ICPU(0x3e, idle_cpu_ivb),
 405         {}
 406 };
 407 MODULE_DEVICE_TABLE(x86cpu, intel_idle_ids);
 408
 409 /*
 410  * intel_idle_probe()
 411  */
 412 static int intel_idle_probe(void)
 413 {
 414         unsigned int eax, ebx, ecx;
 415         const struct x86_cpu_id *id;
 416
 417         if (max_cstate == 0) {
 418                 pr_debug(PREFIX "disabled\n");
 419                 return -EPERM;
 420         }
 421
 422         id = x86_match_cpu(intel_idle_ids);
 423         if (!id) {
 424                 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
 425                     boot_cpu_data.x86 == 6)
 426                         pr_debug(PREFIX "does not run on family %d model %d\n",
 427                                 boot_cpu_data.x86, boot_cpu_data.x86_model);
 428                 return -ENODEV;
 429         }
 430
 431         if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF)
 432                 return -ENODEV;
 433
 434         cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &mwait_substates);
 435
 436         if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) ||
 437             !(ecx & CPUID5_ECX_INTERRUPT_BREAK) ||
 438             !mwait_substates)
 439                         return -ENODEV;
 440
 441         pr_debug(PREFIX "MWAIT substates: 0x%x\n", mwait_substates);
 442
 443         icpu = (const struct idle_cpu *)id->driver_data;
 444         cpuidle_state_table = icpu->state_table;
 445
 446         if (boot_cpu_has(X86_FEATURE_ARAT))     /* Always Reliable APIC Timer */
 447                 lapic_timer_reliable_states = LAPIC_TIMER_ALWAYS_RELIABLE;
 448         else
 449                 on_each_cpu(__setup_broadcast_timer, (void *)true, 1);
 450
 451         pr_debug(PREFIX "v" INTEL_IDLE_VERSION
 452                 " model 0x%X\n", boot_cpu_data.x86_model);
 453
 454         pr_debug(PREFIX "lapic_timer_reliable_states 0x%x\n",
 455                 lapic_timer_reliable_states);
 456         return 0;
 457 }
 458
 459 /*
 460  * intel_idle_cpuidle_devices_uninit()
 461  * unregister, free cpuidle_devices
 462  */
 463 static void intel_idle_cpuidle_devices_uninit(void)
 464 {
 465         int i;
 466         struct cpuidle_device *dev;
 467
 468         for_each_online_cpu(i) {
 469                 dev = per_cpu_ptr(intel_idle_cpuidle_devices, i);
 470                 cpuidle_unregister_device(dev);
 471         }
 472
 473         free_percpu(intel_idle_cpuidle_devices);
 474         return;
 475 }
 476 /*
 477  * intel_idle_cpuidle_driver_init()
 478  * allocate, initialize cpuidle_states
 479  */
 480 static int intel_idle_cpuidle_driver_init(void)
 481 {
 482         int cstate;
 483         struct cpuidle_driver *drv = &intel_idle_driver;
 484
 485         drv->state_count = 1;
 486
 487         for (cstate = 1; cstate < MWAIT_MAX_NUM_CSTATES; ++cstate) {
 488                 int num_substates;
 489
 490                 if (cstate > max_cstate) {
 491                         printk(PREFIX "max_cstate %d reached\n",
 492                                 max_cstate);
 493                         break;
 494                 }
 495
 496                 /* does the state exist in CPUID.MWAIT? */
 497                 num_substates = (mwait_substates >> ((cstate) * 4))
 498                                         & MWAIT_SUBSTATE_MASK;
 499                 if (num_substates == 0)
 500                         continue;
 501                 /* is the state not enabled? */
 502                 if (cpuidle_state_table[cstate].enter == NULL) {
 503                         /* does the driver not know about the state? */
 504                         if (*cpuidle_state_table[cstate].name == '\0')
 505                                 pr_debug(PREFIX "unaware of model 0x%x"
 506                                         " MWAIT %d please"
 507                                         " contact lenb@kernel.org\n",
 508                                 boot_cpu_data.x86_model, cstate);
 509                         continue;
 510                 }
 511
 512                 if ((cstate > 2) &&
 513                         !boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
 514                         mark_tsc_unstable("TSC halts in idle"
 515                                         " states deeper than C2");
 516
 517                 drv->states[drv->state_count] = /* structure copy */
 518                         cpuidle_state_table[cstate];
 519
 520                 drv->state_count += 1;
 521         }
 522
 523         if (icpu->auto_demotion_disable_flags)
 524                 on_each_cpu(auto_demotion_disable, NULL, 1);
 525
 526         return 0;
 527 }
 528
 529
 530 /*
 531  * intel_idle_cpu_init()
 532  * allocate, initialize, register cpuidle_devices
 533  * @cpu: cpu/core to initialize
 534  */
 535 static int intel_idle_cpu_init(int cpu)
 536 {
 537         int cstate;
 538         struct cpuidle_device *dev;
 539
 540         dev = per_cpu_ptr(intel_idle_cpuidle_devices, cpu);
 541
 542         dev->state_count = 1;
 543
 544         for (cstate = 1; cstate < MWAIT_MAX_NUM_CSTATES; ++cstate) {
 545                 int num_substates;
 546
 547                 if (cstate > max_cstate) {
 548                         printk(PREFIX "max_cstate %d reached\n", max_cstate);
 549                         break;
 550                 }
 551
 552                 /* does the state exist in CPUID.MWAIT? */
 553                 num_substates = (mwait_substates >> ((cstate) * 4))
 554                         & MWAIT_SUBSTATE_MASK;
 555                 if (num_substates == 0)
 556                         continue;
 557                 /* is the state not enabled? */
 558                 if (cpuidle_state_table[cstate].enter == NULL)
 559                         continue;
 560
 561                 dev->states_usage[dev->state_count].driver_data =
 562                         (void *)get_driver_data(cstate);
 563
 564                 dev->state_count += 1;
 565         }
 566
 567         dev->cpu = cpu;
 568
 569         if (cpuidle_register_device(dev)) {
 570                 pr_debug(PREFIX "cpuidle_register_device %d failed!\n", cpu);
 571                 intel_idle_cpuidle_devices_uninit();
 572                 return -EIO;
 573         }
 574
 575         if (icpu->auto_demotion_disable_flags)
 576                 smp_call_function_single(cpu, auto_demotion_disable, NULL, 1);
 577
 578         return 0;
 579 }
 580
 581 static int __init intel_idle_init(void)
 582 {
 583         int retval, i;
 584
 585         /* Do not load intel_idle at all for now if idle= is passed */
 586         if (boot_option_idle_override != IDLE_NO_OVERRIDE)
 587                 return -ENODEV;
 588
 589         retval = intel_idle_probe();
 590         if (retval)
 591                 return retval;
 592
 593         intel_idle_cpuidle_driver_init();
 594         retval = cpuidle_register_driver(&intel_idle_driver);
 595         if (retval) {
 596                 struct cpuidle_driver *drv = cpuidle_get_driver();
 597                 printk(KERN_DEBUG PREFIX "intel_idle yielding to %s",
 598                         drv ? drv->name : "none");
 599                 return retval;
 600         }
 601
 602         intel_idle_cpuidle_devices = alloc_percpu(struct cpuidle_device);
 603         if (intel_idle_cpuidle_devices == NULL)
 604                 return -ENOMEM;
 605
 606         for_each_online_cpu(i) {
 607                 retval = intel_idle_cpu_init(i);
 608                 if (retval) {
 609                         cpuidle_unregister_driver(&intel_idle_driver);
 610                         return retval;
 611                 }
 612         }
 613         register_cpu_notifier(&cpu_hotplug_notifier);
 614
 615         return 0;
 616 }
 617
 618 static void __exit intel_idle_exit(void)
 619 {
 620         intel_idle_cpuidle_devices_uninit();
 621         cpuidle_unregister_driver(&intel_idle_driver);
 622
 623
 624         if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE)
 625                 on_each_cpu(__setup_broadcast_timer, (void *)false, 1);
 626         unregister_cpu_notifier(&cpu_hotplug_notifier);
 627
 628         return;
 629 }
 630
 631 module_init(intel_idle_init);
 632 module_exit(intel_idle_exit);
 633
 634 module_param(max_cstate, int, 0444);
 635
 636 MODULE_AUTHOR("Len Brown <len.brown@intel.com>");
 637 MODULE_DESCRIPTION("Cpuidle driver for Intel Hardware v" INTEL_IDLE_VERSION);
 638 MODULE_LICENSE("GPL");