include/asm-s390/pgtable.h

   1 /*
   2  *  include/asm-s390/pgtable.h
   3  *
   4  *  S390 version
   5  *    Copyright (C) 1999,2000 IBM Deutschland Entwicklung GmbH, IBM Corporation
   6  *    Author(s): Hartmut Penner (hp@de.ibm.com)
   7  *               Ulrich Weigand (weigand@de.ibm.com)
   8  *               Martin Schwidefsky (schwidefsky@de.ibm.com)
   9  *
  10  *  Derived from "include/asm-i386/pgtable.h"
  11  */
  12
  13 #ifndef _ASM_S390_PGTABLE_H
  14 #define _ASM_S390_PGTABLE_H
  15
  16 /*
  17  * The Linux memory management assumes a three-level page table setup. For
  18  * s390 31 bit we "fold" the mid level into the top-level page table, so
  19  * that we physically have the same two-level page table as the s390 mmu
  20  * expects in 31 bit mode. For s390 64 bit we use three of the five levels
  21  * the hardware provides (region first and region second tables are not
  22  * used).
  23  *
  24  * The "pgd_xxx()" functions are trivial for a folded two-level
  25  * setup: the pgd is never bad, and a pmd always exists (as it's folded
  26  * into the pgd entry)
  27  *
  28  * This file contains the functions and defines necessary to modify and use
  29  * the S390 page table tree.
  30  */
  31 #ifndef __ASSEMBLY__
  32 #include <linux/mm_types.h>
  33 #include <asm/bug.h>
  34 #include <asm/processor.h>
  35
  36 extern pgd_t swapper_pg_dir[] __attribute__ ((aligned (4096)));
  37 extern void paging_init(void);
  38 extern void vmem_map_init(void);
  39
  40 /*
  41  * The S390 doesn't have any external MMU info: the kernel page
  42  * tables contain all the necessary information.
  43  */
  44 #define update_mmu_cache(vma, address, pte)     do { } while (0)
  45
  46 /*
  47  * ZERO_PAGE is a global shared page that is always zero: used
  48  * for zero-mapped memory areas etc..
  49  */
  50 extern char empty_zero_page[PAGE_SIZE];
  51 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
  52 #endif /* !__ASSEMBLY__ */
  53
  54 /*
  55  * PMD_SHIFT determines the size of the area a second-level page
  56  * table can map
  57  * PGDIR_SHIFT determines what a third-level page table entry can map
  58  */
  59 #ifndef __s390x__
  60 # define PMD_SHIFT      20
  61 # define PUD_SHIFT      20
  62 # define PGDIR_SHIFT    20
  63 #else /* __s390x__ */
  64 # define PMD_SHIFT      20
  65 # define PUD_SHIFT      31
  66 # define PGDIR_SHIFT    31
  67 #endif /* __s390x__ */
  68
  69 #define PMD_SIZE        (1UL << PMD_SHIFT)
  70 #define PMD_MASK        (~(PMD_SIZE-1))
  71 #define PUD_SIZE        (1UL << PUD_SHIFT)
  72 #define PUD_MASK        (~(PUD_SIZE-1))
  73 #define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
  74 #define PGDIR_MASK      (~(PGDIR_SIZE-1))
  75
  76 /*
  77  * entries per page directory level: the S390 is two-level, so
  78  * we don't really have any PMD directory physically.
  79  * for S390 segment-table entries are combined to one PGD
  80  * that leads to 1024 pte per pgd
  81  */
  82 #define PTRS_PER_PTE    256
  83 #ifndef __s390x__
  84 #define PTRS_PER_PMD    1
  85 #else /* __s390x__ */
  86 #define PTRS_PER_PMD    2048
  87 #endif /* __s390x__ */
  88 #define PTRS_PER_PUD    1
  89 #define PTRS_PER_PGD    2048
  90
  91 #define FIRST_USER_ADDRESS  0
  92
  93 #define pte_ERROR(e) \
  94         printk("%s:%d: bad pte %p.\n", __FILE__, __LINE__, (void *) pte_val(e))
  95 #define pmd_ERROR(e) \
  96         printk("%s:%d: bad pmd %p.\n", __FILE__, __LINE__, (void *) pmd_val(e))
  97 #define pud_ERROR(e) \
  98         printk("%s:%d: bad pud %p.\n", __FILE__, __LINE__, (void *) pud_val(e))
  99 #define pgd_ERROR(e) \
 100         printk("%s:%d: bad pgd %p.\n", __FILE__, __LINE__, (void *) pgd_val(e))
 101
 102 #ifndef __ASSEMBLY__
 103 /*
 104  * The vmalloc area will always be on the topmost area of the kernel
 105  * mapping. We reserve 96MB (31bit) / 1GB (64bit) for vmalloc,
 106  * which should be enough for any sane case.
 107  * By putting vmalloc at the top, we maximise the gap between physical
 108  * memory and vmalloc to catch misplaced memory accesses. As a side
 109  * effect, this also makes sure that 64 bit module code cannot be used
 110  * as system call address.
 111  */
 112 #ifndef __s390x__
 113 #define VMALLOC_START   0x78000000UL
 114 #define VMALLOC_END     0x7e000000UL
 115 #define VMEM_MAP_END    0x80000000UL
 116 #else /* __s390x__ */
 117 #define VMALLOC_START   0x3e000000000UL
 118 #define VMALLOC_END     0x3e040000000UL
 119 #define VMEM_MAP_END    0x40000000000UL
 120 #endif /* __s390x__ */
 121
 122 /*
 123  * VMEM_MAX_PHYS is the highest physical address that can be added to the 1:1
 124  * mapping. This needs to be calculated at compile time since the size of the
 125  * VMEM_MAP is static but the size of struct page can change.
 126  */
 127 #define VMEM_MAX_PAGES  ((VMEM_MAP_END - VMALLOC_END) / sizeof(struct page))
 128 #define VMEM_MAX_PFN    min(VMALLOC_START >> PAGE_SHIFT, VMEM_MAX_PAGES)
 129 #define VMEM_MAX_PHYS   ((VMEM_MAX_PFN << PAGE_SHIFT) & ~((16 << 20) - 1))
 130 #define VMEM_MAP        ((struct page *) VMALLOC_END)
 131
 132 /*
 133  * A 31 bit pagetable entry of S390 has following format:
 134  *  |   PFRA          |    |  OS  |
 135  * 0                   0IP0
 136  * 00000000001111111111222222222233
 137  * 01234567890123456789012345678901
 138  *
 139  * I Page-Invalid Bit:    Page is not available for address-translation
 140  * P Page-Protection Bit: Store access not possible for page
 141  *
 142  * A 31 bit segmenttable entry of S390 has following format:
 143  *  |   P-table origin      |  |PTL
 144  * 0                         IC
 145  * 00000000001111111111222222222233
 146  * 01234567890123456789012345678901
 147  *
 148  * I Segment-Invalid Bit:    Segment is not available for address-translation
 149  * C Common-Segment Bit:     Segment is not private (PoP 3-30)
 150  * PTL Page-Table-Length:    Page-table length (PTL+1*16 entries -> up to 256)
 151  *
 152  * The 31 bit segmenttable origin of S390 has following format:
 153  *
 154  *  |S-table origin   |     | STL |
 155  * X                   **GPS
 156  * 00000000001111111111222222222233
 157  * 01234567890123456789012345678901
 158  *
 159  * X Space-Switch event:
 160  * G Segment-Invalid Bit:     *
 161  * P Private-Space Bit:       Segment is not private (PoP 3-30)
 162  * S Storage-Alteration:
 163  * STL Segment-Table-Length:  Segment-table length (STL+1*16 entries -> up to 2048)
 164  *
 165  * A 64 bit pagetable entry of S390 has following format:
 166  * |                     PFRA                         |0IP0|  OS  |
 167  * 0000000000111111111122222222223333333333444444444455555555556666
 168  * 0123456789012345678901234567890123456789012345678901234567890123
 169  *
 170  * I Page-Invalid Bit:    Page is not available for address-translation
 171  * P Page-Protection Bit: Store access not possible for page
 172  *
 173  * A 64 bit segmenttable entry of S390 has following format:
 174  * |        P-table origin                              |      TT
 175  * 0000000000111111111122222222223333333333444444444455555555556666
 176  * 0123456789012345678901234567890123456789012345678901234567890123
 177  *
 178  * I Segment-Invalid Bit:    Segment is not available for address-translation
 179  * C Common-Segment Bit:     Segment is not private (PoP 3-30)
 180  * P Page-Protection Bit: Store access not possible for page
 181  * TT Type 00
 182  *
 183  * A 64 bit region table entry of S390 has following format:
 184  * |        S-table origin                             |   TF  TTTL
 185  * 0000000000111111111122222222223333333333444444444455555555556666
 186  * 0123456789012345678901234567890123456789012345678901234567890123
 187  *
 188  * I Segment-Invalid Bit:    Segment is not available for address-translation
 189  * TT Type 01
 190  * TF
 191  * TL Table length
 192  *
 193  * The 64 bit regiontable origin of S390 has following format:
 194  * |      region table origon                          |       DTTL
 195  * 0000000000111111111122222222223333333333444444444455555555556666
 196  * 0123456789012345678901234567890123456789012345678901234567890123
 197  *
 198  * X Space-Switch event:
 199  * G Segment-Invalid Bit:
 200  * P Private-Space Bit:
 201  * S Storage-Alteration:
 202  * R Real space
 203  * TL Table-Length:
 204  *
 205  * A storage key has the following format:
 206  * | ACC |F|R|C|0|
 207  *  0   3 4 5 6 7
 208  * ACC: access key
 209  * F  : fetch protection bit
 210  * R  : referenced bit
 211  * C  : changed bit
 212  */
 213
 214 /* Hardware bits in the page table entry */
 215 #define _PAGE_RO        0x200           /* HW read-only bit  */
 216 #define _PAGE_INVALID   0x400           /* HW invalid bit    */
 217
 218 /* Software bits in the page table entry */
 219 #define _PAGE_SWT       0x001           /* SW pte type bit t */
 220 #define _PAGE_SWX       0x002           /* SW pte type bit x */
 221
 222 /* Six different types of pages. */
 223 #define _PAGE_TYPE_EMPTY        0x400
 224 #define _PAGE_TYPE_NONE         0x401
 225 #define _PAGE_TYPE_SWAP         0x403
 226 #define _PAGE_TYPE_FILE         0x601   /* bit 0x002 is used for offset !! */
 227 #define _PAGE_TYPE_RO           0x200
 228 #define _PAGE_TYPE_RW           0x000
 229 #define _PAGE_TYPE_EX_RO        0x202
 230 #define _PAGE_TYPE_EX_RW        0x002
 231
 232 /*
 233  * PTE type bits are rather complicated. handle_pte_fault uses pte_present,
 234  * pte_none and pte_file to find out the pte type WITHOUT holding the page
 235  * table lock. ptep_clear_flush on the other hand uses ptep_clear_flush to
 236  * invalidate a given pte. ipte sets the hw invalid bit and clears all tlbs
 237  * for the page. The page table entry is set to _PAGE_TYPE_EMPTY afterwards.
 238  * This change is done while holding the lock, but the intermediate step
 239  * of a previously valid pte with the hw invalid bit set can be observed by
 240  * handle_pte_fault. That makes it necessary that all valid pte types with
 241  * the hw invalid bit set must be distinguishable from the four pte types
 242  * empty, none, swap and file.
 243  *
 244  *                      irxt  ipte  irxt
 245  * _PAGE_TYPE_EMPTY     1000   ->   1000
 246  * _PAGE_TYPE_NONE      1001   ->   1001
 247  * _PAGE_TYPE_SWAP      1011   ->   1011
 248  * _PAGE_TYPE_FILE      11?1   ->   11?1
 249  * _PAGE_TYPE_RO        0100   ->   1100
 250  * _PAGE_TYPE_RW        0000   ->   1000
 251  * _PAGE_TYPE_EX_RO     0110   ->   1110
 252  * _PAGE_TYPE_EX_RW     0010   ->   1010
 253  *
 254  * pte_none is true for bits combinations 1000, 1010, 1100, 1110
 255  * pte_present is true for bits combinations 0000, 0010, 0100, 0110, 1001
 256  * pte_file is true for bits combinations 1101, 1111
 257  * swap pte is 1011 and 0001, 0011, 0101, 0111 are invalid.
 258  */
 259
 260 #ifndef __s390x__
 261
 262 /* Bits in the segment table address-space-control-element */
 263 #define _ASCE_SPACE_SWITCH      0x80000000UL    /* space switch event       */
 264 #define _ASCE_ORIGIN_MASK       0x7ffff000UL    /* segment table origin     */
 265 #define _ASCE_PRIVATE_SPACE     0x100   /* private space control            */
 266 #define _ASCE_ALT_EVENT         0x80    /* storage alteration event control */
 267 #define _ASCE_TABLE_LENGTH      0x7f    /* 128 x 64 entries = 8k            */
 268
 269 /* Bits in the segment table entry */
 270 #define _SEGMENT_ENTRY_ORIGIN   0x7fffffc0UL    /* page table origin        */
 271 #define _SEGMENT_ENTRY_INV      0x20    /* invalid segment table entry      */
 272 #define _SEGMENT_ENTRY_COMMON   0x10    /* common segment bit               */
 273 #define _SEGMENT_ENTRY_PTL      0x0f    /* page table length                */
 274
 275 #define _SEGMENT_ENTRY          (_SEGMENT_ENTRY_PTL)
 276 #define _SEGMENT_ENTRY_EMPTY    (_SEGMENT_ENTRY_INV)
 277
 278 #else /* __s390x__ */
 279
 280 /* Bits in the segment/region table address-space-control-element */
 281 #define _ASCE_ORIGIN            ~0xfffUL/* segment table origin             */
 282 #define _ASCE_PRIVATE_SPACE     0x100   /* private space control            */
 283 #define _ASCE_ALT_EVENT         0x80    /* storage alteration event control */
 284 #define _ASCE_SPACE_SWITCH      0x40    /* space switch event               */
 285 #define _ASCE_REAL_SPACE        0x20    /* real space control               */
 286 #define _ASCE_TYPE_MASK         0x0c    /* asce table type mask             */
 287 #define _ASCE_TYPE_REGION1      0x0c    /* region first table type          */
 288 #define _ASCE_TYPE_REGION2      0x08    /* region second table type         */
 289 #define _ASCE_TYPE_REGION3      0x04    /* region third table type          */
 290 #define _ASCE_TYPE_SEGMENT      0x00    /* segment table type               */
 291 #define _ASCE_TABLE_LENGTH      0x03    /* region table length              */
 292
 293 /* Bits in the region table entry */
 294 #define _REGION_ENTRY_ORIGIN    ~0xfffUL/* region/segment table origin      */
 295 #define _REGION_ENTRY_INV       0x20    /* invalid region table entry       */
 296 #define _REGION_ENTRY_TYPE_MASK 0x0c    /* region/segment table type mask   */
 297 #define _REGION_ENTRY_TYPE_R1   0x0c    /* region first table type          */
 298 #define _REGION_ENTRY_TYPE_R2   0x08    /* region second table type         */
 299 #define _REGION_ENTRY_TYPE_R3   0x04    /* region third table type          */
 300 #define _REGION_ENTRY_LENGTH    0x03    /* region third length              */
 301
 302 #define _REGION1_ENTRY          (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_LENGTH)
 303 #define _REGION1_ENTRY_EMPTY    (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_INV)
 304 #define _REGION2_ENTRY          (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_LENGTH)
 305 #define _REGION2_ENTRY_EMPTY    (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_INV)
 306 #define _REGION3_ENTRY          (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_LENGTH)
 307 #define _REGION3_ENTRY_EMPTY    (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_INV)
 308
 309 /* Bits in the segment table entry */
 310 #define _SEGMENT_ENTRY_ORIGIN   ~0x7ffUL/* segment table origin             */
 311 #define _SEGMENT_ENTRY_RO       0x200   /* page protection bit              */
 312 #define _SEGMENT_ENTRY_INV      0x20    /* invalid segment table entry      */
 313
 314 #define _SEGMENT_ENTRY          (0)
 315 #define _SEGMENT_ENTRY_EMPTY    (_SEGMENT_ENTRY_INV)
 316
 317 #endif /* __s390x__ */
 318
 319 /*
 320  * A user page table pointer has the space-switch-event bit, the
 321  * private-space-control bit and the storage-alteration-event-control
 322  * bit set. A kernel page table pointer doesn't need them.
 323  */
 324 #define _ASCE_USER_BITS         (_ASCE_SPACE_SWITCH | _ASCE_PRIVATE_SPACE | \
 325                                  _ASCE_ALT_EVENT)
 326
 327 /* Bits int the storage key */
 328 #define _PAGE_CHANGED    0x02          /* HW changed bit                   */
 329 #define _PAGE_REFERENCED 0x04          /* HW referenced bit                */
 330
 331 /*
 332  * Page protection definitions.
 333  */
 334 #define PAGE_NONE       __pgprot(_PAGE_TYPE_NONE)
 335 #define PAGE_RO         __pgprot(_PAGE_TYPE_RO)
 336 #define PAGE_RW         __pgprot(_PAGE_TYPE_RW)
 337 #define PAGE_EX_RO      __pgprot(_PAGE_TYPE_EX_RO)
 338 #define PAGE_EX_RW      __pgprot(_PAGE_TYPE_EX_RW)
 339
 340 #define PAGE_KERNEL     PAGE_RW
 341 #define PAGE_COPY       PAGE_RO
 342
 343 /*
 344  * Dependent on the EXEC_PROTECT option s390 can do execute protection.
 345  * Write permission always implies read permission. In theory with a
 346  * primary/secondary page table execute only can be implemented but
 347  * it would cost an additional bit in the pte to distinguish all the
 348  * different pte types. To avoid that execute permission currently
 349  * implies read permission as well.
 350  */
 351          /*xwr*/
 352 #define __P000  PAGE_NONE
 353 #define __P001  PAGE_RO
 354 #define __P010  PAGE_RO
 355 #define __P011  PAGE_RO
 356 #define __P100  PAGE_EX_RO
 357 #define __P101  PAGE_EX_RO
 358 #define __P110  PAGE_EX_RO
 359 #define __P111  PAGE_EX_RO
 360
 361 #define __S000  PAGE_NONE
 362 #define __S001  PAGE_RO
 363 #define __S010  PAGE_RW
 364 #define __S011  PAGE_RW
 365 #define __S100  PAGE_EX_RO
 366 #define __S101  PAGE_EX_RO
 367 #define __S110  PAGE_EX_RW
 368 #define __S111  PAGE_EX_RW
 369
 370 #ifndef __s390x__
 371 # define PxD_SHADOW_SHIFT       1
 372 #else /* __s390x__ */
 373 # define PxD_SHADOW_SHIFT       2
 374 #endif /* __s390x__ */
 375
 376 static inline void *get_shadow_table(void *table)
 377 {
 378         unsigned long addr, offset;
 379         struct page *page;
 380
 381         addr = (unsigned long) table;
 382         offset = addr & ((PAGE_SIZE << PxD_SHADOW_SHIFT) - 1);
 383         page = virt_to_page((void *)(addr ^ offset));
 384         return (void *)(addr_t)(page->index ? (page->index | offset) : 0UL);
 385 }
 386
 387 /*
 388  * Certain architectures need to do special things when PTEs
 389  * within a page table are directly modified.  Thus, the following
 390  * hook is made available.
 391  */
 392 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
 393                               pte_t *ptep, pte_t entry)
 394 {
 395         *ptep = entry;
 396         if (mm->context.noexec) {
 397                 if (!(pte_val(entry) & _PAGE_INVALID) &&
 398                     (pte_val(entry) & _PAGE_SWX))
 399                         pte_val(entry) |= _PAGE_RO;
 400                 else
 401                         pte_val(entry) = _PAGE_TYPE_EMPTY;
 402                 ptep[PTRS_PER_PTE] = entry;
 403         }
 404 }
 405
 406 /*
 407  * pgd/pmd/pte query functions
 408  */
 409 #ifndef __s390x__
 410
 411 static inline int pgd_present(pgd_t pgd) { return 1; }
 412 static inline int pgd_none(pgd_t pgd)    { return 0; }
 413 static inline int pgd_bad(pgd_t pgd)     { return 0; }
 414
 415 static inline int pud_present(pud_t pud) { return 1; }
 416 static inline int pud_none(pud_t pud)    { return 0; }
 417 static inline int pud_bad(pud_t pud)     { return 0; }
 418
 419 #else /* __s390x__ */
 420
 421 static inline int pgd_present(pgd_t pgd) { return 1; }
 422 static inline int pgd_none(pgd_t pgd)    { return 0; }
 423 static inline int pgd_bad(pgd_t pgd)     { return 0; }
 424
 425 static inline int pud_present(pud_t pud)
 426 {
 427         return (pud_val(pud) & _REGION_ENTRY_ORIGIN) != 0UL;
 428 }
 429
 430 static inline int pud_none(pud_t pud)
 431 {
 432         return (pud_val(pud) & _REGION_ENTRY_INV) != 0UL;
 433 }
 434
 435 static inline int pud_bad(pud_t pud)
 436 {
 437         unsigned long mask = ~_REGION_ENTRY_ORIGIN & ~_REGION_ENTRY_INV;
 438         return (pud_val(pud) & mask) != _REGION3_ENTRY;
 439 }
 440
 441 #endif /* __s390x__ */
 442
 443 static inline int pmd_present(pmd_t pmd)
 444 {
 445         return (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN) != 0UL;
 446 }
 447
 448 static inline int pmd_none(pmd_t pmd)
 449 {
 450         return (pmd_val(pmd) & _SEGMENT_ENTRY_INV) != 0UL;
 451 }
 452
 453 static inline int pmd_bad(pmd_t pmd)
 454 {
 455         unsigned long mask = ~_SEGMENT_ENTRY_ORIGIN & ~_SEGMENT_ENTRY_INV;
 456         return (pmd_val(pmd) & mask) != _SEGMENT_ENTRY;
 457 }
 458
 459 static inline int pte_none(pte_t pte)
 460 {
 461         return (pte_val(pte) & _PAGE_INVALID) && !(pte_val(pte) & _PAGE_SWT);
 462 }
 463
 464 static inline int pte_present(pte_t pte)
 465 {
 466         unsigned long mask = _PAGE_RO | _PAGE_INVALID | _PAGE_SWT | _PAGE_SWX;
 467         return (pte_val(pte) & mask) == _PAGE_TYPE_NONE ||
 468                 (!(pte_val(pte) & _PAGE_INVALID) &&
 469                  !(pte_val(pte) & _PAGE_SWT));
 470 }
 471
 472 static inline int pte_file(pte_t pte)
 473 {
 474         unsigned long mask = _PAGE_RO | _PAGE_INVALID | _PAGE_SWT;
 475         return (pte_val(pte) & mask) == _PAGE_TYPE_FILE;
 476 }
 477
 478 #define __HAVE_ARCH_PTE_SAME
 479 #define pte_same(a,b)  (pte_val(a) == pte_val(b))
 480
 481 /*
 482  * query functions pte_write/pte_dirty/pte_young only work if
 483  * pte_present() is true. Undefined behaviour if not..
 484  */
 485 static inline int pte_write(pte_t pte)
 486 {
 487         return (pte_val(pte) & _PAGE_RO) == 0;
 488 }
 489
 490 static inline int pte_dirty(pte_t pte)
 491 {
 492         /* A pte is neither clean nor dirty on s/390. The dirty bit
 493          * is in the storage key. See page_test_and_clear_dirty for
 494          * details.
 495          */
 496         return 0;
 497 }
 498
 499 static inline int pte_young(pte_t pte)
 500 {
 501         /* A pte is neither young nor old on s/390. The young bit
 502          * is in the storage key. See page_test_and_clear_young for
 503          * details.
 504          */
 505         return 0;
 506 }
 507
 508 /*
 509  * pgd/pmd/pte modification functions
 510  */
 511
 512 #ifndef __s390x__
 513
 514 #define pgd_clear(pgd)          do { } while (0)
 515 #define pud_clear(pud)          do { } while (0)
 516
 517 #else /* __s390x__ */
 518
 519 #define pgd_clear(pgd)          do { } while (0)
 520
 521 static inline void pud_clear_kernel(pud_t *pud)
 522 {
 523         pud_val(*pud) = _REGION3_ENTRY_EMPTY;
 524 }
 525
 526 static inline void pud_clear(pud_t * pud)
 527 {
 528         pud_t *shadow = get_shadow_table(pud);
 529
 530         pud_clear_kernel(pud);
 531         if (shadow)
 532                 pud_clear_kernel(shadow);
 533 }
 534
 535 #endif /* __s390x__ */
 536
 537 static inline void pmd_clear_kernel(pmd_t * pmdp)
 538 {
 539         pmd_val(*pmdp) = _SEGMENT_ENTRY_EMPTY;
 540 }
 541
 542 static inline void pmd_clear(pmd_t *pmd)
 543 {
 544         pmd_t *shadow = get_shadow_table(pmd);
 545
 546         pmd_clear_kernel(pmd);
 547         if (shadow)
 548                 pmd_clear_kernel(shadow);
 549 }
 550
 551 static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
 552 {
 553         pte_val(*ptep) = _PAGE_TYPE_EMPTY;
 554         if (mm->context.noexec)
 555                 pte_val(ptep[PTRS_PER_PTE]) = _PAGE_TYPE_EMPTY;
 556 }
 557
 558 /*
 559  * The following pte modification functions only work if
 560  * pte_present() is true. Undefined behaviour if not..
 561  */
 562 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 563 {
 564         pte_val(pte) &= PAGE_MASK;
 565         pte_val(pte) |= pgprot_val(newprot);
 566         return pte;
 567 }
 568
 569 static inline pte_t pte_wrprotect(pte_t pte)
 570 {
 571         /* Do not clobber _PAGE_TYPE_NONE pages!  */
 572         if (!(pte_val(pte) & _PAGE_INVALID))
 573                 pte_val(pte) |= _PAGE_RO;
 574         return pte;
 575 }
 576
 577 static inline pte_t pte_mkwrite(pte_t pte)
 578 {
 579         pte_val(pte) &= ~_PAGE_RO;
 580         return pte;
 581 }
 582
 583 static inline pte_t pte_mkclean(pte_t pte)
 584 {
 585         /* The only user of pte_mkclean is the fork() code.
 586            We must *not* clear the *physical* page dirty bit
 587            just because fork() wants to clear the dirty bit in
 588            *one* of the page's mappings.  So we just do nothing. */
 589         return pte;
 590 }
 591
 592 static inline pte_t pte_mkdirty(pte_t pte)
 593 {
 594         /* We do not explicitly set the dirty bit because the
 595          * sske instruction is slow. It is faster to let the
 596          * next instruction set the dirty bit.
 597          */
 598         return pte;
 599 }
 600
 601 static inline pte_t pte_mkold(pte_t pte)
 602 {
 603         /* S/390 doesn't keep its dirty/referenced bit in the pte.
 604          * There is no point in clearing the real referenced bit.
 605          */
 606         return pte;
 607 }
 608
 609 static inline pte_t pte_mkyoung(pte_t pte)
 610 {
 611         /* S/390 doesn't keep its dirty/referenced bit in the pte.
 612          * There is no point in setting the real referenced bit.
 613          */
 614         return pte;
 615 }
 616
 617 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
 618 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
 619                                             unsigned long addr, pte_t *ptep)
 620 {
 621         return 0;
 622 }
 623
 624 #define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
 625 static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
 626                                          unsigned long address, pte_t *ptep)
 627 {
 628         /* No need to flush TLB; bits are in storage key */
 629         return 0;
 630 }
 631
 632 static inline void __ptep_ipte(unsigned long address, pte_t *ptep)
 633 {
 634         if (!(pte_val(*ptep) & _PAGE_INVALID)) {
 635 #ifndef __s390x__
 636                 /* pto must point to the start of the segment table */
 637                 pte_t *pto = (pte_t *) (((unsigned long) ptep) & 0x7ffffc00);
 638 #else
 639                 /* ipte in zarch mode can do the math */
 640                 pte_t *pto = ptep;
 641 #endif
 642                 asm volatile(
 643                         "       ipte    %2,%3"
 644                         : "=m" (*ptep) : "m" (*ptep),
 645                           "a" (pto), "a" (address));
 646         }
 647         pte_val(*ptep) = _PAGE_TYPE_EMPTY;
 648 }
 649
 650 static inline void ptep_invalidate(struct mm_struct *mm,
 651                                    unsigned long address, pte_t *ptep)
 652 {
 653         __ptep_ipte(address, ptep);
 654         if (mm->context.noexec)
 655                 __ptep_ipte(address, ptep + PTRS_PER_PTE);
 656 }
 657
 658 /*
 659  * This is hard to understand. ptep_get_and_clear and ptep_clear_flush
 660  * both clear the TLB for the unmapped pte. The reason is that
 661  * ptep_get_and_clear is used in common code (e.g. change_pte_range)
 662  * to modify an active pte. The sequence is
 663  *   1) ptep_get_and_clear
 664  *   2) set_pte_at
 665  *   3) flush_tlb_range
 666  * On s390 the tlb needs to get flushed with the modification of the pte
 667  * if the pte is active. The only way how this can be implemented is to
 668  * have ptep_get_and_clear do the tlb flush. In exchange flush_tlb_range
 669  * is a nop.
 670  */
 671 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
 672 #define ptep_get_and_clear(__mm, __address, __ptep)                     \
 673 ({                                                                      \
 674         pte_t __pte = *(__ptep);                                        \
 675         if (atomic_read(&(__mm)->mm_users) > 1 ||                       \
 676             (__mm) != current->active_mm)                               \
 677                 ptep_invalidate(__mm, __address, __ptep);               \
 678         else                                                            \
 679                 pte_clear((__mm), (__address), (__ptep));               \
 680         __pte;                                                          \
 681 })
 682
 683 #define __HAVE_ARCH_PTEP_CLEAR_FLUSH
 684 static inline pte_t ptep_clear_flush(struct vm_area_struct *vma,
 685                                      unsigned long address, pte_t *ptep)
 686 {
 687         pte_t pte = *ptep;
 688         ptep_invalidate(vma->vm_mm, address, ptep);
 689         return pte;
 690 }
 691
 692 /*
 693  * The batched pte unmap code uses ptep_get_and_clear_full to clear the
 694  * ptes. Here an optimization is possible. tlb_gather_mmu flushes all
 695  * tlbs of an mm if it can guarantee that the ptes of the mm_struct
 696  * cannot be accessed while the batched unmap is running. In this case
 697  * full==1 and a simple pte_clear is enough. See tlb.h.
 698  */
 699 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL
 700 static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm,
 701                                             unsigned long addr,
 702                                             pte_t *ptep, int full)
 703 {
 704         pte_t pte = *ptep;
 705
 706         if (full)
 707                 pte_clear(mm, addr, ptep);
 708         else
 709                 ptep_invalidate(mm, addr, ptep);
 710         return pte;
 711 }
 712
 713 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
 714 #define ptep_set_wrprotect(__mm, __addr, __ptep)                        \
 715 ({                                                                      \
 716         pte_t __pte = *(__ptep);                                        \
 717         if (pte_write(__pte)) {                                         \
 718                 if (atomic_read(&(__mm)->mm_users) > 1 ||               \
 719                     (__mm) != current->active_mm)                       \
 720                         ptep_invalidate(__mm, __addr, __ptep);          \
 721                 set_pte_at(__mm, __addr, __ptep, pte_wrprotect(__pte)); \
 722         }                                                               \
 723 })
 724
 725 #define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
 726 #define ptep_set_access_flags(__vma, __addr, __ptep, __entry, __dirty)  \
 727 ({                                                                      \
 728         int __changed = !pte_same(*(__ptep), __entry);                  \
 729         if (__changed) {                                                \
 730                 ptep_invalidate((__vma)->vm_mm, __addr, __ptep);        \
 731                 set_pte_at((__vma)->vm_mm, __addr, __ptep, __entry);    \
 732         }                                                               \
 733         __changed;                                                      \
 734 })
 735
 736 /*
 737  * Test and clear dirty bit in storage key.
 738  * We can't clear the changed bit atomically. This is a potential
 739  * race against modification of the referenced bit. This function
 740  * should therefore only be called if it is not mapped in any
 741  * address space.
 742  */
 743 #define __HAVE_ARCH_PAGE_TEST_DIRTY
 744 static inline int page_test_dirty(struct page *page)
 745 {
 746         return (page_get_storage_key(page_to_phys(page)) & _PAGE_CHANGED) != 0;
 747 }
 748
 749 #define __HAVE_ARCH_PAGE_CLEAR_DIRTY
 750 static inline void page_clear_dirty(struct page *page)
 751 {
 752         page_set_storage_key(page_to_phys(page), PAGE_DEFAULT_KEY);
 753 }
 754
 755 /*
 756  * Test and clear referenced bit in storage key.
 757  */
 758 #define __HAVE_ARCH_PAGE_TEST_AND_CLEAR_YOUNG
 759 static inline int page_test_and_clear_young(struct page *page)
 760 {
 761         unsigned long physpage = page_to_phys(page);
 762         int ccode;
 763
 764         asm volatile(
 765                 "       rrbe    0,%1\n"
 766                 "       ipm     %0\n"
 767                 "       srl     %0,28\n"
 768                 : "=d" (ccode) : "a" (physpage) : "cc" );
 769         return ccode & 2;
 770 }
 771
 772 /*
 773  * Conversion functions: convert a page and protection to a page entry,
 774  * and a page entry and page directory to the page they refer to.
 775  */
 776 static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot)
 777 {
 778         pte_t __pte;
 779         pte_val(__pte) = physpage + pgprot_val(pgprot);
 780         return __pte;
 781 }
 782
 783 static inline pte_t mk_pte(struct page *page, pgprot_t pgprot)
 784 {
 785         unsigned long physpage = page_to_phys(page);
 786
 787         return mk_pte_phys(physpage, pgprot);
 788 }
 789
 790 #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
 791 #define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
 792 #define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
 793 #define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE-1))
 794
 795 #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address))
 796 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
 797
 798 #ifndef __s390x__
 799
 800 #define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN)
 801 #define pud_deref(pmd) ({ BUG(); 0UL; })
 802 #define pgd_deref(pmd) ({ BUG(); 0UL; })
 803
 804 #define pud_offset(pgd, address) ((pud_t *) pgd)
 805 #define pmd_offset(pud, address) ((pmd_t *) pud + pmd_index(address))
 806
 807 #else /* __s390x__ */
 808
 809 #define pmd_deref(pmd) (pmd_val(pmd) & _SEGMENT_ENTRY_ORIGIN)
 810 #define pud_deref(pud) (pud_val(pud) & _REGION_ENTRY_ORIGIN)
 811 #define pgd_deref(pgd) ({ BUG(); 0UL; })
 812
 813 #define pud_offset(pgd, address) ((pud_t *) pgd)
 814
 815 static inline pmd_t *pmd_offset(pud_t *pud, unsigned long address)
 816 {
 817         pmd_t *pmd = (pmd_t *) pud_deref(*pud);
 818         return pmd + pmd_index(address);
 819 }
 820
 821 #endif /* __s390x__ */
 822
 823 #define pfn_pte(pfn,pgprot) mk_pte_phys(__pa((pfn) << PAGE_SHIFT),(pgprot))
 824 #define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT)
 825 #define pte_page(x) pfn_to_page(pte_pfn(x))
 826
 827 #define pmd_page(pmd) pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT)
 828
 829 /* Find an entry in the lowest level page table.. */
 830 #define pte_offset(pmd, addr) ((pte_t *) pmd_deref(*(pmd)) + pte_index(addr))
 831 #define pte_offset_kernel(pmd, address) pte_offset(pmd,address)
 832 #define pte_offset_map(pmd, address) pte_offset_kernel(pmd, address)
 833 #define pte_offset_map_nested(pmd, address) pte_offset_kernel(pmd, address)
 834 #define pte_unmap(pte) do { } while (0)
 835 #define pte_unmap_nested(pte) do { } while (0)
 836
 837 /*
 838  * 31 bit swap entry format:
 839  * A page-table entry has some bits we have to treat in a special way.
 840  * Bits 0, 20 and bit 23 have to be zero, otherwise an specification
 841  * exception will occur instead of a page translation exception. The
 842  * specifiation exception has the bad habit not to store necessary
 843  * information in the lowcore.
 844  * Bit 21 and bit 22 are the page invalid bit and the page protection
 845  * bit. We set both to indicate a swapped page.
 846  * Bit 30 and 31 are used to distinguish the different page types. For
 847  * a swapped page these bits need to be zero.
 848  * This leaves the bits 1-19 and bits 24-29 to store type and offset.
 849  * We use the 5 bits from 25-29 for the type and the 20 bits from 1-19
 850  * plus 24 for the offset.
 851  * 0|     offset        |0110|o|type |00|
 852  * 0 0000000001111111111 2222 2 22222 33
 853  * 0 1234567890123456789 0123 4 56789 01
 854  *
 855  * 64 bit swap entry format:
 856  * A page-table entry has some bits we have to treat in a special way.
 857  * Bits 52 and bit 55 have to be zero, otherwise an specification
 858  * exception will occur instead of a page translation exception. The
 859  * specifiation exception has the bad habit not to store necessary
 860  * information in the lowcore.
 861  * Bit 53 and bit 54 are the page invalid bit and the page protection
 862  * bit. We set both to indicate a swapped page.
 863  * Bit 62 and 63 are used to distinguish the different page types. For
 864  * a swapped page these bits need to be zero.
 865  * This leaves the bits 0-51 and bits 56-61 to store type and offset.
 866  * We use the 5 bits from 57-61 for the type and the 53 bits from 0-51
 867  * plus 56 for the offset.
 868  * |                      offset                        |0110|o|type |00|
 869  *  0000000000111111111122222222223333333333444444444455 5555 5 55566 66
 870  *  0123456789012345678901234567890123456789012345678901 2345 6 78901 23
 871  */
 872 #ifndef __s390x__
 873 #define __SWP_OFFSET_MASK (~0UL >> 12)
 874 #else
 875 #define __SWP_OFFSET_MASK (~0UL >> 11)
 876 #endif
 877 static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset)
 878 {
 879         pte_t pte;
 880         offset &= __SWP_OFFSET_MASK;
 881         pte_val(pte) = _PAGE_TYPE_SWAP | ((type & 0x1f) << 2) |
 882                 ((offset & 1UL) << 7) | ((offset & ~1UL) << 11);
 883         return pte;
 884 }
 885
 886 #define __swp_type(entry)       (((entry).val >> 2) & 0x1f)
 887 #define __swp_offset(entry)     (((entry).val >> 11) | (((entry).val >> 7) & 1))
 888 #define __swp_entry(type,offset) ((swp_entry_t) { pte_val(mk_swap_pte((type),(offset))) })
 889
 890 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
 891 #define __swp_entry_to_pte(x)   ((pte_t) { (x).val })
 892
 893 #ifndef __s390x__
 894 # define PTE_FILE_MAX_BITS      26
 895 #else /* __s390x__ */
 896 # define PTE_FILE_MAX_BITS      59
 897 #endif /* __s390x__ */
 898
 899 #define pte_to_pgoff(__pte) \
 900         ((((__pte).pte >> 12) << 7) + (((__pte).pte >> 1) & 0x7f))
 901
 902 #define pgoff_to_pte(__off) \
 903         ((pte_t) { ((((__off) & 0x7f) << 1) + (((__off) >> 7) << 12)) \
 904                    | _PAGE_TYPE_FILE })
 905
 906 #endif /* !__ASSEMBLY__ */
 907
 908 #define kern_addr_valid(addr)   (1)
 909
 910 extern int add_shared_memory(unsigned long start, unsigned long size);
 911 extern int remove_shared_memory(unsigned long start, unsigned long size);
 912
 913 /*
 914  * No page table caches to initialise
 915  */
 916 #define pgtable_cache_init()    do { } while (0)
 917
 918 #define __HAVE_ARCH_MEMMAP_INIT
 919 extern void memmap_init(unsigned long, int, unsigned long, unsigned long);
 920
 921 #include <asm-generic/pgtable.h>
 922
 923 #endif /* _S390_PAGE_H */