1 /* arch/arm/mach-s3c2410/pll.c
3 * Copyright (c) 2006-2007 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 * Vincent Sanders <vince@arm.linux.org.uk>
8 * S3C2410 CPU PLL tables
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 #include <linux/types.h>
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/device.h>
29 #include <linux/list.h>
30 #include <linux/clk.h>
31 #include <linux/err.h>
34 #include <plat/cpu-freq-core.h>
36 static struct cpufreq_frequency_table pll_vals_12MHz
[] = {
37 { .frequency
= 34000000, .index
= PLLVAL(82, 2, 3), },
38 { .frequency
= 45000000, .index
= PLLVAL(82, 1, 3), },
39 { .frequency
= 51000000, .index
= PLLVAL(161, 3, 3), },
40 { .frequency
= 48000000, .index
= PLLVAL(120, 2, 3), },
41 { .frequency
= 56000000, .index
= PLLVAL(142, 2, 3), },
42 { .frequency
= 68000000, .index
= PLLVAL(82, 2, 2), },
43 { .frequency
= 79000000, .index
= PLLVAL(71, 1, 2), },
44 { .frequency
= 85000000, .index
= PLLVAL(105, 2, 2), },
45 { .frequency
= 90000000, .index
= PLLVAL(112, 2, 2), },
46 { .frequency
= 101000000, .index
= PLLVAL(127, 2, 2), },
47 { .frequency
= 113000000, .index
= PLLVAL(105, 1, 2), },
48 { .frequency
= 118000000, .index
= PLLVAL(150, 2, 2), },
49 { .frequency
= 124000000, .index
= PLLVAL(116, 1, 2), },
50 { .frequency
= 135000000, .index
= PLLVAL(82, 2, 1), },
51 { .frequency
= 147000000, .index
= PLLVAL(90, 2, 1), },
52 { .frequency
= 152000000, .index
= PLLVAL(68, 1, 1), },
53 { .frequency
= 158000000, .index
= PLLVAL(71, 1, 1), },
54 { .frequency
= 170000000, .index
= PLLVAL(77, 1, 1), },
55 { .frequency
= 180000000, .index
= PLLVAL(82, 1, 1), },
56 { .frequency
= 186000000, .index
= PLLVAL(85, 1, 1), },
57 { .frequency
= 192000000, .index
= PLLVAL(88, 1, 1), },
58 { .frequency
= 203000000, .index
= PLLVAL(161, 3, 1), },
62 { .frequency
= 210000000, .index
= PLLVAL(132, 2, 1), },
63 { .frequency
= 226000000, .index
= PLLVAL(105, 1, 1), },
64 { .frequency
= 266000000, .index
= PLLVAL(125, 1, 1), },
65 { .frequency
= 268000000, .index
= PLLVAL(126, 1, 1), },
66 { .frequency
= 270000000, .index
= PLLVAL(127, 1, 1), },
69 static int s3c2410_plls_add(struct device
*dev
, struct subsys_interface
*sif
)
71 return s3c_plltab_register(pll_vals_12MHz
, ARRAY_SIZE(pll_vals_12MHz
));
74 static struct subsys_interface s3c2410_plls_interface
= {
75 .name
= "s3c2410_plls",
76 .subsys
= &s3c2410_subsys
,
77 .add_dev
= s3c2410_plls_add
,
80 static int __init
s3c2410_pll_init(void)
82 return subsys_interface_register(&s3c2410_plls_interface
);
86 arch_initcall(s3c2410_pll_init
);
88 static struct subsys_interface s3c2410a_plls_interface
= {
89 .name
= "s3c2410a_plls",
90 .subsys
= &s3c2410a_subsys
,
91 .add_dev
= s3c2410_plls_add
,
94 static int __init
s3c2410a_pll_init(void)
96 return subsys_interface_register(&s3c2410a_plls_interface
);
99 arch_initcall(s3c2410a_pll_init
);