arch/arm/mach-lpc32xx/common.c

   1 /*
   2  * arch/arm/mach-lpc32xx/common.c
   3  *
   4  * Author: Kevin Wells <kevin.wells@nxp.com>
   5  *
   6  * Copyright (C) 2010 NXP Semiconductors
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/init.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/irq.h>
  23 #include <linux/err.h>
  24 #include <linux/i2c.h>
  25 #include <linux/i2c-pnx.h>
  26 #include <linux/io.h>
  27
  28 #include <asm/mach/map.h>
  29
  30 #include <mach/hardware.h>
  31 #include <mach/platform.h>
  32 #include "common.h"
  33
  34 /*
  35  * Returns the unique ID for the device
  36  */
  37 void lpc32xx_get_uid(u32 devid[4])
  38 {
  39         int i;
  40
  41         for (i = 0; i < 4; i++)
  42                 devid[i] = __raw_readl(LPC32XX_CLKPWR_DEVID(i << 2));
  43 }
  44
  45 /*
  46  * Returns SYSCLK source
  47  * 0 = PLL397, 1 = main oscillator
  48  */
  49 int clk_is_sysclk_mainosc(void)
  50 {
  51         if ((__raw_readl(LPC32XX_CLKPWR_SYSCLK_CTRL) &
  52                 LPC32XX_CLKPWR_SYSCTRL_SYSCLKMUX) == 0)
  53                 return 1;
  54
  55         return 0;
  56 }
  57
  58 /*
  59  * System reset via the watchdog timer
  60  */
  61 static void lpc32xx_watchdog_reset(void)
  62 {
  63         /* Make sure WDT clocks are enabled */
  64         __raw_writel(LPC32XX_CLKPWR_PWMCLK_WDOG_EN,
  65                 LPC32XX_CLKPWR_TIMER_CLK_CTRL);
  66
  67         /* Instant assert of RESETOUT_N with pulse length 1mS */
  68         __raw_writel(13000, io_p2v(LPC32XX_WDTIM_BASE + 0x18));
  69         __raw_writel(0x70, io_p2v(LPC32XX_WDTIM_BASE + 0xC));
  70 }
  71
  72 /*
  73  * Detects and returns IRAM size for the device variation
  74  */
  75 #define LPC32XX_IRAM_BANK_SIZE SZ_128K
  76 static u32 iram_size;
  77 u32 lpc32xx_return_iram_size(void)
  78 {
  79         if (iram_size == 0) {
  80                 u32 savedval1, savedval2;
  81                 void __iomem *iramptr1, *iramptr2;
  82
  83                 iramptr1 = io_p2v(LPC32XX_IRAM_BASE);
  84                 iramptr2 = io_p2v(LPC32XX_IRAM_BASE + LPC32XX_IRAM_BANK_SIZE);
  85                 savedval1 = __raw_readl(iramptr1);
  86                 savedval2 = __raw_readl(iramptr2);
  87
  88                 if (savedval1 == savedval2) {
  89                         __raw_writel(savedval2 + 1, iramptr2);
  90                         if (__raw_readl(iramptr1) == savedval2 + 1)
  91                                 iram_size = LPC32XX_IRAM_BANK_SIZE;
  92                         else
  93                                 iram_size = LPC32XX_IRAM_BANK_SIZE * 2;
  94                         __raw_writel(savedval2, iramptr2);
  95                 } else
  96                         iram_size = LPC32XX_IRAM_BANK_SIZE * 2;
  97         }
  98
  99         return iram_size;
 100 }
 101
 102 /*
 103  * Computes PLL rate from PLL register and input clock
 104  */
 105 u32 clk_check_pll_setup(u32 ifreq, struct clk_pll_setup *pllsetup)
 106 {
 107         u32 ilfreq, p, m, n, fcco, fref, cfreq;
 108         int mode;
 109
 110         /*
 111          * PLL requirements
 112          * ifreq must be >= 1MHz and <= 20MHz
 113          * FCCO must be >= 156MHz and <= 320MHz
 114          * FREF must be >= 1MHz and <= 27MHz
 115          * Assume the passed input data is not valid
 116          */
 117
 118         ilfreq = ifreq;
 119         m = pllsetup->pll_m;
 120         n = pllsetup->pll_n;
 121         p = pllsetup->pll_p;
 122
 123         mode = (pllsetup->cco_bypass_b15 << 2) |
 124                 (pllsetup->direct_output_b14 << 1) |
 125         pllsetup->fdbk_div_ctrl_b13;
 126
 127         switch (mode) {
 128         case 0x0: /* Non-integer mode */
 129                 cfreq = (m * ilfreq) / (2 * p * n);
 130                 fcco = (m * ilfreq) / n;
 131                 fref = ilfreq / n;
 132                 break;
 133
 134         case 0x1: /* integer mode */
 135                 cfreq = (m * ilfreq) / n;
 136                 fcco = (m * ilfreq) / (n * 2 * p);
 137                 fref = ilfreq / n;
 138                 break;
 139
 140         case 0x2:
 141         case 0x3: /* Direct mode */
 142                 cfreq = (m * ilfreq) / n;
 143                 fcco = cfreq;
 144                 fref = ilfreq / n;
 145                 break;
 146
 147         case 0x4:
 148         case 0x5: /* Bypass mode */
 149                 cfreq = ilfreq / (2 * p);
 150                 fcco = 156000000;
 151                 fref = 1000000;
 152                 break;
 153
 154         case 0x6:
 155         case 0x7: /* Direct bypass mode */
 156         default:
 157                 cfreq = ilfreq;
 158                 fcco = 156000000;
 159                 fref = 1000000;
 160                 break;
 161         }
 162
 163         if (fcco < 156000000 || fcco > 320000000)
 164                 cfreq = 0;
 165
 166         if (fref < 1000000 || fref > 27000000)
 167                 cfreq = 0;
 168
 169         return (u32) cfreq;
 170 }
 171
 172 u32 clk_get_pclk_div(void)
 173 {
 174         return 1 + ((__raw_readl(LPC32XX_CLKPWR_HCLK_DIV) >> 2) & 0x1F);
 175 }
 176
 177 static struct map_desc lpc32xx_io_desc[] __initdata = {
 178         {
 179                 .virtual        = IO_ADDRESS(LPC32XX_AHB0_START),
 180                 .pfn            = __phys_to_pfn(LPC32XX_AHB0_START),
 181                 .length         = LPC32XX_AHB0_SIZE,
 182                 .type           = MT_DEVICE
 183         },
 184         {
 185                 .virtual        = IO_ADDRESS(LPC32XX_AHB1_START),
 186                 .pfn            = __phys_to_pfn(LPC32XX_AHB1_START),
 187                 .length         = LPC32XX_AHB1_SIZE,
 188                 .type           = MT_DEVICE
 189         },
 190         {
 191                 .virtual        = IO_ADDRESS(LPC32XX_FABAPB_START),
 192                 .pfn            = __phys_to_pfn(LPC32XX_FABAPB_START),
 193                 .length         = LPC32XX_FABAPB_SIZE,
 194                 .type           = MT_DEVICE
 195         },
 196         {
 197                 .virtual        = IO_ADDRESS(LPC32XX_IRAM_BASE),
 198                 .pfn            = __phys_to_pfn(LPC32XX_IRAM_BASE),
 199                 .length         = (LPC32XX_IRAM_BANK_SIZE * 2),
 200                 .type           = MT_DEVICE
 201         },
 202 };
 203
 204 void __init lpc32xx_map_io(void)
 205 {
 206         iotable_init(lpc32xx_io_desc, ARRAY_SIZE(lpc32xx_io_desc));
 207 }
 208
 209 void lpc23xx_restart(char mode, const char *cmd)
 210 {
 211         switch (mode) {
 212         case 's':
 213         case 'h':
 214                 lpc32xx_watchdog_reset();
 215                 break;
 216
 217         default:
 218                 /* Do nothing */
 219                 break;
 220         }
 221
 222         /* Wait for watchdog to reset system */
 223         while (1)
 224                 ;
 225 }
 226
 227 static int __init lpc32xx_display_uid(void)
 228 {
 229         u32 uid[4];
 230
 231         lpc32xx_get_uid(uid);
 232
 233         printk(KERN_INFO "LPC32XX unique ID: %08x%08x%08x%08x\n",
 234                 uid[3], uid[2], uid[1], uid[0]);
 235
 236         return 1;
 237 }
 238 arch_initcall(lpc32xx_display_uid);