2 * arch/arm/mach-lpc32xx/clock.c
4 * Author: Kevin Wells <kevin.wells@nxp.com>
6 * Copyright (C) 2010 NXP Semiconductors
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
20 * LPC32xx clock management driver overview
22 * The LPC32XX contains a number of high level system clocks that can be
23 * generated from different sources. These system clocks are used to
24 * generate the CPU and bus rates and the individual peripheral clocks in
25 * the system. When Linux is started by the boot loader, the system
26 * clocks are already running. Stopping a system clock during normal
27 * Linux operation should never be attempted, as peripherals that require
28 * those clocks will quit working (ie, DRAM).
30 * The LPC32xx high level clock tree looks as follows. Clocks marked with
31 * an asterisk are always on and cannot be disabled. Clocks marked with
32 * an ampersand can only be disabled in CPU suspend mode. Clocks marked
33 * with a caret are always on if it is the selected clock for the SYSCLK
34 * source. The clock that isn't used for SYSCLK can be enabled and
47 * USB host/device PCLK& |
51 * The CPU and chip bus rates are derived from the HCLK PLL, which can
52 * generate various clock rates up to 266MHz and beyond. The internal bus
53 * rates (PCLK and HCLK) are generated from dividers based on the HCLK
54 * PLL rate. HCLK can be a ratio of 1:1, 1:2, or 1:4 or HCLK PLL rate,
55 * while PCLK can be 1:1 to 1:32 of HCLK PLL rate. Most peripherals high
56 * level clocks are based on either HCLK or PCLK, but have their own
57 * dividers as part of the IP itself. Because of this, the system clock
58 * rates should not be changed.
60 * The HCLK PLL is clocked from SYSCLK, which can be derived from the
61 * main oscillator or PLL397. PLL397 generates a rate that is 397 times
62 * the 32KHz oscillator rate. The main oscillator runs at the selected
63 * oscillator/crystal rate on the mosc_in pin of the LPC32xx. This rate
64 * is normally 13MHz, but depends on the selection of external crystals
65 * or oscillators. If USB operation is required, the main oscillator must
66 * be used in the system.
68 * Switching SYSCLK between sources during normal Linux operation is not
69 * supported. SYSCLK is preset in the bootloader. Because of the
70 * complexities of clock management during clock frequency changes,
71 * there are some limitations to the clock driver explained below:
72 * - The PLL397 and main oscillator can be enabled and disabled by the
73 * clk_enable() and clk_disable() functions unless SYSCLK is based
74 * on that clock. This allows the other oscillator that isn't driving
75 * the HCLK PLL to be used as another system clock that can be routed
77 * - The muxed SYSCLK input and HCLK_PLL rate cannot be changed with
79 * - HCLK and PCLK rates cannot be changed as part of this driver.
80 * - Most peripherals have their own dividers are part of the peripheral
81 * block. Changing SYSCLK, HCLK PLL, HCLK, or PCLK sources or rates
82 * will also impact the individual peripheral rates.
85 #include <linux/export.h>
86 #include <linux/kernel.h>
87 #include <linux/list.h>
88 #include <linux/errno.h>
89 #include <linux/device.h>
90 #include <linux/delay.h>
91 #include <linux/err.h>
92 #include <linux/clk.h>
93 #include <linux/amba/bus.h>
94 #include <linux/amba/clcd.h>
95 #include <linux/clkdev.h>
97 #include <mach/hardware.h>
98 #include <mach/platform.h>
102 static DEFINE_SPINLOCK(global_clkregs_lock
);
104 static int usb_pll_enable
, usb_pll_valid
;
106 static struct clk clk_armpll
;
107 static struct clk clk_usbpll
;
110 * Post divider values for PLLs based on selected register value
112 static const u32 pll_postdivs
[4] = {1, 2, 4, 8};
114 static unsigned long local_return_parent_rate(struct clk
*clk
)
117 * If a clock has a rate of 0, then it inherits it's parent
120 while (clk
->rate
== 0)
126 /* 32KHz clock has a fixed rate and is not stoppable */
127 static struct clk osc_32KHz
= {
128 .rate
= LPC32XX_CLOCK_OSC_FREQ
,
129 .get_rate
= local_return_parent_rate
,
132 static int local_pll397_enable(struct clk
*clk
, int enable
)
135 unsigned long timeout
= jiffies
+ msecs_to_jiffies(10);
137 reg
= __raw_readl(LPC32XX_CLKPWR_PLL397_CTRL
);
140 reg
|= LPC32XX_CLKPWR_SYSCTRL_PLL397_DIS
;
141 __raw_writel(reg
, LPC32XX_CLKPWR_PLL397_CTRL
);
144 reg
&= ~LPC32XX_CLKPWR_SYSCTRL_PLL397_DIS
;
145 __raw_writel(reg
, LPC32XX_CLKPWR_PLL397_CTRL
);
147 /* Wait for PLL397 lock */
148 while (((__raw_readl(LPC32XX_CLKPWR_PLL397_CTRL
) &
149 LPC32XX_CLKPWR_SYSCTRL_PLL397_STS
) == 0) &&
150 time_before(jiffies
, timeout
))
153 if ((__raw_readl(LPC32XX_CLKPWR_PLL397_CTRL
) &
154 LPC32XX_CLKPWR_SYSCTRL_PLL397_STS
) == 0)
161 static int local_oscmain_enable(struct clk
*clk
, int enable
)
164 unsigned long timeout
= jiffies
+ msecs_to_jiffies(10);
166 reg
= __raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL
);
169 reg
|= LPC32XX_CLKPWR_MOSC_DISABLE
;
170 __raw_writel(reg
, LPC32XX_CLKPWR_MAIN_OSC_CTRL
);
172 /* Enable main oscillator */
173 reg
&= ~LPC32XX_CLKPWR_MOSC_DISABLE
;
174 __raw_writel(reg
, LPC32XX_CLKPWR_MAIN_OSC_CTRL
);
176 /* Wait for main oscillator to start */
177 while (((__raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL
) &
178 LPC32XX_CLKPWR_MOSC_DISABLE
) != 0) &&
179 time_before(jiffies
, timeout
))
182 if ((__raw_readl(LPC32XX_CLKPWR_MAIN_OSC_CTRL
) &
183 LPC32XX_CLKPWR_MOSC_DISABLE
) != 0)
190 static struct clk osc_pll397
= {
191 .parent
= &osc_32KHz
,
192 .enable
= local_pll397_enable
,
193 .rate
= LPC32XX_CLOCK_OSC_FREQ
* 397,
194 .get_rate
= local_return_parent_rate
,
197 static struct clk osc_main
= {
198 .enable
= local_oscmain_enable
,
199 .rate
= LPC32XX_MAIN_OSC_FREQ
,
200 .get_rate
= local_return_parent_rate
,
203 static struct clk clk_sys
;
206 * Convert a PLL register value to a PLL output frequency
208 u32
clk_get_pllrate_from_reg(u32 inputclk
, u32 regval
)
210 struct clk_pll_setup pllcfg
;
212 pllcfg
.cco_bypass_b15
= 0;
213 pllcfg
.direct_output_b14
= 0;
214 pllcfg
.fdbk_div_ctrl_b13
= 0;
215 if ((regval
& LPC32XX_CLKPWR_HCLKPLL_CCO_BYPASS
) != 0)
216 pllcfg
.cco_bypass_b15
= 1;
217 if ((regval
& LPC32XX_CLKPWR_HCLKPLL_POSTDIV_BYPASS
) != 0)
218 pllcfg
.direct_output_b14
= 1;
219 if ((regval
& LPC32XX_CLKPWR_HCLKPLL_FDBK_SEL_FCLK
) != 0)
220 pllcfg
.fdbk_div_ctrl_b13
= 1;
221 pllcfg
.pll_m
= 1 + ((regval
>> 1) & 0xFF);
222 pllcfg
.pll_n
= 1 + ((regval
>> 9) & 0x3);
223 pllcfg
.pll_p
= pll_postdivs
[((regval
>> 11) & 0x3)];
225 return clk_check_pll_setup(inputclk
, &pllcfg
);
229 * Setup the HCLK PLL with a PLL structure
231 static u32
local_clk_pll_setup(struct clk_pll_setup
*PllSetup
)
235 if (PllSetup
->analog_on
!= 0)
236 tmp
|= LPC32XX_CLKPWR_HCLKPLL_POWER_UP
;
237 if (PllSetup
->cco_bypass_b15
!= 0)
238 tmp
|= LPC32XX_CLKPWR_HCLKPLL_CCO_BYPASS
;
239 if (PllSetup
->direct_output_b14
!= 0)
240 tmp
|= LPC32XX_CLKPWR_HCLKPLL_POSTDIV_BYPASS
;
241 if (PllSetup
->fdbk_div_ctrl_b13
!= 0)
242 tmp
|= LPC32XX_CLKPWR_HCLKPLL_FDBK_SEL_FCLK
;
244 tv
= ffs(PllSetup
->pll_p
) - 1;
245 if ((!is_power_of_2(PllSetup
->pll_p
)) || (tv
> 3))
248 tmp
|= LPC32XX_CLKPWR_HCLKPLL_POSTDIV_2POW(tv
);
249 tmp
|= LPC32XX_CLKPWR_HCLKPLL_PREDIV_PLUS1(PllSetup
->pll_n
- 1);
250 tmp
|= LPC32XX_CLKPWR_HCLKPLL_PLLM(PllSetup
->pll_m
- 1);
256 * Update the ARM core PLL frequency rate variable from the actual PLL setting
258 static void local_update_armpll_rate(void)
262 clkin
= clk_armpll
.parent
->rate
;
263 pllreg
= __raw_readl(LPC32XX_CLKPWR_HCLKPLL_CTRL
) & 0x1FFFF;
265 clk_armpll
.rate
= clk_get_pllrate_from_reg(clkin
, pllreg
);
269 * Find a PLL configuration for the selected input frequency
271 static u32
local_clk_find_pll_cfg(u32 pllin_freq
, u32 target_freq
,
272 struct clk_pll_setup
*pllsetup
)
274 u32 ifreq
, freqtol
, m
, n
, p
, fclkout
;
276 /* Determine frequency tolerance limits */
277 freqtol
= target_freq
/ 250;
280 /* Is direct bypass mode possible? */
281 if (abs(pllin_freq
- target_freq
) <= freqtol
) {
282 pllsetup
->analog_on
= 0;
283 pllsetup
->cco_bypass_b15
= 1;
284 pllsetup
->direct_output_b14
= 1;
285 pllsetup
->fdbk_div_ctrl_b13
= 1;
286 pllsetup
->pll_p
= pll_postdivs
[0];
289 return clk_check_pll_setup(ifreq
, pllsetup
);
290 } else if (target_freq
<= ifreq
) {
291 pllsetup
->analog_on
= 0;
292 pllsetup
->cco_bypass_b15
= 1;
293 pllsetup
->direct_output_b14
= 0;
294 pllsetup
->fdbk_div_ctrl_b13
= 1;
297 for (p
= 0; p
<= 3; p
++) {
298 pllsetup
->pll_p
= pll_postdivs
[p
];
299 fclkout
= clk_check_pll_setup(ifreq
, pllsetup
);
300 if (abs(target_freq
- fclkout
) <= freqtol
)
305 /* Is direct mode possible? */
306 pllsetup
->analog_on
= 1;
307 pllsetup
->cco_bypass_b15
= 0;
308 pllsetup
->direct_output_b14
= 1;
309 pllsetup
->fdbk_div_ctrl_b13
= 0;
310 pllsetup
->pll_p
= pll_postdivs
[0];
311 for (m
= 1; m
<= 256; m
++) {
312 for (n
= 1; n
<= 4; n
++) {
313 /* Compute output frequency for this value */
316 fclkout
= clk_check_pll_setup(ifreq
,
318 if (abs(target_freq
- fclkout
) <=
324 /* Is integer mode possible? */
325 pllsetup
->analog_on
= 1;
326 pllsetup
->cco_bypass_b15
= 0;
327 pllsetup
->direct_output_b14
= 0;
328 pllsetup
->fdbk_div_ctrl_b13
= 1;
329 for (m
= 1; m
<= 256; m
++) {
330 for (n
= 1; n
<= 4; n
++) {
331 for (p
= 0; p
< 4; p
++) {
332 /* Compute output frequency */
333 pllsetup
->pll_p
= pll_postdivs
[p
];
336 fclkout
= clk_check_pll_setup(
338 if (abs(target_freq
- fclkout
) <= freqtol
)
344 /* Try non-integer mode */
345 pllsetup
->analog_on
= 1;
346 pllsetup
->cco_bypass_b15
= 0;
347 pllsetup
->direct_output_b14
= 0;
348 pllsetup
->fdbk_div_ctrl_b13
= 0;
349 for (m
= 1; m
<= 256; m
++) {
350 for (n
= 1; n
<= 4; n
++) {
351 for (p
= 0; p
< 4; p
++) {
352 /* Compute output frequency */
353 pllsetup
->pll_p
= pll_postdivs
[p
];
356 fclkout
= clk_check_pll_setup(
358 if (abs(target_freq
- fclkout
) <= freqtol
)
367 static struct clk clk_armpll
= {
369 .get_rate
= local_return_parent_rate
,
373 * Setup the USB PLL with a PLL structure
375 static u32
local_clk_usbpll_setup(struct clk_pll_setup
*pHCLKPllSetup
)
377 u32 reg
, tmp
= local_clk_pll_setup(pHCLKPllSetup
);
379 reg
= __raw_readl(LPC32XX_CLKPWR_USB_CTRL
) & ~0x1FFFF;
381 __raw_writel(reg
, LPC32XX_CLKPWR_USB_CTRL
);
383 return clk_check_pll_setup(clk_usbpll
.parent
->rate
,
387 static int local_usbpll_enable(struct clk
*clk
, int enable
)
391 unsigned long timeout
= jiffies
+ msecs_to_jiffies(20);
393 reg
= __raw_readl(LPC32XX_CLKPWR_USB_CTRL
);
395 __raw_writel(reg
& ~(LPC32XX_CLKPWR_USBCTRL_CLK_EN2
|
396 LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP
),
397 LPC32XX_CLKPWR_USB_CTRL
);
398 __raw_writel(reg
& ~LPC32XX_CLKPWR_USBCTRL_CLK_EN1
,
399 LPC32XX_CLKPWR_USB_CTRL
);
401 if (enable
&& usb_pll_valid
&& usb_pll_enable
) {
404 * If the PLL rate has been previously set, then the rate
405 * in the PLL register is valid and can be enabled here.
406 * Otherwise, it needs to be enabled as part of setrate.
410 * Gate clock into PLL
412 reg
|= LPC32XX_CLKPWR_USBCTRL_CLK_EN1
;
413 __raw_writel(reg
, LPC32XX_CLKPWR_USB_CTRL
);
418 reg
|= LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP
;
419 __raw_writel(reg
, LPC32XX_CLKPWR_USB_CTRL
);
422 * Wait for PLL to lock
424 while (time_before(jiffies
, timeout
) && (ret
== -ENODEV
)) {
425 reg
= __raw_readl(LPC32XX_CLKPWR_USB_CTRL
);
426 if (reg
& LPC32XX_CLKPWR_USBCTRL_PLL_STS
)
433 * Gate clock from PLL if PLL is locked
436 __raw_writel(reg
| LPC32XX_CLKPWR_USBCTRL_CLK_EN2
,
437 LPC32XX_CLKPWR_USB_CTRL
);
439 __raw_writel(reg
& ~(LPC32XX_CLKPWR_USBCTRL_CLK_EN1
|
440 LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP
),
441 LPC32XX_CLKPWR_USB_CTRL
);
443 } else if ((enable
== 0) && usb_pll_valid
&& usb_pll_enable
) {
451 static unsigned long local_usbpll_round_rate(struct clk
*clk
,
455 struct clk_pll_setup pllsetup
;
458 * Unlike other clocks, this clock has a KHz input rate, so bump
459 * it up to work with the PLL function
463 clkin
= clk
->get_rate(clk
);
464 usbdiv
= (__raw_readl(LPC32XX_CLKPWR_USBCLK_PDIV
) &
465 LPC32XX_CLKPWR_USBPDIV_PLL_MASK
) + 1;
466 clkin
= clkin
/ usbdiv
;
468 /* Try to find a good rate setup */
469 if (local_clk_find_pll_cfg(clkin
, rate
, &pllsetup
) == 0)
472 return clk_check_pll_setup(clkin
, &pllsetup
);
475 static int local_usbpll_set_rate(struct clk
*clk
, unsigned long rate
)
479 struct clk_pll_setup pllsetup
;
482 * Unlike other clocks, this clock has a KHz input rate, so bump
483 * it up to work with the PLL function
487 clkin
= clk
->get_rate(clk
->parent
);
488 usbdiv
= (__raw_readl(LPC32XX_CLKPWR_USBCLK_PDIV
) &
489 LPC32XX_CLKPWR_USBPDIV_PLL_MASK
) + 1;
490 clkin
= clkin
/ usbdiv
;
492 /* Try to find a good rate setup */
493 if (local_clk_find_pll_cfg(clkin
, rate
, &pllsetup
) == 0)
497 * Disable PLL clocks during PLL change
499 local_usbpll_enable(clk
, 0);
500 pllsetup
.analog_on
= 0;
501 local_clk_usbpll_setup(&pllsetup
);
504 * Start USB PLL and check PLL status
510 ret
= local_usbpll_enable(clk
, 1);
512 clk
->rate
= clk_check_pll_setup(clkin
, &pllsetup
);
517 static struct clk clk_usbpll
= {
519 .set_rate
= local_usbpll_set_rate
,
520 .enable
= local_usbpll_enable
,
521 .rate
= 48000, /* In KHz */
522 .get_rate
= local_return_parent_rate
,
523 .round_rate
= local_usbpll_round_rate
,
526 static u32
clk_get_hclk_div(void)
528 static const u32 hclkdivs
[4] = {1, 2, 4, 4};
529 return hclkdivs
[LPC32XX_CLKPWR_HCLKDIV_DIV_2POW(
530 __raw_readl(LPC32XX_CLKPWR_HCLK_DIV
))];
533 static struct clk clk_hclk
= {
534 .parent
= &clk_armpll
,
535 .get_rate
= local_return_parent_rate
,
538 static struct clk clk_pclk
= {
539 .parent
= &clk_armpll
,
540 .get_rate
= local_return_parent_rate
,
543 static int local_onoff_enable(struct clk
*clk
, int enable
)
547 tmp
= __raw_readl(clk
->enable_reg
);
550 tmp
&= ~clk
->enable_mask
;
552 tmp
|= clk
->enable_mask
;
554 __raw_writel(tmp
, clk
->enable_reg
);
559 /* Peripheral clock sources */
560 static struct clk clk_timer0
= {
562 .enable
= local_onoff_enable
,
563 .enable_reg
= LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1
,
564 .enable_mask
= LPC32XX_CLKPWR_TMRPWMCLK_TIMER0_EN
,
565 .get_rate
= local_return_parent_rate
,
567 static struct clk clk_timer1
= {
569 .enable
= local_onoff_enable
,
570 .enable_reg
= LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1
,
571 .enable_mask
= LPC32XX_CLKPWR_TMRPWMCLK_TIMER1_EN
,
572 .get_rate
= local_return_parent_rate
,
574 static struct clk clk_timer2
= {
576 .enable
= local_onoff_enable
,
577 .enable_reg
= LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1
,
578 .enable_mask
= LPC32XX_CLKPWR_TMRPWMCLK_TIMER2_EN
,
579 .get_rate
= local_return_parent_rate
,
581 static struct clk clk_timer3
= {
583 .enable
= local_onoff_enable
,
584 .enable_reg
= LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1
,
585 .enable_mask
= LPC32XX_CLKPWR_TMRPWMCLK_TIMER3_EN
,
586 .get_rate
= local_return_parent_rate
,
588 static struct clk clk_wdt
= {
590 .enable
= local_onoff_enable
,
591 .enable_reg
= LPC32XX_CLKPWR_TIMER_CLK_CTRL
,
592 .enable_mask
= LPC32XX_CLKPWR_PWMCLK_WDOG_EN
,
593 .get_rate
= local_return_parent_rate
,
595 static struct clk clk_vfp9
= {
597 .enable
= local_onoff_enable
,
598 .enable_reg
= LPC32XX_CLKPWR_DEBUG_CTRL
,
599 .enable_mask
= LPC32XX_CLKPWR_VFP_CLOCK_ENABLE_BIT
,
600 .get_rate
= local_return_parent_rate
,
602 static struct clk clk_dma
= {
604 .enable
= local_onoff_enable
,
605 .enable_reg
= LPC32XX_CLKPWR_DMA_CLK_CTRL
,
606 .enable_mask
= LPC32XX_CLKPWR_DMACLKCTRL_CLK_EN
,
607 .get_rate
= local_return_parent_rate
,
610 static struct clk clk_uart3
= {
612 .enable
= local_onoff_enable
,
613 .enable_reg
= LPC32XX_CLKPWR_UART_CLK_CTRL
,
614 .enable_mask
= LPC32XX_CLKPWR_UARTCLKCTRL_UART3_EN
,
615 .get_rate
= local_return_parent_rate
,
618 static struct clk clk_uart4
= {
620 .enable
= local_onoff_enable
,
621 .enable_reg
= LPC32XX_CLKPWR_UART_CLK_CTRL
,
622 .enable_mask
= LPC32XX_CLKPWR_UARTCLKCTRL_UART4_EN
,
623 .get_rate
= local_return_parent_rate
,
626 static struct clk clk_uart5
= {
628 .enable
= local_onoff_enable
,
629 .enable_reg
= LPC32XX_CLKPWR_UART_CLK_CTRL
,
630 .enable_mask
= LPC32XX_CLKPWR_UARTCLKCTRL_UART5_EN
,
631 .get_rate
= local_return_parent_rate
,
634 static struct clk clk_uart6
= {
636 .enable
= local_onoff_enable
,
637 .enable_reg
= LPC32XX_CLKPWR_UART_CLK_CTRL
,
638 .enable_mask
= LPC32XX_CLKPWR_UARTCLKCTRL_UART6_EN
,
639 .get_rate
= local_return_parent_rate
,
642 static struct clk clk_i2c0
= {
644 .enable
= local_onoff_enable
,
645 .enable_reg
= LPC32XX_CLKPWR_I2C_CLK_CTRL
,
646 .enable_mask
= LPC32XX_CLKPWR_I2CCLK_I2C1CLK_EN
,
647 .get_rate
= local_return_parent_rate
,
650 static struct clk clk_i2c1
= {
652 .enable
= local_onoff_enable
,
653 .enable_reg
= LPC32XX_CLKPWR_I2C_CLK_CTRL
,
654 .enable_mask
= LPC32XX_CLKPWR_I2CCLK_I2C2CLK_EN
,
655 .get_rate
= local_return_parent_rate
,
658 static struct clk clk_i2c2
= {
660 .enable
= local_onoff_enable
,
661 .enable_reg
= io_p2v(LPC32XX_USB_BASE
+ 0xFF4),
663 .get_rate
= local_return_parent_rate
,
666 static struct clk clk_ssp0
= {
668 .enable
= local_onoff_enable
,
669 .enable_reg
= LPC32XX_CLKPWR_SSP_CLK_CTRL
,
670 .enable_mask
= LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN
,
671 .get_rate
= local_return_parent_rate
,
674 static struct clk clk_ssp1
= {
676 .enable
= local_onoff_enable
,
677 .enable_reg
= LPC32XX_CLKPWR_SSP_CLK_CTRL
,
678 .enable_mask
= LPC32XX_CLKPWR_SSPCTRL_SSPCLK1_EN
,
679 .get_rate
= local_return_parent_rate
,
682 static struct clk clk_kscan
= {
683 .parent
= &osc_32KHz
,
684 .enable
= local_onoff_enable
,
685 .enable_reg
= LPC32XX_CLKPWR_KEY_CLK_CTRL
,
686 .enable_mask
= LPC32XX_CLKPWR_KEYCLKCTRL_CLK_EN
,
687 .get_rate
= local_return_parent_rate
,
690 static struct clk clk_nand
= {
692 .enable
= local_onoff_enable
,
693 .enable_reg
= LPC32XX_CLKPWR_NAND_CLK_CTRL
,
694 .enable_mask
= LPC32XX_CLKPWR_NANDCLK_SLCCLK_EN
,
695 .get_rate
= local_return_parent_rate
,
698 static struct clk clk_i2s0
= {
700 .enable
= local_onoff_enable
,
701 .enable_reg
= LPC32XX_CLKPWR_I2S_CLK_CTRL
,
702 .enable_mask
= LPC32XX_CLKPWR_I2SCTRL_I2SCLK0_EN
,
703 .get_rate
= local_return_parent_rate
,
706 static struct clk clk_i2s1
= {
708 .enable
= local_onoff_enable
,
709 .enable_reg
= LPC32XX_CLKPWR_I2S_CLK_CTRL
,
710 .enable_mask
= LPC32XX_CLKPWR_I2SCTRL_I2SCLK1_EN
,
711 .get_rate
= local_return_parent_rate
,
714 static struct clk clk_net
= {
716 .enable
= local_onoff_enable
,
717 .enable_reg
= LPC32XX_CLKPWR_MACCLK_CTRL
,
718 .enable_mask
= (LPC32XX_CLKPWR_MACCTRL_DMACLK_EN
|
719 LPC32XX_CLKPWR_MACCTRL_MMIOCLK_EN
|
720 LPC32XX_CLKPWR_MACCTRL_HRCCLK_EN
),
721 .get_rate
= local_return_parent_rate
,
724 static struct clk clk_rtc
= {
725 .parent
= &osc_32KHz
,
726 .rate
= 1, /* 1 Hz */
727 .get_rate
= local_return_parent_rate
,
730 static struct clk clk_usbd
= {
731 .parent
= &clk_usbpll
,
732 .enable
= local_onoff_enable
,
733 .enable_reg
= LPC32XX_CLKPWR_USB_CTRL
,
734 .enable_mask
= LPC32XX_CLKPWR_USBCTRL_HCLK_EN
,
735 .get_rate
= local_return_parent_rate
,
738 static int tsc_onoff_enable(struct clk
*clk
, int enable
)
742 /* Make sure 32KHz clock is the selected clock */
743 tmp
= __raw_readl(LPC32XX_CLKPWR_ADC_CLK_CTRL_1
);
744 tmp
&= ~LPC32XX_CLKPWR_ADCCTRL1_PCLK_SEL
;
745 __raw_writel(tmp
, LPC32XX_CLKPWR_ADC_CLK_CTRL_1
);
748 __raw_writel(0, clk
->enable_reg
);
750 __raw_writel(clk
->enable_mask
, clk
->enable_reg
);
755 static struct clk clk_tsc
= {
756 .parent
= &osc_32KHz
,
757 .enable
= tsc_onoff_enable
,
758 .enable_reg
= LPC32XX_CLKPWR_ADC_CLK_CTRL
,
759 .enable_mask
= LPC32XX_CLKPWR_ADC32CLKCTRL_CLK_EN
,
760 .get_rate
= local_return_parent_rate
,
763 static int adc_onoff_enable(struct clk
*clk
, int enable
)
768 /* Use PERIPH_CLOCK */
769 tmp
= __raw_readl(LPC32XX_CLKPWR_ADC_CLK_CTRL_1
);
770 tmp
|= LPC32XX_CLKPWR_ADCCTRL1_PCLK_SEL
;
772 * Set clock divider so that we have equal to or less than
773 * 4.5MHz clock at ADC
775 divider
= clk
->get_rate(clk
) / 4500000 + 1;
777 __raw_writel(tmp
, LPC32XX_CLKPWR_ADC_CLK_CTRL_1
);
779 /* synchronize rate of this clock w/ actual HW setting */
780 clk
->rate
= clk
->get_rate(clk
->parent
) / divider
;
783 __raw_writel(0, clk
->enable_reg
);
785 __raw_writel(clk
->enable_mask
, clk
->enable_reg
);
790 static struct clk clk_adc
= {
792 .enable
= adc_onoff_enable
,
793 .enable_reg
= LPC32XX_CLKPWR_ADC_CLK_CTRL
,
794 .enable_mask
= LPC32XX_CLKPWR_ADC32CLKCTRL_CLK_EN
,
795 .get_rate
= local_return_parent_rate
,
798 static int mmc_onoff_enable(struct clk
*clk
, int enable
)
802 tmp
= __raw_readl(LPC32XX_CLKPWR_MS_CTRL
) &
803 ~LPC32XX_CLKPWR_MSCARD_SDCARD_EN
;
805 /* If rate is 0, disable clock */
807 tmp
|= LPC32XX_CLKPWR_MSCARD_SDCARD_EN
;
809 __raw_writel(tmp
, LPC32XX_CLKPWR_MS_CTRL
);
814 static unsigned long mmc_get_rate(struct clk
*clk
)
816 u32 div
, rate
, oldclk
;
818 /* The MMC clock must be on when accessing an MMC register */
819 oldclk
= __raw_readl(LPC32XX_CLKPWR_MS_CTRL
);
820 __raw_writel(oldclk
| LPC32XX_CLKPWR_MSCARD_SDCARD_EN
,
821 LPC32XX_CLKPWR_MS_CTRL
);
822 div
= __raw_readl(LPC32XX_CLKPWR_MS_CTRL
);
823 __raw_writel(oldclk
, LPC32XX_CLKPWR_MS_CTRL
);
825 /* Get the parent clock rate */
826 rate
= clk
->parent
->get_rate(clk
->parent
);
828 /* Get the MMC controller clock divider value */
829 div
= div
& LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(0xf);
837 static unsigned long mmc_round_rate(struct clk
*clk
, unsigned long rate
)
839 unsigned long div
, prate
;
841 /* Get the parent clock rate */
842 prate
= clk
->parent
->get_rate(clk
->parent
);
854 static int mmc_set_rate(struct clk
*clk
, unsigned long rate
)
857 unsigned long prate
, div
, crate
= mmc_round_rate(clk
, rate
);
859 prate
= clk
->parent
->get_rate(clk
->parent
);
863 /* The MMC clock must be on when accessing an MMC register */
864 oldclk
= __raw_readl(LPC32XX_CLKPWR_MS_CTRL
);
865 __raw_writel(oldclk
| LPC32XX_CLKPWR_MSCARD_SDCARD_EN
,
866 LPC32XX_CLKPWR_MS_CTRL
);
867 tmp
= __raw_readl(LPC32XX_CLKPWR_MS_CTRL
) &
868 ~LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(0xf);
869 tmp
|= LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(div
);
870 __raw_writel(tmp
, LPC32XX_CLKPWR_MS_CTRL
);
872 __raw_writel(oldclk
, LPC32XX_CLKPWR_MS_CTRL
);
877 static struct clk clk_mmc
= {
878 .parent
= &clk_armpll
,
879 .set_rate
= mmc_set_rate
,
880 .get_rate
= mmc_get_rate
,
881 .round_rate
= mmc_round_rate
,
882 .enable
= mmc_onoff_enable
,
883 .enable_reg
= LPC32XX_CLKPWR_MS_CTRL
,
884 .enable_mask
= LPC32XX_CLKPWR_MSCARD_SDCARD_EN
,
887 static unsigned long clcd_get_rate(struct clk
*clk
)
889 u32 tmp
, div
, rate
, oldclk
;
891 /* The LCD clock must be on when accessing an LCD register */
892 oldclk
= __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL
);
893 __raw_writel(oldclk
| LPC32XX_CLKPWR_LCDCTRL_CLK_EN
,
894 LPC32XX_CLKPWR_LCDCLK_CTRL
);
895 tmp
= __raw_readl(io_p2v(LPC32XX_LCD_BASE
+ CLCD_TIM2
));
896 __raw_writel(oldclk
, LPC32XX_CLKPWR_LCDCLK_CTRL
);
898 rate
= clk
->parent
->get_rate(clk
->parent
);
900 /* Only supports internal clocking */
904 div
= (tmp
& 0x1F) | ((tmp
& 0xF8) >> 22);
905 tmp
= rate
/ (2 + div
);
910 static int clcd_set_rate(struct clk
*clk
, unsigned long rate
)
912 u32 tmp
, prate
, div
, oldclk
;
914 /* The LCD clock must be on when accessing an LCD register */
915 oldclk
= __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL
);
916 __raw_writel(oldclk
| LPC32XX_CLKPWR_LCDCTRL_CLK_EN
,
917 LPC32XX_CLKPWR_LCDCLK_CTRL
);
919 tmp
= __raw_readl(io_p2v(LPC32XX_LCD_BASE
+ CLCD_TIM2
)) | TIM2_BCD
;
920 prate
= clk
->parent
->get_rate(clk
->parent
);
923 /* Find closest divider */
930 tmp
&= ~(0xF800001F);
932 tmp
|= (((div
>> 5) & 0x1F) << 27);
935 __raw_writel(tmp
, io_p2v(LPC32XX_LCD_BASE
+ CLCD_TIM2
));
936 __raw_writel(oldclk
, LPC32XX_CLKPWR_LCDCLK_CTRL
);
941 static unsigned long clcd_round_rate(struct clk
*clk
, unsigned long rate
)
945 prate
= clk
->parent
->get_rate(clk
->parent
);
960 static struct clk clk_lcd
= {
962 .set_rate
= clcd_set_rate
,
963 .get_rate
= clcd_get_rate
,
964 .round_rate
= clcd_round_rate
,
965 .enable
= local_onoff_enable
,
966 .enable_reg
= LPC32XX_CLKPWR_LCDCLK_CTRL
,
967 .enable_mask
= LPC32XX_CLKPWR_LCDCTRL_CLK_EN
,
970 static void local_clk_disable(struct clk
*clk
)
972 /* Don't attempt to disable clock if it has no users */
973 if (clk
->usecount
> 0) {
976 /* Only disable clock when it has no more users */
977 if ((clk
->usecount
== 0) && (clk
->enable
))
980 /* Check parent clocks, they may need to be disabled too */
982 local_clk_disable(clk
->parent
);
986 static int local_clk_enable(struct clk
*clk
)
990 /* Enable parent clocks first and update use counts */
992 ret
= local_clk_enable(clk
->parent
);
995 /* Only enable clock if it's currently disabled */
996 if ((clk
->usecount
== 0) && (clk
->enable
))
997 ret
= clk
->enable(clk
, 1);
1001 else if (clk
->parent
)
1002 local_clk_disable(clk
->parent
);
1009 * clk_enable - inform the system when the clock source should be running.
1011 int clk_enable(struct clk
*clk
)
1014 unsigned long flags
;
1016 spin_lock_irqsave(&global_clkregs_lock
, flags
);
1017 ret
= local_clk_enable(clk
);
1018 spin_unlock_irqrestore(&global_clkregs_lock
, flags
);
1022 EXPORT_SYMBOL(clk_enable
);
1025 * clk_disable - inform the system when the clock source is no longer required
1027 void clk_disable(struct clk
*clk
)
1029 unsigned long flags
;
1031 spin_lock_irqsave(&global_clkregs_lock
, flags
);
1032 local_clk_disable(clk
);
1033 spin_unlock_irqrestore(&global_clkregs_lock
, flags
);
1035 EXPORT_SYMBOL(clk_disable
);
1038 * clk_get_rate - obtain the current clock rate (in Hz) for a clock source
1040 unsigned long clk_get_rate(struct clk
*clk
)
1042 return clk
->get_rate(clk
);
1044 EXPORT_SYMBOL(clk_get_rate
);
1047 * clk_set_rate - set the clock rate for a clock source
1049 int clk_set_rate(struct clk
*clk
, unsigned long rate
)
1054 * Most system clocks can only be enabled or disabled, with
1055 * the actual rate set as part of the peripheral dividers
1056 * instead of high level clock control
1059 ret
= clk
->set_rate(clk
, rate
);
1063 EXPORT_SYMBOL(clk_set_rate
);
1066 * clk_round_rate - adjust a rate to the exact rate a clock can provide
1068 long clk_round_rate(struct clk
*clk
, unsigned long rate
)
1070 if (clk
->round_rate
)
1071 rate
= clk
->round_rate(clk
, rate
);
1073 rate
= clk
->get_rate(clk
);
1077 EXPORT_SYMBOL(clk_round_rate
);
1080 * clk_set_parent - set the parent clock source for this clock
1082 int clk_set_parent(struct clk
*clk
, struct clk
*parent
)
1084 /* Clock re-parenting is not supported */
1087 EXPORT_SYMBOL(clk_set_parent
);
1090 * clk_get_parent - get the parent clock source for this clock
1092 struct clk
*clk_get_parent(struct clk
*clk
)
1096 EXPORT_SYMBOL(clk_get_parent
);
1098 static struct clk_lookup lookups
[] = {
1099 CLKDEV_INIT(NULL
, "osc_32KHz", &osc_32KHz
),
1100 CLKDEV_INIT(NULL
, "osc_pll397", &osc_pll397
),
1101 CLKDEV_INIT(NULL
, "osc_main", &osc_main
),
1102 CLKDEV_INIT(NULL
, "sys_ck", &clk_sys
),
1103 CLKDEV_INIT(NULL
, "arm_pll_ck", &clk_armpll
),
1104 CLKDEV_INIT(NULL
, "ck_pll5", &clk_usbpll
),
1105 CLKDEV_INIT(NULL
, "hclk_ck", &clk_hclk
),
1106 CLKDEV_INIT(NULL
, "pclk_ck", &clk_pclk
),
1107 CLKDEV_INIT(NULL
, "timer0_ck", &clk_timer0
),
1108 CLKDEV_INIT(NULL
, "timer1_ck", &clk_timer1
),
1109 CLKDEV_INIT(NULL
, "timer2_ck", &clk_timer2
),
1110 CLKDEV_INIT(NULL
, "timer3_ck", &clk_timer3
),
1111 CLKDEV_INIT(NULL
, "vfp9_ck", &clk_vfp9
),
1112 CLKDEV_INIT("pl08xdmac", NULL
, &clk_dma
),
1113 CLKDEV_INIT("4003c000.watchdog", NULL
, &clk_wdt
),
1114 CLKDEV_INIT(NULL
, "uart3_ck", &clk_uart3
),
1115 CLKDEV_INIT(NULL
, "uart4_ck", &clk_uart4
),
1116 CLKDEV_INIT(NULL
, "uart5_ck", &clk_uart5
),
1117 CLKDEV_INIT(NULL
, "uart6_ck", &clk_uart6
),
1118 CLKDEV_INIT("400a0000.i2c", NULL
, &clk_i2c0
),
1119 CLKDEV_INIT("400a8000.i2c", NULL
, &clk_i2c1
),
1120 CLKDEV_INIT("31020300.i2c", NULL
, &clk_i2c2
),
1121 CLKDEV_INIT("dev:ssp0", NULL
, &clk_ssp0
),
1122 CLKDEV_INIT("dev:ssp1", NULL
, &clk_ssp1
),
1123 CLKDEV_INIT("lpc32xx_keys.0", NULL
, &clk_kscan
),
1124 CLKDEV_INIT("lpc32xx-nand.0", "nand_ck", &clk_nand
),
1125 CLKDEV_INIT("40048000.adc", NULL
, &clk_adc
),
1126 CLKDEV_INIT(NULL
, "i2s0_ck", &clk_i2s0
),
1127 CLKDEV_INIT(NULL
, "i2s1_ck", &clk_i2s1
),
1128 CLKDEV_INIT("40048000.tsc", NULL
, &clk_tsc
),
1129 CLKDEV_INIT("20098000.sd", NULL
, &clk_mmc
),
1130 CLKDEV_INIT("31060000.ethernet", NULL
, &clk_net
),
1131 CLKDEV_INIT("dev:clcd", NULL
, &clk_lcd
),
1132 CLKDEV_INIT("31020000.usbd", "ck_usbd", &clk_usbd
),
1133 CLKDEV_INIT("lpc32xx_rtc", NULL
, &clk_rtc
),
1136 static int __init
clk_init(void)
1140 for (i
= 0; i
< ARRAY_SIZE(lookups
); i
++)
1141 clkdev_add(&lookups
[i
]);
1144 * Setup muxed SYSCLK for HCLK PLL base -this selects the
1145 * parent clock used for the ARM PLL and is used to derive
1146 * the many system clock rates in the device.
1148 if (clk_is_sysclk_mainosc() != 0)
1149 clk_sys
.parent
= &osc_main
;
1151 clk_sys
.parent
= &osc_pll397
;
1153 clk_sys
.rate
= clk_sys
.parent
->rate
;
1155 /* Compute the current ARM PLL and USB PLL frequencies */
1156 local_update_armpll_rate();
1158 /* Compute HCLK and PCLK bus rates */
1159 clk_hclk
.rate
= clk_hclk
.parent
->rate
/ clk_get_hclk_div();
1160 clk_pclk
.rate
= clk_pclk
.parent
->rate
/ clk_get_pclk_div();
1163 * Enable system clocks - this step is somewhat formal, as the
1164 * clocks are already running, but it does get the clock data
1165 * inline with the actual system state. Never disable these
1166 * clocks as they will only stop if the system is going to sleep.
1167 * In that case, the chip/system power management functions will
1168 * handle clock gating.
1170 if (clk_enable(&clk_hclk
) || clk_enable(&clk_pclk
))
1171 printk(KERN_ERR
"Error enabling system HCLK and PCLK\n");
1174 * Timers 0 and 1 were enabled and are being used by the high
1175 * resolution tick function prior to this driver being initialized.
1176 * Tag them now as used.
1178 if (clk_enable(&clk_timer0
) || clk_enable(&clk_timer1
))
1179 printk(KERN_ERR
"Error enabling timer tick clocks\n");
1183 core_initcall(clk_init
);