drivers/net/wireless/b43/phy_lcn.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4   IEEE 802.11n LCN-PHY support
   5
   6   Copyright (c) 2011 Rafał Miłecki <zajec5@gmail.com>
   7
   8   This program is free software; you can redistribute it and/or modify
   9   it under the terms of the GNU General Public License as published by
  10   the Free Software Foundation; either version 2 of the License, or
  11   (at your option) any later version.
  12
  13   This program is distributed in the hope that it will be useful,
  14   but WITHOUT ANY WARRANTY; without even the implied warranty of
  15   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16   GNU General Public License for more details.
  17
  18   You should have received a copy of the GNU General Public License
  19   along with this program; see the file COPYING.  If not, write to
  20   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  21   Boston, MA 02110-1301, USA.
  22
  23 */
  24
  25 #include <linux/slab.h>
  26
  27 #include "b43.h"
  28 #include "phy_lcn.h"
  29 #include "tables_phy_lcn.h"
  30 #include "main.h"
  31
  32 /**************************************************
  33  * Radio 2064.
  34  **************************************************/
  35
  36 /* wlc_lcnphy_radio_2064_channel_tune_4313 */
  37 static void b43_radio_2064_channel_setup(struct b43_wldev *dev)
  38 {
  39         u16 save[2];
  40
  41         b43_radio_set(dev, 0x09d, 0x4);
  42         b43_radio_write(dev, 0x09e, 0xf);
  43
  44         /* Channel specific values in theory, in practice always the same */
  45         b43_radio_write(dev, 0x02a, 0xb);
  46         b43_radio_maskset(dev, 0x030, ~0x3, 0xa);
  47         b43_radio_maskset(dev, 0x091, ~0x3, 0);
  48         b43_radio_maskset(dev, 0x038, ~0xf, 0x7);
  49         b43_radio_maskset(dev, 0x030, ~0xc, 0x8);
  50         b43_radio_maskset(dev, 0x05e, ~0xf, 0x8);
  51         b43_radio_maskset(dev, 0x05e, ~0xf0, 0x80);
  52         b43_radio_write(dev, 0x06c, 0x80);
  53
  54         save[0] = b43_radio_read(dev, 0x044);
  55         save[1] = b43_radio_read(dev, 0x12b);
  56
  57         b43_radio_set(dev, 0x044, 0x7);
  58         b43_radio_set(dev, 0x12b, 0xe);
  59
  60         /* TODO */
  61
  62         b43_radio_write(dev, 0x040, 0xfb);
  63
  64         b43_radio_write(dev, 0x041, 0x9a);
  65         b43_radio_write(dev, 0x042, 0xa3);
  66         b43_radio_write(dev, 0x043, 0x0c);
  67
  68         /* TODO */
  69
  70         b43_radio_set(dev, 0x044, 0x0c);
  71         udelay(1);
  72
  73         b43_radio_write(dev, 0x044, save[0]);
  74         b43_radio_write(dev, 0x12b, save[1]);
  75
  76         if (dev->phy.rev == 1) {
  77                 /* brcmsmac uses outdated 0x3 for 0x038 */
  78                 b43_radio_write(dev, 0x038, 0x0);
  79                 b43_radio_write(dev, 0x091, 0x7);
  80         }
  81 }
  82
  83 /* wlc_radio_2064_init */
  84 static void b43_radio_2064_init(struct b43_wldev *dev)
  85 {
  86         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
  87                 b43_radio_write(dev, 0x09c, 0x0020);
  88                 b43_radio_write(dev, 0x105, 0x0008);
  89         } else {
  90                 /* TODO */
  91         }
  92         b43_radio_write(dev, 0x032, 0x0062);
  93         b43_radio_write(dev, 0x033, 0x0019);
  94         b43_radio_write(dev, 0x090, 0x0010);
  95         b43_radio_write(dev, 0x010, 0x0000);
  96         if (dev->phy.rev == 1) {
  97                 b43_radio_write(dev, 0x060, 0x007f);
  98                 b43_radio_write(dev, 0x061, 0x0072);
  99                 b43_radio_write(dev, 0x062, 0x007f);
 100         }
 101         b43_radio_write(dev, 0x01d, 0x0002);
 102         b43_radio_write(dev, 0x01e, 0x0006);
 103
 104         b43_phy_write(dev, 0x4ea, 0x4688);
 105         b43_phy_maskset(dev, 0x4eb, ~0x7, 0x2);
 106         b43_phy_mask(dev, 0x4eb, ~0x01c0);
 107         b43_phy_maskset(dev, 0x46a, 0xff00, 0x19);
 108
 109         b43_lcntab_write(dev, B43_LCNTAB16(0x00, 0x55), 0);
 110
 111         b43_radio_mask(dev, 0x05b, (u16) ~0xff02);
 112         b43_radio_set(dev, 0x004, 0x40);
 113         b43_radio_set(dev, 0x120, 0x10);
 114         b43_radio_set(dev, 0x078, 0x80);
 115         b43_radio_set(dev, 0x129, 0x2);
 116         b43_radio_set(dev, 0x057, 0x1);
 117         b43_radio_set(dev, 0x05b, 0x2);
 118
 119         /* TODO: wait for some bit to be set */
 120         b43_radio_read(dev, 0x05c);
 121
 122         b43_radio_mask(dev, 0x05b, (u16) ~0xff02);
 123         b43_radio_mask(dev, 0x057, (u16) ~0xff01);
 124
 125         b43_phy_write(dev, 0x933, 0x2d6b);
 126         b43_phy_write(dev, 0x934, 0x2d6b);
 127         b43_phy_write(dev, 0x935, 0x2d6b);
 128         b43_phy_write(dev, 0x936, 0x2d6b);
 129         b43_phy_write(dev, 0x937, 0x016b);
 130
 131         b43_radio_mask(dev, 0x057, (u16) ~0xff02);
 132         b43_radio_write(dev, 0x0c2, 0x006f);
 133 }
 134
 135 /**************************************************
 136  * Various PHY ops
 137  **************************************************/
 138
 139 /* wlc_lcnphy_toggle_afe_pwdn */
 140 static void b43_phy_lcn_afe_set_unset(struct b43_wldev *dev)
 141 {
 142         u16 afe_ctl2 = b43_phy_read(dev, B43_PHY_LCN_AFE_CTL2);
 143         u16 afe_ctl1 = b43_phy_read(dev, B43_PHY_LCN_AFE_CTL1);
 144
 145         b43_phy_write(dev, B43_PHY_LCN_AFE_CTL2, afe_ctl2 | 0x1);
 146         b43_phy_write(dev, B43_PHY_LCN_AFE_CTL1, afe_ctl1 | 0x1);
 147
 148         b43_phy_write(dev, B43_PHY_LCN_AFE_CTL2, afe_ctl2 & ~0x1);
 149         b43_phy_write(dev, B43_PHY_LCN_AFE_CTL1, afe_ctl1 & ~0x1);
 150
 151         b43_phy_write(dev, B43_PHY_LCN_AFE_CTL2, afe_ctl2);
 152         b43_phy_write(dev, B43_PHY_LCN_AFE_CTL1, afe_ctl1);
 153 }
 154
 155 /* wlc_lcnphy_clear_tx_power_offsets */
 156 static void b43_phy_lcn_clear_tx_power_offsets(struct b43_wldev *dev)
 157 {
 158         u8 i;
 159
 160         if (1) { /* FIXME */
 161                 b43_phy_write(dev, B43_PHY_LCN_TABLE_ADDR, (0x7 << 10) | 0x340);
 162                 for (i = 0; i < 30; i++) {
 163                         b43_phy_write(dev, B43_PHY_LCN_TABLE_DATAHI, 0);
 164                         b43_phy_write(dev, B43_PHY_LCN_TABLE_DATALO, 0);
 165                 }
 166         }
 167
 168         b43_phy_write(dev, B43_PHY_LCN_TABLE_ADDR, (0x7 << 10) | 0x80);
 169         for (i = 0; i < 64; i++) {
 170                 b43_phy_write(dev, B43_PHY_LCN_TABLE_DATAHI, 0);
 171                 b43_phy_write(dev, B43_PHY_LCN_TABLE_DATALO, 0);
 172         }
 173 }
 174
 175 /* wlc_lcnphy_rev0_baseband_init */
 176 static void b43_phy_lcn_rev0_baseband_init(struct b43_wldev *dev)
 177 {
 178         b43_radio_write(dev, 0x11c, 0);
 179
 180         b43_phy_write(dev, 0x43b, 0);
 181         b43_phy_write(dev, 0x43c, 0);
 182         b43_phy_write(dev, 0x44c, 0);
 183         b43_phy_write(dev, 0x4e6, 0);
 184         b43_phy_write(dev, 0x4f9, 0);
 185         b43_phy_write(dev, 0x4b0, 0);
 186         b43_phy_write(dev, 0x938, 0);
 187         b43_phy_write(dev, 0x4b0, 0);
 188         b43_phy_write(dev, 0x44e, 0);
 189
 190         b43_phy_set(dev, 0x567, 0x03);
 191
 192         b43_phy_set(dev, 0x44a, 0x44);
 193         b43_phy_write(dev, 0x44a, 0x80);
 194
 195         if (!(dev->dev->bus_sprom->boardflags_lo & B43_BFL_FEM))
 196                 ; /* TODO */
 197         b43_phy_maskset(dev, 0x634, ~0xff, 0xc);
 198         if (dev->dev->bus_sprom->boardflags_lo & B43_BFL_FEM) {
 199                 b43_phy_maskset(dev, 0x634, ~0xff, 0xa);
 200                 b43_phy_write(dev, 0x910, 0x1);
 201         }
 202
 203         b43_phy_write(dev, 0x910, 0x1);
 204
 205         b43_phy_maskset(dev, 0x448, ~0x300, 0x100);
 206         b43_phy_maskset(dev, 0x608, ~0xff, 0x17);
 207         b43_phy_maskset(dev, 0x604, ~0x7ff, 0x3ea);
 208 }
 209
 210 /* wlc_lcnphy_bu_tweaks */
 211 static void b43_phy_lcn_bu_tweaks(struct b43_wldev *dev)
 212 {
 213         b43_phy_set(dev, 0x805, 0x1);
 214
 215         b43_phy_maskset(dev, 0x42f, ~0x7, 0x3);
 216         b43_phy_maskset(dev, 0x030, ~0x7, 0x3);
 217
 218         b43_phy_write(dev, 0x414, 0x1e10);
 219         b43_phy_write(dev, 0x415, 0x0640);
 220
 221         b43_phy_maskset(dev, 0x4df, (u16) ~0xff00, 0xf700);
 222
 223         b43_phy_set(dev, 0x44a, 0x44);
 224         b43_phy_write(dev, 0x44a, 0x80);
 225
 226         b43_phy_maskset(dev, 0x434, ~0xff, 0xfd);
 227         b43_phy_maskset(dev, 0x420, ~0xff, 0x10);
 228
 229         if (dev->dev->bus_sprom->board_rev >= 0x1204)
 230                 b43_radio_set(dev, 0x09b, 0xf0);
 231
 232         b43_phy_write(dev, 0x7d6, 0x0902);
 233
 234         /* TODO: more ops */
 235
 236         if (dev->phy.rev == 1) {
 237                 /* TODO: more ops */
 238
 239                 b43_phy_lcn_clear_tx_power_offsets(dev);
 240         }
 241 }
 242
 243 /* wlc_lcnphy_vbat_temp_sense_setup */
 244 static void b43_phy_lcn_sense_setup(struct b43_wldev *dev)
 245 {
 246         u8 i;
 247
 248         u16 save_radio_regs[6][2] = {
 249                 { 0x007, 0 }, { 0x0ff, 0 }, { 0x11f, 0 }, { 0x005, 0 },
 250                 { 0x025, 0 }, { 0x112, 0 },
 251         };
 252         u16 save_phy_regs[14][2] = {
 253                 { 0x503, 0 }, { 0x4a4, 0 }, { 0x4d0, 0 }, { 0x4d9, 0 },
 254                 { 0x4da, 0 }, { 0x4a6, 0 }, { 0x938, 0 }, { 0x939, 0 },
 255                 { 0x4d8, 0 }, { 0x4d0, 0 }, { 0x4d7, 0 }, { 0x4a5, 0 },
 256                 { 0x40d, 0 }, { 0x4a2, 0 },
 257         };
 258         u16 save_radio_4a4;
 259
 260         for (i = 0; i < 6; i++)
 261                 save_radio_regs[i][1] = b43_radio_read(dev,
 262                                                        save_radio_regs[i][0]);
 263         for (i = 0; i < 14; i++)
 264                 save_phy_regs[i][1] = b43_phy_read(dev, save_phy_regs[i][0]);
 265         save_radio_4a4 = b43_radio_read(dev, 0x4a4);
 266
 267         /* TODO: config sth */
 268
 269         for (i = 0; i < 6; i++)
 270                 b43_radio_write(dev, save_radio_regs[i][0],
 271                                 save_radio_regs[i][1]);
 272         for (i = 0; i < 14; i++)
 273                 b43_phy_write(dev, save_phy_regs[i][0], save_phy_regs[i][1]);
 274         b43_radio_write(dev, 0x4a4, save_radio_4a4);
 275 }
 276
 277 /**************************************************
 278  * Channel switching ops.
 279  **************************************************/
 280
 281 static int b43_phy_lcn_set_channel(struct b43_wldev *dev,
 282                                    struct ieee80211_channel *channel,
 283                                    enum nl80211_channel_type channel_type)
 284 {
 285         /* TODO: PLL and PHY ops */
 286
 287         b43_phy_set(dev, 0x44a, 0x44);
 288         b43_phy_write(dev, 0x44a, 0x80);
 289
 290         b43_phy_set(dev, 0x44a, 0x44);
 291         b43_phy_write(dev, 0x44a, 0x80);
 292
 293         b43_radio_2064_channel_setup(dev);
 294         mdelay(1);
 295
 296         b43_phy_lcn_afe_set_unset(dev);
 297
 298         /* TODO */
 299
 300         return 0;
 301 }
 302
 303 /**************************************************
 304  * Basic PHY ops.
 305  **************************************************/
 306
 307 static int b43_phy_lcn_op_allocate(struct b43_wldev *dev)
 308 {
 309         struct b43_phy_lcn *phy_lcn;
 310
 311         phy_lcn = kzalloc(sizeof(*phy_lcn), GFP_KERNEL);
 312         if (!phy_lcn)
 313                 return -ENOMEM;
 314         dev->phy.lcn = phy_lcn;
 315
 316         return 0;
 317 }
 318
 319 static void b43_phy_lcn_op_free(struct b43_wldev *dev)
 320 {
 321         struct b43_phy *phy = &dev->phy;
 322         struct b43_phy_lcn *phy_lcn = phy->lcn;
 323
 324         kfree(phy_lcn);
 325         phy->lcn = NULL;
 326 }
 327
 328 static void b43_phy_lcn_op_prepare_structs(struct b43_wldev *dev)
 329 {
 330         struct b43_phy *phy = &dev->phy;
 331         struct b43_phy_lcn *phy_lcn = phy->lcn;
 332
 333         memset(phy_lcn, 0, sizeof(*phy_lcn));
 334 }
 335
 336 /* wlc_phy_init_lcnphy */
 337 static int b43_phy_lcn_op_init(struct b43_wldev *dev)
 338 {
 339         b43_phy_set(dev, 0x44a, 0x80);
 340         b43_phy_mask(dev, 0x44a, 0x7f);
 341         b43_phy_set(dev, 0x6d1, 0x80);
 342         b43_phy_write(dev, 0x6d0, 0x7);
 343
 344         b43_phy_lcn_afe_set_unset(dev);
 345
 346         b43_phy_write(dev, 0x60a, 0xa0);
 347         b43_phy_write(dev, 0x46a, 0x19);
 348         b43_phy_maskset(dev, 0x663, 0xFF00, 0x64);
 349
 350         b43_phy_lcn_tables_init(dev);
 351
 352         b43_phy_lcn_rev0_baseband_init(dev);
 353         b43_phy_lcn_bu_tweaks(dev);
 354
 355         if (dev->phy.radio_ver == 0x2064)
 356                 b43_radio_2064_init(dev);
 357         else
 358                 B43_WARN_ON(1);
 359
 360         b43_phy_lcn_sense_setup(dev);
 361
 362         return 0;
 363 }
 364
 365 static void b43_phy_lcn_op_software_rfkill(struct b43_wldev *dev,
 366                                         bool blocked)
 367 {
 368         if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
 369                 b43err(dev->wl, "MAC not suspended\n");
 370
 371         if (blocked) {
 372                 b43_phy_mask(dev, B43_PHY_LCN_RF_CTL2, ~0x7c00);
 373                 b43_phy_set(dev, B43_PHY_LCN_RF_CTL1, 0x1f00);
 374
 375                 b43_phy_mask(dev, B43_PHY_LCN_RF_CTL5, ~0x7f00);
 376                 b43_phy_mask(dev, B43_PHY_LCN_RF_CTL4, ~0x2);
 377                 b43_phy_set(dev, B43_PHY_LCN_RF_CTL3, 0x808);
 378
 379                 b43_phy_mask(dev, B43_PHY_LCN_RF_CTL7, ~0x8);
 380                 b43_phy_set(dev, B43_PHY_LCN_RF_CTL6, 0x8);
 381         } else {
 382                 b43_phy_mask(dev, B43_PHY_LCN_RF_CTL1, ~0x1f00);
 383                 b43_phy_mask(dev, B43_PHY_LCN_RF_CTL3, ~0x808);
 384                 b43_phy_mask(dev, B43_PHY_LCN_RF_CTL6, ~0x8);
 385         }
 386 }
 387
 388 static void b43_phy_lcn_op_switch_analog(struct b43_wldev *dev, bool on)
 389 {
 390         if (on) {
 391                 b43_phy_mask(dev, B43_PHY_LCN_AFE_CTL1, ~0x7);
 392         } else {
 393                 b43_phy_set(dev, B43_PHY_LCN_AFE_CTL2, 0x7);
 394                 b43_phy_set(dev, B43_PHY_LCN_AFE_CTL1, 0x7);
 395         }
 396 }
 397
 398 static int b43_phy_lcn_op_switch_channel(struct b43_wldev *dev,
 399                                         unsigned int new_channel)
 400 {
 401         struct ieee80211_channel *channel = dev->wl->hw->conf.channel;
 402         enum nl80211_channel_type channel_type = dev->wl->hw->conf.channel_type;
 403
 404         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
 405                 if ((new_channel < 1) || (new_channel > 14))
 406                         return -EINVAL;
 407         } else {
 408                 return -EINVAL;
 409         }
 410
 411         return b43_phy_lcn_set_channel(dev, channel, channel_type);
 412 }
 413
 414 static unsigned int b43_phy_lcn_op_get_default_chan(struct b43_wldev *dev)
 415 {
 416         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
 417                 return 1;
 418         return 36;
 419 }
 420
 421 static enum b43_txpwr_result
 422 b43_phy_lcn_op_recalc_txpower(struct b43_wldev *dev, bool ignore_tssi)
 423 {
 424         return B43_TXPWR_RES_DONE;
 425 }
 426
 427 static void b43_phy_lcn_op_adjust_txpower(struct b43_wldev *dev)
 428 {
 429 }
 430
 431 /**************************************************
 432  * R/W ops.
 433  **************************************************/
 434
 435 static u16 b43_phy_lcn_op_read(struct b43_wldev *dev, u16 reg)
 436 {
 437         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
 438         return b43_read16(dev, B43_MMIO_PHY_DATA);
 439 }
 440
 441 static void b43_phy_lcn_op_write(struct b43_wldev *dev, u16 reg, u16 value)
 442 {
 443         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
 444         b43_write16(dev, B43_MMIO_PHY_DATA, value);
 445 }
 446
 447 static void b43_phy_lcn_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
 448                                    u16 set)
 449 {
 450         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
 451         b43_write16(dev, B43_MMIO_PHY_DATA,
 452                     (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set);
 453 }
 454
 455 static u16 b43_phy_lcn_op_radio_read(struct b43_wldev *dev, u16 reg)
 456 {
 457         /* LCN-PHY needs 0x200 for read access */
 458         reg |= 0x200;
 459
 460         b43_write16(dev, B43_MMIO_RADIO24_CONTROL, reg);
 461         return b43_read16(dev, B43_MMIO_RADIO24_DATA);
 462 }
 463
 464 static void b43_phy_lcn_op_radio_write(struct b43_wldev *dev, u16 reg,
 465                                        u16 value)
 466 {
 467         b43_write16(dev, B43_MMIO_RADIO24_CONTROL, reg);
 468         b43_write16(dev, B43_MMIO_RADIO24_DATA, value);
 469 }
 470
 471 /**************************************************
 472  * PHY ops struct.
 473  **************************************************/
 474
 475 const struct b43_phy_operations b43_phyops_lcn = {
 476         .allocate               = b43_phy_lcn_op_allocate,
 477         .free                   = b43_phy_lcn_op_free,
 478         .prepare_structs        = b43_phy_lcn_op_prepare_structs,
 479         .init                   = b43_phy_lcn_op_init,
 480         .phy_read               = b43_phy_lcn_op_read,
 481         .phy_write              = b43_phy_lcn_op_write,
 482         .phy_maskset            = b43_phy_lcn_op_maskset,
 483         .radio_read             = b43_phy_lcn_op_radio_read,
 484         .radio_write            = b43_phy_lcn_op_radio_write,
 485         .software_rfkill        = b43_phy_lcn_op_software_rfkill,
 486         .switch_analog          = b43_phy_lcn_op_switch_analog,
 487         .switch_channel         = b43_phy_lcn_op_switch_channel,
 488         .get_default_chan       = b43_phy_lcn_op_get_default_chan,
 489         .recalc_txpower         = b43_phy_lcn_op_recalc_txpower,
 490         .adjust_txpower         = b43_phy_lcn_op_adjust_txpower,
 491 };