arch/x86/kernel/cpu/common.c

   1 #include <linux/bootmem.h>
   2 #include <linux/linkage.h>
   3 #include <linux/bitops.h>
   4 #include <linux/kernel.h>
   5 #include <linux/module.h>
   6 #include <linux/percpu.h>
   7 #include <linux/string.h>
   8 #include <linux/delay.h>
   9 #include <linux/sched.h>
  10 #include <linux/init.h>
  11 #include <linux/kgdb.h>
  12 #include <linux/smp.h>
  13 #include <linux/io.h>
  14
  15 #include <asm/stackprotector.h>
  16 #include <asm/mmu_context.h>
  17 #include <asm/hypervisor.h>
  18 #include <asm/processor.h>
  19 #include <asm/sections.h>
  20 #include <asm/topology.h>
  21 #include <asm/cpumask.h>
  22 #include <asm/pgtable.h>
  23 #include <asm/atomic.h>
  24 #include <asm/proto.h>
  25 #include <asm/setup.h>
  26 #include <asm/apic.h>
  27 #include <asm/desc.h>
  28 #include <asm/i387.h>
  29 #include <asm/mtrr.h>
  30 #include <asm/numa.h>
  31 #include <asm/asm.h>
  32 #include <asm/cpu.h>
  33 #include <asm/mce.h>
  34 #include <asm/msr.h>
  35 #include <asm/pat.h>
  36 #include <asm/smp.h>
  37
  38 #ifdef CONFIG_X86_LOCAL_APIC
  39 #include <asm/uv/uv.h>
  40 #endif
  41
  42 #include "cpu.h"
  43
  44 #ifdef CONFIG_X86_64
  45
  46 /* all of these masks are initialized in setup_cpu_local_masks() */
  47 cpumask_var_t cpu_initialized_mask;
  48 cpumask_var_t cpu_callout_mask;
  49 cpumask_var_t cpu_callin_mask;
  50
  51 /* representing cpus for which sibling maps can be computed */
  52 cpumask_var_t cpu_sibling_setup_mask;
  53
  54 /* correctly size the local cpu masks */
  55 void __init setup_cpu_local_masks(void)
  56 {
  57         alloc_bootmem_cpumask_var(&cpu_initialized_mask);
  58         alloc_bootmem_cpumask_var(&cpu_callin_mask);
  59         alloc_bootmem_cpumask_var(&cpu_callout_mask);
  60         alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask);
  61 }
  62
  63 #else /* CONFIG_X86_32 */
  64
  65 cpumask_t cpu_sibling_setup_map;
  66 cpumask_t cpu_callout_map;
  67 cpumask_t cpu_initialized;
  68 cpumask_t cpu_callin_map;
  69
  70 #endif /* CONFIG_X86_32 */
  71
  72
  73 static struct cpu_dev *this_cpu __cpuinitdata;
  74
  75 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
  76 #ifdef CONFIG_X86_64
  77         /*
  78          * We need valid kernel segments for data and code in long mode too
  79          * IRET will check the segment types  kkeil 2000/10/28
  80          * Also sysret mandates a special GDT layout
  81          *
  82          * TLS descriptors are currently at a different place compared to i386.
  83          * Hopefully nobody expects them at a fixed place (Wine?)
  84          */
  85         [GDT_ENTRY_KERNEL32_CS]         = { { { 0x0000ffff, 0x00cf9b00 } } },
  86         [GDT_ENTRY_KERNEL_CS]           = { { { 0x0000ffff, 0x00af9b00 } } },
  87         [GDT_ENTRY_KERNEL_DS]           = { { { 0x0000ffff, 0x00cf9300 } } },
  88         [GDT_ENTRY_DEFAULT_USER32_CS]   = { { { 0x0000ffff, 0x00cffb00 } } },
  89         [GDT_ENTRY_DEFAULT_USER_DS]     = { { { 0x0000ffff, 0x00cff300 } } },
  90         [GDT_ENTRY_DEFAULT_USER_CS]     = { { { 0x0000ffff, 0x00affb00 } } },
  91 #else
  92         [GDT_ENTRY_KERNEL_CS]           = { { { 0x0000ffff, 0x00cf9a00 } } },
  93         [GDT_ENTRY_KERNEL_DS]           = { { { 0x0000ffff, 0x00cf9200 } } },
  94         [GDT_ENTRY_DEFAULT_USER_CS]     = { { { 0x0000ffff, 0x00cffa00 } } },
  95         [GDT_ENTRY_DEFAULT_USER_DS]     = { { { 0x0000ffff, 0x00cff200 } } },
  96         /*
  97          * Segments used for calling PnP BIOS have byte granularity.
  98          * They code segments and data segments have fixed 64k limits,
  99          * the transfer segment sizes are set at run time.
 100          */
 101         /* 32-bit code */
 102         [GDT_ENTRY_PNPBIOS_CS32]        = { { { 0x0000ffff, 0x00409a00 } } },
 103         /* 16-bit code */
 104         [GDT_ENTRY_PNPBIOS_CS16]        = { { { 0x0000ffff, 0x00009a00 } } },
 105         /* 16-bit data */
 106         [GDT_ENTRY_PNPBIOS_DS]          = { { { 0x0000ffff, 0x00009200 } } },
 107         /* 16-bit data */
 108         [GDT_ENTRY_PNPBIOS_TS1]         = { { { 0x00000000, 0x00009200 } } },
 109         /* 16-bit data */
 110         [GDT_ENTRY_PNPBIOS_TS2]         = { { { 0x00000000, 0x00009200 } } },
 111         /*
 112          * The APM segments have byte granularity and their bases
 113          * are set at run time.  All have 64k limits.
 114          */
 115         /* 32-bit code */
 116         [GDT_ENTRY_APMBIOS_BASE]        = { { { 0x0000ffff, 0x00409a00 } } },
 117         /* 16-bit code */
 118         [GDT_ENTRY_APMBIOS_BASE+1]      = { { { 0x0000ffff, 0x00009a00 } } },
 119         /* data */
 120         [GDT_ENTRY_APMBIOS_BASE+2]      = { { { 0x0000ffff, 0x00409200 } } },
 121
 122         [GDT_ENTRY_ESPFIX_SS]           = { { { 0x00000000, 0x00c09200 } } },
 123         [GDT_ENTRY_PERCPU]              = { { { 0x0000ffff, 0x00cf9200 } } },
 124         GDT_STACK_CANARY_INIT
 125 #endif
 126 } };
 127 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
 128
 129 #ifdef CONFIG_X86_32
 130 static int cachesize_override __cpuinitdata = -1;
 131 static int disable_x86_serial_nr __cpuinitdata = 1;
 132
 133 static int __init cachesize_setup(char *str)
 134 {
 135         get_option(&str, &cachesize_override);
 136         return 1;
 137 }
 138 __setup("cachesize=", cachesize_setup);
 139
 140 static int __init x86_fxsr_setup(char *s)
 141 {
 142         setup_clear_cpu_cap(X86_FEATURE_FXSR);
 143         setup_clear_cpu_cap(X86_FEATURE_XMM);
 144         return 1;
 145 }
 146 __setup("nofxsr", x86_fxsr_setup);
 147
 148 static int __init x86_sep_setup(char *s)
 149 {
 150         setup_clear_cpu_cap(X86_FEATURE_SEP);
 151         return 1;
 152 }
 153 __setup("nosep", x86_sep_setup);
 154
 155 /* Standard macro to see if a specific flag is changeable */
 156 static inline int flag_is_changeable_p(u32 flag)
 157 {
 158         u32 f1, f2;
 159
 160         /*
 161          * Cyrix and IDT cpus allow disabling of CPUID
 162          * so the code below may return different results
 163          * when it is executed before and after enabling
 164          * the CPUID. Add "volatile" to not allow gcc to
 165          * optimize the subsequent calls to this function.
 166          */
 167         asm volatile ("pushfl           \n\t"
 168                       "pushfl           \n\t"
 169                       "popl %0          \n\t"
 170                       "movl %0, %1      \n\t"
 171                       "xorl %2, %0      \n\t"
 172                       "pushl %0         \n\t"
 173                       "popfl            \n\t"
 174                       "pushfl           \n\t"
 175                       "popl %0          \n\t"
 176                       "popfl            \n\t"
 177
 178                       : "=&r" (f1), "=&r" (f2)
 179                       : "ir" (flag));
 180
 181         return ((f1^f2) & flag) != 0;
 182 }
 183
 184 /* Probe for the CPUID instruction */
 185 static int __cpuinit have_cpuid_p(void)
 186 {
 187         return flag_is_changeable_p(X86_EFLAGS_ID);
 188 }
 189
 190 static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
 191 {
 192         unsigned long lo, hi;
 193
 194         if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr)
 195                 return;
 196
 197         /* Disable processor serial number: */
 198
 199         rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
 200         lo |= 0x200000;
 201         wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
 202
 203         printk(KERN_NOTICE "CPU serial number disabled.\n");
 204         clear_cpu_cap(c, X86_FEATURE_PN);
 205
 206         /* Disabling the serial number may affect the cpuid level */
 207         c->cpuid_level = cpuid_eax(0);
 208 }
 209
 210 static int __init x86_serial_nr_setup(char *s)
 211 {
 212         disable_x86_serial_nr = 0;
 213         return 1;
 214 }
 215 __setup("serialnumber", x86_serial_nr_setup);
 216 #else
 217 static inline int flag_is_changeable_p(u32 flag)
 218 {
 219         return 1;
 220 }
 221 /* Probe for the CPUID instruction */
 222 static inline int have_cpuid_p(void)
 223 {
 224         return 1;
 225 }
 226 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
 227 {
 228 }
 229 #endif
 230
 231 /*
 232  * Some CPU features depend on higher CPUID levels, which may not always
 233  * be available due to CPUID level capping or broken virtualization
 234  * software.  Add those features to this table to auto-disable them.
 235  */
 236 struct cpuid_dependent_feature {
 237         u32 feature;
 238         u32 level;
 239 };
 240
 241 static const struct cpuid_dependent_feature __cpuinitconst
 242 cpuid_dependent_features[] = {
 243         { X86_FEATURE_MWAIT,            0x00000005 },
 244         { X86_FEATURE_DCA,              0x00000009 },
 245         { X86_FEATURE_XSAVE,            0x0000000d },
 246         { 0, 0 }
 247 };
 248
 249 static void __cpuinit filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
 250 {
 251         const struct cpuid_dependent_feature *df;
 252
 253         for (df = cpuid_dependent_features; df->feature; df++) {
 254
 255                 if (!cpu_has(c, df->feature))
 256                         continue;
 257                 /*
 258                  * Note: cpuid_level is set to -1 if unavailable, but
 259                  * extended_extended_level is set to 0 if unavailable
 260                  * and the legitimate extended levels are all negative
 261                  * when signed; hence the weird messing around with
 262                  * signs here...
 263                  */
 264                 if (!((s32)df->level < 0 ?
 265                      (u32)df->level > (u32)c->extended_cpuid_level :
 266                      (s32)df->level > (s32)c->cpuid_level))
 267                         continue;
 268
 269                 clear_cpu_cap(c, df->feature);
 270                 if (!warn)
 271                         continue;
 272
 273                 printk(KERN_WARNING
 274                        "CPU: CPU feature %s disabled, no CPUID level 0x%x\n",
 275                                 x86_cap_flags[df->feature], df->level);
 276         }
 277 }
 278
 279 /*
 280  * Naming convention should be: <Name> [(<Codename>)]
 281  * This table only is used unless init_<vendor>() below doesn't set it;
 282  * in particular, if CPUID levels 0x80000002..4 are supported, this
 283  * isn't used
 284  */
 285
 286 /* Look up CPU names by table lookup. */
 287 static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c)
 288 {
 289         struct cpu_model_info *info;
 290
 291         if (c->x86_model >= 16)
 292                 return NULL;    /* Range check */
 293
 294         if (!this_cpu)
 295                 return NULL;
 296
 297         info = this_cpu->c_models;
 298
 299         while (info && info->family) {
 300                 if (info->family == c->x86)
 301                         return info->model_names[c->x86_model];
 302                 info++;
 303         }
 304         return NULL;            /* Not found */
 305 }
 306
 307 __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata;
 308
 309 void load_percpu_segment(int cpu)
 310 {
 311 #ifdef CONFIG_X86_32
 312         loadsegment(fs, __KERNEL_PERCPU);
 313 #else
 314         loadsegment(gs, 0);
 315         wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu));
 316 #endif
 317         load_stack_canary_segment();
 318 }
 319
 320 /*
 321  * Current gdt points %fs at the "master" per-cpu area: after this,
 322  * it's on the real one.
 323  */
 324 void switch_to_new_gdt(int cpu)
 325 {
 326         struct desc_ptr gdt_descr;
 327
 328         gdt_descr.address = (long)get_cpu_gdt_table(cpu);
 329         gdt_descr.size = GDT_SIZE - 1;
 330         load_gdt(&gdt_descr);
 331         /* Reload the per-cpu base */
 332
 333         load_percpu_segment(cpu);
 334 }
 335
 336 static struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
 337
 338 static void __cpuinit default_init(struct cpuinfo_x86 *c)
 339 {
 340 #ifdef CONFIG_X86_64
 341         display_cacheinfo(c);
 342 #else
 343         /* Not much we can do here... */
 344         /* Check if at least it has cpuid */
 345         if (c->cpuid_level == -1) {
 346                 /* No cpuid. It must be an ancient CPU */
 347                 if (c->x86 == 4)
 348                         strcpy(c->x86_model_id, "486");
 349                 else if (c->x86 == 3)
 350                         strcpy(c->x86_model_id, "386");
 351         }
 352 #endif
 353 }
 354
 355 static struct cpu_dev __cpuinitdata default_cpu = {
 356         .c_init = default_init,
 357         .c_vendor = "Unknown",
 358         .c_x86_vendor = X86_VENDOR_UNKNOWN,
 359 };
 360
 361 static void __cpuinit get_model_name(struct cpuinfo_x86 *c)
 362 {
 363         unsigned int *v;
 364         char *p, *q;
 365
 366         if (c->extended_cpuid_level < 0x80000004)
 367                 return;
 368
 369         v = (unsigned int *)c->x86_model_id;
 370         cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
 371         cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
 372         cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
 373         c->x86_model_id[48] = 0;
 374
 375         /*
 376          * Intel chips right-justify this string for some dumb reason;
 377          * undo that brain damage:
 378          */
 379         p = q = &c->x86_model_id[0];
 380         while (*p == ' ')
 381                 p++;
 382         if (p != q) {
 383                 while (*p)
 384                         *q++ = *p++;
 385                 while (q <= &c->x86_model_id[48])
 386                         *q++ = '\0';    /* Zero-pad the rest */
 387         }
 388 }
 389
 390 void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
 391 {
 392         unsigned int n, dummy, ebx, ecx, edx, l2size;
 393
 394         n = c->extended_cpuid_level;
 395
 396         if (n >= 0x80000005) {
 397                 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
 398                 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
 399                                 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
 400                 c->x86_cache_size = (ecx>>24) + (edx>>24);
 401 #ifdef CONFIG_X86_64
 402                 /* On K8 L1 TLB is inclusive, so don't count it */
 403                 c->x86_tlbsize = 0;
 404 #endif
 405         }
 406
 407         if (n < 0x80000006)     /* Some chips just has a large L1. */
 408                 return;
 409
 410         cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
 411         l2size = ecx >> 16;
 412
 413 #ifdef CONFIG_X86_64
 414         c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
 415 #else
 416         /* do processor-specific cache resizing */
 417         if (this_cpu->c_size_cache)
 418                 l2size = this_cpu->c_size_cache(c, l2size);
 419
 420         /* Allow user to override all this if necessary. */
 421         if (cachesize_override != -1)
 422                 l2size = cachesize_override;
 423
 424         if (l2size == 0)
 425                 return;         /* Again, no L2 cache is possible */
 426 #endif
 427
 428         c->x86_cache_size = l2size;
 429
 430         printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
 431                         l2size, ecx & 0xFF);
 432 }
 433
 434 void __cpuinit detect_ht(struct cpuinfo_x86 *c)
 435 {
 436 #ifdef CONFIG_X86_HT
 437         u32 eax, ebx, ecx, edx;
 438         int index_msb, core_bits;
 439
 440         if (!cpu_has(c, X86_FEATURE_HT))
 441                 return;
 442
 443         if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
 444                 goto out;
 445
 446         if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
 447                 return;
 448
 449         cpuid(1, &eax, &ebx, &ecx, &edx);
 450
 451         smp_num_siblings = (ebx & 0xff0000) >> 16;
 452
 453         if (smp_num_siblings == 1) {
 454                 printk(KERN_INFO  "CPU: Hyper-Threading is disabled\n");
 455                 goto out;
 456         }
 457
 458         if (smp_num_siblings <= 1)
 459                 goto out;
 460
 461         if (smp_num_siblings > nr_cpu_ids) {
 462                 pr_warning("CPU: Unsupported number of siblings %d",
 463                            smp_num_siblings);
 464                 smp_num_siblings = 1;
 465                 return;
 466         }
 467
 468         index_msb = get_count_order(smp_num_siblings);
 469         c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb);
 470
 471         smp_num_siblings = smp_num_siblings / c->x86_max_cores;
 472
 473         index_msb = get_count_order(smp_num_siblings);
 474
 475         core_bits = get_count_order(c->x86_max_cores);
 476
 477         c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) &
 478                                        ((1 << core_bits) - 1);
 479
 480 out:
 481         if ((c->x86_max_cores * smp_num_siblings) > 1) {
 482                 printk(KERN_INFO  "CPU: Physical Processor ID: %d\n",
 483                        c->phys_proc_id);
 484                 printk(KERN_INFO  "CPU: Processor Core ID: %d\n",
 485                        c->cpu_core_id);
 486         }
 487 #endif
 488 }
 489
 490 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
 491 {
 492         char *v = c->x86_vendor_id;
 493         static int printed;
 494         int i;
 495
 496         for (i = 0; i < X86_VENDOR_NUM; i++) {
 497                 if (!cpu_devs[i])
 498                         break;
 499
 500                 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
 501                     (cpu_devs[i]->c_ident[1] &&
 502                      !strcmp(v, cpu_devs[i]->c_ident[1]))) {
 503
 504                         this_cpu = cpu_devs[i];
 505                         c->x86_vendor = this_cpu->c_x86_vendor;
 506                         return;
 507                 }
 508         }
 509
 510         if (!printed) {
 511                 printed++;
 512                 printk(KERN_ERR
 513                     "CPU: vendor_id '%s' unknown, using generic init.\n", v);
 514
 515                 printk(KERN_ERR "CPU: Your system may be unstable.\n");
 516         }
 517
 518         c->x86_vendor = X86_VENDOR_UNKNOWN;
 519         this_cpu = &default_cpu;
 520 }
 521
 522 void __cpuinit cpu_detect(struct cpuinfo_x86 *c)
 523 {
 524         /* Get vendor name */
 525         cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
 526               (unsigned int *)&c->x86_vendor_id[0],
 527               (unsigned int *)&c->x86_vendor_id[8],
 528               (unsigned int *)&c->x86_vendor_id[4]);
 529
 530         c->x86 = 4;
 531         /* Intel-defined flags: level 0x00000001 */
 532         if (c->cpuid_level >= 0x00000001) {
 533                 u32 junk, tfms, cap0, misc;
 534
 535                 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
 536                 c->x86 = (tfms >> 8) & 0xf;
 537                 c->x86_model = (tfms >> 4) & 0xf;
 538                 c->x86_mask = tfms & 0xf;
 539
 540                 if (c->x86 == 0xf)
 541                         c->x86 += (tfms >> 20) & 0xff;
 542                 if (c->x86 >= 0x6)
 543                         c->x86_model += ((tfms >> 16) & 0xf) << 4;
 544
 545                 if (cap0 & (1<<19)) {
 546                         c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
 547                         c->x86_cache_alignment = c->x86_clflush_size;
 548                 }
 549         }
 550 }
 551
 552 static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c)
 553 {
 554         u32 tfms, xlvl;
 555         u32 ebx;
 556
 557         /* Intel-defined flags: level 0x00000001 */
 558         if (c->cpuid_level >= 0x00000001) {
 559                 u32 capability, excap;
 560
 561                 cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
 562                 c->x86_capability[0] = capability;
 563                 c->x86_capability[4] = excap;
 564         }
 565
 566         /* AMD-defined flags: level 0x80000001 */
 567         xlvl = cpuid_eax(0x80000000);
 568         c->extended_cpuid_level = xlvl;
 569
 570         if ((xlvl & 0xffff0000) == 0x80000000) {
 571                 if (xlvl >= 0x80000001) {
 572                         c->x86_capability[1] = cpuid_edx(0x80000001);
 573                         c->x86_capability[6] = cpuid_ecx(0x80000001);
 574                 }
 575         }
 576
 577 #ifdef CONFIG_X86_64
 578         if (c->extended_cpuid_level >= 0x80000008) {
 579                 u32 eax = cpuid_eax(0x80000008);
 580
 581                 c->x86_virt_bits = (eax >> 8) & 0xff;
 582                 c->x86_phys_bits = eax & 0xff;
 583         }
 584 #endif
 585
 586         if (c->extended_cpuid_level >= 0x80000007)
 587                 c->x86_power = cpuid_edx(0x80000007);
 588
 589 }
 590
 591 static void __cpuinit identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
 592 {
 593 #ifdef CONFIG_X86_32
 594         int i;
 595
 596         /*
 597          * First of all, decide if this is a 486 or higher
 598          * It's a 486 if we can modify the AC flag
 599          */
 600         if (flag_is_changeable_p(X86_EFLAGS_AC))
 601                 c->x86 = 4;
 602         else
 603                 c->x86 = 3;
 604
 605         for (i = 0; i < X86_VENDOR_NUM; i++)
 606                 if (cpu_devs[i] && cpu_devs[i]->c_identify) {
 607                         c->x86_vendor_id[0] = 0;
 608                         cpu_devs[i]->c_identify(c);
 609                         if (c->x86_vendor_id[0]) {
 610                                 get_cpu_vendor(c);
 611                                 break;
 612                         }
 613                 }
 614 #endif
 615 }
 616
 617 /*
 618  * Do minimum CPU detection early.
 619  * Fields really needed: vendor, cpuid_level, family, model, mask,
 620  * cache alignment.
 621  * The others are not touched to avoid unwanted side effects.
 622  *
 623  * WARNING: this function is only called on the BP.  Don't add code here
 624  * that is supposed to run on all CPUs.
 625  */
 626 static void __init early_identify_cpu(struct cpuinfo_x86 *c)
 627 {
 628 #ifdef CONFIG_X86_64
 629         c->x86_clflush_size = 64;
 630 #else
 631         c->x86_clflush_size = 32;
 632 #endif
 633         c->x86_cache_alignment = c->x86_clflush_size;
 634
 635         memset(&c->x86_capability, 0, sizeof c->x86_capability);
 636         c->extended_cpuid_level = 0;
 637
 638         if (!have_cpuid_p())
 639                 identify_cpu_without_cpuid(c);
 640
 641         /* cyrix could have cpuid enabled via c_identify()*/
 642         if (!have_cpuid_p())
 643                 return;
 644
 645         cpu_detect(c);
 646
 647         get_cpu_vendor(c);
 648
 649         get_cpu_cap(c);
 650
 651         if (this_cpu->c_early_init)
 652                 this_cpu->c_early_init(c);
 653
 654 #ifdef CONFIG_SMP
 655         c->cpu_index = boot_cpu_id;
 656 #endif
 657         filter_cpuid_features(c, false);
 658 }
 659
 660 void __init early_cpu_init(void)
 661 {
 662         struct cpu_dev **cdev;
 663         int count = 0;
 664
 665         printk(KERN_INFO "KERNEL supported cpus:\n");
 666         for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
 667                 struct cpu_dev *cpudev = *cdev;
 668                 unsigned int j;
 669
 670                 if (count >= X86_VENDOR_NUM)
 671                         break;
 672                 cpu_devs[count] = cpudev;
 673                 count++;
 674
 675                 for (j = 0; j < 2; j++) {
 676                         if (!cpudev->c_ident[j])
 677                                 continue;
 678                         printk(KERN_INFO "  %s %s\n", cpudev->c_vendor,
 679                                 cpudev->c_ident[j]);
 680                 }
 681         }
 682
 683         early_identify_cpu(&boot_cpu_data);
 684 }
 685
 686 /*
 687  * The NOPL instruction is supposed to exist on all CPUs with
 688  * family >= 6; unfortunately, that's not true in practice because
 689  * of early VIA chips and (more importantly) broken virtualizers that
 690  * are not easy to detect.  In the latter case it doesn't even *fail*
 691  * reliably, so probing for it doesn't even work.  Disable it completely
 692  * unless we can find a reliable way to detect all the broken cases.
 693  */
 694 static void __cpuinit detect_nopl(struct cpuinfo_x86 *c)
 695 {
 696         clear_cpu_cap(c, X86_FEATURE_NOPL);
 697 }
 698
 699 static void __cpuinit generic_identify(struct cpuinfo_x86 *c)
 700 {
 701         c->extended_cpuid_level = 0;
 702
 703         if (!have_cpuid_p())
 704                 identify_cpu_without_cpuid(c);
 705
 706         /* cyrix could have cpuid enabled via c_identify()*/
 707         if (!have_cpuid_p())
 708                 return;
 709
 710         cpu_detect(c);
 711
 712         get_cpu_vendor(c);
 713
 714         get_cpu_cap(c);
 715
 716         if (c->cpuid_level >= 0x00000001) {
 717                 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
 718 #ifdef CONFIG_X86_32
 719 # ifdef CONFIG_X86_HT
 720                 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
 721 # else
 722                 c->apicid = c->initial_apicid;
 723 # endif
 724 #endif
 725
 726 #ifdef CONFIG_X86_HT
 727                 c->phys_proc_id = c->initial_apicid;
 728 #endif
 729         }
 730
 731         get_model_name(c); /* Default name */
 732
 733         init_scattered_cpuid_features(c);
 734         detect_nopl(c);
 735 }
 736
 737 /*
 738  * This does the hard work of actually picking apart the CPU stuff...
 739  */
 740 static void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
 741 {
 742         int i;
 743
 744         c->loops_per_jiffy = loops_per_jiffy;
 745         c->x86_cache_size = -1;
 746         c->x86_vendor = X86_VENDOR_UNKNOWN;
 747         c->x86_model = c->x86_mask = 0; /* So far unknown... */
 748         c->x86_vendor_id[0] = '\0'; /* Unset */
 749         c->x86_model_id[0] = '\0';  /* Unset */
 750         c->x86_max_cores = 1;
 751         c->x86_coreid_bits = 0;
 752 #ifdef CONFIG_X86_64
 753         c->x86_clflush_size = 64;
 754 #else
 755         c->cpuid_level = -1;    /* CPUID not detected */
 756         c->x86_clflush_size = 32;
 757 #endif
 758         c->x86_cache_alignment = c->x86_clflush_size;
 759         memset(&c->x86_capability, 0, sizeof c->x86_capability);
 760
 761         generic_identify(c);
 762
 763         if (this_cpu->c_identify)
 764                 this_cpu->c_identify(c);
 765
 766 #ifdef CONFIG_X86_64
 767         c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
 768 #endif
 769
 770         /*
 771          * Vendor-specific initialization.  In this section we
 772          * canonicalize the feature flags, meaning if there are
 773          * features a certain CPU supports which CPUID doesn't
 774          * tell us, CPUID claiming incorrect flags, or other bugs,
 775          * we handle them here.
 776          *
 777          * At the end of this section, c->x86_capability better
 778          * indicate the features this CPU genuinely supports!
 779          */
 780         if (this_cpu->c_init)
 781                 this_cpu->c_init(c);
 782
 783         /* Disable the PN if appropriate */
 784         squash_the_stupid_serial_number(c);
 785
 786         /*
 787          * The vendor-specific functions might have changed features.
 788          * Now we do "generic changes."
 789          */
 790
 791         /* Filter out anything that depends on CPUID levels we don't have */
 792         filter_cpuid_features(c, true);
 793
 794         /* If the model name is still unset, do table lookup. */
 795         if (!c->x86_model_id[0]) {
 796                 char *p;
 797                 p = table_lookup_model(c);
 798                 if (p)
 799                         strcpy(c->x86_model_id, p);
 800                 else
 801                         /* Last resort... */
 802                         sprintf(c->x86_model_id, "%02x/%02x",
 803                                 c->x86, c->x86_model);
 804         }
 805
 806 #ifdef CONFIG_X86_64
 807         detect_ht(c);
 808 #endif
 809
 810         init_hypervisor(c);
 811         /*
 812          * On SMP, boot_cpu_data holds the common feature set between
 813          * all CPUs; so make sure that we indicate which features are
 814          * common between the CPUs.  The first time this routine gets
 815          * executed, c == &boot_cpu_data.
 816          */
 817         if (c != &boot_cpu_data) {
 818                 /* AND the already accumulated flags with these */
 819                 for (i = 0; i < NCAPINTS; i++)
 820                         boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
 821         }
 822
 823         /* Clear all flags overriden by options */
 824         for (i = 0; i < NCAPINTS; i++)
 825                 c->x86_capability[i] &= ~cleared_cpu_caps[i];
 826
 827 #ifdef CONFIG_X86_MCE
 828         /* Init Machine Check Exception if available. */
 829         mcheck_init(c);
 830 #endif
 831
 832         select_idle_routine(c);
 833
 834 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
 835         numa_add_cpu(smp_processor_id());
 836 #endif
 837 }
 838
 839 #ifdef CONFIG_X86_64
 840 static void vgetcpu_set_mode(void)
 841 {
 842         if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP))
 843                 vgetcpu_mode = VGETCPU_RDTSCP;
 844         else
 845                 vgetcpu_mode = VGETCPU_LSL;
 846 }
 847 #endif
 848
 849 void __init identify_boot_cpu(void)
 850 {
 851         identify_cpu(&boot_cpu_data);
 852 #ifdef CONFIG_X86_32
 853         sysenter_setup();
 854         enable_sep_cpu();
 855 #else
 856         vgetcpu_set_mode();
 857 #endif
 858 }
 859
 860 void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
 861 {
 862         BUG_ON(c == &boot_cpu_data);
 863         identify_cpu(c);
 864 #ifdef CONFIG_X86_32
 865         enable_sep_cpu();
 866 #endif
 867         mtrr_ap_init();
 868 }
 869
 870 struct msr_range {
 871         unsigned        min;
 872         unsigned        max;
 873 };
 874
 875 static struct msr_range msr_range_array[] __cpuinitdata = {
 876         { 0x00000000, 0x00000418},
 877         { 0xc0000000, 0xc000040b},
 878         { 0xc0010000, 0xc0010142},
 879         { 0xc0011000, 0xc001103b},
 880 };
 881
 882 static void __cpuinit print_cpu_msr(void)
 883 {
 884         unsigned index_min, index_max;
 885         unsigned index;
 886         u64 val;
 887         int i;
 888
 889         for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) {
 890                 index_min = msr_range_array[i].min;
 891                 index_max = msr_range_array[i].max;
 892
 893                 for (index = index_min; index < index_max; index++) {
 894                         if (rdmsrl_amd_safe(index, &val))
 895                                 continue;
 896                         printk(KERN_INFO " MSR%08x: %016llx\n", index, val);
 897                 }
 898         }
 899 }
 900
 901 static int show_msr __cpuinitdata;
 902
 903 static __init int setup_show_msr(char *arg)
 904 {
 905         int num;
 906
 907         get_option(&arg, &num);
 908
 909         if (num > 0)
 910                 show_msr = num;
 911         return 1;
 912 }
 913 __setup("show_msr=", setup_show_msr);
 914
 915 static __init int setup_noclflush(char *arg)
 916 {
 917         setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
 918         return 1;
 919 }
 920 __setup("noclflush", setup_noclflush);
 921
 922 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
 923 {
 924         char *vendor = NULL;
 925
 926         if (c->x86_vendor < X86_VENDOR_NUM) {
 927                 vendor = this_cpu->c_vendor;
 928         } else {
 929                 if (c->cpuid_level >= 0)
 930                         vendor = c->x86_vendor_id;
 931         }
 932
 933         if (vendor && !strstr(c->x86_model_id, vendor))
 934                 printk(KERN_CONT "%s ", vendor);
 935
 936         if (c->x86_model_id[0])
 937                 printk(KERN_CONT "%s", c->x86_model_id);
 938         else
 939                 printk(KERN_CONT "%d86", c->x86);
 940
 941         if (c->x86_mask || c->cpuid_level >= 0)
 942                 printk(KERN_CONT " stepping %02x\n", c->x86_mask);
 943         else
 944                 printk(KERN_CONT "\n");
 945
 946 #ifdef CONFIG_SMP
 947         if (c->cpu_index < show_msr)
 948                 print_cpu_msr();
 949 #else
 950         if (show_msr)
 951                 print_cpu_msr();
 952 #endif
 953 }
 954
 955 static __init int setup_disablecpuid(char *arg)
 956 {
 957         int bit;
 958
 959         if (get_option(&arg, &bit) && bit < NCAPINTS*32)
 960                 setup_clear_cpu_cap(bit);
 961         else
 962                 return 0;
 963
 964         return 1;
 965 }
 966 __setup("clearcpuid=", setup_disablecpuid);
 967
 968 #ifdef CONFIG_X86_64
 969 struct desc_ptr idt_descr = { 256 * 16 - 1, (unsigned long) idt_table };
 970
 971 DEFINE_PER_CPU_FIRST(union irq_stack_union,
 972                      irq_stack_union) __aligned(PAGE_SIZE);
 973
 974 DEFINE_PER_CPU(char *, irq_stack_ptr) =
 975         init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64;
 976
 977 DEFINE_PER_CPU(unsigned long, kernel_stack) =
 978         (unsigned long)&init_thread_union - KERNEL_STACK_OFFSET + THREAD_SIZE;
 979 EXPORT_PER_CPU_SYMBOL(kernel_stack);
 980
 981 DEFINE_PER_CPU(unsigned int, irq_count) = -1;
 982
 983 /*
 984  * Special IST stacks which the CPU switches to when it calls
 985  * an IST-marked descriptor entry. Up to 7 stacks (hardware
 986  * limit), all of them are 4K, except the debug stack which
 987  * is 8K.
 988  */
 989 static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = {
 990           [0 ... N_EXCEPTION_STACKS - 1]        = EXCEPTION_STKSZ,
 991           [DEBUG_STACK - 1]                     = DEBUG_STKSZ
 992 };
 993
 994 static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks
 995         [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ])
 996         __aligned(PAGE_SIZE);
 997
 998 /* May not be marked __init: used by software suspend */
 999 void syscall_init(void)
1000 {
1001         /*
1002          * LSTAR and STAR live in a bit strange symbiosis.
1003          * They both write to the same internal register. STAR allows to
1004          * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip.
1005          */
1006         wrmsrl(MSR_STAR,  ((u64)__USER32_CS)<<48  | ((u64)__KERNEL_CS)<<32);
1007         wrmsrl(MSR_LSTAR, system_call);
1008         wrmsrl(MSR_CSTAR, ignore_sysret);
1009
1010 #ifdef CONFIG_IA32_EMULATION
1011         syscall32_cpu_init();
1012 #endif
1013
1014         /* Flags to clear on syscall */
1015         wrmsrl(MSR_SYSCALL_MASK,
1016                X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL);
1017 }
1018
1019 unsigned long kernel_eflags;
1020
1021 /*
1022  * Copies of the original ist values from the tss are only accessed during
1023  * debugging, no special alignment required.
1024  */
1025 DEFINE_PER_CPU(struct orig_ist, orig_ist);
1026
1027 #else   /* CONFIG_X86_64 */
1028
1029 #ifdef CONFIG_CC_STACKPROTECTOR
1030 DEFINE_PER_CPU(unsigned long, stack_canary);
1031 #endif
1032
1033 /* Make sure %fs and %gs are initialized properly in idle threads */
1034 struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs)
1035 {
1036         memset(regs, 0, sizeof(struct pt_regs));
1037         regs->fs = __KERNEL_PERCPU;
1038         regs->gs = __KERNEL_STACK_CANARY;
1039
1040         return regs;
1041 }
1042 #endif  /* CONFIG_X86_64 */
1043
1044 /*
1045  * Clear all 6 debug registers:
1046  */
1047 static void clear_all_debug_regs(void)
1048 {
1049         int i;
1050
1051         for (i = 0; i < 8; i++) {
1052                 /* Ignore db4, db5 */
1053                 if ((i == 4) || (i == 5))
1054                         continue;
1055
1056                 set_debugreg(0, i);
1057         }
1058 }
1059
1060 /*
1061  * cpu_init() initializes state that is per-CPU. Some data is already
1062  * initialized (naturally) in the bootstrap process, such as the GDT
1063  * and IDT. We reload them nevertheless, this function acts as a
1064  * 'CPU state barrier', nothing should get across.
1065  * A lot of state is already set up in PDA init for 64 bit
1066  */
1067 #ifdef CONFIG_X86_64
1068
1069 void __cpuinit cpu_init(void)
1070 {
1071         struct orig_ist *orig_ist;
1072         struct task_struct *me;
1073         struct tss_struct *t;
1074         unsigned long v;
1075         int cpu;
1076         int i;
1077
1078         cpu = stack_smp_processor_id();
1079         t = &per_cpu(init_tss, cpu);
1080         orig_ist = &per_cpu(orig_ist, cpu);
1081
1082 #ifdef CONFIG_NUMA
1083         if (cpu != 0 && percpu_read(node_number) == 0 &&
1084             cpu_to_node(cpu) != NUMA_NO_NODE)
1085                 percpu_write(node_number, cpu_to_node(cpu));
1086 #endif
1087
1088         me = current;
1089
1090         if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask))
1091                 panic("CPU#%d already initialized!\n", cpu);
1092
1093         printk(KERN_INFO "Initializing CPU#%d\n", cpu);
1094
1095         clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1096
1097         /*
1098          * Initialize the per-CPU GDT with the boot GDT,
1099          * and set up the GDT descriptor:
1100          */
1101
1102         switch_to_new_gdt(cpu);
1103         loadsegment(fs, 0);
1104
1105         load_idt((const struct desc_ptr *)&idt_descr);
1106
1107         memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
1108         syscall_init();
1109
1110         wrmsrl(MSR_FS_BASE, 0);
1111         wrmsrl(MSR_KERNEL_GS_BASE, 0);
1112         barrier();
1113
1114         check_efer();
1115         if (cpu != 0)
1116                 enable_x2apic();
1117
1118         /*
1119          * set up and load the per-CPU TSS
1120          */
1121         if (!orig_ist->ist[0]) {
1122                 char *estacks = per_cpu(exception_stacks, cpu);
1123
1124                 for (v = 0; v < N_EXCEPTION_STACKS; v++) {
1125                         estacks += exception_stack_sizes[v];
1126                         orig_ist->ist[v] = t->x86_tss.ist[v] =
1127                                         (unsigned long)estacks;
1128                 }
1129         }
1130
1131         t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1132
1133         /*
1134          * <= is required because the CPU will access up to
1135          * 8 bits beyond the end of the IO permission bitmap.
1136          */
1137         for (i = 0; i <= IO_BITMAP_LONGS; i++)
1138                 t->io_bitmap[i] = ~0UL;
1139
1140         atomic_inc(&init_mm.mm_count);
1141         me->active_mm = &init_mm;
1142         if (me->mm)
1143                 BUG();
1144         enter_lazy_tlb(&init_mm, me);
1145
1146         load_sp0(t, &current->thread);
1147         set_tss_desc(cpu, t);
1148         load_TR_desc();
1149         load_LDT(&init_mm.context);
1150
1151 #ifdef CONFIG_KGDB
1152         /*
1153          * If the kgdb is connected no debug regs should be altered.  This
1154          * is only applicable when KGDB and a KGDB I/O module are built
1155          * into the kernel and you are using early debugging with
1156          * kgdbwait. KGDB will control the kernel HW breakpoint registers.
1157          */
1158         if (kgdb_connected && arch_kgdb_ops.correct_hw_break)
1159                 arch_kgdb_ops.correct_hw_break();
1160         else
1161 #endif
1162                 clear_all_debug_regs();
1163
1164         fpu_init();
1165
1166         raw_local_save_flags(kernel_eflags);
1167
1168         if (is_uv_system())
1169                 uv_cpu_init();
1170 }
1171
1172 #else
1173
1174 void __cpuinit cpu_init(void)
1175 {
1176         int cpu = smp_processor_id();
1177         struct task_struct *curr = current;
1178         struct tss_struct *t = &per_cpu(init_tss, cpu);
1179         struct thread_struct *thread = &curr->thread;
1180
1181         if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) {
1182                 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu);
1183                 for (;;)
1184                         local_irq_enable();
1185         }
1186
1187         printk(KERN_INFO "Initializing CPU#%d\n", cpu);
1188
1189         if (cpu_has_vme || cpu_has_tsc || cpu_has_de)
1190                 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1191
1192         load_idt(&idt_descr);
1193         switch_to_new_gdt(cpu);
1194
1195         /*
1196          * Set up and load the per-CPU TSS and LDT
1197          */
1198         atomic_inc(&init_mm.mm_count);
1199         curr->active_mm = &init_mm;
1200         if (curr->mm)
1201                 BUG();
1202         enter_lazy_tlb(&init_mm, curr);
1203
1204         load_sp0(t, thread);
1205         set_tss_desc(cpu, t);
1206         load_TR_desc();
1207         load_LDT(&init_mm.context);
1208
1209 #ifdef CONFIG_DOUBLEFAULT
1210         /* Set up doublefault TSS pointer in the GDT */
1211         __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
1212 #endif
1213
1214         clear_all_debug_regs();
1215
1216         /*
1217          * Force FPU initialization:
1218          */
1219         if (cpu_has_xsave)
1220                 current_thread_info()->status = TS_XSAVE;
1221         else
1222                 current_thread_info()->status = 0;
1223         clear_used_math();
1224         mxcsr_feature_mask_init();
1225
1226         /*
1227          * Boot processor to setup the FP and extended state context info.
1228          */
1229         if (smp_processor_id() == boot_cpu_id)
1230                 init_thread_xstate();
1231
1232         xsave_init();
1233 }
1234 #endif