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[POWERPC] Add workaround for MPICs with broken register reads
[linux-2.6/libata-dev.git] / arch / powerpc / sysdev / mpic.c
blob8de29f28b4c7a6da03f749760b7777dc7356977b
1 /*
2 * arch/powerpc/kernel/mpic.c
3 *
4 * Driver for interrupt controllers following the OpenPIC standard, the
5 * common implementation beeing IBM's MPIC. This driver also can deal
6 * with various broken implementations of this HW.
7 *
8 * Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp.
9 *
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file COPYING in the main directory of this archive
12 * for more details.
13 */
14
15 #undef DEBUG
16 #undef DEBUG_IPI
17 #undef DEBUG_IRQ
18 #undef DEBUG_LOW
19
20 #include <linux/types.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/irq.h>
24 #include <linux/smp.h>
25 #include <linux/interrupt.h>
26 #include <linux/bootmem.h>
27 #include <linux/spinlock.h>
28 #include <linux/pci.h>
29
30 #include <asm/ptrace.h>
31 #include <asm/signal.h>
32 #include <asm/io.h>
33 #include <asm/pgtable.h>
34 #include <asm/irq.h>
35 #include <asm/machdep.h>
36 #include <asm/mpic.h>
37 #include <asm/smp.h>
38
39 #include "mpic.h"
40
41 #ifdef DEBUG
42 #define DBG(fmt...) printk(fmt)
43 #else
44 #define DBG(fmt...)
45 #endif
46
47 static struct mpic *mpics;
48 static struct mpic *mpic_primary;
49 static DEFINE_SPINLOCK(mpic_lock);
50
51 #ifdef CONFIG_PPC32 /* XXX for now */
52 #ifdef CONFIG_IRQ_ALL_CPUS
53 #define distribute_irqs (1)
54 #else
55 #define distribute_irqs (0)
56 #endif
57 #endif
58
59 #ifdef CONFIG_MPIC_WEIRD
60 static u32 mpic_infos[][MPIC_IDX_END] = {
61 [0] = { /* Original OpenPIC compatible MPIC */
62 MPIC_GREG_BASE,
63 MPIC_GREG_FEATURE_0,
64 MPIC_GREG_GLOBAL_CONF_0,
65 MPIC_GREG_VENDOR_ID,
66 MPIC_GREG_IPI_VECTOR_PRI_0,
67 MPIC_GREG_IPI_STRIDE,
68 MPIC_GREG_SPURIOUS,
69 MPIC_GREG_TIMER_FREQ,
70
71 MPIC_TIMER_BASE,
72 MPIC_TIMER_STRIDE,
73 MPIC_TIMER_CURRENT_CNT,
74 MPIC_TIMER_BASE_CNT,
75 MPIC_TIMER_VECTOR_PRI,
76 MPIC_TIMER_DESTINATION,
77
78 MPIC_CPU_BASE,
79 MPIC_CPU_STRIDE,
80 MPIC_CPU_IPI_DISPATCH_0,
81 MPIC_CPU_IPI_DISPATCH_STRIDE,
82 MPIC_CPU_CURRENT_TASK_PRI,
83 MPIC_CPU_WHOAMI,
84 MPIC_CPU_INTACK,
85 MPIC_CPU_EOI,
86
87 MPIC_IRQ_BASE,
88 MPIC_IRQ_STRIDE,
89 MPIC_IRQ_VECTOR_PRI,
90 MPIC_VECPRI_VECTOR_MASK,
91 MPIC_VECPRI_POLARITY_POSITIVE,
92 MPIC_VECPRI_POLARITY_NEGATIVE,
93 MPIC_VECPRI_SENSE_LEVEL,
94 MPIC_VECPRI_SENSE_EDGE,
95 MPIC_VECPRI_POLARITY_MASK,
96 MPIC_VECPRI_SENSE_MASK,
97 MPIC_IRQ_DESTINATION
98 },
99 [1] = { /* Tsi108/109 PIC */
100 TSI108_GREG_BASE,
101 TSI108_GREG_FEATURE_0,
102 TSI108_GREG_GLOBAL_CONF_0,
103 TSI108_GREG_VENDOR_ID,
104 TSI108_GREG_IPI_VECTOR_PRI_0,
105 TSI108_GREG_IPI_STRIDE,
106 TSI108_GREG_SPURIOUS,
107 TSI108_GREG_TIMER_FREQ,
108
109 TSI108_TIMER_BASE,
110 TSI108_TIMER_STRIDE,
111 TSI108_TIMER_CURRENT_CNT,
112 TSI108_TIMER_BASE_CNT,
113 TSI108_TIMER_VECTOR_PRI,
114 TSI108_TIMER_DESTINATION,
115
116 TSI108_CPU_BASE,
117 TSI108_CPU_STRIDE,
118 TSI108_CPU_IPI_DISPATCH_0,
119 TSI108_CPU_IPI_DISPATCH_STRIDE,
120 TSI108_CPU_CURRENT_TASK_PRI,
121 TSI108_CPU_WHOAMI,
122 TSI108_CPU_INTACK,
123 TSI108_CPU_EOI,
124
125 TSI108_IRQ_BASE,
126 TSI108_IRQ_STRIDE,
127 TSI108_IRQ_VECTOR_PRI,
128 TSI108_VECPRI_VECTOR_MASK,
129 TSI108_VECPRI_POLARITY_POSITIVE,
130 TSI108_VECPRI_POLARITY_NEGATIVE,
131 TSI108_VECPRI_SENSE_LEVEL,
132 TSI108_VECPRI_SENSE_EDGE,
133 TSI108_VECPRI_POLARITY_MASK,
134 TSI108_VECPRI_SENSE_MASK,
135 TSI108_IRQ_DESTINATION
136 },
137 };
138
139 #define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name]
140
141 #else /* CONFIG_MPIC_WEIRD */
142
143 #define MPIC_INFO(name) MPIC_##name
144
145 #endif /* CONFIG_MPIC_WEIRD */
146
147 /*
148 * Register accessor functions
149 */
150
151
152 static inline u32 _mpic_read(enum mpic_reg_type type,
153 struct mpic_reg_bank *rb,
154 unsigned int reg)
155 {
156 switch(type) {
157 #ifdef CONFIG_PPC_DCR
158 case mpic_access_dcr:
159 return dcr_read(rb->dhost,
160 rb->dbase + reg + rb->doff);
161 #endif
162 case mpic_access_mmio_be:
163 return in_be32(rb->base + (reg >> 2));
164 case mpic_access_mmio_le:
165 default:
166 return in_le32(rb->base + (reg >> 2));
167 }
168 }
169
170 static inline void _mpic_write(enum mpic_reg_type type,
171 struct mpic_reg_bank *rb,
172 unsigned int reg, u32 value)
173 {
174 switch(type) {
175 #ifdef CONFIG_PPC_DCR
176 case mpic_access_dcr:
177 return dcr_write(rb->dhost,
178 rb->dbase + reg + rb->doff, value);
179 #endif
180 case mpic_access_mmio_be:
181 return out_be32(rb->base + (reg >> 2), value);
182 case mpic_access_mmio_le:
183 default:
184 return out_le32(rb->base + (reg >> 2), value);
185 }
186 }
187
188 static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)
189 {
190 enum mpic_reg_type type = mpic->reg_type;
191 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
192 (ipi * MPIC_INFO(GREG_IPI_STRIDE));
193
194 if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le)
195 type = mpic_access_mmio_be;
196 return _mpic_read(type, &mpic->gregs, offset);
197 }
198
199 static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value)
200 {
201 unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
202 (ipi * MPIC_INFO(GREG_IPI_STRIDE));
203
204 _mpic_write(mpic->reg_type, &mpic->gregs, offset, value);
205 }
206
207 static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg)
208 {
209 unsigned int cpu = 0;
210
211 if (mpic->flags & MPIC_PRIMARY)
212 cpu = hard_smp_processor_id();
213 return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg);
214 }
215
216 static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value)
217 {
218 unsigned int cpu = 0;
219
220 if (mpic->flags & MPIC_PRIMARY)
221 cpu = hard_smp_processor_id();
222
223 _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value);
224 }
225
226 static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg)
227 {
228 unsigned int isu = src_no >> mpic->isu_shift;
229 unsigned int idx = src_no & mpic->isu_mask;
230
231 #ifdef CONFIG_MPIC_BROKEN_REGREAD
232 if (reg == 0)
233 return mpic->isu_reg0_shadow[idx];
234 else
235 #endif
236 return _mpic_read(mpic->reg_type, &mpic->isus[isu],
237 reg + (idx * MPIC_INFO(IRQ_STRIDE)));
238 }
239
240 static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
241 unsigned int reg, u32 value)
242 {
243 unsigned int isu = src_no >> mpic->isu_shift;
244 unsigned int idx = src_no & mpic->isu_mask;
245
246 _mpic_write(mpic->reg_type, &mpic->isus[isu],
247 reg + (idx * MPIC_INFO(IRQ_STRIDE)), value);
248
249 #ifdef CONFIG_MPIC_BROKEN_REGREAD
250 if (reg == 0)
251 mpic->isu_reg0_shadow[idx] = value;
252 #endif
253 }
254
255 #define mpic_read(b,r) _mpic_read(mpic->reg_type,&(b),(r))
256 #define mpic_write(b,r,v) _mpic_write(mpic->reg_type,&(b),(r),(v))
257 #define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i))
258 #define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v))
259 #define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i))
260 #define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v))
261 #define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r))
262 #define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v))
263
264
265 /*
266 * Low level utility functions
267 */
268
269
270 static void _mpic_map_mmio(struct mpic *mpic, unsigned long phys_addr,
271 struct mpic_reg_bank *rb, unsigned int offset,
272 unsigned int size)
273 {
274 rb->base = ioremap(phys_addr + offset, size);
275 BUG_ON(rb->base == NULL);
276 }
277
278 #ifdef CONFIG_PPC_DCR
279 static void _mpic_map_dcr(struct mpic *mpic, struct mpic_reg_bank *rb,
280 unsigned int offset, unsigned int size)
281 {
282 rb->dbase = mpic->dcr_base;
283 rb->doff = offset;
284 rb->dhost = dcr_map(mpic->irqhost->of_node, rb->dbase + rb->doff, size);
285 BUG_ON(!DCR_MAP_OK(rb->dhost));
286 }
287
288 static inline void mpic_map(struct mpic *mpic, unsigned long phys_addr,
289 struct mpic_reg_bank *rb, unsigned int offset,
290 unsigned int size)
291 {
292 if (mpic->flags & MPIC_USES_DCR)
293 _mpic_map_dcr(mpic, rb, offset, size);
294 else
295 _mpic_map_mmio(mpic, phys_addr, rb, offset, size);
296 }
297 #else /* CONFIG_PPC_DCR */
298 #define mpic_map(m,p,b,o,s) _mpic_map_mmio(m,p,b,o,s)
299 #endif /* !CONFIG_PPC_DCR */
300
301
302
303 /* Check if we have one of those nice broken MPICs with a flipped endian on
304 * reads from IPI registers
305 */
306 static void __init mpic_test_broken_ipi(struct mpic *mpic)
307 {
308 u32 r;
309
310 mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK);
311 r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0));
312
313 if (r == le32_to_cpu(MPIC_VECPRI_MASK)) {
314 printk(KERN_INFO "mpic: Detected reversed IPI registers\n");
315 mpic->flags |= MPIC_BROKEN_IPI;
316 }
317 }
318
319 #ifdef CONFIG_MPIC_U3_HT_IRQS
320
321 /* Test if an interrupt is sourced from HyperTransport (used on broken U3s)
322 * to force the edge setting on the MPIC and do the ack workaround.
323 */
324 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
325 {
326 if (source >= 128 || !mpic->fixups)
327 return 0;
328 return mpic->fixups[source].base != NULL;
329 }
330
331
332 static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source)
333 {
334 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
335
336 if (fixup->applebase) {
337 unsigned int soff = (fixup->index >> 3) & ~3;
338 unsigned int mask = 1U << (fixup->index & 0x1f);
339 writel(mask, fixup->applebase + soff);
340 } else {
341 spin_lock(&mpic->fixup_lock);
342 writeb(0x11 + 2 * fixup->index, fixup->base + 2);
343 writel(fixup->data, fixup->base + 4);
344 spin_unlock(&mpic->fixup_lock);
345 }
346 }
347
348 static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source,
349 unsigned int irqflags)
350 {
351 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
352 unsigned long flags;
353 u32 tmp;
354
355 if (fixup->base == NULL)
356 return;
357
358 DBG("startup_ht_interrupt(0x%x, 0x%x) index: %d\n",
359 source, irqflags, fixup->index);
360 spin_lock_irqsave(&mpic->fixup_lock, flags);
361 /* Enable and configure */
362 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
363 tmp = readl(fixup->base + 4);
364 tmp &= ~(0x23U);
365 if (irqflags & IRQ_LEVEL)
366 tmp |= 0x22;
367 writel(tmp, fixup->base + 4);
368 spin_unlock_irqrestore(&mpic->fixup_lock, flags);
369
370 #ifdef CONFIG_PM
371 /* use the lowest bit inverted to the actual HW,
372 * set if this fixup was enabled, clear otherwise */
373 mpic->save_data[source].fixup_data = tmp | 1;
374 #endif
375 }
376
377 static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source,
378 unsigned int irqflags)
379 {
380 struct mpic_irq_fixup *fixup = &mpic->fixups[source];
381 unsigned long flags;
382 u32 tmp;
383
384 if (fixup->base == NULL)
385 return;
386
387 DBG("shutdown_ht_interrupt(0x%x, 0x%x)\n", source, irqflags);
388
389 /* Disable */
390 spin_lock_irqsave(&mpic->fixup_lock, flags);
391 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
392 tmp = readl(fixup->base + 4);
393 tmp |= 1;
394 writel(tmp, fixup->base + 4);
395 spin_unlock_irqrestore(&mpic->fixup_lock, flags);
396
397 #ifdef CONFIG_PM
398 /* use the lowest bit inverted to the actual HW,
399 * set if this fixup was enabled, clear otherwise */
400 mpic->save_data[source].fixup_data = tmp & ~1;
401 #endif
402 }
403
404 #ifdef CONFIG_PCI_MSI
405 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
406 unsigned int devfn)
407 {
408 u8 __iomem *base;
409 u8 pos, flags;
410 u64 addr = 0;
411
412 for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
413 pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
414 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
415 if (id == PCI_CAP_ID_HT) {
416 id = readb(devbase + pos + 3);
417 if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_MSI_MAPPING)
418 break;
419 }
420 }
421
422 if (pos == 0)
423 return;
424
425 base = devbase + pos;
426
427 flags = readb(base + HT_MSI_FLAGS);
428 if (!(flags & HT_MSI_FLAGS_FIXED)) {
429 addr = readl(base + HT_MSI_ADDR_LO) & HT_MSI_ADDR_LO_MASK;
430 addr = addr | ((u64)readl(base + HT_MSI_ADDR_HI) << 32);
431 }
432
433 printk(KERN_DEBUG "mpic: - HT:%02x.%x %s MSI mapping found @ 0x%lx\n",
434 PCI_SLOT(devfn), PCI_FUNC(devfn),
435 flags & HT_MSI_FLAGS_ENABLE ? "enabled" : "disabled", addr);
436
437 if (!(flags & HT_MSI_FLAGS_ENABLE))
438 writeb(flags | HT_MSI_FLAGS_ENABLE, base + HT_MSI_FLAGS);
439 }
440 #else
441 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
442 unsigned int devfn)
443 {
444 return;
445 }
446 #endif
447
448 static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase,
449 unsigned int devfn, u32 vdid)
450 {
451 int i, irq, n;
452 u8 __iomem *base;
453 u32 tmp;
454 u8 pos;
455
456 for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
457 pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
458 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
459 if (id == PCI_CAP_ID_HT) {
460 id = readb(devbase + pos + 3);
461 if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_IRQ)
462 break;
463 }
464 }
465 if (pos == 0)
466 return;
467
468 base = devbase + pos;
469 writeb(0x01, base + 2);
470 n = (readl(base + 4) >> 16) & 0xff;
471
472 printk(KERN_INFO "mpic: - HT:%02x.%x [0x%02x] vendor %04x device %04x"
473 " has %d irqs\n",
474 devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1);
475
476 for (i = 0; i <= n; i++) {
477 writeb(0x10 + 2 * i, base + 2);
478 tmp = readl(base + 4);
479 irq = (tmp >> 16) & 0xff;
480 DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp);
481 /* mask it , will be unmasked later */
482 tmp |= 0x1;
483 writel(tmp, base + 4);
484 mpic->fixups[irq].index = i;
485 mpic->fixups[irq].base = base;
486 /* Apple HT PIC has a non-standard way of doing EOIs */
487 if ((vdid & 0xffff) == 0x106b)
488 mpic->fixups[irq].applebase = devbase + 0x60;
489 else
490 mpic->fixups[irq].applebase = NULL;
491 writeb(0x11 + 2 * i, base + 2);
492 mpic->fixups[irq].data = readl(base + 4) | 0x80000000;
493 }
494 }
495
496
497 static void __init mpic_scan_ht_pics(struct mpic *mpic)
498 {
499 unsigned int devfn;
500 u8 __iomem *cfgspace;
501
502 printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n");
503
504 /* Allocate fixups array */
505 mpic->fixups = alloc_bootmem(128 * sizeof(struct mpic_irq_fixup));
506 BUG_ON(mpic->fixups == NULL);
507 memset(mpic->fixups, 0, 128 * sizeof(struct mpic_irq_fixup));
508
509 /* Init spinlock */
510 spin_lock_init(&mpic->fixup_lock);
511
512 /* Map U3 config space. We assume all IO-APICs are on the primary bus
513 * so we only need to map 64kB.
514 */
515 cfgspace = ioremap(0xf2000000, 0x10000);
516 BUG_ON(cfgspace == NULL);
517
518 /* Now we scan all slots. We do a very quick scan, we read the header
519 * type, vendor ID and device ID only, that's plenty enough
520 */
521 for (devfn = 0; devfn < 0x100; devfn++) {
522 u8 __iomem *devbase = cfgspace + (devfn << 8);
523 u8 hdr_type = readb(devbase + PCI_HEADER_TYPE);
524 u32 l = readl(devbase + PCI_VENDOR_ID);
525 u16 s;
526
527 DBG("devfn %x, l: %x\n", devfn, l);
528
529 /* If no device, skip */
530 if (l == 0xffffffff || l == 0x00000000 ||
531 l == 0x0000ffff || l == 0xffff0000)
532 goto next;
533 /* Check if is supports capability lists */
534 s = readw(devbase + PCI_STATUS);
535 if (!(s & PCI_STATUS_CAP_LIST))
536 goto next;
537
538 mpic_scan_ht_pic(mpic, devbase, devfn, l);
539 mpic_scan_ht_msi(mpic, devbase, devfn);
540
541 next:
542 /* next device, if function 0 */
543 if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0)
544 devfn += 7;
545 }
546 }
547
548 #else /* CONFIG_MPIC_U3_HT_IRQS */
549
550 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
551 {
552 return 0;
553 }
554
555 static void __init mpic_scan_ht_pics(struct mpic *mpic)
556 {
557 }
558
559 #endif /* CONFIG_MPIC_U3_HT_IRQS */
560
561
562 #define mpic_irq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq)
563
564 /* Find an mpic associated with a given linux interrupt */
565 static struct mpic *mpic_find(unsigned int irq, unsigned int *is_ipi)
566 {
567 unsigned int src = mpic_irq_to_hw(irq);
568 struct mpic *mpic;
569
570 if (irq < NUM_ISA_INTERRUPTS)
571 return NULL;
572
573 mpic = irq_desc[irq].chip_data;
574
575 if (is_ipi)
576 *is_ipi = (src >= mpic->ipi_vecs[0] &&
577 src <= mpic->ipi_vecs[3]);
578
579 return mpic;
580 }
581
582 /* Convert a cpu mask from logical to physical cpu numbers. */
583 static inline u32 mpic_physmask(u32 cpumask)
584 {
585 int i;
586 u32 mask = 0;
587
588 for (i = 0; i < NR_CPUS; ++i, cpumask >>= 1)
589 mask |= (cpumask & 1) << get_hard_smp_processor_id(i);
590 return mask;
591 }
592
593 #ifdef CONFIG_SMP
594 /* Get the mpic structure from the IPI number */
595 static inline struct mpic * mpic_from_ipi(unsigned int ipi)
596 {
597 return irq_desc[ipi].chip_data;
598 }
599 #endif
600
601 /* Get the mpic structure from the irq number */
602 static inline struct mpic * mpic_from_irq(unsigned int irq)
603 {
604 return irq_desc[irq].chip_data;
605 }
606
607 /* Send an EOI */
608 static inline void mpic_eoi(struct mpic *mpic)
609 {
610 mpic_cpu_write(MPIC_INFO(CPU_EOI), 0);
611 (void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI));
612 }
613
614 #ifdef CONFIG_SMP
615 static irqreturn_t mpic_ipi_action(int irq, void *dev_id)
616 {
617 struct mpic *mpic;
618
619 mpic = mpic_find(irq, NULL);
620 smp_message_recv(mpic_irq_to_hw(irq) - mpic->ipi_vecs[0]);
621
622 return IRQ_HANDLED;
623 }
624 #endif /* CONFIG_SMP */
625
626 /*
627 * Linux descriptor level callbacks
628 */
629
630
631 void mpic_unmask_irq(unsigned int irq)
632 {
633 unsigned int loops = 100000;
634 struct mpic *mpic = mpic_from_irq(irq);
635 unsigned int src = mpic_irq_to_hw(irq);
636
637 DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, irq, src);
638
639 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
640 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) &
641 ~MPIC_VECPRI_MASK);
642 /* make sure mask gets to controller before we return to user */
643 do {
644 if (!loops--) {
645 printk(KERN_ERR "mpic_enable_irq timeout\n");
646 break;
647 }
648 } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK);
649 }
650
651 void mpic_mask_irq(unsigned int irq)
652 {
653 unsigned int loops = 100000;
654 struct mpic *mpic = mpic_from_irq(irq);
655 unsigned int src = mpic_irq_to_hw(irq);
656
657 DBG("%s: disable_irq: %d (src %d)\n", mpic->name, irq, src);
658
659 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
660 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) |
661 MPIC_VECPRI_MASK);
662
663 /* make sure mask gets to controller before we return to user */
664 do {
665 if (!loops--) {
666 printk(KERN_ERR "mpic_enable_irq timeout\n");
667 break;
668 }
669 } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK));
670 }
671
672 void mpic_end_irq(unsigned int irq)
673 {
674 struct mpic *mpic = mpic_from_irq(irq);
675
676 #ifdef DEBUG_IRQ
677 DBG("%s: end_irq: %d\n", mpic->name, irq);
678 #endif
679 /* We always EOI on end_irq() even for edge interrupts since that
680 * should only lower the priority, the MPIC should have properly
681 * latched another edge interrupt coming in anyway
682 */
683
684 mpic_eoi(mpic);
685 }
686
687 #ifdef CONFIG_MPIC_U3_HT_IRQS
688
689 static void mpic_unmask_ht_irq(unsigned int irq)
690 {
691 struct mpic *mpic = mpic_from_irq(irq);
692 unsigned int src = mpic_irq_to_hw(irq);
693
694 mpic_unmask_irq(irq);
695
696 if (irq_desc[irq].status & IRQ_LEVEL)
697 mpic_ht_end_irq(mpic, src);
698 }
699
700 static unsigned int mpic_startup_ht_irq(unsigned int irq)
701 {
702 struct mpic *mpic = mpic_from_irq(irq);
703 unsigned int src = mpic_irq_to_hw(irq);
704
705 mpic_unmask_irq(irq);
706 mpic_startup_ht_interrupt(mpic, src, irq_desc[irq].status);
707
708 return 0;
709 }
710
711 static void mpic_shutdown_ht_irq(unsigned int irq)
712 {
713 struct mpic *mpic = mpic_from_irq(irq);
714 unsigned int src = mpic_irq_to_hw(irq);
715
716 mpic_shutdown_ht_interrupt(mpic, src, irq_desc[irq].status);
717 mpic_mask_irq(irq);
718 }
719
720 static void mpic_end_ht_irq(unsigned int irq)
721 {
722 struct mpic *mpic = mpic_from_irq(irq);
723 unsigned int src = mpic_irq_to_hw(irq);
724
725 #ifdef DEBUG_IRQ
726 DBG("%s: end_irq: %d\n", mpic->name, irq);
727 #endif
728 /* We always EOI on end_irq() even for edge interrupts since that
729 * should only lower the priority, the MPIC should have properly
730 * latched another edge interrupt coming in anyway
731 */
732
733 if (irq_desc[irq].status & IRQ_LEVEL)
734 mpic_ht_end_irq(mpic, src);
735 mpic_eoi(mpic);
736 }
737 #endif /* !CONFIG_MPIC_U3_HT_IRQS */
738
739 #ifdef CONFIG_SMP
740
741 static void mpic_unmask_ipi(unsigned int irq)
742 {
743 struct mpic *mpic = mpic_from_ipi(irq);
744 unsigned int src = mpic_irq_to_hw(irq) - mpic->ipi_vecs[0];
745
746 DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, irq, src);
747 mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK);
748 }
749
750 static void mpic_mask_ipi(unsigned int irq)
751 {
752 /* NEVER disable an IPI... that's just plain wrong! */
753 }
754
755 static void mpic_end_ipi(unsigned int irq)
756 {
757 struct mpic *mpic = mpic_from_ipi(irq);
758
759 /*
760 * IPIs are marked IRQ_PER_CPU. This has the side effect of
761 * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from
762 * applying to them. We EOI them late to avoid re-entering.
763 * We mark IPI's with IRQF_DISABLED as they must run with
764 * irqs disabled.
765 */
766 mpic_eoi(mpic);
767 }
768
769 #endif /* CONFIG_SMP */
770
771 static void mpic_set_affinity(unsigned int irq, cpumask_t cpumask)
772 {
773 struct mpic *mpic = mpic_from_irq(irq);
774 unsigned int src = mpic_irq_to_hw(irq);
775
776 cpumask_t tmp;
777
778 cpus_and(tmp, cpumask, cpu_online_map);
779
780 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION),
781 mpic_physmask(cpus_addr(tmp)[0]));
782 }
783
784 static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type)
785 {
786 /* Now convert sense value */
787 switch(type & IRQ_TYPE_SENSE_MASK) {
788 case IRQ_TYPE_EDGE_RISING:
789 return MPIC_INFO(VECPRI_SENSE_EDGE) |
790 MPIC_INFO(VECPRI_POLARITY_POSITIVE);
791 case IRQ_TYPE_EDGE_FALLING:
792 case IRQ_TYPE_EDGE_BOTH:
793 return MPIC_INFO(VECPRI_SENSE_EDGE) |
794 MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
795 case IRQ_TYPE_LEVEL_HIGH:
796 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
797 MPIC_INFO(VECPRI_POLARITY_POSITIVE);
798 case IRQ_TYPE_LEVEL_LOW:
799 default:
800 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
801 MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
802 }
803 }
804
805 int mpic_set_irq_type(unsigned int virq, unsigned int flow_type)
806 {
807 struct mpic *mpic = mpic_from_irq(virq);
808 unsigned int src = mpic_irq_to_hw(virq);
809 struct irq_desc *desc = get_irq_desc(virq);
810 unsigned int vecpri, vold, vnew;
811
812 DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n",
813 mpic, virq, src, flow_type);
814
815 if (src >= mpic->irq_count)
816 return -EINVAL;
817
818 if (flow_type == IRQ_TYPE_NONE)
819 if (mpic->senses && src < mpic->senses_count)
820 flow_type = mpic->senses[src];
821 if (flow_type == IRQ_TYPE_NONE)
822 flow_type = IRQ_TYPE_LEVEL_LOW;
823
824 desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
825 desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
826 if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
827 desc->status |= IRQ_LEVEL;
828
829 if (mpic_is_ht_interrupt(mpic, src))
830 vecpri = MPIC_VECPRI_POLARITY_POSITIVE |
831 MPIC_VECPRI_SENSE_EDGE;
832 else
833 vecpri = mpic_type_to_vecpri(mpic, flow_type);
834
835 vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
836 vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) |
837 MPIC_INFO(VECPRI_SENSE_MASK));
838 vnew |= vecpri;
839 if (vold != vnew)
840 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew);
841
842 return 0;
843 }
844
845 static struct irq_chip mpic_irq_chip = {
846 .mask = mpic_mask_irq,
847 .unmask = mpic_unmask_irq,
848 .eoi = mpic_end_irq,
849 .set_type = mpic_set_irq_type,
850 };
851
852 #ifdef CONFIG_SMP
853 static struct irq_chip mpic_ipi_chip = {
854 .mask = mpic_mask_ipi,
855 .unmask = mpic_unmask_ipi,
856 .eoi = mpic_end_ipi,
857 };
858 #endif /* CONFIG_SMP */
859
860 #ifdef CONFIG_MPIC_U3_HT_IRQS
861 static struct irq_chip mpic_irq_ht_chip = {
862 .startup = mpic_startup_ht_irq,
863 .shutdown = mpic_shutdown_ht_irq,
864 .mask = mpic_mask_irq,
865 .unmask = mpic_unmask_ht_irq,
866 .eoi = mpic_end_ht_irq,
867 .set_type = mpic_set_irq_type,
868 };
869 #endif /* CONFIG_MPIC_U3_HT_IRQS */
870
871
872 static int mpic_host_match(struct irq_host *h, struct device_node *node)
873 {
874 /* Exact match, unless mpic node is NULL */
875 return h->of_node == NULL || h->of_node == node;
876 }
877
878 static int mpic_host_map(struct irq_host *h, unsigned int virq,
879 irq_hw_number_t hw)
880 {
881 struct mpic *mpic = h->host_data;
882 struct irq_chip *chip;
883
884 DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw);
885
886 if (hw == mpic->spurious_vec)
887 return -EINVAL;
888 if (mpic->protected && test_bit(hw, mpic->protected))
889 return -EINVAL;
890
891 #ifdef CONFIG_SMP
892 else if (hw >= mpic->ipi_vecs[0]) {
893 WARN_ON(!(mpic->flags & MPIC_PRIMARY));
894
895 DBG("mpic: mapping as IPI\n");
896 set_irq_chip_data(virq, mpic);
897 set_irq_chip_and_handler(virq, &mpic->hc_ipi,
898 handle_percpu_irq);
899 return 0;
900 }
901 #endif /* CONFIG_SMP */
902
903 if (hw >= mpic->irq_count)
904 return -EINVAL;
905
906 mpic_msi_reserve_hwirq(mpic, hw);
907
908 /* Default chip */
909 chip = &mpic->hc_irq;
910
911 #ifdef CONFIG_MPIC_U3_HT_IRQS
912 /* Check for HT interrupts, override vecpri */
913 if (mpic_is_ht_interrupt(mpic, hw))
914 chip = &mpic->hc_ht_irq;
915 #endif /* CONFIG_MPIC_U3_HT_IRQS */
916
917 DBG("mpic: mapping to irq chip @%p\n", chip);
918
919 set_irq_chip_data(virq, mpic);
920 set_irq_chip_and_handler(virq, chip, handle_fasteoi_irq);
921
922 /* Set default irq type */
923 set_irq_type(virq, IRQ_TYPE_NONE);
924
925 return 0;
926 }
927
928 static int mpic_host_xlate(struct irq_host *h, struct device_node *ct,
929 u32 *intspec, unsigned int intsize,
930 irq_hw_number_t *out_hwirq, unsigned int *out_flags)
931
932 {
933 static unsigned char map_mpic_senses[4] = {
934 IRQ_TYPE_EDGE_RISING,
935 IRQ_TYPE_LEVEL_LOW,
936 IRQ_TYPE_LEVEL_HIGH,
937 IRQ_TYPE_EDGE_FALLING,
938 };
939
940 *out_hwirq = intspec[0];
941 if (intsize > 1) {
942 u32 mask = 0x3;
943
944 /* Apple invented a new race of encoding on machines with
945 * an HT APIC. They encode, among others, the index within
946 * the HT APIC. We don't care about it here since thankfully,
947 * it appears that they have the APIC already properly
948 * configured, and thus our current fixup code that reads the
949 * APIC config works fine. However, we still need to mask out
950 * bits in the specifier to make sure we only get bit 0 which
951 * is the level/edge bit (the only sense bit exposed by Apple),
952 * as their bit 1 means something else.
953 */
954 if (machine_is(powermac))
955 mask = 0x1;
956 *out_flags = map_mpic_senses[intspec[1] & mask];
957 } else
958 *out_flags = IRQ_TYPE_NONE;
959
960 DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n",
961 intsize, intspec[0], intspec[1], *out_hwirq, *out_flags);
962
963 return 0;
964 }
965
966 static struct irq_host_ops mpic_host_ops = {
967 .match = mpic_host_match,
968 .map = mpic_host_map,
969 .xlate = mpic_host_xlate,
970 };
971
972 /*
973 * Exported functions
974 */
975
976 struct mpic * __init mpic_alloc(struct device_node *node,
977 phys_addr_t phys_addr,
978 unsigned int flags,
979 unsigned int isu_size,
980 unsigned int irq_count,
981 const char *name)
982 {
983 struct mpic *mpic;
984 u32 reg;
985 const char *vers;
986 int i;
987 int intvec_top;
988 u64 paddr = phys_addr;
989
990 mpic = alloc_bootmem(sizeof(struct mpic));
991 if (mpic == NULL)
992 return NULL;
993
994 memset(mpic, 0, sizeof(struct mpic));
995 mpic->name = name;
996
997 mpic->irqhost = irq_alloc_host(of_node_get(node), IRQ_HOST_MAP_LINEAR,
998 isu_size, &mpic_host_ops,
999 flags & MPIC_LARGE_VECTORS ? 2048 : 256);
1000 if (mpic->irqhost == NULL) {
1001 of_node_put(node);
1002 return NULL;
1003 }
1004
1005 mpic->irqhost->host_data = mpic;
1006 mpic->hc_irq = mpic_irq_chip;
1007 mpic->hc_irq.typename = name;
1008 if (flags & MPIC_PRIMARY)
1009 mpic->hc_irq.set_affinity = mpic_set_affinity;
1010 #ifdef CONFIG_MPIC_U3_HT_IRQS
1011 mpic->hc_ht_irq = mpic_irq_ht_chip;
1012 mpic->hc_ht_irq.typename = name;
1013 if (flags & MPIC_PRIMARY)
1014 mpic->hc_ht_irq.set_affinity = mpic_set_affinity;
1015 #endif /* CONFIG_MPIC_U3_HT_IRQS */
1016
1017 #ifdef CONFIG_SMP
1018 mpic->hc_ipi = mpic_ipi_chip;
1019 mpic->hc_ipi.typename = name;
1020 #endif /* CONFIG_SMP */
1021
1022 mpic->flags = flags;
1023 mpic->isu_size = isu_size;
1024 mpic->irq_count = irq_count;
1025 mpic->num_sources = 0; /* so far */
1026
1027 if (flags & MPIC_LARGE_VECTORS)
1028 intvec_top = 2047;
1029 else
1030 intvec_top = 255;
1031
1032 mpic->timer_vecs[0] = intvec_top - 8;
1033 mpic->timer_vecs[1] = intvec_top - 7;
1034 mpic->timer_vecs[2] = intvec_top - 6;
1035 mpic->timer_vecs[3] = intvec_top - 5;
1036 mpic->ipi_vecs[0] = intvec_top - 4;
1037 mpic->ipi_vecs[1] = intvec_top - 3;
1038 mpic->ipi_vecs[2] = intvec_top - 2;
1039 mpic->ipi_vecs[3] = intvec_top - 1;
1040 mpic->spurious_vec = intvec_top;
1041
1042 /* Check for "big-endian" in device-tree */
1043 if (node && of_get_property(node, "big-endian", NULL) != NULL)
1044 mpic->flags |= MPIC_BIG_ENDIAN;
1045
1046 /* Look for protected sources */
1047 if (node) {
1048 unsigned int psize, bits, mapsize;
1049 const u32 *psrc =
1050 of_get_property(node, "protected-sources", &psize);
1051 if (psrc) {
1052 psize /= 4;
1053 bits = intvec_top + 1;
1054 mapsize = BITS_TO_LONGS(bits) * sizeof(unsigned long);
1055 mpic->protected = alloc_bootmem(mapsize);
1056 BUG_ON(mpic->protected == NULL);
1057 memset(mpic->protected, 0, mapsize);
1058 for (i = 0; i < psize; i++) {
1059 if (psrc[i] > intvec_top)
1060 continue;
1061 __set_bit(psrc[i], mpic->protected);
1062 }
1063 }
1064 }
1065
1066 #ifdef CONFIG_MPIC_WEIRD
1067 mpic->hw_set = mpic_infos[MPIC_GET_REGSET(flags)];
1068 #endif
1069
1070 /* default register type */
1071 mpic->reg_type = (flags & MPIC_BIG_ENDIAN) ?
1072 mpic_access_mmio_be : mpic_access_mmio_le;
1073
1074 /* If no physical address is passed in, a device-node is mandatory */
1075 BUG_ON(paddr == 0 && node == NULL);
1076
1077 /* If no physical address passed in, check if it's dcr based */
1078 if (paddr == 0 && of_get_property(node, "dcr-reg", NULL) != NULL)
1079 mpic->flags |= MPIC_USES_DCR;
1080
1081 #ifdef CONFIG_PPC_DCR
1082 if (mpic->flags & MPIC_USES_DCR) {
1083 const u32 *dbasep;
1084 dbasep = of_get_property(node, "dcr-reg", NULL);
1085 BUG_ON(dbasep == NULL);
1086 mpic->dcr_base = *dbasep;
1087 mpic->reg_type = mpic_access_dcr;
1088 }
1089 #else
1090 BUG_ON (mpic->flags & MPIC_USES_DCR);
1091 #endif /* CONFIG_PPC_DCR */
1092
1093 /* If the MPIC is not DCR based, and no physical address was passed
1094 * in, try to obtain one
1095 */
1096 if (paddr == 0 && !(mpic->flags & MPIC_USES_DCR)) {
1097 const u32 *reg;
1098 reg = of_get_property(node, "reg", NULL);
1099 BUG_ON(reg == NULL);
1100 paddr = of_translate_address(node, reg);
1101 BUG_ON(paddr == OF_BAD_ADDR);
1102 }
1103
1104 /* Map the global registers */
1105 mpic_map(mpic, paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000);
1106 mpic_map(mpic, paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000);
1107
1108 /* Reset */
1109 if (flags & MPIC_WANTS_RESET) {
1110 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1111 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1112 | MPIC_GREG_GCONF_RESET);
1113 while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1114 & MPIC_GREG_GCONF_RESET)
1115 mb();
1116 }
1117
1118 /* Read feature register, calculate num CPUs and, for non-ISU
1119 * MPICs, num sources as well. On ISU MPICs, sources are counted
1120 * as ISUs are added
1121 */
1122 reg = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0));
1123 mpic->num_cpus = ((reg & MPIC_GREG_FEATURE_LAST_CPU_MASK)
1124 >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT) + 1;
1125 if (isu_size == 0)
1126 mpic->num_sources = ((reg & MPIC_GREG_FEATURE_LAST_SRC_MASK)
1127 >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT) + 1;
1128
1129 /* Map the per-CPU registers */
1130 for (i = 0; i < mpic->num_cpus; i++) {
1131 mpic_map(mpic, paddr, &mpic->cpuregs[i],
1132 MPIC_INFO(CPU_BASE) + i * MPIC_INFO(CPU_STRIDE),
1133 0x1000);
1134 }
1135
1136 /* Initialize main ISU if none provided */
1137 if (mpic->isu_size == 0) {
1138 mpic->isu_size = mpic->num_sources;
1139 mpic_map(mpic, paddr, &mpic->isus[0],
1140 MPIC_INFO(IRQ_BASE), MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1141 }
1142 mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
1143 mpic->isu_mask = (1 << mpic->isu_shift) - 1;
1144
1145 /* Display version */
1146 switch (reg & MPIC_GREG_FEATURE_VERSION_MASK) {
1147 case 1:
1148 vers = "1.0";
1149 break;
1150 case 2:
1151 vers = "1.2";
1152 break;
1153 case 3:
1154 vers = "1.3";
1155 break;
1156 default:
1157 vers = "<unknown>";
1158 break;
1159 }
1160 printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx,"
1161 " max %d CPUs\n",
1162 name, vers, (unsigned long long)paddr, mpic->num_cpus);
1163 printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n",
1164 mpic->isu_size, mpic->isu_shift, mpic->isu_mask);
1165
1166 mpic->next = mpics;
1167 mpics = mpic;
1168
1169 if (flags & MPIC_PRIMARY) {
1170 mpic_primary = mpic;
1171 irq_set_default_host(mpic->irqhost);
1172 }
1173
1174 return mpic;
1175 }
1176
1177 void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
1178 phys_addr_t paddr)
1179 {
1180 unsigned int isu_first = isu_num * mpic->isu_size;
1181
1182 BUG_ON(isu_num >= MPIC_MAX_ISU);
1183
1184 mpic_map(mpic, paddr, &mpic->isus[isu_num], 0,
1185 MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1186 if ((isu_first + mpic->isu_size) > mpic->num_sources)
1187 mpic->num_sources = isu_first + mpic->isu_size;
1188 }
1189
1190 void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count)
1191 {
1192 mpic->senses = senses;
1193 mpic->senses_count = count;
1194 }
1195
1196 void __init mpic_init(struct mpic *mpic)
1197 {
1198 int i;
1199
1200 BUG_ON(mpic->num_sources == 0);
1201
1202 printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources);
1203
1204 /* Set current processor priority to max */
1205 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1206
1207 /* Initialize timers: just disable them all */
1208 for (i = 0; i < 4; i++) {
1209 mpic_write(mpic->tmregs,
1210 i * MPIC_INFO(TIMER_STRIDE) +
1211 MPIC_INFO(TIMER_DESTINATION), 0);
1212 mpic_write(mpic->tmregs,
1213 i * MPIC_INFO(TIMER_STRIDE) +
1214 MPIC_INFO(TIMER_VECTOR_PRI),
1215 MPIC_VECPRI_MASK |
1216 (mpic->timer_vecs[0] + i));
1217 }
1218
1219 /* Initialize IPIs to our reserved vectors and mark them disabled for now */
1220 mpic_test_broken_ipi(mpic);
1221 for (i = 0; i < 4; i++) {
1222 mpic_ipi_write(i,
1223 MPIC_VECPRI_MASK |
1224 (10 << MPIC_VECPRI_PRIORITY_SHIFT) |
1225 (mpic->ipi_vecs[0] + i));
1226 }
1227
1228 /* Initialize interrupt sources */
1229 if (mpic->irq_count == 0)
1230 mpic->irq_count = mpic->num_sources;
1231
1232 /* Do the HT PIC fixups on U3 broken mpic */
1233 DBG("MPIC flags: %x\n", mpic->flags);
1234 if ((mpic->flags & MPIC_U3_HT_IRQS) && (mpic->flags & MPIC_PRIMARY)) {
1235 mpic_scan_ht_pics(mpic);
1236 mpic_u3msi_init(mpic);
1237 }
1238
1239 for (i = 0; i < mpic->num_sources; i++) {
1240 /* start with vector = source number, and masked */
1241 u32 vecpri = MPIC_VECPRI_MASK | i |
1242 (8 << MPIC_VECPRI_PRIORITY_SHIFT);
1243
1244 /* check if protected */
1245 if (mpic->protected && test_bit(i, mpic->protected))
1246 continue;
1247 /* init hw */
1248 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
1249 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1250 1 << hard_smp_processor_id());
1251 }
1252
1253 /* Init spurious vector */
1254 mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec);
1255
1256 /* Disable 8259 passthrough, if supported */
1257 if (!(mpic->flags & MPIC_NO_PTHROU_DIS))
1258 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1259 mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1260 | MPIC_GREG_GCONF_8259_PTHROU_DIS);
1261
1262 /* Set current processor priority to 0 */
1263 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1264
1265 #ifdef CONFIG_PM
1266 /* allocate memory to save mpic state */
1267 mpic->save_data = alloc_bootmem(mpic->num_sources * sizeof(struct mpic_irq_save));
1268 BUG_ON(mpic->save_data == NULL);
1269 #endif
1270 }
1271
1272 void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio)
1273 {
1274 u32 v;
1275
1276 v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
1277 v &= ~MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK;
1278 v |= MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(clock_ratio);
1279 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
1280 }
1281
1282 void __init mpic_set_serial_int(struct mpic *mpic, int enable)
1283 {
1284 unsigned long flags;
1285 u32 v;
1286
1287 spin_lock_irqsave(&mpic_lock, flags);
1288 v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
1289 if (enable)
1290 v |= MPIC_GREG_GLOBAL_CONF_1_SIE;
1291 else
1292 v &= ~MPIC_GREG_GLOBAL_CONF_1_SIE;
1293 mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
1294 spin_unlock_irqrestore(&mpic_lock, flags);
1295 }
1296
1297 void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
1298 {
1299 int is_ipi;
1300 struct mpic *mpic = mpic_find(irq, &is_ipi);
1301 unsigned int src = mpic_irq_to_hw(irq);
1302 unsigned long flags;
1303 u32 reg;
1304
1305 spin_lock_irqsave(&mpic_lock, flags);
1306 if (is_ipi) {
1307 reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) &
1308 ~MPIC_VECPRI_PRIORITY_MASK;
1309 mpic_ipi_write(src - mpic->ipi_vecs[0],
1310 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1311 } else {
1312 reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI))
1313 & ~MPIC_VECPRI_PRIORITY_MASK;
1314 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
1315 reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1316 }
1317 spin_unlock_irqrestore(&mpic_lock, flags);
1318 }
1319
1320 unsigned int mpic_irq_get_priority(unsigned int irq)
1321 {
1322 int is_ipi;
1323 struct mpic *mpic = mpic_find(irq, &is_ipi);
1324 unsigned int src = mpic_irq_to_hw(irq);
1325 unsigned long flags;
1326 u32 reg;
1327
1328 spin_lock_irqsave(&mpic_lock, flags);
1329 if (is_ipi)
1330 reg = mpic_ipi_read(src = mpic->ipi_vecs[0]);
1331 else
1332 reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
1333 spin_unlock_irqrestore(&mpic_lock, flags);
1334 return (reg & MPIC_VECPRI_PRIORITY_MASK) >> MPIC_VECPRI_PRIORITY_SHIFT;
1335 }
1336
1337 void mpic_setup_this_cpu(void)
1338 {
1339 #ifdef CONFIG_SMP
1340 struct mpic *mpic = mpic_primary;
1341 unsigned long flags;
1342 u32 msk = 1 << hard_smp_processor_id();
1343 unsigned int i;
1344
1345 BUG_ON(mpic == NULL);
1346
1347 DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1348
1349 spin_lock_irqsave(&mpic_lock, flags);
1350
1351 /* let the mpic know we want intrs. default affinity is 0xffffffff
1352 * until changed via /proc. That's how it's done on x86. If we want
1353 * it differently, then we should make sure we also change the default
1354 * values of irq_desc[].affinity in irq.c.
1355 */
1356 if (distribute_irqs) {
1357 for (i = 0; i < mpic->num_sources ; i++)
1358 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1359 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk);
1360 }
1361
1362 /* Set current processor priority to 0 */
1363 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1364
1365 spin_unlock_irqrestore(&mpic_lock, flags);
1366 #endif /* CONFIG_SMP */
1367 }
1368
1369 int mpic_cpu_get_priority(void)
1370 {
1371 struct mpic *mpic = mpic_primary;
1372
1373 return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI));
1374 }
1375
1376 void mpic_cpu_set_priority(int prio)
1377 {
1378 struct mpic *mpic = mpic_primary;
1379
1380 prio &= MPIC_CPU_TASKPRI_MASK;
1381 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio);
1382 }
1383
1384 /*
1385 * XXX: someone who knows mpic should check this.
1386 * do we need to eoi the ipi including for kexec cpu here (see xics comments)?
1387 * or can we reset the mpic in the new kernel?
1388 */
1389 void mpic_teardown_this_cpu(int secondary)
1390 {
1391 struct mpic *mpic = mpic_primary;
1392 unsigned long flags;
1393 u32 msk = 1 << hard_smp_processor_id();
1394 unsigned int i;
1395
1396 BUG_ON(mpic == NULL);
1397
1398 DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1399 spin_lock_irqsave(&mpic_lock, flags);
1400
1401 /* let the mpic know we don't want intrs. */
1402 for (i = 0; i < mpic->num_sources ; i++)
1403 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1404 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk);
1405
1406 /* Set current processor priority to max */
1407 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1408
1409 spin_unlock_irqrestore(&mpic_lock, flags);
1410 }
1411
1412
1413 void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask)
1414 {
1415 struct mpic *mpic = mpic_primary;
1416
1417 BUG_ON(mpic == NULL);
1418
1419 #ifdef DEBUG_IPI
1420 DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, ipi_no);
1421 #endif
1422
1423 mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) +
1424 ipi_no * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE),
1425 mpic_physmask(cpu_mask & cpus_addr(cpu_online_map)[0]));
1426 }
1427
1428 unsigned int mpic_get_one_irq(struct mpic *mpic)
1429 {
1430 u32 src;
1431
1432 src = mpic_cpu_read(MPIC_INFO(CPU_INTACK)) & MPIC_INFO(VECPRI_VECTOR_MASK);
1433 #ifdef DEBUG_LOW
1434 DBG("%s: get_one_irq(): %d\n", mpic->name, src);
1435 #endif
1436 if (unlikely(src == mpic->spurious_vec)) {
1437 if (mpic->flags & MPIC_SPV_EOI)
1438 mpic_eoi(mpic);
1439 return NO_IRQ;
1440 }
1441 if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
1442 if (printk_ratelimit())
1443 printk(KERN_WARNING "%s: Got protected source %d !\n",
1444 mpic->name, (int)src);
1445 mpic_eoi(mpic);
1446 return NO_IRQ;
1447 }
1448
1449 return irq_linear_revmap(mpic->irqhost, src);
1450 }
1451
1452 unsigned int mpic_get_irq(void)
1453 {
1454 struct mpic *mpic = mpic_primary;
1455
1456 BUG_ON(mpic == NULL);
1457
1458 return mpic_get_one_irq(mpic);
1459 }
1460
1461
1462 #ifdef CONFIG_SMP
1463 void mpic_request_ipis(void)
1464 {
1465 struct mpic *mpic = mpic_primary;
1466 int i, err;
1467 static char *ipi_names[] = {
1468 "IPI0 (call function)",
1469 "IPI1 (reschedule)",
1470 "IPI2 (unused)",
1471 "IPI3 (debugger break)",
1472 };
1473 BUG_ON(mpic == NULL);
1474
1475 printk(KERN_INFO "mpic: requesting IPIs ... \n");
1476
1477 for (i = 0; i < 4; i++) {
1478 unsigned int vipi = irq_create_mapping(mpic->irqhost,
1479 mpic->ipi_vecs[0] + i);
1480 if (vipi == NO_IRQ) {
1481 printk(KERN_ERR "Failed to map IPI %d\n", i);
1482 break;
1483 }
1484 err = request_irq(vipi, mpic_ipi_action,
1485 IRQF_DISABLED|IRQF_PERCPU,
1486 ipi_names[i], mpic);
1487 if (err) {
1488 printk(KERN_ERR "Request of irq %d for IPI %d failed\n",
1489 vipi, i);
1490 break;
1491 }
1492 }
1493 }
1494
1495 void smp_mpic_message_pass(int target, int msg)
1496 {
1497 /* make sure we're sending something that translates to an IPI */
1498 if ((unsigned int)msg > 3) {
1499 printk("SMP %d: smp_message_pass: unknown msg %d\n",
1500 smp_processor_id(), msg);
1501 return;
1502 }
1503 switch (target) {
1504 case MSG_ALL:
1505 mpic_send_ipi(msg, 0xffffffff);
1506 break;
1507 case MSG_ALL_BUT_SELF:
1508 mpic_send_ipi(msg, 0xffffffff & ~(1 << smp_processor_id()));
1509 break;
1510 default:
1511 mpic_send_ipi(msg, 1 << target);
1512 break;
1513 }
1514 }
1515
1516 int __init smp_mpic_probe(void)
1517 {
1518 int nr_cpus;
1519
1520 DBG("smp_mpic_probe()...\n");
1521
1522 nr_cpus = cpus_weight(cpu_possible_map);
1523
1524 DBG("nr_cpus: %d\n", nr_cpus);
1525
1526 if (nr_cpus > 1)
1527 mpic_request_ipis();
1528
1529 return nr_cpus;
1530 }
1531
1532 void __devinit smp_mpic_setup_cpu(int cpu)
1533 {
1534 mpic_setup_this_cpu();
1535 }
1536 #endif /* CONFIG_SMP */
1537
1538 #ifdef CONFIG_PM
1539 static int mpic_suspend(struct sys_device *dev, pm_message_t state)
1540 {
1541 struct mpic *mpic = container_of(dev, struct mpic, sysdev);
1542 int i;
1543
1544 for (i = 0; i < mpic->num_sources; i++) {
1545 mpic->save_data[i].vecprio =
1546 mpic_irq_read(i, MPIC_INFO(IRQ_VECTOR_PRI));
1547 mpic->save_data[i].dest =
1548 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION));
1549 }
1550
1551 return 0;
1552 }
1553
1554 static int mpic_resume(struct sys_device *dev)
1555 {
1556 struct mpic *mpic = container_of(dev, struct mpic, sysdev);
1557 int i;
1558
1559 for (i = 0; i < mpic->num_sources; i++) {
1560 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI),
1561 mpic->save_data[i].vecprio);
1562 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1563 mpic->save_data[i].dest);
1564
1565 #ifdef CONFIG_MPIC_U3_HT_IRQS
1566 {
1567 struct mpic_irq_fixup *fixup = &mpic->fixups[i];
1568
1569 if (fixup->base) {
1570 /* we use the lowest bit in an inverted meaning */
1571 if ((mpic->save_data[i].fixup_data & 1) == 0)
1572 continue;
1573
1574 /* Enable and configure */
1575 writeb(0x10 + 2 * fixup->index, fixup->base + 2);
1576
1577 writel(mpic->save_data[i].fixup_data & ~1,
1578 fixup->base + 4);
1579 }
1580 }
1581 #endif
1582 } /* end for loop */
1583
1584 return 0;
1585 }
1586 #endif
1587
1588 static struct sysdev_class mpic_sysclass = {
1589 #ifdef CONFIG_PM
1590 .resume = mpic_resume,
1591 .suspend = mpic_suspend,
1592 #endif
1593 set_kset_name("mpic"),
1594 };
1595
1596 static int mpic_init_sys(void)
1597 {
1598 struct mpic *mpic = mpics;
1599 int error, id = 0;
1600
1601 error = sysdev_class_register(&mpic_sysclass);
1602
1603 while (mpic && !error) {
1604 mpic->sysdev.cls = &mpic_sysclass;
1605 mpic->sysdev.id = id++;
1606 error = sysdev_register(&mpic->sysdev);
1607 mpic = mpic->next;
1608 }
1609 return error;
1610 }
1611
1612 device_initcall(mpic_init_sys);
Linux 2.6 libata-dev (mirror)