?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
ixgbe: add device support for 82598AT (copper 10GbE) adapters
[linux-2.6/libata-dev.git] / drivers / net / ixgbe / ixgbe_type.h
blob51df39dae81654ebaf1a84a6eb73c0d77136e9ad
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2008 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #ifndef _IXGBE_TYPE_H_
29 #define _IXGBE_TYPE_H_
30
31 #include <linux/types.h>
32
33 /* Vendor ID */
34 #define IXGBE_INTEL_VENDOR_ID 0x8086
35
36 /* Device IDs */
37 #define IXGBE_DEV_ID_82598AF_DUAL_PORT 0x10C6
38 #define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7
39 #define IXGBE_DEV_ID_82598AT 0x10C8
40 #define IXGBE_DEV_ID_82598EB_CX4 0x10DD
41 #define IXGBE_DEV_ID_82598_CX4_DUAL_PORT 0x10EC
42 #define IXGBE_DEV_ID_82598EB_XF_LR 0x10F4
43
44 /* General Registers */
45 #define IXGBE_CTRL 0x00000
46 #define IXGBE_STATUS 0x00008
47 #define IXGBE_CTRL_EXT 0x00018
48 #define IXGBE_ESDP 0x00020
49 #define IXGBE_EODSDP 0x00028
50 #define IXGBE_LEDCTL 0x00200
51 #define IXGBE_FRTIMER 0x00048
52 #define IXGBE_TCPTIMER 0x0004C
53
54 /* NVM Registers */
55 #define IXGBE_EEC 0x10010
56 #define IXGBE_EERD 0x10014
57 #define IXGBE_FLA 0x1001C
58 #define IXGBE_EEMNGCTL 0x10110
59 #define IXGBE_EEMNGDATA 0x10114
60 #define IXGBE_FLMNGCTL 0x10118
61 #define IXGBE_FLMNGDATA 0x1011C
62 #define IXGBE_FLMNGCNT 0x10120
63 #define IXGBE_FLOP 0x1013C
64 #define IXGBE_GRC 0x10200
65
66 /* Interrupt Registers */
67 #define IXGBE_EICR 0x00800
68 #define IXGBE_EICS 0x00808
69 #define IXGBE_EIMS 0x00880
70 #define IXGBE_EIMC 0x00888
71 #define IXGBE_EIAC 0x00810
72 #define IXGBE_EIAM 0x00890
73 #define IXGBE_EITR(_i) (((_i) <= 23) ? (0x00820 + ((_i) * 4)) : (0x012300 + ((_i) * 4)))
74 #define IXGBE_IVAR(_i) (0x00900 + ((_i) * 4)) /* 24 at 0x900-0x960 */
75 #define IXGBE_MSIXT 0x00000 /* MSI-X Table. 0x0000 - 0x01C */
76 #define IXGBE_MSIXPBA 0x02000 /* MSI-X Pending bit array */
77 #define IXGBE_PBACL(_i) (((_i) == 0) ? (0x11068) : (0x110C0 + ((_i) * 4)))
78 #define IXGBE_GPIE 0x00898
79
80 /* Flow Control Registers */
81 #define IXGBE_PFCTOP 0x03008
82 #define IXGBE_FCTTV(_i) (0x03200 + ((_i) * 4)) /* 4 of these (0-3) */
83 #define IXGBE_FCRTL(_i) (0x03220 + ((_i) * 8)) /* 8 of these (0-7) */
84 #define IXGBE_FCRTH(_i) (0x03260 + ((_i) * 8)) /* 8 of these (0-7) */
85 #define IXGBE_FCRTV 0x032A0
86 #define IXGBE_TFCS 0x0CE00
87
88 /* Receive DMA Registers */
89 #define IXGBE_RDBAL(_i) (((_i) < 64) ? (0x01000 + ((_i) * 0x40)) : (0x0D000 + ((_i - 64) * 0x40)))
90 #define IXGBE_RDBAH(_i) (((_i) < 64) ? (0x01004 + ((_i) * 0x40)) : (0x0D004 + ((_i - 64) * 0x40)))
91 #define IXGBE_RDLEN(_i) (((_i) < 64) ? (0x01008 + ((_i) * 0x40)) : (0x0D008 + ((_i - 64) * 0x40)))
92 #define IXGBE_RDH(_i) (((_i) < 64) ? (0x01010 + ((_i) * 0x40)) : (0x0D010 + ((_i - 64) * 0x40)))
93 #define IXGBE_RDT(_i) (((_i) < 64) ? (0x01018 + ((_i) * 0x40)) : (0x0D018 + ((_i - 64) * 0x40)))
94 #define IXGBE_RXDCTL(_i) (((_i) < 64) ? (0x01028 + ((_i) * 0x40)) : (0x0D028 + ((_i - 64) * 0x40)))
95 /*
96 * Split and Replication Receive Control Registers
97 * 00-15 : 0x02100 + n*4
98 * 16-64 : 0x01014 + n*0x40
99 * 64-127: 0x0D014 + (n-64)*0x40
100 */
101 #define IXGBE_SRRCTL(_i) (((_i) <= 15) ? (0x02100 + ((_i) * 4)) : \
102 (((_i) < 64) ? (0x01014 + ((_i) * 0x40)) : \
103 (0x0D014 + ((_i - 64) * 0x40))))
104 /*
105 * Rx DCA Control Register:
106 * 00-15 : 0x02200 + n*4
107 * 16-64 : 0x0100C + n*0x40
108 * 64-127: 0x0D00C + (n-64)*0x40
109 */
110 #define IXGBE_DCA_RXCTRL(_i) (((_i) <= 15) ? (0x02200 + ((_i) * 4)) : \
111 (((_i) < 64) ? (0x0100C + ((_i) * 0x40)) : \
112 (0x0D00C + ((_i - 64) * 0x40))))
113 #define IXGBE_RDRXCTL 0x02F00
114 #define IXGBE_RXPBSIZE(_i) (0x03C00 + ((_i) * 4))
115 /* 8 of these 0x03C00 - 0x03C1C */
116 #define IXGBE_RXCTRL 0x03000
117 #define IXGBE_DROPEN 0x03D04
118 #define IXGBE_RXPBSIZE_SHIFT 10
119
120 /* Receive Registers */
121 #define IXGBE_RXCSUM 0x05000
122 #define IXGBE_RFCTL 0x05008
123 #define IXGBE_DRECCCTL 0x02F08
124 #define IXGBE_DRECCCTL_DISABLE 0
125 /* Multicast Table Array - 128 entries */
126 #define IXGBE_MTA(_i) (0x05200 + ((_i) * 4))
127 #define IXGBE_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : (0x0A200 + ((_i) * 8)))
128 #define IXGBE_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : (0x0A204 + ((_i) * 8)))
129 /* Packet split receive type */
130 #define IXGBE_PSRTYPE(_i) (((_i) <= 15) ? (0x05480 + ((_i) * 4)) : (0x0EA00 + ((_i) * 4)))
131 /* array of 4096 1-bit vlan filters */
132 #define IXGBE_VFTA(_i) (0x0A000 + ((_i) * 4))
133 /*array of 4096 4-bit vlan vmdq indices */
134 #define IXGBE_VFTAVIND(_j, _i) (0x0A200 + ((_j) * 0x200) + ((_i) * 4))
135 #define IXGBE_FCTRL 0x05080
136 #define IXGBE_VLNCTRL 0x05088
137 #define IXGBE_MCSTCTRL 0x05090
138 #define IXGBE_MRQC 0x05818
139 #define IXGBE_IMIR(_i) (0x05A80 + ((_i) * 4)) /* 8 of these (0-7) */
140 #define IXGBE_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* 8 of these (0-7) */
141 #define IXGBE_IMIRVP 0x05AC0
142 #define IXGBE_VMD_CTL 0x0581C
143 #define IXGBE_RETA(_i) (0x05C00 + ((_i) * 4)) /* 32 of these (0-31) */
144 #define IXGBE_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* 10 of these (0-9) */
145
146
147 /* Transmit DMA registers */
148 #define IXGBE_TDBAL(_i) (0x06000 + ((_i) * 0x40)) /* 32 of these (0-31)*/
149 #define IXGBE_TDBAH(_i) (0x06004 + ((_i) * 0x40))
150 #define IXGBE_TDLEN(_i) (0x06008 + ((_i) * 0x40))
151 #define IXGBE_TDH(_i) (0x06010 + ((_i) * 0x40))
152 #define IXGBE_TDT(_i) (0x06018 + ((_i) * 0x40))
153 #define IXGBE_TXDCTL(_i) (0x06028 + ((_i) * 0x40))
154 #define IXGBE_TDWBAL(_i) (0x06038 + ((_i) * 0x40))
155 #define IXGBE_TDWBAH(_i) (0x0603C + ((_i) * 0x40))
156 #define IXGBE_DTXCTL 0x07E00
157
158 #define IXGBE_DCA_TXCTRL(_i) (0x07200 + ((_i) * 4)) /* 16 of these (0-15) */
159 #define IXGBE_TIPG 0x0CB00
160 #define IXGBE_TXPBSIZE(_i) (0x0CC00 + ((_i) * 4)) /* 8 of these */
161 #define IXGBE_MNGTXMAP 0x0CD10
162 #define IXGBE_TIPG_FIBER_DEFAULT 3
163 #define IXGBE_TXPBSIZE_SHIFT 10
164
165 /* Wake up registers */
166 #define IXGBE_WUC 0x05800
167 #define IXGBE_WUFC 0x05808
168 #define IXGBE_WUS 0x05810
169 #define IXGBE_IPAV 0x05838
170 #define IXGBE_IP4AT 0x05840 /* IPv4 table 0x5840-0x5858 */
171 #define IXGBE_IP6AT 0x05880 /* IPv6 table 0x5880-0x588F */
172
173 #define IXGBE_WUPL 0x05900
174 #define IXGBE_WUPM 0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */
175 #define IXGBE_FHFT 0x09000 /* Flex host filter table 9000-93FC */
176
177 /* Music registers */
178 #define IXGBE_RMCS 0x03D00
179 #define IXGBE_DPMCS 0x07F40
180 #define IXGBE_PDPMCS 0x0CD00
181 #define IXGBE_RUPPBMR 0x050A0
182 #define IXGBE_RT2CR(_i) (0x03C20 + ((_i) * 4)) /* 8 of these (0-7) */
183 #define IXGBE_RT2SR(_i) (0x03C40 + ((_i) * 4)) /* 8 of these (0-7) */
184 #define IXGBE_TDTQ2TCCR(_i) (0x0602C + ((_i) * 0x40)) /* 8 of these (0-7) */
185 #define IXGBE_TDTQ2TCSR(_i) (0x0622C + ((_i) * 0x40)) /* 8 of these (0-7) */
186 #define IXGBE_TDPT2TCCR(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */
187 #define IXGBE_TDPT2TCSR(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */
188
189
190
191 /* Stats registers */
192 #define IXGBE_CRCERRS 0x04000
193 #define IXGBE_ILLERRC 0x04004
194 #define IXGBE_ERRBC 0x04008
195 #define IXGBE_MSPDC 0x04010
196 #define IXGBE_MPC(_i) (0x03FA0 + ((_i) * 4)) /* 8 of these 3FA0-3FBC*/
197 #define IXGBE_MLFC 0x04034
198 #define IXGBE_MRFC 0x04038
199 #define IXGBE_RLEC 0x04040
200 #define IXGBE_LXONTXC 0x03F60
201 #define IXGBE_LXONRXC 0x0CF60
202 #define IXGBE_LXOFFTXC 0x03F68
203 #define IXGBE_LXOFFRXC 0x0CF68
204 #define IXGBE_PXONTXC(_i) (0x03F00 + ((_i) * 4)) /* 8 of these 3F00-3F1C*/
205 #define IXGBE_PXONRXC(_i) (0x0CF00 + ((_i) * 4)) /* 8 of these CF00-CF1C*/
206 #define IXGBE_PXOFFTXC(_i) (0x03F20 + ((_i) * 4)) /* 8 of these 3F20-3F3C*/
207 #define IXGBE_PXOFFRXC(_i) (0x0CF20 + ((_i) * 4)) /* 8 of these CF20-CF3C*/
208 #define IXGBE_PRC64 0x0405C
209 #define IXGBE_PRC127 0x04060
210 #define IXGBE_PRC255 0x04064
211 #define IXGBE_PRC511 0x04068
212 #define IXGBE_PRC1023 0x0406C
213 #define IXGBE_PRC1522 0x04070
214 #define IXGBE_GPRC 0x04074
215 #define IXGBE_BPRC 0x04078
216 #define IXGBE_MPRC 0x0407C
217 #define IXGBE_GPTC 0x04080
218 #define IXGBE_GORCL 0x04088
219 #define IXGBE_GORCH 0x0408C
220 #define IXGBE_GOTCL 0x04090
221 #define IXGBE_GOTCH 0x04094
222 #define IXGBE_RNBC(_i) (0x03FC0 + ((_i) * 4)) /* 8 of these 3FC0-3FDC*/
223 #define IXGBE_RUC 0x040A4
224 #define IXGBE_RFC 0x040A8
225 #define IXGBE_ROC 0x040AC
226 #define IXGBE_RJC 0x040B0
227 #define IXGBE_MNGPRC 0x040B4
228 #define IXGBE_MNGPDC 0x040B8
229 #define IXGBE_MNGPTC 0x0CF90
230 #define IXGBE_TORL 0x040C0
231 #define IXGBE_TORH 0x040C4
232 #define IXGBE_TPR 0x040D0
233 #define IXGBE_TPT 0x040D4
234 #define IXGBE_PTC64 0x040D8
235 #define IXGBE_PTC127 0x040DC
236 #define IXGBE_PTC255 0x040E0
237 #define IXGBE_PTC511 0x040E4
238 #define IXGBE_PTC1023 0x040E8
239 #define IXGBE_PTC1522 0x040EC
240 #define IXGBE_MPTC 0x040F0
241 #define IXGBE_BPTC 0x040F4
242 #define IXGBE_XEC 0x04120
243
244 #define IXGBE_RQSMR(_i) (0x02300 + ((_i) * 4)) /* 16 of these */
245 #define IXGBE_TQSMR(_i) (((_i) <= 7) ? (0x07300 + ((_i) * 4)) : (0x08600 + ((_i) * 4)))
246
247 #define IXGBE_QPRC(_i) (0x01030 + ((_i) * 0x40)) /* 16 of these */
248 #define IXGBE_QPTC(_i) (0x06030 + ((_i) * 0x40)) /* 16 of these */
249 #define IXGBE_QBRC(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */
250 #define IXGBE_QBTC(_i) (0x06034 + ((_i) * 0x40)) /* 16 of these */
251
252 /* Management */
253 #define IXGBE_MAVTV(_i) (0x05010 + ((_i) * 4)) /* 8 of these (0-7) */
254 #define IXGBE_MFUTP(_i) (0x05030 + ((_i) * 4)) /* 8 of these (0-7) */
255 #define IXGBE_MANC 0x05820
256 #define IXGBE_MFVAL 0x05824
257 #define IXGBE_MANC2H 0x05860
258 #define IXGBE_MDEF(_i) (0x05890 + ((_i) * 4)) /* 8 of these (0-7) */
259 #define IXGBE_MIPAF 0x058B0
260 #define IXGBE_MMAL(_i) (0x05910 + ((_i) * 8)) /* 4 of these (0-3) */
261 #define IXGBE_MMAH(_i) (0x05914 + ((_i) * 8)) /* 4 of these (0-3) */
262 #define IXGBE_FTFT 0x09400 /* 0x9400-0x97FC */
263
264 /* ARC Subsystem registers */
265 #define IXGBE_HICR 0x15F00
266 #define IXGBE_FWSTS 0x15F0C
267 #define IXGBE_HSMC0R 0x15F04
268 #define IXGBE_HSMC1R 0x15F08
269 #define IXGBE_SWSR 0x15F10
270 #define IXGBE_HFDR 0x15FE8
271 #define IXGBE_FLEX_MNG 0x15800 /* 0x15800 - 0x15EFC */
272
273 /* PCI-E registers */
274 #define IXGBE_GCR 0x11000
275 #define IXGBE_GTV 0x11004
276 #define IXGBE_FUNCTAG 0x11008
277 #define IXGBE_GLT 0x1100C
278 #define IXGBE_GSCL_1 0x11010
279 #define IXGBE_GSCL_2 0x11014
280 #define IXGBE_GSCL_3 0x11018
281 #define IXGBE_GSCL_4 0x1101C
282 #define IXGBE_GSCN_0 0x11020
283 #define IXGBE_GSCN_1 0x11024
284 #define IXGBE_GSCN_2 0x11028
285 #define IXGBE_GSCN_3 0x1102C
286 #define IXGBE_FACTPS 0x10150
287 #define IXGBE_PCIEANACTL 0x11040
288 #define IXGBE_SWSM 0x10140
289 #define IXGBE_FWSM 0x10148
290 #define IXGBE_GSSR 0x10160
291 #define IXGBE_MREVID 0x11064
292 #define IXGBE_DCA_ID 0x11070
293 #define IXGBE_DCA_CTRL 0x11074
294
295 /* Diagnostic Registers */
296 #define IXGBE_RDSTATCTL 0x02C20
297 #define IXGBE_RDSTAT(_i) (0x02C00 + ((_i) * 4)) /* 0x02C00-0x02C1C */
298 #define IXGBE_RDHMPN 0x02F08
299 #define IXGBE_RIC_DW(_i) (0x02F10 + ((_i) * 4))
300 #define IXGBE_RDPROBE 0x02F20
301 #define IXGBE_TDSTATCTL 0x07C20
302 #define IXGBE_TDSTAT(_i) (0x07C00 + ((_i) * 4)) /* 0x07C00 - 0x07C1C */
303 #define IXGBE_TDHMPN 0x07F08
304 #define IXGBE_TIC_DW(_i) (0x07F10 + ((_i) * 4))
305 #define IXGBE_TDPROBE 0x07F20
306 #define IXGBE_TXBUFCTRL 0x0C600
307 #define IXGBE_TXBUFDATA0 0x0C610
308 #define IXGBE_TXBUFDATA1 0x0C614
309 #define IXGBE_TXBUFDATA2 0x0C618
310 #define IXGBE_TXBUFDATA3 0x0C61C
311 #define IXGBE_RXBUFCTRL 0x03600
312 #define IXGBE_RXBUFDATA0 0x03610
313 #define IXGBE_RXBUFDATA1 0x03614
314 #define IXGBE_RXBUFDATA2 0x03618
315 #define IXGBE_RXBUFDATA3 0x0361C
316 #define IXGBE_PCIE_DIAG(_i) (0x11090 + ((_i) * 4)) /* 8 of these */
317 #define IXGBE_RFVAL 0x050A4
318 #define IXGBE_MDFTC1 0x042B8
319 #define IXGBE_MDFTC2 0x042C0
320 #define IXGBE_MDFTFIFO1 0x042C4
321 #define IXGBE_MDFTFIFO2 0x042C8
322 #define IXGBE_MDFTS 0x042CC
323 #define IXGBE_RXDATAWRPTR(_i) (0x03700 + ((_i) * 4)) /* 8 of these 3700-370C*/
324 #define IXGBE_RXDESCWRPTR(_i) (0x03710 + ((_i) * 4)) /* 8 of these 3710-371C*/
325 #define IXGBE_RXDATARDPTR(_i) (0x03720 + ((_i) * 4)) /* 8 of these 3720-372C*/
326 #define IXGBE_RXDESCRDPTR(_i) (0x03730 + ((_i) * 4)) /* 8 of these 3730-373C*/
327 #define IXGBE_TXDATAWRPTR(_i) (0x0C700 + ((_i) * 4)) /* 8 of these C700-C70C*/
328 #define IXGBE_TXDESCWRPTR(_i) (0x0C710 + ((_i) * 4)) /* 8 of these C710-C71C*/
329 #define IXGBE_TXDATARDPTR(_i) (0x0C720 + ((_i) * 4)) /* 8 of these C720-C72C*/
330 #define IXGBE_TXDESCRDPTR(_i) (0x0C730 + ((_i) * 4)) /* 8 of these C730-C73C*/
331 #define IXGBE_PCIEECCCTL 0x1106C
332 #define IXGBE_PBTXECC 0x0C300
333 #define IXGBE_PBRXECC 0x03300
334 #define IXGBE_GHECCR 0x110B0
335
336 /* MAC Registers */
337 #define IXGBE_PCS1GCFIG 0x04200
338 #define IXGBE_PCS1GLCTL 0x04208
339 #define IXGBE_PCS1GLSTA 0x0420C
340 #define IXGBE_PCS1GDBG0 0x04210
341 #define IXGBE_PCS1GDBG1 0x04214
342 #define IXGBE_PCS1GANA 0x04218
343 #define IXGBE_PCS1GANLP 0x0421C
344 #define IXGBE_PCS1GANNP 0x04220
345 #define IXGBE_PCS1GANLPNP 0x04224
346 #define IXGBE_HLREG0 0x04240
347 #define IXGBE_HLREG1 0x04244
348 #define IXGBE_PAP 0x04248
349 #define IXGBE_MACA 0x0424C
350 #define IXGBE_APAE 0x04250
351 #define IXGBE_ARD 0x04254
352 #define IXGBE_AIS 0x04258
353 #define IXGBE_MSCA 0x0425C
354 #define IXGBE_MSRWD 0x04260
355 #define IXGBE_MLADD 0x04264
356 #define IXGBE_MHADD 0x04268
357 #define IXGBE_TREG 0x0426C
358 #define IXGBE_PCSS1 0x04288
359 #define IXGBE_PCSS2 0x0428C
360 #define IXGBE_XPCSS 0x04290
361 #define IXGBE_SERDESC 0x04298
362 #define IXGBE_MACS 0x0429C
363 #define IXGBE_AUTOC 0x042A0
364 #define IXGBE_LINKS 0x042A4
365 #define IXGBE_AUTOC2 0x042A8
366 #define IXGBE_AUTOC3 0x042AC
367 #define IXGBE_ANLP1 0x042B0
368 #define IXGBE_ANLP2 0x042B4
369 #define IXGBE_ATLASCTL 0x04800
370
371 /* RDRXCTL Bit Masks */
372 #define IXGBE_RDRXCTL_RDMTS_1_2 0x00000000 /* Rx Desc Min Threshold Size */
373 #define IXGBE_RDRXCTL_MVMEN 0x00000020
374 #define IXGBE_RDRXCTL_DMAIDONE 0x00000008 /* DMA init cycle done */
375
376 /* CTRL Bit Masks */
377 #define IXGBE_CTRL_GIO_DIS 0x00000004 /* Global IO Master Disable bit */
378 #define IXGBE_CTRL_LNK_RST 0x00000008 /* Link Reset. Resets everything. */
379 #define IXGBE_CTRL_RST 0x04000000 /* Reset (SW) */
380
381 /* FACTPS */
382 #define IXGBE_FACTPS_LFS 0x40000000 /* LAN Function Select */
383
384 /* MHADD Bit Masks */
385 #define IXGBE_MHADD_MFS_MASK 0xFFFF0000
386 #define IXGBE_MHADD_MFS_SHIFT 16
387
388 /* Extended Device Control */
389 #define IXGBE_CTRL_EXT_NS_DIS 0x00010000 /* No Snoop disable */
390 #define IXGBE_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */
391 #define IXGBE_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
392
393 /* Direct Cache Access (DCA) definitions */
394 #define IXGBE_DCA_CTRL_DCA_ENABLE 0x00000000 /* DCA Enable */
395 #define IXGBE_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */
396
397 #define IXGBE_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */
398 #define IXGBE_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */
399
400 #define IXGBE_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
401 #define IXGBE_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */
402 #define IXGBE_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */
403 #define IXGBE_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */
404
405 #define IXGBE_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
406 #define IXGBE_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */
407 #define IXGBE_DCA_TXCTRL_TX_WB_RO_EN (1 << 11) /* Tx Desc writeback RO bit */
408 #define IXGBE_DCA_MAX_QUEUES_82598 16 /* DCA regs only on 16 queues */
409
410 /* MSCA Bit Masks */
411 #define IXGBE_MSCA_NP_ADDR_MASK 0x0000FFFF /* MDI Address (new protocol) */
412 #define IXGBE_MSCA_NP_ADDR_SHIFT 0
413 #define IXGBE_MSCA_DEV_TYPE_MASK 0x001F0000 /* Device Type (new protocol) */
414 #define IXGBE_MSCA_DEV_TYPE_SHIFT 16 /* Register Address (old protocol */
415 #define IXGBE_MSCA_PHY_ADDR_MASK 0x03E00000 /* PHY Address mask */
416 #define IXGBE_MSCA_PHY_ADDR_SHIFT 21 /* PHY Address shift*/
417 #define IXGBE_MSCA_OP_CODE_MASK 0x0C000000 /* OP CODE mask */
418 #define IXGBE_MSCA_OP_CODE_SHIFT 26 /* OP CODE shift */
419 #define IXGBE_MSCA_ADDR_CYCLE 0x00000000 /* OP CODE 00 (addr cycle) */
420 #define IXGBE_MSCA_WRITE 0x04000000 /* OP CODE 01 (write) */
421 #define IXGBE_MSCA_READ 0x08000000 /* OP CODE 10 (read) */
422 #define IXGBE_MSCA_READ_AUTOINC 0x0C000000 /* OP CODE 11 (read, auto inc)*/
423 #define IXGBE_MSCA_ST_CODE_MASK 0x30000000 /* ST Code mask */
424 #define IXGBE_MSCA_ST_CODE_SHIFT 28 /* ST Code shift */
425 #define IXGBE_MSCA_NEW_PROTOCOL 0x00000000 /* ST CODE 00 (new protocol) */
426 #define IXGBE_MSCA_OLD_PROTOCOL 0x10000000 /* ST CODE 01 (old protocol) */
427 #define IXGBE_MSCA_MDI_COMMAND 0x40000000 /* Initiate MDI command */
428 #define IXGBE_MSCA_MDI_IN_PROG_EN 0x80000000 /* MDI in progress enable */
429
430 /* MSRWD bit masks */
431 #define IXGBE_MSRWD_WRITE_DATA_MASK 0x0000FFFF
432 #define IXGBE_MSRWD_WRITE_DATA_SHIFT 0
433 #define IXGBE_MSRWD_READ_DATA_MASK 0xFFFF0000
434 #define IXGBE_MSRWD_READ_DATA_SHIFT 16
435
436 /* Atlas registers */
437 #define IXGBE_ATLAS_PDN_LPBK 0x24
438 #define IXGBE_ATLAS_PDN_10G 0xB
439 #define IXGBE_ATLAS_PDN_1G 0xC
440 #define IXGBE_ATLAS_PDN_AN 0xD
441
442 /* Atlas bit masks */
443 #define IXGBE_ATLASCTL_WRITE_CMD 0x00010000
444 #define IXGBE_ATLAS_PDN_TX_REG_EN 0x10
445 #define IXGBE_ATLAS_PDN_TX_10G_QL_ALL 0xF0
446 #define IXGBE_ATLAS_PDN_TX_1G_QL_ALL 0xF0
447 #define IXGBE_ATLAS_PDN_TX_AN_QL_ALL 0xF0
448
449
450 /* Device Type definitions for new protocol MDIO commands */
451 #define IXGBE_MDIO_PMA_PMD_DEV_TYPE 0x1
452 #define IXGBE_MDIO_PCS_DEV_TYPE 0x3
453 #define IXGBE_MDIO_PHY_XS_DEV_TYPE 0x4
454 #define IXGBE_MDIO_AUTO_NEG_DEV_TYPE 0x7
455 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE 0x1E /* Device 30 */
456
457 #define IXGBE_MDIO_COMMAND_TIMEOUT 100 /* PHY Timeout for 1 GB mode */
458
459 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL 0x0 /* VS1 Control Reg */
460 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS 0x1 /* VS1 Status Reg */
461 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS 0x0008 /* 1 = Link Up */
462 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS 0x0010 /* 0 - 10G, 1 - 1G */
463 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_10G_SPEED 0x0018
464 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_1G_SPEED 0x0010
465
466 #define IXGBE_MDIO_AUTO_NEG_CONTROL 0x0 /* AUTO_NEG Control Reg */
467 #define IXGBE_MDIO_AUTO_NEG_STATUS 0x1 /* AUTO_NEG Status Reg */
468 #define IXGBE_MDIO_PHY_XS_CONTROL 0x0 /* PHY_XS Control Reg */
469 #define IXGBE_MDIO_PHY_XS_RESET 0x8000 /* PHY_XS Reset */
470 #define IXGBE_MDIO_PHY_ID_HIGH 0x2 /* PHY ID High Reg*/
471 #define IXGBE_MDIO_PHY_ID_LOW 0x3 /* PHY ID Low Reg*/
472 #define IXGBE_MDIO_PHY_SPEED_ABILITY 0x4 /* Speed Ability Reg */
473 #define IXGBE_MDIO_PHY_SPEED_10G 0x0001 /* 10G capable */
474 #define IXGBE_MDIO_PHY_SPEED_1G 0x0010 /* 1G capable */
475
476 #define IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR 0xC30A /* PHY_XS SDA/SCL Address Reg */
477 #define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA 0xC30B /* PHY_XS SDA/SCL Data Reg */
478 #define IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT 0xC30C /* PHY_XS SDA/SCL Status Reg */
479
480 /* MII clause 22/28 definitions */
481 #define IXGBE_MDIO_PHY_LOW_POWER_MODE 0x0800
482
483 #define IXGBE_MII_SPEED_SELECTION_REG 0x10
484 #define IXGBE_MII_RESTART 0x200
485 #define IXGBE_MII_AUTONEG_COMPLETE 0x20
486 #define IXGBE_MII_AUTONEG_REG 0x0
487
488 #define IXGBE_PHY_REVISION_MASK 0xFFFFFFF0
489 #define IXGBE_MAX_PHY_ADDR 32
490
491 /* PHY IDs*/
492 #define TN1010_PHY_ID 0x00A19410
493 #define TNX_FW_REV 0xB
494 #define QT2022_PHY_ID 0x0043A400
495
496 /* PHY Types */
497 #define IXGBE_M88E1145_E_PHY_ID 0x01410CD0
498
499 /* General purpose Interrupt Enable */
500 #define IXGBE_SDP0_GPIEN 0x00000001 /* SDP0 */
501 #define IXGBE_SDP1_GPIEN 0x00000002 /* SDP1 */
502 #define IXGBE_GPIE_MSIX_MODE 0x00000010 /* MSI-X mode */
503 #define IXGBE_GPIE_OCD 0x00000020 /* Other Clear Disable */
504 #define IXGBE_GPIE_EIMEN 0x00000040 /* Immediate Interrupt Enable */
505 #define IXGBE_GPIE_EIAME 0x40000000
506 #define IXGBE_GPIE_PBA_SUPPORT 0x80000000
507
508 /* Transmit Flow Control status */
509 #define IXGBE_TFCS_TXOFF 0x00000001
510 #define IXGBE_TFCS_TXOFF0 0x00000100
511 #define IXGBE_TFCS_TXOFF1 0x00000200
512 #define IXGBE_TFCS_TXOFF2 0x00000400
513 #define IXGBE_TFCS_TXOFF3 0x00000800
514 #define IXGBE_TFCS_TXOFF4 0x00001000
515 #define IXGBE_TFCS_TXOFF5 0x00002000
516 #define IXGBE_TFCS_TXOFF6 0x00004000
517 #define IXGBE_TFCS_TXOFF7 0x00008000
518
519 /* TCP Timer */
520 #define IXGBE_TCPTIMER_KS 0x00000100
521 #define IXGBE_TCPTIMER_COUNT_ENABLE 0x00000200
522 #define IXGBE_TCPTIMER_COUNT_FINISH 0x00000400
523 #define IXGBE_TCPTIMER_LOOP 0x00000800
524 #define IXGBE_TCPTIMER_DURATION_MASK 0x000000FF
525
526 /* HLREG0 Bit Masks */
527 #define IXGBE_HLREG0_TXCRCEN 0x00000001 /* bit 0 */
528 #define IXGBE_HLREG0_RXCRCSTRP 0x00000002 /* bit 1 */
529 #define IXGBE_HLREG0_JUMBOEN 0x00000004 /* bit 2 */
530 #define IXGBE_HLREG0_TXPADEN 0x00000400 /* bit 10 */
531 #define IXGBE_HLREG0_TXPAUSEEN 0x00001000 /* bit 12 */
532 #define IXGBE_HLREG0_RXPAUSEEN 0x00004000 /* bit 14 */
533 #define IXGBE_HLREG0_LPBK 0x00008000 /* bit 15 */
534 #define IXGBE_HLREG0_MDCSPD 0x00010000 /* bit 16 */
535 #define IXGBE_HLREG0_CONTMDC 0x00020000 /* bit 17 */
536 #define IXGBE_HLREG0_CTRLFLTR 0x00040000 /* bit 18 */
537 #define IXGBE_HLREG0_PREPEND 0x00F00000 /* bits 20-23 */
538 #define IXGBE_HLREG0_PRIPAUSEEN 0x01000000 /* bit 24 */
539 #define IXGBE_HLREG0_RXPAUSERECDA 0x06000000 /* bits 25-26 */
540 #define IXGBE_HLREG0_RXLNGTHERREN 0x08000000 /* bit 27 */
541 #define IXGBE_HLREG0_RXPADSTRIPEN 0x10000000 /* bit 28 */
542
543 /* VMD_CTL bitmasks */
544 #define IXGBE_VMD_CTL_VMDQ_EN 0x00000001
545 #define IXGBE_VMD_CTL_VMDQ_FILTER 0x00000002
546
547 /* RDHMPN and TDHMPN bitmasks */
548 #define IXGBE_RDHMPN_RDICADDR 0x007FF800
549 #define IXGBE_RDHMPN_RDICRDREQ 0x00800000
550 #define IXGBE_RDHMPN_RDICADDR_SHIFT 11
551 #define IXGBE_TDHMPN_TDICADDR 0x003FF800
552 #define IXGBE_TDHMPN_TDICRDREQ 0x00800000
553 #define IXGBE_TDHMPN_TDICADDR_SHIFT 11
554
555 /* Receive Checksum Control */
556 #define IXGBE_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */
557 #define IXGBE_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */
558
559 /* FCRTL Bit Masks */
560 #define IXGBE_FCRTL_XONE 0x80000000 /* bit 31, XON enable */
561 #define IXGBE_FCRTH_FCEN 0x80000000 /* Rx Flow control enable */
562
563 /* PAP bit masks*/
564 #define IXGBE_PAP_TXPAUSECNT_MASK 0x0000FFFF /* Pause counter mask */
565
566 /* RMCS Bit Masks */
567 #define IXGBE_RMCS_RRM 0x00000002 /* Receive Recycle Mode enable */
568 /* Receive Arbitration Control: 0 Round Robin, 1 DFP */
569 #define IXGBE_RMCS_RAC 0x00000004
570 #define IXGBE_RMCS_DFP IXGBE_RMCS_RAC /* Deficit Fixed Priority ena */
571 #define IXGBE_RMCS_TFCE_802_3X 0x00000008 /* Tx Priority flow control ena */
572 #define IXGBE_RMCS_TFCE_PRIORITY 0x00000010 /* Tx Priority flow control ena */
573 #define IXGBE_RMCS_ARBDIS 0x00000040 /* Arbitration disable bit */
574
575
576 /* Interrupt register bitmasks */
577
578 /* Extended Interrupt Cause Read */
579 #define IXGBE_EICR_RTX_QUEUE 0x0000FFFF /* RTx Queue Interrupt */
580 #define IXGBE_EICR_LSC 0x00100000 /* Link Status Change */
581 #define IXGBE_EICR_MNG 0x00400000 /* Manageability Event Interrupt */
582 #define IXGBE_EICR_GPI_SDP0 0x01000000 /* Gen Purpose Interrupt on SDP0 */
583 #define IXGBE_EICR_GPI_SDP1 0x02000000 /* Gen Purpose Interrupt on SDP1 */
584 #define IXGBE_EICR_PBUR 0x10000000 /* Packet Buffer Handler Error */
585 #define IXGBE_EICR_DHER 0x20000000 /* Descriptor Handler Error */
586 #define IXGBE_EICR_TCP_TIMER 0x40000000 /* TCP Timer */
587 #define IXGBE_EICR_OTHER 0x80000000 /* Interrupt Cause Active */
588
589 /* Extended Interrupt Cause Set */
590 #define IXGBE_EICS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
591 #define IXGBE_EICS_LSC IXGBE_EICR_LSC /* Link Status Change */
592 #define IXGBE_EICS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */
593 #define IXGBE_EICS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
594 #define IXGBE_EICS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
595 #define IXGBE_EICS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */
596 #define IXGBE_EICS_DHER IXGBE_EICR_DHER /* Desc Handler Error */
597 #define IXGBE_EICS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */
598 #define IXGBE_EICS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
599
600 /* Extended Interrupt Mask Set */
601 #define IXGBE_EIMS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
602 #define IXGBE_EIMS_LSC IXGBE_EICR_LSC /* Link Status Change */
603 #define IXGBE_EIMS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */
604 #define IXGBE_EIMS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
605 #define IXGBE_EIMS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
606 #define IXGBE_EIMS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */
607 #define IXGBE_EIMS_DHER IXGBE_EICR_DHER /* Descr Handler Error */
608 #define IXGBE_EIMS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */
609 #define IXGBE_EIMS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
610
611 /* Extended Interrupt Mask Clear */
612 #define IXGBE_EIMC_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
613 #define IXGBE_EIMC_LSC IXGBE_EICR_LSC /* Link Status Change */
614 #define IXGBE_EIMC_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */
615 #define IXGBE_EIMC_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */
616 #define IXGBE_EIMC_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */
617 #define IXGBE_EIMC_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */
618 #define IXGBE_EIMC_DHER IXGBE_EICR_DHER /* Desc Handler Err */
619 #define IXGBE_EIMC_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */
620 #define IXGBE_EIMC_OTHER IXGBE_EICR_OTHER /* INT Cause Active */
621
622 #define IXGBE_EIMS_ENABLE_MASK ( \
623 IXGBE_EIMS_RTX_QUEUE | \
624 IXGBE_EIMS_LSC | \
625 IXGBE_EIMS_TCP_TIMER | \
626 IXGBE_EIMS_OTHER)
627
628 /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
629 #define IXGBE_IMIR_PORT_IM_EN 0x00010000 /* TCP port enable */
630 #define IXGBE_IMIR_PORT_BP 0x00020000 /* TCP port check bypass */
631 #define IXGBE_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */
632 #define IXGBE_IMIREXT_CTRL_URG 0x00002000 /* Check URG bit in header */
633 #define IXGBE_IMIREXT_CTRL_ACK 0x00004000 /* Check ACK bit in header */
634 #define IXGBE_IMIREXT_CTRL_PSH 0x00008000 /* Check PSH bit in header */
635 #define IXGBE_IMIREXT_CTRL_RST 0x00010000 /* Check RST bit in header */
636 #define IXGBE_IMIREXT_CTRL_SYN 0x00020000 /* Check SYN bit in header */
637 #define IXGBE_IMIREXT_CTRL_FIN 0x00040000 /* Check FIN bit in header */
638 #define IXGBE_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of control bits */
639
640 /* Interrupt clear mask */
641 #define IXGBE_IRQ_CLEAR_MASK 0xFFFFFFFF
642
643 /* Interrupt Vector Allocation Registers */
644 #define IXGBE_IVAR_REG_NUM 25
645 #define IXGBE_IVAR_TXRX_ENTRY 96
646 #define IXGBE_IVAR_RX_ENTRY 64
647 #define IXGBE_IVAR_RX_QUEUE(_i) (0 + (_i))
648 #define IXGBE_IVAR_TX_QUEUE(_i) (64 + (_i))
649 #define IXGBE_IVAR_TX_ENTRY 32
650
651 #define IXGBE_IVAR_TCP_TIMER_INDEX 96 /* 0 based index */
652 #define IXGBE_IVAR_OTHER_CAUSES_INDEX 97 /* 0 based index */
653
654 #define IXGBE_MSIX_VECTOR(_i) (0 + (_i))
655
656 #define IXGBE_IVAR_ALLOC_VAL 0x80 /* Interrupt Allocation valid */
657
658 /* VLAN Control Bit Masks */
659 #define IXGBE_VLNCTRL_VET 0x0000FFFF /* bits 0-15 */
660 #define IXGBE_VLNCTRL_CFI 0x10000000 /* bit 28 */
661 #define IXGBE_VLNCTRL_CFIEN 0x20000000 /* bit 29 */
662 #define IXGBE_VLNCTRL_VFE 0x40000000 /* bit 30 */
663 #define IXGBE_VLNCTRL_VME 0x80000000 /* bit 31 */
664
665
666 #define IXGBE_ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.1q protocol */
667
668 /* STATUS Bit Masks */
669 #define IXGBE_STATUS_LAN_ID 0x0000000C /* LAN ID */
670 #define IXGBE_STATUS_GIO 0x00080000 /* GIO Master Enable Status */
671
672 #define IXGBE_STATUS_LAN_ID_0 0x00000000 /* LAN ID 0 */
673 #define IXGBE_STATUS_LAN_ID_1 0x00000004 /* LAN ID 1 */
674
675 /* ESDP Bit Masks */
676 #define IXGBE_ESDP_SDP4 0x00000001 /* SDP4 Data Value */
677 #define IXGBE_ESDP_SDP5 0x00000002 /* SDP5 Data Value */
678 #define IXGBE_ESDP_SDP4_DIR 0x00000004 /* SDP4 IO direction */
679 #define IXGBE_ESDP_SDP5_DIR 0x00000008 /* SDP5 IO direction */
680
681 /* LEDCTL Bit Masks */
682 #define IXGBE_LED_IVRT_BASE 0x00000040
683 #define IXGBE_LED_BLINK_BASE 0x00000080
684 #define IXGBE_LED_MODE_MASK_BASE 0x0000000F
685 #define IXGBE_LED_OFFSET(_base, _i) (_base << (8 * (_i)))
686 #define IXGBE_LED_MODE_SHIFT(_i) (8*(_i))
687 #define IXGBE_LED_IVRT(_i) IXGBE_LED_OFFSET(IXGBE_LED_IVRT_BASE, _i)
688 #define IXGBE_LED_BLINK(_i) IXGBE_LED_OFFSET(IXGBE_LED_BLINK_BASE, _i)
689 #define IXGBE_LED_MODE_MASK(_i) IXGBE_LED_OFFSET(IXGBE_LED_MODE_MASK_BASE, _i)
690
691 /* LED modes */
692 #define IXGBE_LED_LINK_UP 0x0
693 #define IXGBE_LED_LINK_10G 0x1
694 #define IXGBE_LED_MAC 0x2
695 #define IXGBE_LED_FILTER 0x3
696 #define IXGBE_LED_LINK_ACTIVE 0x4
697 #define IXGBE_LED_LINK_1G 0x5
698 #define IXGBE_LED_ON 0xE
699 #define IXGBE_LED_OFF 0xF
700
701 /* AUTOC Bit Masks */
702 #define IXGBE_AUTOC_KX4_SUPP 0x80000000
703 #define IXGBE_AUTOC_KX_SUPP 0x40000000
704 #define IXGBE_AUTOC_PAUSE 0x30000000
705 #define IXGBE_AUTOC_RF 0x08000000
706 #define IXGBE_AUTOC_PD_TMR 0x06000000
707 #define IXGBE_AUTOC_AN_RX_LOOSE 0x01000000
708 #define IXGBE_AUTOC_AN_RX_DRIFT 0x00800000
709 #define IXGBE_AUTOC_AN_RX_ALIGN 0x007C0000
710 #define IXGBE_AUTOC_AN_RESTART 0x00001000
711 #define IXGBE_AUTOC_FLU 0x00000001
712 #define IXGBE_AUTOC_LMS_SHIFT 13
713 #define IXGBE_AUTOC_LMS_MASK (0x7 << IXGBE_AUTOC_LMS_SHIFT)
714 #define IXGBE_AUTOC_LMS_1G_LINK_NO_AN (0x0 << IXGBE_AUTOC_LMS_SHIFT)
715 #define IXGBE_AUTOC_LMS_10G_LINK_NO_AN (0x1 << IXGBE_AUTOC_LMS_SHIFT)
716 #define IXGBE_AUTOC_LMS_1G_AN (0x2 << IXGBE_AUTOC_LMS_SHIFT)
717 #define IXGBE_AUTOC_LMS_KX4_AN (0x4 << IXGBE_AUTOC_LMS_SHIFT)
718 #define IXGBE_AUTOC_LMS_KX4_AN_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT)
719 #define IXGBE_AUTOC_LMS_ATTACH_TYPE (0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
720
721 #define IXGBE_AUTOC_1G_PMA_PMD 0x00000200
722 #define IXGBE_AUTOC_10G_PMA_PMD 0x00000180
723 #define IXGBE_AUTOC_10G_PMA_PMD_SHIFT 7
724 #define IXGBE_AUTOC_1G_PMA_PMD_SHIFT 9
725 #define IXGBE_AUTOC_10G_XAUI (0x0 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
726 #define IXGBE_AUTOC_10G_KX4 (0x1 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
727 #define IXGBE_AUTOC_10G_CX4 (0x2 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
728 #define IXGBE_AUTOC_1G_BX (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
729 #define IXGBE_AUTOC_1G_KX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
730
731 /* LINKS Bit Masks */
732 #define IXGBE_LINKS_KX_AN_COMP 0x80000000
733 #define IXGBE_LINKS_UP 0x40000000
734 #define IXGBE_LINKS_SPEED 0x20000000
735 #define IXGBE_LINKS_MODE 0x18000000
736 #define IXGBE_LINKS_RX_MODE 0x06000000
737 #define IXGBE_LINKS_TX_MODE 0x01800000
738 #define IXGBE_LINKS_XGXS_EN 0x00400000
739 #define IXGBE_LINKS_PCS_1G_EN 0x00200000
740 #define IXGBE_LINKS_1G_AN_EN 0x00100000
741 #define IXGBE_LINKS_KX_AN_IDLE 0x00080000
742 #define IXGBE_LINKS_1G_SYNC 0x00040000
743 #define IXGBE_LINKS_10G_ALIGN 0x00020000
744 #define IXGBE_LINKS_10G_LANE_SYNC 0x00017000
745 #define IXGBE_LINKS_TL_FAULT 0x00001000
746 #define IXGBE_LINKS_SIGNAL 0x00000F00
747
748 #define IXGBE_LINK_UP_TIME 90 /* 9.0 Seconds */
749 #define IXGBE_AUTO_NEG_TIME 45 /* 4.5 Seconds */
750
751 /* SW Semaphore Register bitmasks */
752 #define IXGBE_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
753 #define IXGBE_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
754 #define IXGBE_SWSM_WMNG 0x00000004 /* Wake MNG Clock */
755
756 /* GSSR definitions */
757 #define IXGBE_GSSR_EEP_SM 0x0001
758 #define IXGBE_GSSR_PHY0_SM 0x0002
759 #define IXGBE_GSSR_PHY1_SM 0x0004
760 #define IXGBE_GSSR_MAC_CSR_SM 0x0008
761 #define IXGBE_GSSR_FLASH_SM 0x0010
762
763 /* EEC Register */
764 #define IXGBE_EEC_SK 0x00000001 /* EEPROM Clock */
765 #define IXGBE_EEC_CS 0x00000002 /* EEPROM Chip Select */
766 #define IXGBE_EEC_DI 0x00000004 /* EEPROM Data In */
767 #define IXGBE_EEC_DO 0x00000008 /* EEPROM Data Out */
768 #define IXGBE_EEC_FWE_MASK 0x00000030 /* FLASH Write Enable */
769 #define IXGBE_EEC_FWE_DIS 0x00000010 /* Disable FLASH writes */
770 #define IXGBE_EEC_FWE_EN 0x00000020 /* Enable FLASH writes */
771 #define IXGBE_EEC_FWE_SHIFT 4
772 #define IXGBE_EEC_REQ 0x00000040 /* EEPROM Access Request */
773 #define IXGBE_EEC_GNT 0x00000080 /* EEPROM Access Grant */
774 #define IXGBE_EEC_PRES 0x00000100 /* EEPROM Present */
775 #define IXGBE_EEC_ARD 0x00000200 /* EEPROM Auto Read Done */
776 /* EEPROM Addressing bits based on type (0-small, 1-large) */
777 #define IXGBE_EEC_ADDR_SIZE 0x00000400
778 #define IXGBE_EEC_SIZE 0x00007800 /* EEPROM Size */
779
780 #define IXGBE_EEC_SIZE_SHIFT 11
781 #define IXGBE_EEPROM_WORD_SIZE_SHIFT 6
782 #define IXGBE_EEPROM_OPCODE_BITS 8
783
784 /* Checksum and EEPROM pointers */
785 #define IXGBE_EEPROM_CHECKSUM 0x3F
786 #define IXGBE_EEPROM_SUM 0xBABA
787 #define IXGBE_PCIE_ANALOG_PTR 0x03
788 #define IXGBE_ATLAS0_CONFIG_PTR 0x04
789 #define IXGBE_ATLAS1_CONFIG_PTR 0x05
790 #define IXGBE_PCIE_GENERAL_PTR 0x06
791 #define IXGBE_PCIE_CONFIG0_PTR 0x07
792 #define IXGBE_PCIE_CONFIG1_PTR 0x08
793 #define IXGBE_CORE0_PTR 0x09
794 #define IXGBE_CORE1_PTR 0x0A
795 #define IXGBE_MAC0_PTR 0x0B
796 #define IXGBE_MAC1_PTR 0x0C
797 #define IXGBE_CSR0_CONFIG_PTR 0x0D
798 #define IXGBE_CSR1_CONFIG_PTR 0x0E
799 #define IXGBE_FW_PTR 0x0F
800 #define IXGBE_PBANUM0_PTR 0x15
801 #define IXGBE_PBANUM1_PTR 0x16
802
803 /* Legacy EEPROM word offsets */
804 #define IXGBE_ISCSI_BOOT_CAPS 0x0033
805 #define IXGBE_ISCSI_SETUP_PORT_0 0x0030
806 #define IXGBE_ISCSI_SETUP_PORT_1 0x0034
807
808 /* EEPROM Commands - SPI */
809 #define IXGBE_EEPROM_MAX_RETRY_SPI 5000 /* Max wait 5ms for RDY signal */
810 #define IXGBE_EEPROM_STATUS_RDY_SPI 0x01
811 #define IXGBE_EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */
812 #define IXGBE_EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */
813 #define IXGBE_EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = addr bit-8 */
814 #define IXGBE_EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Ena latch */
815 /* EEPROM reset Write Enable latch */
816 #define IXGBE_EEPROM_WRDI_OPCODE_SPI 0x04
817 #define IXGBE_EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status reg */
818 #define IXGBE_EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status reg */
819 #define IXGBE_EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */
820 #define IXGBE_EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */
821 #define IXGBE_EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */
822
823 /* EEPROM Read Register */
824 #define IXGBE_EEPROM_READ_REG_DATA 16 /* data offset in EEPROM read reg */
825 #define IXGBE_EEPROM_READ_REG_DONE 2 /* Offset to READ done bit */
826 #define IXGBE_EEPROM_READ_REG_START 1 /* First bit to start operation */
827 #define IXGBE_EEPROM_READ_ADDR_SHIFT 2 /* Shift to the address bits */
828
829 #define IXGBE_ETH_LENGTH_OF_ADDRESS 6
830
831 #ifndef IXGBE_EEPROM_GRANT_ATTEMPTS
832 #define IXGBE_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */
833 #endif
834
835 #ifndef IXGBE_EERD_ATTEMPTS
836 /* Number of 5 microseconds we wait for EERD read to complete */
837 #define IXGBE_EERD_ATTEMPTS 100000
838 #endif
839
840 /* PCI Bus Info */
841 #define IXGBE_PCI_LINK_STATUS 0xB2
842 #define IXGBE_PCI_LINK_WIDTH 0x3F0
843 #define IXGBE_PCI_LINK_WIDTH_1 0x10
844 #define IXGBE_PCI_LINK_WIDTH_2 0x20
845 #define IXGBE_PCI_LINK_WIDTH_4 0x40
846 #define IXGBE_PCI_LINK_WIDTH_8 0x80
847 #define IXGBE_PCI_LINK_SPEED 0xF
848 #define IXGBE_PCI_LINK_SPEED_2500 0x1
849 #define IXGBE_PCI_LINK_SPEED_5000 0x2
850
851 /* Number of 100 microseconds we wait for PCI Express master disable */
852 #define IXGBE_PCI_MASTER_DISABLE_TIMEOUT 800
853
854 /* Check whether address is multicast. This is little-endian specific check.*/
855 #define IXGBE_IS_MULTICAST(Address) \
856 (bool)(((u8 *)(Address))[0] & ((u8)0x01))
857
858 /* Check whether an address is broadcast. */
859 #define IXGBE_IS_BROADCAST(Address) \
860 ((((u8 *)(Address))[0] == ((u8)0xff)) && \
861 (((u8 *)(Address))[1] == ((u8)0xff)))
862
863 /* RAH */
864 #define IXGBE_RAH_VIND_MASK 0x003C0000
865 #define IXGBE_RAH_VIND_SHIFT 18
866 #define IXGBE_RAH_AV 0x80000000
867 #define IXGBE_CLEAR_VMDQ_ALL 0xFFFFFFFF
868
869 /* Header split receive */
870 #define IXGBE_RFCTL_ISCSI_DIS 0x00000001
871 #define IXGBE_RFCTL_ISCSI_DWC_MASK 0x0000003E
872 #define IXGBE_RFCTL_ISCSI_DWC_SHIFT 1
873 #define IXGBE_RFCTL_NFSW_DIS 0x00000040
874 #define IXGBE_RFCTL_NFSR_DIS 0x00000080
875 #define IXGBE_RFCTL_NFS_VER_MASK 0x00000300
876 #define IXGBE_RFCTL_NFS_VER_SHIFT 8
877 #define IXGBE_RFCTL_NFS_VER_2 0
878 #define IXGBE_RFCTL_NFS_VER_3 1
879 #define IXGBE_RFCTL_NFS_VER_4 2
880 #define IXGBE_RFCTL_IPV6_DIS 0x00000400
881 #define IXGBE_RFCTL_IPV6_XSUM_DIS 0x00000800
882 #define IXGBE_RFCTL_IPFRSP_DIS 0x00004000
883 #define IXGBE_RFCTL_IPV6_EX_DIS 0x00010000
884 #define IXGBE_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
885
886 /* Transmit Config masks */
887 #define IXGBE_TXDCTL_ENABLE 0x02000000 /* Enable specific Tx Queue */
888 #define IXGBE_TXDCTL_SWFLSH 0x04000000 /* Tx Desc. write-back flushing */
889 /* Enable short packet padding to 64 bytes */
890 #define IXGBE_TX_PAD_ENABLE 0x00000400
891 #define IXGBE_JUMBO_FRAME_ENABLE 0x00000004 /* Allow jumbo frames */
892 /* This allows for 16K packets + 4k for vlan */
893 #define IXGBE_MAX_FRAME_SZ 0x40040000
894
895 #define IXGBE_TDWBAL_HEAD_WB_ENABLE 0x1 /* Tx head write-back enable */
896 #define IXGBE_TDWBAL_SEQNUM_WB_ENABLE 0x2 /* Tx seq# write-back enable */
897
898 /* Receive Config masks */
899 #define IXGBE_RXCTRL_RXEN 0x00000001 /* Enable Receiver */
900 #define IXGBE_RXCTRL_DMBYPS 0x00000002 /* Descriptor Monitor Bypass */
901 #define IXGBE_RXDCTL_ENABLE 0x02000000 /* Enable specific Rx Queue */
902
903 #define IXGBE_FCTRL_SBP 0x00000002 /* Store Bad Packet */
904 #define IXGBE_FCTRL_MPE 0x00000100 /* Multicast Promiscuous Ena*/
905 #define IXGBE_FCTRL_UPE 0x00000200 /* Unicast Promiscuous Ena */
906 #define IXGBE_FCTRL_BAM 0x00000400 /* Broadcast Accept Mode */
907 #define IXGBE_FCTRL_PMCF 0x00001000 /* Pass MAC Control Frames */
908 #define IXGBE_FCTRL_DPF 0x00002000 /* Discard Pause Frame */
909 /* Receive Priority Flow Control Enable */
910 #define IXGBE_FCTRL_RPFCE 0x00004000
911 #define IXGBE_FCTRL_RFCE 0x00008000 /* Receive Flow Control Ena */
912
913 /* Multiple Receive Queue Control */
914 #define IXGBE_MRQC_RSSEN 0x00000001 /* RSS Enable */
915 #define IXGBE_MRQC_RSS_FIELD_MASK 0xFFFF0000
916 #define IXGBE_MRQC_RSS_FIELD_IPV4_TCP 0x00010000
917 #define IXGBE_MRQC_RSS_FIELD_IPV4 0x00020000
918 #define IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP 0x00040000
919 #define IXGBE_MRQC_RSS_FIELD_IPV6_EX 0x00080000
920 #define IXGBE_MRQC_RSS_FIELD_IPV6 0x00100000
921 #define IXGBE_MRQC_RSS_FIELD_IPV6_TCP 0x00200000
922 #define IXGBE_MRQC_RSS_FIELD_IPV4_UDP 0x00400000
923 #define IXGBE_MRQC_RSS_FIELD_IPV6_UDP 0x00800000
924 #define IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP 0x01000000
925
926 #define IXGBE_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
927 #define IXGBE_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
928 #define IXGBE_TXD_CMD_EOP 0x01000000 /* End of Packet */
929 #define IXGBE_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
930 #define IXGBE_TXD_CMD_IC 0x04000000 /* Insert Checksum */
931 #define IXGBE_TXD_CMD_RS 0x08000000 /* Report Status */
932 #define IXGBE_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
933 #define IXGBE_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
934 #define IXGBE_TXD_STAT_DD 0x00000001 /* Descriptor Done */
935
936 /* Receive Descriptor bit definitions */
937 #define IXGBE_RXD_STAT_DD 0x01 /* Descriptor Done */
938 #define IXGBE_RXD_STAT_EOP 0x02 /* End of Packet */
939 #define IXGBE_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
940 #define IXGBE_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */
941 #define IXGBE_RXD_STAT_L4CS 0x20 /* L4 xsum calculated */
942 #define IXGBE_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
943 #define IXGBE_RXD_STAT_PIF 0x80 /* passed in-exact filter */
944 #define IXGBE_RXD_STAT_CRCV 0x100 /* Speculative CRC Valid */
945 #define IXGBE_RXD_STAT_VEXT 0x200 /* 1st VLAN found */
946 #define IXGBE_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */
947 #define IXGBE_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */
948 #define IXGBE_RXD_STAT_ACK 0x8000 /* ACK Packet indication */
949 #define IXGBE_RXD_ERR_CE 0x01 /* CRC Error */
950 #define IXGBE_RXD_ERR_LE 0x02 /* Length Error */
951 #define IXGBE_RXD_ERR_PE 0x08 /* Packet Error */
952 #define IXGBE_RXD_ERR_OSE 0x10 /* Oversize Error */
953 #define IXGBE_RXD_ERR_USE 0x20 /* Undersize Error */
954 #define IXGBE_RXD_ERR_TCPE 0x40 /* TCP/UDP Checksum Error */
955 #define IXGBE_RXD_ERR_IPE 0x80 /* IP Checksum Error */
956 #define IXGBE_RXDADV_ERR_HBO 0x00800000 /*Header Buffer Overflow */
957 #define IXGBE_RXDADV_ERR_CE 0x01000000 /* CRC Error */
958 #define IXGBE_RXDADV_ERR_LE 0x02000000 /* Length Error */
959 #define IXGBE_RXDADV_ERR_PE 0x08000000 /* Packet Error */
960 #define IXGBE_RXDADV_ERR_OSE 0x10000000 /* Oversize Error */
961 #define IXGBE_RXDADV_ERR_USE 0x20000000 /* Undersize Error */
962 #define IXGBE_RXDADV_ERR_TCPE 0x40000000 /* TCP/UDP Checksum Error */
963 #define IXGBE_RXDADV_ERR_IPE 0x80000000 /* IP Checksum Error */
964 #define IXGBE_RXD_VLAN_ID_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
965 #define IXGBE_RXD_PRI_MASK 0xE000 /* Priority is in upper 3 bits */
966 #define IXGBE_RXD_PRI_SHIFT 13
967 #define IXGBE_RXD_CFI_MASK 0x1000 /* CFI is bit 12 */
968 #define IXGBE_RXD_CFI_SHIFT 12
969
970
971 /* SRRCTL bit definitions */
972 #define IXGBE_SRRCTL_BSIZEPKT_SHIFT 10 /* so many KBs */
973 #define IXGBE_SRRCTL_BSIZEPKT_MASK 0x0000007F
974 #define IXGBE_SRRCTL_BSIZEHDR_MASK 0x00003F00
975 #define IXGBE_SRRCTL_DESCTYPE_LEGACY 0x00000000
976 #define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
977 #define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000
978 #define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
979 #define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
980 #define IXGBE_SRRCTL_DESCTYPE_MASK 0x0E000000
981
982 #define IXGBE_RXDPS_HDRSTAT_HDRSP 0x00008000
983 #define IXGBE_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF
984
985 #define IXGBE_RXDADV_RSSTYPE_MASK 0x0000000F
986 #define IXGBE_RXDADV_PKTTYPE_MASK 0x0000FFF0
987 #define IXGBE_RXDADV_HDRBUFLEN_MASK 0x00007FE0
988 #define IXGBE_RXDADV_HDRBUFLEN_SHIFT 5
989 #define IXGBE_RXDADV_SPLITHEADER_EN 0x00001000
990 #define IXGBE_RXDADV_SPH 0x8000
991
992 /* RSS Hash results */
993 #define IXGBE_RXDADV_RSSTYPE_NONE 0x00000000
994 #define IXGBE_RXDADV_RSSTYPE_IPV4_TCP 0x00000001
995 #define IXGBE_RXDADV_RSSTYPE_IPV4 0x00000002
996 #define IXGBE_RXDADV_RSSTYPE_IPV6_TCP 0x00000003
997 #define IXGBE_RXDADV_RSSTYPE_IPV6_EX 0x00000004
998 #define IXGBE_RXDADV_RSSTYPE_IPV6 0x00000005
999 #define IXGBE_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006
1000 #define IXGBE_RXDADV_RSSTYPE_IPV4_UDP 0x00000007
1001 #define IXGBE_RXDADV_RSSTYPE_IPV6_UDP 0x00000008
1002 #define IXGBE_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009
1003
1004 /* RSS Packet Types as indicated in the receive descriptor. */
1005 #define IXGBE_RXDADV_PKTTYPE_NONE 0x00000000
1006 #define IXGBE_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPv4 hdr present */
1007 #define IXGBE_RXDADV_PKTTYPE_IPV4_EX 0x00000020 /* IPv4 hdr + extensions */
1008 #define IXGBE_RXDADV_PKTTYPE_IPV6 0x00000040 /* IPv6 hdr present */
1009 #define IXGBE_RXDADV_PKTTYPE_IPV6_EX 0x00000080 /* IPv6 hdr + extensions */
1010 #define IXGBE_RXDADV_PKTTYPE_TCP 0x00000100 /* TCP hdr present */
1011 #define IXGBE_RXDADV_PKTTYPE_UDP 0x00000200 /* UDP hdr present */
1012 #define IXGBE_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */
1013 #define IXGBE_RXDADV_PKTTYPE_NFS 0x00000800 /* NFS hdr present */
1014 /* Masks to determine if packets should be dropped due to frame errors */
1015 #define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \
1016 IXGBE_RXD_ERR_CE | \
1017 IXGBE_RXD_ERR_LE | \
1018 IXGBE_RXD_ERR_PE | \
1019 IXGBE_RXD_ERR_OSE | \
1020 IXGBE_RXD_ERR_USE)
1021
1022 #define IXGBE_RXDADV_ERR_FRAME_ERR_MASK ( \
1023 IXGBE_RXDADV_ERR_CE | \
1024 IXGBE_RXDADV_ERR_LE | \
1025 IXGBE_RXDADV_ERR_PE | \
1026 IXGBE_RXDADV_ERR_OSE | \
1027 IXGBE_RXDADV_ERR_USE)
1028
1029 /* Multicast bit mask */
1030 #define IXGBE_MCSTCTRL_MFE 0x4
1031
1032 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */
1033 #define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE 8
1034 #define IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE 8
1035 #define IXGBE_REQ_TX_BUFFER_GRANULARITY 1024
1036
1037 /* Vlan-specific macros */
1038 #define IXGBE_RX_DESC_SPECIAL_VLAN_MASK 0x0FFF /* VLAN ID in lower 12 bits */
1039 #define IXGBE_RX_DESC_SPECIAL_PRI_MASK 0xE000 /* Priority in upper 3 bits */
1040 #define IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 0x000D /* Priority in upper 3 of 16 */
1041 #define IXGBE_TX_DESC_SPECIAL_PRI_SHIFT IXGBE_RX_DESC_SPECIAL_PRI_SHIFT
1042
1043
1044 /* Transmit Descriptor - Legacy */
1045 struct ixgbe_legacy_tx_desc {
1046 u64 buffer_addr; /* Address of the descriptor's data buffer */
1047 union {
1048 __le32 data;
1049 struct {
1050 __le16 length; /* Data buffer length */
1051 u8 cso; /* Checksum offset */
1052 u8 cmd; /* Descriptor control */
1053 } flags;
1054 } lower;
1055 union {
1056 __le32 data;
1057 struct {
1058 u8 status; /* Descriptor status */
1059 u8 css; /* Checksum start */
1060 __le16 vlan;
1061 } fields;
1062 } upper;
1063 };
1064
1065 /* Transmit Descriptor - Advanced */
1066 union ixgbe_adv_tx_desc {
1067 struct {
1068 __le64 buffer_addr; /* Address of descriptor's data buf */
1069 __le32 cmd_type_len;
1070 __le32 olinfo_status;
1071 } read;
1072 struct {
1073 __le64 rsvd; /* Reserved */
1074 __le32 nxtseq_seed;
1075 __le32 status;
1076 } wb;
1077 };
1078
1079 /* Receive Descriptor - Legacy */
1080 struct ixgbe_legacy_rx_desc {
1081 __le64 buffer_addr; /* Address of the descriptor's data buffer */
1082 __le16 length; /* Length of data DMAed into data buffer */
1083 __le16 csum; /* Packet checksum */
1084 u8 status; /* Descriptor status */
1085 u8 errors; /* Descriptor Errors */
1086 __le16 vlan;
1087 };
1088
1089 /* Receive Descriptor - Advanced */
1090 union ixgbe_adv_rx_desc {
1091 struct {
1092 __le64 pkt_addr; /* Packet buffer address */
1093 __le64 hdr_addr; /* Header buffer address */
1094 } read;
1095 struct {
1096 struct {
1097 union {
1098 __le32 data;
1099 struct {
1100 __le16 pkt_info; /* RSS, Pkt type */
1101 __le16 hdr_info; /* Splithdr, hdrlen */
1102 } hs_rss;
1103 } lo_dword;
1104 union {
1105 __le32 rss; /* RSS Hash */
1106 struct {
1107 __le16 ip_id; /* IP id */
1108 __le16 csum; /* Packet Checksum */
1109 } csum_ip;
1110 } hi_dword;
1111 } lower;
1112 struct {
1113 __le32 status_error; /* ext status/error */
1114 __le16 length; /* Packet length */
1115 __le16 vlan; /* VLAN tag */
1116 } upper;
1117 } wb; /* writeback */
1118 };
1119
1120 /* Context descriptors */
1121 struct ixgbe_adv_tx_context_desc {
1122 __le32 vlan_macip_lens;
1123 __le32 seqnum_seed;
1124 __le32 type_tucmd_mlhl;
1125 __le32 mss_l4len_idx;
1126 };
1127
1128 /* Adv Transmit Descriptor Config Masks */
1129 #define IXGBE_ADVTXD_DTALEN_MASK 0x0000FFFF /* Data buf length(bytes) */
1130 #define IXGBE_ADVTXD_DTYP_MASK 0x00F00000 /* DTYP mask */
1131 #define IXGBE_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Desc */
1132 #define IXGBE_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */
1133 #define IXGBE_ADVTXD_DCMD_EOP IXGBE_TXD_CMD_EOP /* End of Packet */
1134 #define IXGBE_ADVTXD_DCMD_IFCS IXGBE_TXD_CMD_IFCS /* Insert FCS */
1135 #define IXGBE_ADVTXD_DCMD_RS IXGBE_TXD_CMD_RS /* Report Status */
1136 #define IXGBE_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000 /* DDP hdr type or iSCSI */
1137 #define IXGBE_ADVTXD_DCMD_DEXT IXGBE_TXD_CMD_DEXT /* Desc ext (1=Adv) */
1138 #define IXGBE_ADVTXD_DCMD_VLE IXGBE_TXD_CMD_VLE /* VLAN pkt enable */
1139 #define IXGBE_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */
1140 #define IXGBE_ADVTXD_STAT_DD IXGBE_TXD_STAT_DD /* Descriptor Done */
1141 #define IXGBE_ADVTXD_STAT_SN_CRC 0x00000002 /* NXTSEQ/SEED pres in WB */
1142 #define IXGBE_ADVTXD_STAT_RSV 0x0000000C /* STA Reserved */
1143 #define IXGBE_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */
1144 #define IXGBE_ADVTXD_CC 0x00000080 /* Check Context */
1145 #define IXGBE_ADVTXD_POPTS_SHIFT 8 /* Adv desc POPTS shift */
1146 #define IXGBE_ADVTXD_POPTS_IXSM (IXGBE_TXD_POPTS_IXSM << \
1147 IXGBE_ADVTXD_POPTS_SHIFT)
1148 #define IXGBE_ADVTXD_POPTS_TXSM (IXGBE_TXD_POPTS_TXSM << \
1149 IXGBE_ADVTXD_POPTS_SHIFT)
1150 #define IXGBE_ADVTXD_POPTS_ISCO_1ST 0x00000000 /* 1st TSO of iSCSI PDU */
1151 #define IXGBE_ADVTXD_POPTS_ISCO_MDL 0x00000800 /* Middle TSO of iSCSI PDU */
1152 #define IXGBE_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */
1153 #define IXGBE_ADVTXD_POPTS_ISCO_FULL 0x00001800 /* 1st&Last TSO-full iSCSI PDU */
1154 #define IXGBE_ADVTXD_POPTS_RSV 0x00002000 /* POPTS Reserved */
1155 #define IXGBE_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */
1156 #define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
1157 #define IXGBE_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */
1158 #define IXGBE_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */
1159 #define IXGBE_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */
1160 #define IXGBE_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */
1161 #define IXGBE_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */
1162 #define IXGBE_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */
1163 #define IXGBE_ADVTXD_TUCMD_MKRREQ 0x00002000 /*Req requires Markers and CRC*/
1164 #define IXGBE_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
1165 #define IXGBE_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
1166
1167 /* Autonegotiation advertised speeds */
1168 typedef u32 ixgbe_autoneg_advertised;
1169 /* Link speed */
1170 typedef u32 ixgbe_link_speed;
1171 #define IXGBE_LINK_SPEED_UNKNOWN 0
1172 #define IXGBE_LINK_SPEED_100_FULL 0x0008
1173 #define IXGBE_LINK_SPEED_1GB_FULL 0x0020
1174 #define IXGBE_LINK_SPEED_10GB_FULL 0x0080
1175 #define IXGBE_LINK_SPEED_82598_AUTONEG (IXGBE_LINK_SPEED_1GB_FULL | \
1176 IXGBE_LINK_SPEED_10GB_FULL)
1177
1178 /* Physical layer type */
1179 typedef u32 ixgbe_physical_layer;
1180 #define IXGBE_PHYSICAL_LAYER_UNKNOWN 0
1181 #define IXGBE_PHYSICAL_LAYER_10GBASE_T 0x0001
1182 #define IXGBE_PHYSICAL_LAYER_1000BASE_T 0x0002
1183 #define IXGBE_PHYSICAL_LAYER_100BASE_T 0x0004
1184 #define IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU 0x0008
1185 #define IXGBE_PHYSICAL_LAYER_10GBASE_LR 0x0010
1186 #define IXGBE_PHYSICAL_LAYER_10GBASE_LRM 0x0020
1187 #define IXGBE_PHYSICAL_LAYER_10GBASE_SR 0x0040
1188 #define IXGBE_PHYSICAL_LAYER_10GBASE_KX4 0x0080
1189 #define IXGBE_PHYSICAL_LAYER_10GBASE_CX4 0x0100
1190 #define IXGBE_PHYSICAL_LAYER_1000BASE_KX 0x0200
1191 #define IXGBE_PHYSICAL_LAYER_1000BASE_BX 0x0400
1192
1193
1194 enum ixgbe_eeprom_type {
1195 ixgbe_eeprom_uninitialized = 0,
1196 ixgbe_eeprom_spi,
1197 ixgbe_eeprom_none /* No NVM support */
1198 };
1199
1200 enum ixgbe_mac_type {
1201 ixgbe_mac_unknown = 0,
1202 ixgbe_mac_82598EB,
1203 ixgbe_num_macs
1204 };
1205
1206 enum ixgbe_phy_type {
1207 ixgbe_phy_unknown = 0,
1208 ixgbe_phy_tn,
1209 ixgbe_phy_qt,
1210 ixgbe_phy_xaui,
1211 ixgbe_phy_tw_tyco,
1212 ixgbe_phy_tw_unknown,
1213 ixgbe_phy_sfp_avago,
1214 ixgbe_phy_sfp_ftl,
1215 ixgbe_phy_sfp_unknown,
1216 ixgbe_phy_generic
1217 };
1218
1219 /*
1220 * SFP+ module type IDs:
1221 *
1222 * ID Module Type
1223 * =============
1224 * 0 SFP_DA_CU
1225 * 1 SFP_SR
1226 * 2 SFP_LR
1227 */
1228 enum ixgbe_sfp_type {
1229 ixgbe_sfp_type_da_cu = 0,
1230 ixgbe_sfp_type_sr = 1,
1231 ixgbe_sfp_type_lr = 2,
1232 ixgbe_sfp_type_unknown = 0xFFFF
1233 };
1234
1235 enum ixgbe_media_type {
1236 ixgbe_media_type_unknown = 0,
1237 ixgbe_media_type_fiber,
1238 ixgbe_media_type_copper,
1239 ixgbe_media_type_backplane,
1240 ixgbe_media_type_virtual
1241 };
1242
1243 /* Flow Control Settings */
1244 enum ixgbe_fc_type {
1245 ixgbe_fc_none = 0,
1246 ixgbe_fc_rx_pause,
1247 ixgbe_fc_tx_pause,
1248 ixgbe_fc_full,
1249 ixgbe_fc_default
1250 };
1251
1252 struct ixgbe_addr_filter_info {
1253 u32 num_mc_addrs;
1254 u32 rar_used_count;
1255 u32 mc_addr_in_rar_count;
1256 u32 mta_in_use;
1257 u32 overflow_promisc;
1258 bool user_set_promisc;
1259 };
1260
1261 /* Flow control parameters */
1262 struct ixgbe_fc_info {
1263 u32 high_water; /* Flow Control High-water */
1264 u32 low_water; /* Flow Control Low-water */
1265 u16 pause_time; /* Flow Control Pause timer */
1266 bool send_xon; /* Flow control send XON */
1267 bool strict_ieee; /* Strict IEEE mode */
1268 enum ixgbe_fc_type type; /* Type of flow control */
1269 enum ixgbe_fc_type original_type;
1270 };
1271
1272 /* Statistics counters collected by the MAC */
1273 struct ixgbe_hw_stats {
1274 u64 crcerrs;
1275 u64 illerrc;
1276 u64 errbc;
1277 u64 mspdc;
1278 u64 mpctotal;
1279 u64 mpc[8];
1280 u64 mlfc;
1281 u64 mrfc;
1282 u64 rlec;
1283 u64 lxontxc;
1284 u64 lxonrxc;
1285 u64 lxofftxc;
1286 u64 lxoffrxc;
1287 u64 pxontxc[8];
1288 u64 pxonrxc[8];
1289 u64 pxofftxc[8];
1290 u64 pxoffrxc[8];
1291 u64 prc64;
1292 u64 prc127;
1293 u64 prc255;
1294 u64 prc511;
1295 u64 prc1023;
1296 u64 prc1522;
1297 u64 gprc;
1298 u64 bprc;
1299 u64 mprc;
1300 u64 gptc;
1301 u64 gorc;
1302 u64 gotc;
1303 u64 rnbc[8];
1304 u64 ruc;
1305 u64 rfc;
1306 u64 roc;
1307 u64 rjc;
1308 u64 mngprc;
1309 u64 mngpdc;
1310 u64 mngptc;
1311 u64 tor;
1312 u64 tpr;
1313 u64 tpt;
1314 u64 ptc64;
1315 u64 ptc127;
1316 u64 ptc255;
1317 u64 ptc511;
1318 u64 ptc1023;
1319 u64 ptc1522;
1320 u64 mptc;
1321 u64 bptc;
1322 u64 xec;
1323 u64 rqsmr[16];
1324 u64 tqsmr[8];
1325 u64 qprc[16];
1326 u64 qptc[16];
1327 u64 qbrc[16];
1328 u64 qbtc[16];
1329 };
1330
1331 /* forward declaration */
1332 struct ixgbe_hw;
1333
1334 /* iterator type for walking multicast address lists */
1335 typedef u8* (*ixgbe_mc_addr_itr) (struct ixgbe_hw *hw, u8 **mc_addr_ptr,
1336 u32 *vmdq);
1337
1338 /* Function pointer table */
1339 struct ixgbe_eeprom_operations {
1340 s32 (*init_params)(struct ixgbe_hw *);
1341 s32 (*read)(struct ixgbe_hw *, u16, u16 *);
1342 s32 (*write)(struct ixgbe_hw *, u16, u16);
1343 s32 (*validate_checksum)(struct ixgbe_hw *, u16 *);
1344 s32 (*update_checksum)(struct ixgbe_hw *);
1345 };
1346
1347 struct ixgbe_mac_operations {
1348 s32 (*init_hw)(struct ixgbe_hw *);
1349 s32 (*reset_hw)(struct ixgbe_hw *);
1350 s32 (*start_hw)(struct ixgbe_hw *);
1351 s32 (*clear_hw_cntrs)(struct ixgbe_hw *);
1352 enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *);
1353 s32 (*get_supported_physical_layer)(struct ixgbe_hw *);
1354 s32 (*get_mac_addr)(struct ixgbe_hw *, u8 *);
1355 s32 (*stop_adapter)(struct ixgbe_hw *);
1356 s32 (*get_bus_info)(struct ixgbe_hw *);
1357 s32 (*read_analog_reg8)(struct ixgbe_hw*, u32, u8*);
1358 s32 (*write_analog_reg8)(struct ixgbe_hw*, u32, u8);
1359
1360 /* Link */
1361 s32 (*setup_link)(struct ixgbe_hw *);
1362 s32 (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool,
1363 bool);
1364 s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool);
1365 s32 (*get_link_capabilities)(struct ixgbe_hw *, ixgbe_link_speed *,
1366 bool *);
1367
1368 /* LED */
1369 s32 (*led_on)(struct ixgbe_hw *, u32);
1370 s32 (*led_off)(struct ixgbe_hw *, u32);
1371 s32 (*blink_led_start)(struct ixgbe_hw *, u32);
1372 s32 (*blink_led_stop)(struct ixgbe_hw *, u32);
1373
1374 /* RAR, Multicast, VLAN */
1375 s32 (*set_rar)(struct ixgbe_hw *, u32, u8 *, u32, u32);
1376 s32 (*clear_rar)(struct ixgbe_hw *, u32);
1377 s32 (*set_vmdq)(struct ixgbe_hw *, u32, u32);
1378 s32 (*clear_vmdq)(struct ixgbe_hw *, u32, u32);
1379 s32 (*init_rx_addrs)(struct ixgbe_hw *);
1380 s32 (*update_uc_addr_list)(struct ixgbe_hw *, u8 *, u32,
1381 ixgbe_mc_addr_itr);
1382 s32 (*update_mc_addr_list)(struct ixgbe_hw *, u8 *, u32,
1383 ixgbe_mc_addr_itr);
1384 s32 (*enable_mc)(struct ixgbe_hw *);
1385 s32 (*disable_mc)(struct ixgbe_hw *);
1386 s32 (*clear_vfta)(struct ixgbe_hw *);
1387 s32 (*set_vfta)(struct ixgbe_hw *, u32, u32, bool);
1388 s32 (*init_uta_tables)(struct ixgbe_hw *);
1389
1390 /* Flow Control */
1391 s32 (*setup_fc)(struct ixgbe_hw *, s32);
1392 };
1393
1394 struct ixgbe_phy_operations {
1395 s32 (*identify)(struct ixgbe_hw *);
1396 s32 (*identify_sfp)(struct ixgbe_hw *);
1397 s32 (*reset)(struct ixgbe_hw *);
1398 s32 (*read_reg)(struct ixgbe_hw *, u32, u32, u16 *);
1399 s32 (*write_reg)(struct ixgbe_hw *, u32, u32, u16);
1400 s32 (*setup_link)(struct ixgbe_hw *);
1401 s32 (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool,
1402 bool);
1403 s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *);
1404 s32 (*get_firmware_version)(struct ixgbe_hw *, u16 *);
1405 s32 (*read_i2c_byte)(struct ixgbe_hw *, u8, u8, u8 *);
1406 s32 (*write_i2c_byte)(struct ixgbe_hw *, u8, u8, u8);
1407 s32 (*read_i2c_eeprom)(struct ixgbe_hw *, u8 , u8 *);
1408 s32 (*write_i2c_eeprom)(struct ixgbe_hw *, u8, u8);
1409 };
1410
1411 struct ixgbe_eeprom_info {
1412 struct ixgbe_eeprom_operations ops;
1413 enum ixgbe_eeprom_type type;
1414 u32 semaphore_delay;
1415 u16 word_size;
1416 u16 address_bits;
1417 };
1418
1419 struct ixgbe_mac_info {
1420 struct ixgbe_mac_operations ops;
1421 enum ixgbe_mac_type type;
1422 u8 addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
1423 u8 perm_addr[IXGBE_ETH_LENGTH_OF_ADDRESS];
1424 s32 mc_filter_type;
1425 u32 mcft_size;
1426 u32 vft_size;
1427 u32 num_rar_entries;
1428 u32 max_tx_queues;
1429 u32 max_rx_queues;
1430 u32 link_attach_type;
1431 u32 link_mode_select;
1432 bool link_settings_loaded;
1433 bool autoneg;
1434 bool autoneg_failed;
1435 };
1436
1437 struct ixgbe_phy_info {
1438 struct ixgbe_phy_operations ops;
1439 enum ixgbe_phy_type type;
1440 u32 addr;
1441 u32 id;
1442 enum ixgbe_sfp_type sfp_type;
1443 u32 revision;
1444 enum ixgbe_media_type media_type;
1445 bool reset_disable;
1446 ixgbe_autoneg_advertised autoneg_advertised;
1447 bool autoneg_wait_to_complete;
1448 };
1449
1450 struct ixgbe_hw {
1451 u8 __iomem *hw_addr;
1452 void *back;
1453 struct ixgbe_mac_info mac;
1454 struct ixgbe_addr_filter_info addr_ctrl;
1455 struct ixgbe_fc_info fc;
1456 struct ixgbe_phy_info phy;
1457 struct ixgbe_eeprom_info eeprom;
1458 u16 device_id;
1459 u16 vendor_id;
1460 u16 subsystem_device_id;
1461 u16 subsystem_vendor_id;
1462 u8 revision_id;
1463 bool adapter_stopped;
1464 };
1465
1466 struct ixgbe_info {
1467 enum ixgbe_mac_type mac;
1468 s32 (*get_invariants)(struct ixgbe_hw *);
1469 struct ixgbe_mac_operations *mac_ops;
1470 struct ixgbe_eeprom_operations *eeprom_ops;
1471 struct ixgbe_phy_operations *phy_ops;
1472 };
1473
1474
1475 /* Error Codes */
1476 #define IXGBE_ERR_EEPROM -1
1477 #define IXGBE_ERR_EEPROM_CHECKSUM -2
1478 #define IXGBE_ERR_PHY -3
1479 #define IXGBE_ERR_CONFIG -4
1480 #define IXGBE_ERR_PARAM -5
1481 #define IXGBE_ERR_MAC_TYPE -6
1482 #define IXGBE_ERR_UNKNOWN_PHY -7
1483 #define IXGBE_ERR_LINK_SETUP -8
1484 #define IXGBE_ERR_ADAPTER_STOPPED -9
1485 #define IXGBE_ERR_INVALID_MAC_ADDR -10
1486 #define IXGBE_ERR_DEVICE_NOT_SUPPORTED -11
1487 #define IXGBE_ERR_MASTER_REQUESTS_PENDING -12
1488 #define IXGBE_ERR_INVALID_LINK_SETTINGS -13
1489 #define IXGBE_ERR_AUTONEG_NOT_COMPLETE -14
1490 #define IXGBE_ERR_RESET_FAILED -15
1491 #define IXGBE_ERR_SWFW_SYNC -16
1492 #define IXGBE_ERR_PHY_ADDR_INVALID -17
1493 #define IXGBE_ERR_I2C -18
1494 #define IXGBE_ERR_SFP_NOT_SUPPORTED -19
1495 #define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF
1496
1497 #endif /* _IXGBE_TYPE_H_ */
Linux 2.6 libata-dev (mirror)