arch/arm/mach-pxa/time.c

   1 /*
   2  * arch/arm/mach-pxa/time.c
   3  *
   4  * PXA clocksource, clockevents, and OST interrupt handlers.
   5  * Copyright (c) 2007 by Bill Gatliff <bgat@billgatliff.com>.
   6  *
   7  * Derived from Nicolas Pitre's PXA timer handler Copyright (c) 2001
   8  * by MontaVista Software, Inc.  (Nico, your code rocks!)
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/clockchips.h>
  19 #include <linux/sched.h>
  20
  21 #include <asm/div64.h>
  22 #include <asm/cnt32_to_63.h>
  23 #include <asm/mach/irq.h>
  24 #include <asm/mach/time.h>
  25 #include <asm/arch/pxa-regs.h>
  26 #include <asm/mach-types.h>
  27
  28 /*
  29  * This is PXA's sched_clock implementation. This has a resolution
  30  * of at least 308 ns and a maximum value of 208 days.
  31  *
  32  * The return value is guaranteed to be monotonic in that range as
  33  * long as there is always less than 582 seconds between successive
  34  * calls to sched_clock() which should always be the case in practice.
  35  */
  36
  37 #define OSCR2NS_SCALE_FACTOR 10
  38
  39 static unsigned long oscr2ns_scale;
  40
  41 static void __init set_oscr2ns_scale(unsigned long oscr_rate)
  42 {
  43         unsigned long long v = 1000000000ULL << OSCR2NS_SCALE_FACTOR;
  44         do_div(v, oscr_rate);
  45         oscr2ns_scale = v;
  46         /*
  47          * We want an even value to automatically clear the top bit
  48          * returned by cnt32_to_63() without an additional run time
  49          * instruction. So if the LSB is 1 then round it up.
  50          */
  51         if (oscr2ns_scale & 1)
  52                 oscr2ns_scale++;
  53 }
  54
  55 unsigned long long sched_clock(void)
  56 {
  57         unsigned long long v = cnt32_to_63(OSCR);
  58         return (v * oscr2ns_scale) >> OSCR2NS_SCALE_FACTOR;
  59 }
  60
  61
  62 static irqreturn_t
  63 pxa_ost0_interrupt(int irq, void *dev_id)
  64 {
  65         int next_match;
  66         struct clock_event_device *c = dev_id;
  67
  68         if (c->mode == CLOCK_EVT_MODE_ONESHOT) {
  69                 /* Disarm the compare/match, signal the event. */
  70                 OIER &= ~OIER_E0;
  71                 c->event_handler(c);
  72         } else if (c->mode == CLOCK_EVT_MODE_PERIODIC) {
  73                 /* Call the event handler as many times as necessary
  74                  * to recover missed events, if any (if we update
  75                  * OSMR0 and OSCR0 is still ahead of us, we've missed
  76                  * the event).  As we're dealing with that, re-arm the
  77                  * compare/match for the next event.
  78                  *
  79                  * HACK ALERT:
  80                  *
  81                  * There's a latency between the instruction that
  82                  * writes to OSMR0 and the actual commit to the
  83                  * physical hardware, because the CPU doesn't (have
  84                  * to) run at bus speed, there's a write buffer
  85                  * between the CPU and the bus, etc. etc.  So if the
  86                  * target OSCR0 is "very close", to the OSMR0 load
  87                  * value, the update to OSMR0 might not get to the
  88                  * hardware in time and we'll miss that interrupt.
  89                  *
  90                  * To be safe, if the new OSMR0 is "very close" to the
  91                  * target OSCR0 value, we call the event_handler as
  92                  * though the event actually happened.  According to
  93                  * Nico's comment in the previous version of this
  94                  * code, experience has shown that 6 OSCR ticks is
  95                  * "very close" but he went with 8.  We will use 16,
  96                  * based on the results of testing on PXA270.
  97                  *
  98                  * To be doubly sure, we also tell clkevt via
  99                  * clockevents_register_device() not to ask for
 100                  * anything that might put us "very close".
 101          */
 102 #define MIN_OSCR_DELTA 16
 103         do {
 104                         OSSR = OSSR_M0;
 105                 next_match = (OSMR0 += LATCH);
 106                         c->event_handler(c);
 107                 } while (((signed long)(next_match - OSCR) <= MIN_OSCR_DELTA)
 108                          && (c->mode == CLOCK_EVT_MODE_PERIODIC));
 109         }
 110
 111         return IRQ_HANDLED;
 112 }
 113
 114 static int
 115 pxa_osmr0_set_next_event(unsigned long delta, struct clock_event_device *dev)
 116 {
 117         unsigned long irqflags;
 118
 119         raw_local_irq_save(irqflags);
 120         OSMR0 = OSCR + delta;
 121         OSSR = OSSR_M0;
 122         OIER |= OIER_E0;
 123         raw_local_irq_restore(irqflags);
 124         return 0;
 125 }
 126
 127 static void
 128 pxa_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *dev)
 129 {
 130         unsigned long irqflags;
 131
 132         switch (mode) {
 133         case CLOCK_EVT_MODE_PERIODIC:
 134                 raw_local_irq_save(irqflags);
 135                 OSMR0 = OSCR + LATCH;
 136                 OSSR = OSSR_M0;
 137                 OIER |= OIER_E0;
 138                 raw_local_irq_restore(irqflags);
 139                 break;
 140
 141         case CLOCK_EVT_MODE_ONESHOT:
 142                 raw_local_irq_save(irqflags);
 143                 OIER &= ~OIER_E0;
 144                 raw_local_irq_restore(irqflags);
 145                 break;
 146
 147         case CLOCK_EVT_MODE_UNUSED:
 148         case CLOCK_EVT_MODE_SHUTDOWN:
 149                 /* initializing, released, or preparing for suspend */
 150                 raw_local_irq_save(irqflags);
 151                 OIER &= ~OIER_E0;
 152                 raw_local_irq_restore(irqflags);
 153                 break;
 154         }
 155 }
 156
 157 static struct clock_event_device ckevt_pxa_osmr0 = {
 158         .name           = "osmr0",
 159         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 160         .shift          = 32,
 161         .rating         = 200,
 162         .cpumask        = CPU_MASK_CPU0,
 163         .set_next_event = pxa_osmr0_set_next_event,
 164         .set_mode       = pxa_osmr0_set_mode,
 165 };
 166
 167 static cycle_t pxa_read_oscr(void)
 168 {
 169         return OSCR;
 170 }
 171
 172 static struct clocksource cksrc_pxa_oscr0 = {
 173         .name           = "oscr0",
 174         .rating         = 200,
 175         .read           = pxa_read_oscr,
 176         .mask           = CLOCKSOURCE_MASK(32),
 177         .shift          = 20,
 178         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 179 };
 180
 181 static struct irqaction pxa_ost0_irq = {
 182         .name           = "ost0",
 183         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 184         .handler        = pxa_ost0_interrupt,
 185         .dev_id         = &ckevt_pxa_osmr0,
 186 };
 187
 188 static void __init pxa_timer_init(void)
 189 {
 190         unsigned long clock_tick_rate;
 191
 192         OIER = 0;
 193         OSSR = OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3;
 194
 195         if (cpu_is_pxa21x() || cpu_is_pxa25x())
 196                 clock_tick_rate = 3686400;
 197         else if (machine_is_mainstone())
 198                 clock_tick_rate = 3249600;
 199         else
 200                 clock_tick_rate = 3250000;
 201
 202         set_oscr2ns_scale(clock_tick_rate);
 203
 204         ckevt_pxa_osmr0.mult =
 205                 div_sc(clock_tick_rate, NSEC_PER_SEC, ckevt_pxa_osmr0.shift);
 206         ckevt_pxa_osmr0.max_delta_ns =
 207                 clockevent_delta2ns(0x7fffffff, &ckevt_pxa_osmr0);
 208         ckevt_pxa_osmr0.min_delta_ns =
 209                 clockevent_delta2ns(MIN_OSCR_DELTA, &ckevt_pxa_osmr0) + 1;
 210
 211         cksrc_pxa_oscr0.mult =
 212                 clocksource_hz2mult(clock_tick_rate, cksrc_pxa_oscr0.shift);
 213
 214         setup_irq(IRQ_OST0, &pxa_ost0_irq);
 215
 216         clocksource_register(&cksrc_pxa_oscr0);
 217         clockevents_register_device(&ckevt_pxa_osmr0);
 218 }
 219
 220 #ifdef CONFIG_PM
 221 static unsigned long osmr[4], oier;
 222
 223 static void pxa_timer_suspend(void)
 224 {
 225         osmr[0] = OSMR0;
 226         osmr[1] = OSMR1;
 227         osmr[2] = OSMR2;
 228         osmr[3] = OSMR3;
 229         oier = OIER;
 230 }
 231
 232 static void pxa_timer_resume(void)
 233 {
 234         OSMR0 = osmr[0];
 235         OSMR1 = osmr[1];
 236         OSMR2 = osmr[2];
 237         OSMR3 = osmr[3];
 238         OIER = oier;
 239
 240         /*
 241          * OSCR0 is the system timer, which has to increase
 242          * monotonically until it rolls over in hardware.  The value
 243          * (OSMR0 - LATCH) is OSCR0 at the most recent system tick,
 244          * which is a handy value to restore to OSCR0.
 245          */
 246         OSCR = OSMR0 - LATCH;
 247 }
 248 #else
 249 #define pxa_timer_suspend NULL
 250 #define pxa_timer_resume NULL
 251 #endif
 252
 253 struct sys_timer pxa_timer = {
 254         .init           = pxa_timer_init,
 255         .suspend        = pxa_timer_suspend,
 256         .resume         = pxa_timer_resume,
 257 };