| blob | f261d2a9a5f00bafd2e02f6cb4b119378773c04a |
1 /*
2 * amd5536.c -- AMD 5536 UDC high/full speed USB device controller
3 *
4 * Copyright (C) 2005-2007 AMD (http://www.amd.com)
5 * Author: Thomas Dahlmann
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
22 /*
23 * The AMD5536 UDC is part of the x86 southbridge AMD Geode CS5536.
24 * It is a USB Highspeed DMA capable USB device controller. Beside ep0 it
25 * provides 4 IN and 4 OUT endpoints (bulk or interrupt type).
26 *
27 * Make sure that UDC is assigned to port 4 by BIOS settings (port can also
28 * be used as host port) and UOC bits PAD_EN and APU are set (should be done
29 * by BIOS init).
30 *
31 * UDC DMA requires 32-bit aligned buffers so DMA with gadget ether does not
32 * work without updating NET_IP_ALIGN. Or PIO mode (module param "use_dma=0")
33 * can be used with gadget ether.
34 */
36 /* debug control */
37 /* #define UDC_VERBOSE */
39 /* Driver strings */
43 /* system */
44 #include <linux/module.h>
45 #include <linux/pci.h>
46 #include <linux/kernel.h>
47 #include <linux/version.h>
48 #include <linux/delay.h>
49 #include <linux/ioport.h>
50 #include <linux/sched.h>
51 #include <linux/slab.h>
52 #include <linux/smp_lock.h>
53 #include <linux/errno.h>
54 #include <linux/init.h>
55 #include <linux/timer.h>
56 #include <linux/list.h>
57 #include <linux/interrupt.h>
58 #include <linux/ioctl.h>
59 #include <linux/fs.h>
60 #include <linux/dmapool.h>
61 #include <linux/moduleparam.h>
62 #include <linux/device.h>
63 #include <linux/io.h>
64 #include <linux/irq.h>
66 #include <asm/byteorder.h>
67 #include <asm/system.h>
68 #include <asm/unaligned.h>
70 /* gadget stack */
71 #include <linux/usb/ch9.h>
72 #include <linux/usb/gadget.h>
74 /* udc specific */
93 /* description */
97 /* structure to hold endpoint function pointers */
100 /* received setup data */
103 /* pointer to device object */
106 /* irq spin lock for soft reset */
108 /* stall spin lock */
111 /*
112 * slave mode: pending bytes in rx fifo after nyet,
113 * used if EPIN irq came but no req was available
114 */
117 /* count soft resets after suspend to avoid loop */
121 /* timer */
125 /* set_rde -- Is used to control enabling of RX DMA. Problem is
126 * that UDC has only one bit (RDE) to enable/disable RX DMA for
127 * all OUT endpoints. So we have to handle race conditions like
128 * when OUT data reaches the fifo but no request was queued yet.
129 * This cannot be solved by letting the RX DMA disabled until a
130 * request gets queued because there may be other OUT packets
131 * in the FIFO (important for not blocking control traffic).
132 * The value of set_rde controls the correspondig timer.
133 *
134 * set_rde -1 == not used, means it is alloed to be set to 0 or 1
135 * set_rde 0 == do not touch RDE, do no start the RDE timer
136 * set_rde 1 == timer function will look whether FIFO has data
137 * set_rde 2 == set by timer function to enable RX DMA on next call
138 */
146 /* tasklet for usb disconnect */
151 /* endpoint names used for print */
154 ep0_string,
162 };
164 /* DMA usage flag */
166 /* packet per buffer dma */
168 /* with per descr. update */
170 /* buffer fill mode */
172 /* full speed only mode */
174 /* tx buffer size for high speed */
177 /* module parameters */
188 /*---------------------------------------------------------------------------*/
189 /* Prints UDC device registers and endpoint irq registers */
191 {
212 }
216 }
219 }
221 }
223 /* Masks unused interrupts */
225 {
226 u32 tmp;
228 /* mask all dev interrupts */
239 /* mask all ep interrupts */
243 }
245 /* Enables endpoint 0 interrupts */
247 {
248 u32 tmp;
252 /* read irq mask */
254 /* enable ep0 irq's */
260 }
262 /* Enables device interrupts for SET_INTF and SET_CONFIG */
264 {
265 u32 tmp;
269 /* read irq mask */
272 /* enable SET_INTERFACE, SET_CONFIG and other needed irq's */
281 }
283 /* Calculates fifo start of endpoint based on preceeding endpoints */
285 {
287 u32 tmp;
296 /* traverse ep's */
299 /* read fifo size */
303 }
304 }
306 }
308 /* CNAK pending field: bit0 = ep0in, bit16 = ep0out */
312 {
319 }
322 /* Enables endpoint, is called by gadget driver */
323 static int
325 {
328 u32 tmp;
330 u8 udc_csr_epix;
335 || !desc
352 /* set traffic type */
357 /* set max packet size */
364 /* IN ep */
367 /* ep ix in UDC CSR register space */
370 /* set buffer size (tx fifo entries) */
372 /* double buffering: fifo size = 2 x max packet size */
374 tmp,
375 maxpacket * UDC_EPIN_BUFF_SIZE_MULT
377 UDC_EPIN_BUFF_SIZE);
380 /* calc. tx fifo base addr */
383 /* flush fifo */
388 /* OUT ep */
390 /* ep ix in UDC CSR register space */
393 /* set max packet size UDC CSR */
396 UDC_CSR_NE_MAX_PKT);
400 /* alloc and init BNA dummy request */
403 }
407 }
409 /* set ep values */
411 /* max packet */
413 /* ep number */
415 /* ep direction */
417 /* ep type */
419 /* ep config */
421 /* ep interface */
423 /* ep alt */
425 /* write reg */
428 /* enable ep irq */
433 /*
434 * clear NAK by writing CNAK
435 * avoid BNA for OUT DMA, don't clear NAK until DMA desc. written
436 */
443 }
449 }
451 /* Resets endpoint */
453 {
454 u32 tmp;
462 /* set NAK */
468 /* disable interrupt */
474 /* unset P and IN bit of potential former DMA */
483 /* flush the fifo */
488 }
489 /* reset desc pointer */
491 }
493 /* Disables endpoint, is called by gadget driver */
495 {
515 }
517 /* Allocates request packet, called by gadget driver */
520 {
539 /* ep0 in requests are allocated from data pool here */
545 }
551 /* prevent from using desc. - set HOST BUSY */
553 UDC_DMA_STP_STS_BS_HOST_BUSY,
554 UDC_DMA_STP_STS_BS);
559 }
562 }
564 /* Frees request packet, called by gadget driver */
565 static void
567 {
581 /* free dma chain if created */
584 }
588 }
590 }
592 /* Init BNA dummy descriptor for HOST BUSY and pointing to itself */
594 {
596 /* set last bit */
598 /* set next pointer to itself */
600 /* set HOST BUSY */
603 UDC_DMA_STP_STS_BS_DMA_DONE,
604 UDC_DMA_STP_STS_BS);
605 #ifdef UDC_VERBOSE
608 #endif
609 }
610 }
612 /* Allocate BNA dummy descriptor */
614 {
618 /* alloc the dummy request */
624 }
626 }
628 /* Write data to TX fifo for IN packets */
629 static void
631 {
651 /* dwords first */
654 }
656 /* remaining bytes must be written by byte access */
660 }
662 /* dummy write confirm */
664 }
666 /* Read dwords from RX fifo for OUT transfers */
668 {
675 }
677 }
679 /* Read bytes from RX fifo for OUT transfers */
681 {
683 u32 tmp;
687 /* dwords first */
690 }
692 /* remaining bytes must be read by byte access */
698 }
699 }
702 }
704 /* Read data from RX fifo for OUT transfers */
705 static int
707 {
713 /* received number bytes */
725 }
727 }
730 /* last packet ? */
735 /* read rx fifo bytes */
740 }
742 /* create/re-init a DMA descriptor or a DMA descriptor chain */
744 {
746 u32 tmp;
752 /* set buffer pointer */
755 /* set last bit */
758 /* build/re-init dma chain if maxpkt scatter mode, not for EP0 */
766 }
769 /* write tx bytes */
773 UDC_DMA_IN_STS_TXBYTES);
775 }
776 }
778 }
785 /*
786 * if bytes < max packet then tx bytes must
787 * be written in packet per buffer mode
788 */
792 /* write tx bytes */
796 UDC_DMA_IN_STS_TXBYTES);
797 /* reset frame num */
801 UDC_DMA_IN_STS_FRAMENUM);
802 }
803 /* set HOST BUSY */
806 UDC_DMA_STP_STS_BS_HOST_BUSY,
807 UDC_DMA_STP_STS_BS);
810 /* set HOST READY */
813 UDC_DMA_STP_STS_BS_HOST_READY,
814 UDC_DMA_STP_STS_BS);
817 /* clear NAK by writing CNAK */
824 }
826 }
829 }
831 /* Completes request packet ... caller MUST hold lock */
832 static void
836 {
843 /* unmap DMA */
849 PCI_DMA_TODEVICE);
850 else
854 PCI_DMA_FROMDEVICE);
857 }
862 /* set new status if pending */
866 /* remove from ep queue */
876 }
878 /* frees pci pool descriptors of a DMA chain */
880 {
889 /* do not free first desc., will be done by free for request */
899 }
902 }
904 /* Iterates to the end of a DMA chain and returns last descriptor */
906 {
912 }
916 }
918 /* Iterates to the end of a DMA chain and counts bytes received */
920 {
922 u32 count;
925 /* received number bytes */
930 /* received number bytes */
933 UDC_DMA_OUT_STS_RXBYTES);
934 }
935 }
939 }
941 /* Creates or re-inits a DMA chain */
946 )
947 {
950 dma_addr_t dma_addr;
961 /* unset L bit in first desc for OUT */
964 }
966 /* alloc only new desc's if not already available */
969 len++;
970 }
973 /* shorter chain already allocated before */
976 }
979 }
982 /* gen. required number of descriptors and buffers */
984 /* create or determine next desc. */
994 /* first td */
1001 }
1006 else
1009 /* short packet ? */
1013 /* short packet */
1015 }
1017 /* link td and assign tx bytes */
1022 /* req->td_data->next = virt_to_phys(td); */
1023 }
1024 /* write tx bytes */
1026 /* first desc */
1030 UDC_DMA_IN_STS_TXBYTES);
1031 /* second desc */
1033 txbytes,
1034 UDC_DMA_IN_STS_TXBYTES);
1035 }
1040 /* last->next = virt_to_phys(td); */
1041 }
1043 /* write tx bytes */
1045 txbytes,
1046 UDC_DMA_IN_STS_TXBYTES);
1047 }
1048 }
1050 }
1051 /* set last bit */
1054 /* last desc. points to itself */
1056 }
1059 }
1061 /* Enabling RX DMA */
1063 {
1064 u32 tmp;
1067 /* stop RDE timer */
1071 }
1072 /* set RDE */
1076 }
1078 /* Queues a request packet, called by gadget driver */
1079 static int
1081 {
1088 u32 tmp;
1090 /* check the inputs */
1107 /* map dma (usually done before) */
1115 PCI_DMA_TODEVICE);
1116 else
1120 PCI_DMA_FROMDEVICE);
1122 }
1133 /* on empty queue just do first transfer */
1135 /* zlp */
1137 /* IN zlp's are handled by hardware */
1140 /*
1141 * if set_config or set_intf is waiting for ack by zlp
1142 * then set CSR_DONE
1143 */
1149 }
1150 /* setup command is ACK'ed now by zlp */
1152 /* clear NAK by writing CNAK in EP0_IN */
1158 UDC_EP0IN_IX);
1160 }
1162 }
1167 /* write desc pointer to enable DMA */
1169 /* set HOST READY */
1172 UDC_DMA_IN_STS_BS_HOST_READY,
1173 UDC_DMA_IN_STS_BS);
1174 }
1176 /* disabled rx dma while descriptor update */
1178 /* stop RDE timer */
1182 }
1183 /* clear RDE */
1189 /*
1190 * if BNA occurred then let BNA dummy desc.
1191 * point to current desc.
1192 */
1198 }
1199 }
1200 /* write desc pointer */
1203 /* clear NAK by writing CNAK */
1210 }
1213 /* enable ep irq */
1217 }
1218 }
1222 /*
1223 * prep_dma not used for OUT ep's, this is not possible
1224 * for PPB modes, because of chain creation reasons
1225 */
1230 }
1231 }
1233 /* add request to ep queue */
1238 /* open rxfifo if out data queued */
1240 /* enable DMA */
1245 }
1246 /* stop OUT naking */
1251 /*
1252 * read pending bytes afer nyet:
1253 * referring to isr
1254 */
1256 /* finish */
1258 }
1261 }
1262 }
1263 }
1265 finished:
1268 }
1270 /* Empty request queue of an endpoint; caller holds spinlock */
1272 {
1279 queue);
1281 }
1282 }
1284 /* Dequeues a request packet, called by gadget driver */
1286 {
1302 /* request in processing or next one */
1308 u32 tmp;
1309 u32 dma_sts;
1310 /* stop potential receive DMA */
1314 /*
1315 * Cancel transfer later in ISR
1316 * if descriptor was touched.
1317 */
1319 UDC_DMA_OUT_STS_BS);
1326 }
1328 }
1329 }
1330 }
1336 }
1338 /* Halt or clear halt of endpoint */
1339 static int
1341 {
1343 u32 tmp;
1359 /* halt or clear halt */
1364 /*
1365 * set STALL
1366 * rxfifo empty not taken into acount
1367 */
1373 /* setup poll timer */
1376 HZ * UDC_POLLSTALL_TIMER_USECONDS
1381 }
1382 }
1383 }
1385 /* ep is halted by set_halt() before */
1388 /* clear stall bit */
1390 /* clear NAK by writing CNAK */
1395 }
1396 }
1399 }
1401 /* gadget interface */
1413 /* fifo ops not implemented */
1414 };
1416 /*-------------------------------------------------------------------------*/
1418 /* Get frame counter (not implemented) */
1420 {
1422 }
1424 /* Remote wakeup gadget interface */
1426 {
1435 }
1437 /* gadget operations */
1441 };
1443 /* Setups endpoint parameters, adds endpoints to linked list */
1445 {
1446 /* make gadget ep lists */
1455 /* fifo config */
1462 }
1464 /* init registers at driver load time */
1466 {
1467 u32 tmp;
1469 /* init controller by soft reset */
1472 /* mask not needed interrupts */
1475 /* put into initial config */
1477 /* link up all endpoints */
1480 /* program speed */
1486 }
1490 }
1492 /* Inits UDC context */
1494 {
1495 u32 tmp;
1501 /* stop RDE timer */
1505 }
1506 /* stop poll stall timer */
1509 }
1510 /* disable DMA */
1516 /* enable dynamic CSR programming */
1519 /* set self powered */
1521 /* set remote wakeupable */
1529 }
1531 /* Sets initial endpoint parameters */
1533 {
1535 u32 tmp;
1536 u32 reg;
1540 /* read enum speed */
1547 }
1549 /* set basic ep parameters */
1555 /* txfifo size is calculated at enable time */
1558 /* fifo size */
1566 }
1568 /*
1569 * ep will be reset only if ep was not enabled before to avoid
1570 * disabling ep interrupts when ENUM interrupt occurs but ep is
1571 * not enabled by gadget driver
1572 */
1575 }
1578 /*
1579 * ep->dma is not really used, just to indicate that
1580 * DMA is active: remove this
1581 * dma regs = dev control regs
1582 */
1585 /* nak OUT endpoints until enable - not for ep0 */
1588 /* set NAK */
1594 }
1595 }
1596 }
1597 /* EP0 max packet */
1601 UDC_FS_EP0OUT_MAX_PKT_SIZE;
1605 }
1607 /*
1608 * with suspend bug workaround, ep0 params for gadget driver
1609 * are set at gadget driver bind() call
1610 */
1615 /* init cfg/alt/int */
1619 }
1621 /* Bringup after Connect event, initial bringup to be ready for ep0 events */
1623 {
1629 /* put into initial config */
1632 /* enable device setup interrupts */
1634 }
1636 /*
1637 * Calls gadget with disconnect event and resets the UDC and makes
1638 * initial bringup to be ready for ep0 events
1639 */
1641 {
1647 /* mask interrupts */
1650 /* REVISIT there doesn't seem to be a point to having this
1651 * talk to a tasklet ... do it directly, we already hold
1652 * the spinlock needed to process the disconnect.
1653 */
1656 }
1658 /* Tasklet for disconnect to be outside of interrupt context */
1660 {
1662 u32 tmp;
1672 /* empty queues */
1675 }
1677 }
1679 /* disable ep0 */
1685 /* init controller by soft reset */
1687 soft_reset_occured++;
1688 }
1690 /* re-enable dev interrupts */
1692 /* back to full speed ? */
1697 }
1700 }
1702 /* Reset the UDC core */
1704 {
1708 /*
1709 * reset possible waiting interrupts, because int.
1710 * status is lost after soft reset,
1711 * ep int. status reset
1712 */
1714 /* device int. status reset */
1722 }
1724 /* RDE timer callback to set RDE bit */
1726 {
1727 u32 tmp;
1732 /*
1733 * open the fifo if fifo was filled on last timer call
1734 * conditionally
1735 */
1737 /* set RDE to receive setup data */
1744 /*
1745 * if fifo empty setup polling, do not just
1746 * open the fifo
1747 */
1751 }
1753 /*
1754 * fifo contains data now, setup timer for opening
1755 * the fifo when timer expires to be able to receive
1756 * setup packets, when data packets gets queued by
1757 * gadget layer then timer will forced to expire with
1758 * set_rde=0 (RDE is set in udc_queue())
1759 */
1760 set_rde++;
1761 /* debug: lhadmot_timer_start = 221070 */
1765 }
1766 }
1774 }
1776 /* Handle halt state, used in stall poll timer */
1778 {
1779 u32 tmp;
1780 /* set stall as long not halted */
1783 /* STALL cleared ? */
1785 /*
1786 * FIXME: MSC spec requires that stall remains
1787 * even on receivng of CLEAR_FEATURE HALT. So
1788 * we would set STALL again here to be compliant.
1789 * But with current mass storage drivers this does
1790 * not work (would produce endless host retries).
1791 * So we clear halt on CLEAR_FEATURE.
1792 *
1793 DBG(ep->dev, "ep %d: set STALL again\n", ep->num);
1794 tmp |= AMD_BIT(UDC_EPCTL_S);
1795 writel(tmp, &ep->regs->ctl);*/
1797 /* clear NAK by writing CNAK */
1802 }
1803 }
1804 }
1806 /* Stall timer callback to poll S bit and set it again after */
1808 {
1813 /*
1814 * only one IN and OUT endpoints are handled
1815 * IN poll stall
1816 */
1821 /* OUT poll stall */
1827 /* setup timer again when still halted */
1830 HZ * UDC_POLLSTALL_TIMER_USECONDS
1833 }
1838 }
1840 /* Inits endpoint 0 so that SETUP packets are processed */
1842 {
1843 u32 tmp;
1847 /* flush fifo */
1852 /* set ep0 directions */
1856 /* set buffer size (tx fifo entries) of EP0_IN */
1860 UDC_EPIN_BUFF_SIZE);
1863 UDC_EPIN_BUFF_SIZE);
1866 /* set max packet size of EP0_IN */
1870 UDC_EP_MAX_PKT_SIZE);
1873 UDC_EP_MAX_PKT_SIZE);
1876 /* set max packet size of EP0_OUT */
1880 UDC_EP_MAX_PKT_SIZE);
1883 UDC_EP_MAX_PKT_SIZE);
1886 /* set max packet size of EP0 in UDC CSR */
1890 UDC_CSR_NE_MAX_PKT);
1893 UDC_CSR_NE_MAX_PKT);
1899 /* write dma desc address */
1904 /* stop RDE timer */
1908 }
1909 /* stop pollstall timer */
1912 }
1913 /* enable DMA */
1922 }
1924 }
1926 /* clear NAK by writing CNAK for EP0IN */
1933 /* clear NAK by writing CNAK for EP0OUT */
1939 }
1941 /* Make endpoint 0 ready for control traffic */
1943 {
1945 /* enable ep0 interrupts */
1947 /* enable device setup interrupts */
1951 }
1953 /* Called by gadget driver to register itself */
1955 {
1958 u32 tmp;
1974 /* Some gadget drivers use both ep0 directions.
1975 * NOTE: to gadget driver, ep0 is just one endpoint...
1976 */
1986 }
1988 /* get ready for ep0 traffic */
1991 /* clear SD */
1999 }
2002 /* shutdown requests and disconnect from gadget */
2003 static void
2007 {
2010 /* empty queues and init hardware */
2014 }
2020 }
2021 /* init */
2023 }
2025 /* Called by gadget driver to unregister itself */
2027 {
2030 u32 tmp;
2046 /* set SD */
2055 }
2059 /* Clear pending NAK bits */
2061 {
2062 u32 tmp;
2063 u32 reg;
2065 /* check epin's */
2070 /* clear NAK by writing CNAK */
2076 }
2077 }
2078 /* ... and ep0out */
2081 /* clear NAK by writing CNAK */
2088 }
2089 }
2091 /* Enabling RX DMA after setup packet */
2093 {
2095 /*
2096 * only enable RXDMA when no data endpoint enabled
2097 * or data is queued
2098 */
2102 /*
2103 * setup timer for enabling RDE (to not enable
2104 * RXFIFO DMA for data endpoints to early)
2105 */
2112 }
2113 }
2114 }
2115 }
2116 }
2119 /* Interrupt handler for data OUT traffic */
2121 {
2123 u32 tmp;
2135 /* BNA event ? */
2139 /* clear BNA */
2143 else
2147 }
2148 }
2149 /* HE event ? */
2153 /* clear HE */
2157 }
2161 /* next request */
2167 }
2169 /* fifo mode */
2172 /* read fifo */
2176 /* finish */
2178 /* next request */
2184 }
2186 /* DMA */
2190 /* check for DMA done */
2193 UDC_DMA_OUT_STS_BS);
2194 /* packet per buffer mode - rx bytes */
2196 /*
2197 * if BNA occurred then recover desc. from
2198 * BNA dummy desc.
2199 */
2206 }
2209 }
2211 /* buffer fill mode - rx bytes */
2213 /* received number bytes */
2215 UDC_DMA_OUT_STS_RXBYTES);
2217 /* packet per buffer mode - rx bytes */
2221 /* received number bytes */
2223 /* every desc. counts bytes */
2226 /* last desc. counts bytes */
2228 UDC_DMA_OUT_STS_RXBYTES);
2231 /*
2232 * on 64k packets the RXBYTES
2233 * field is zero
2234 */
2236 }
2237 }
2239 }
2247 }
2249 }
2252 /* complete request */
2255 /* next request */
2259 queue);
2260 /*
2261 * DMA may be already started by udc_queue()
2262 * called by gadget drivers completion
2263 * routine. This happens when queue
2264 * holds one request only.
2265 */
2267 /* next dma */
2270 /* write desc pointer */
2274 /* enable DMA */
2276 }
2278 /*
2279 * implant BNA dummy descriptor to allow
2280 * RXFIFO opening by RDE
2281 */
2283 /* write desc pointer */
2287 }
2289 /*
2290 * schedule timer for setting RDE if queue
2291 * remains empty to allow ep0 packets pass
2292 * through
2293 */
2297 jiffies
2302 }
2303 }
2306 }
2309 /*
2310 * RX DMA must be reenabled for each desc in PPBDU mode
2311 * and must be enabled for PPBNDU mode in case of BNA
2312 */
2314 }
2319 }
2321 /* check pending CNAKS */
2323 /* CNAk processing when rxfifo empty only */
2326 }
2327 }
2329 /* clear OUT bits in ep status */
2331 finished:
2333 }
2335 /* Interrupt handler for data IN traffic */
2337 {
2339 u32 tmp;
2340 u32 epsts;
2351 /* BNA ? */
2358 /* clear BNA */
2362 }
2363 }
2364 /* HE event ? */
2370 /* clear HE */
2374 }
2376 /* DMA completion */
2384 /*
2385 * length bytes transfered
2386 * check dma done of last desc. in PPBDU mode
2387 */
2391 dma_done =
2393 UDC_DMA_IN_STS_BS);
2394 /* don't care DMA done */
2397 }
2399 /* assume all bytes transferred */
2401 }
2404 /* complete req */
2407 /* further request available ? */
2409 /* disable interrupt */
2415 }
2417 }
2418 }
2419 }
2422 }
2423 /*
2424 * status reg has IN bit set and TDC not set (if TDC was handled,
2425 * IN must not be handled (UDC defect) ?
2426 */
2431 /* next request */
2434 /* FIFO mode */
2436 /* write fifo */
2444 /* complete req */
2446 }
2447 /* DMA */
2455 /*
2456 * unset L bit of first desc.
2457 * for chain
2458 */
2463 UDC_DMA_IN_STS_L);
2464 }
2466 /* write desc pointer */
2469 /* set HOST READY */
2473 UDC_DMA_IN_STS_BS_HOST_READY,
2474 UDC_DMA_IN_STS_BS);
2476 /* set poll demand bit */
2480 }
2481 }
2483 }
2484 }
2485 /* clear status bits */
2488 finished:
2491 }
2493 /* Interrupt handler for Control OUT traffic */
2497 {
2499 u32 tmp;
2501 u32 count;
2508 /* clear irq */
2512 /* check BNA and clear if set */
2520 }
2522 /* type of data: SETUP or DATA 0 bytes */
2526 /* setup data */
2533 /* set NAK for EP0_IN */
2538 /* get setup data */
2541 /* clear OUT bits in ep status */
2549 /* set HOST READY */
2551 UDC_DMA_STP_STS_BS_HOST_READY;
2553 /* read fifo */
2555 }
2557 /* determine direction of control data */
2560 /* enable RDE */
2565 /*
2566 * implant BNA dummy descriptor to allow RXFIFO opening
2567 * by RDE
2568 */
2570 /* write desc pointer */
2574 }
2578 /*
2579 * setup timer for enabling RDE (to not enable
2580 * RXFIFO DMA for data to early)
2581 */
2588 }
2589 }
2590 }
2592 /*
2593 * mass storage reset must be processed here because
2594 * next packet may be a CLEAR_FEATURE HALT which would not
2595 * clear the stall bit when no STALL handshake was received
2596 * before (autostall can cause this)
2597 */
2601 /*
2602 * clear stall bits
2603 * only one IN and OUT endpoints are handled
2604 */
2609 }
2611 /* call gadget with setup data received */
2618 /* ep0 in returns data (not zlp) on IN phase */
2620 UDC_EP0IN_MAXPACKET) {
2621 /* clear NAK by writing CNAK in EP0_IN */
2627 /* if unsupported request then stall */
2635 /* clear NAK by writing CNAK in EP0_OUT */
2642 }
2645 /* clear OUT bits in ep status */
2648 }
2650 /* data packet 0 bytes */
2652 /* clear OUT bits in ep status */
2655 /* get setup data: only 0 packet */
2657 /* no req if 0 packet, just reactivate */
2661 /* set HOST READY */
2665 UDC_DMA_OUT_STS_BS_HOST_READY,
2666 UDC_DMA_OUT_STS_BS);
2667 /* enable RDE */
2672 /* control write */
2674 /* re-program desc. pointer for possible ZLPs */
2677 /* enable RDE */
2679 }
2682 /* received number bytes */
2685 /* out data for fifo mode not working */
2688 /* 0 packet or real data ? */
2692 /* dummy read confirm */
2695 }
2696 }
2697 }
2699 /* check pending CNAKS */
2701 /* CNAk processing when rxfifo empty only */
2704 }
2705 }
2707 finished:
2709 }
2711 /* Interrupt handler for Control IN traffic */
2713 {
2715 u32 tmp;
2722 /* clear irq */
2726 /* DMA completion */
2731 /* clear TDC bit */
2735 /* status reg has IN bit set ? */
2740 /* clear IN bit */
2743 }
2746 /* halt ep0in */
2752 /* next request */
2757 /* write desc pointer */
2759 /* set HOST READY */
2763 UDC_DMA_STP_STS_BS_HOST_READY,
2764 UDC_DMA_STP_STS_BS);
2766 /* set poll demand bit */
2767 tmp =
2773 /* all bytes will be transferred */
2776 /* complete req */
2780 /* write fifo */
2783 /* lengh bytes transfered */
2791 /* complete req */
2793 }
2794 }
2796 }
2797 }
2801 /* clear IN bit */
2804 }
2805 }
2808 }
2811 /* Interrupt handler for global device events */
2815 {
2817 u32 tmp;
2818 u32 cfg;
2820 u16 i;
2821 u8 udc_csr_epix;
2823 /* SET_CONFIG irq ? */
2827 /* read config value */
2834 /* make usb request for gadget driver */
2839 /* programm the NE registers */
2844 /* ep ix in UDC CSR register space */
2848 /* OUT ep */
2850 /* ep ix in UDC CSR register space */
2852 }
2855 /* ep cfg */
2857 UDC_CSR_NE_CFG);
2858 /* write reg */
2861 /* clear stall bits */
2866 }
2867 /* call gadget zero with setup data received */
2877 /* read interface and alt setting values */
2882 /* make usb request for gadget driver */
2892 /* programm the NE registers */
2897 /* ep ix in UDC CSR register space */
2901 /* OUT ep */
2903 /* ep ix in UDC CSR register space */
2905 }
2907 /* UDC CSR reg */
2908 /* set ep values */
2910 /* ep interface */
2912 UDC_CSR_NE_INTF);
2913 /* tmp = AMD_ADDBITS(tmp, 2, UDC_CSR_NE_INTF); */
2914 /* ep alt */
2916 UDC_CSR_NE_ALT);
2917 /* write reg */
2920 /* clear stall bits */
2925 }
2927 /* call gadget zero with setup data received */
2937 /* allow soft reset when suspend occurs */
2943 /* mask not needed interrupts */
2946 /* call gadget to resume and reset configs etc. */
2951 }
2955 /* disable ep0 to empty req queue */
2959 /* soft reset when rxfifo not empty */
2964 soft_reset_after_usbreset_occured++;
2965 }
2967 /*
2968 * DMA reset to kill potential old DMA hw hang,
2969 * POLL bit is already reset by ep_init() through
2970 * disconnect()
2971 */
2977 /* put into initial config */
2980 /* enable device setup interrupts */
2983 /* enable suspend interrupt */
2997 }
3004 /* disable ep0 to empty req queue */
3008 /* link up all endpoints */
3016 }
3018 /* init ep 0 */
3021 /* enable ep0 interrupts */
3023 }
3024 /* session valid change interrupt */
3029 /* check that session is not valid to detect disconnect */
3032 /* disable suspend interrupt */
3037 /* cleanup on disconnect */
3039 }
3041 }
3044 }
3046 /* Interrupt Service Routine, see Linux Kernel Doc for parameters */
3048 {
3050 u32 reg;
3051 u16 i;
3052 u32 ep_irq;
3057 /* check for ep irq */
3065 /*
3066 * data endpoint
3067 * iterate ep's
3068 */
3074 /* clear irq status */
3077 /* irq for out ep ? */
3080 else
3082 }
3084 }
3087 /* check for dev irq */
3090 /* clear irq */
3093 }
3098 }
3100 /* Tears down device */
3102 {
3105 }
3107 /* Cleanup on device remove */
3109 {
3110 /* remove timer */
3111 stop_timer++;
3116 /* remove pollstall timer */
3117 stop_pollstall_timer++;
3123 }
3125 /* Reset all pci context */
3127 {
3132 /* gadget driver must not be registered */
3135 /* dma pool cleanup */
3140 /* cleanup DMA desc's for ep0in */
3149 }
3151 /* reset controller */
3167 }
3169 /* create dma pools on init */
3171 {
3176 /* consistent DMA mode setting ? */
3182 }
3184 /* DMA setup */
3191 }
3193 /* EP0 in dma regs = dev control regs */
3196 /* dma desc for setup data */
3203 }
3204 /* setup */
3210 }
3213 /* data: 0 packets !? */
3219 }
3223 finished:
3225 }
3227 /* Called by pci bus driver to init pci context */
3231 )
3232 {
3238 /* one udc only */
3242 }
3244 /* init */
3249 }
3251 /* pci setup */
3257 }
3260 /* PCI resource allocation */
3270 }
3280 }
3288 }
3296 }
3301 /* chip revision for Hs AMD5536 */
3307 /* init dma pools */
3312 }
3320 /* general probing */
3324 finished:
3328 }
3330 /* general probe */
3332 {
3334 u32 reg;
3337 /* mark timer as not initialized */
3341 /* device struct setup */
3351 /* udc csr registers base */
3353 /* dev registers base */
3355 /* ep registers base */
3357 /* fifo's base */
3361 /* init registers, interrupts, ... */
3376 }
3385 /* timer init */
3389 /* timer pollstall init */
3394 /* set SD */
3399 /* print dev register info */
3404 finished:
3406 }
3408 /* Initiates a remote wakeup */
3410 {
3412 u32 tmp;
3426 }
3428 /* PCI device parameters */
3430 {
3434 },
3435 {},
3436 };
3439 /* PCI functions */
3445 };
3447 /* Inits driver */
3449 {
3451 }
3454 /* Cleans driver */
3456 {
3458 }