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ppc64: Minor compilation fixes
[linux-2.6/libata-dev.git] / drivers / net / skge.c
blobc2e6484ef138f6e0c8d7548fd340a61028c85c81
1 /*
2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
5 *
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
9 *
10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26
27 #include <linux/config.h>
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/moduleparam.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/ethtool.h>
34 #include <linux/pci.h>
35 #include <linux/if_vlan.h>
36 #include <linux/ip.h>
37 #include <linux/delay.h>
38 #include <linux/crc32.h>
39 #include <linux/dma-mapping.h>
40 #include <asm/irq.h>
41
42 #include "skge.h"
43
44 #define DRV_NAME "skge"
45 #define DRV_VERSION "1.1"
46 #define PFX DRV_NAME " "
47
48 #define DEFAULT_TX_RING_SIZE 128
49 #define DEFAULT_RX_RING_SIZE 512
50 #define MAX_TX_RING_SIZE 1024
51 #define MAX_RX_RING_SIZE 4096
52 #define RX_COPY_THRESHOLD 128
53 #define RX_BUF_SIZE 1536
54 #define PHY_RETRIES 1000
55 #define ETH_JUMBO_MTU 9000
56 #define TX_WATCHDOG (5 * HZ)
57 #define NAPI_WEIGHT 64
58 #define BLINK_MS 250
59
60 MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
61 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
62 MODULE_LICENSE("GPL");
63 MODULE_VERSION(DRV_VERSION);
64
65 static const u32 default_msg
66 = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK
67 | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;
68
69 static int debug = -1; /* defaults above */
70 module_param(debug, int, 0);
71 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
72
73 static const struct pci_device_id skge_id_table[] = {
74 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
75 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
76 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
77 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
78 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T), },
79 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
80 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
81 { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
82 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
83 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015, },
84 { 0 }
85 };
86 MODULE_DEVICE_TABLE(pci, skge_id_table);
87
88 static int skge_up(struct net_device *dev);
89 static int skge_down(struct net_device *dev);
90 static void skge_tx_clean(struct skge_port *skge);
91 static void xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
92 static void gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
93 static void genesis_get_stats(struct skge_port *skge, u64 *data);
94 static void yukon_get_stats(struct skge_port *skge, u64 *data);
95 static void yukon_init(struct skge_hw *hw, int port);
96 static void yukon_reset(struct skge_hw *hw, int port);
97 static void genesis_mac_init(struct skge_hw *hw, int port);
98 static void genesis_reset(struct skge_hw *hw, int port);
99 static void genesis_link_up(struct skge_port *skge);
100
101 /* Avoid conditionals by using array */
102 static const int txqaddr[] = { Q_XA1, Q_XA2 };
103 static const int rxqaddr[] = { Q_R1, Q_R2 };
104 static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
105 static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
106 static const u32 portirqmask[] = { IS_PORT_1, IS_PORT_2 };
107
108 static int skge_get_regs_len(struct net_device *dev)
109 {
110 return 0x4000;
111 }
112
113 /*
114 * Returns copy of whole control register region
115 * Note: skip RAM address register because accessing it will
116 * cause bus hangs!
117 */
118 static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
119 void *p)
120 {
121 const struct skge_port *skge = netdev_priv(dev);
122 const void __iomem *io = skge->hw->regs;
123
124 regs->version = 1;
125 memset(p, 0, regs->len);
126 memcpy_fromio(p, io, B3_RAM_ADDR);
127
128 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
129 regs->len - B3_RI_WTO_R1);
130 }
131
132 /* Wake on Lan only supported on Yukon chps with rev 1 or above */
133 static int wol_supported(const struct skge_hw *hw)
134 {
135 return !((hw->chip_id == CHIP_ID_GENESIS ||
136 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)));
137 }
138
139 static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
140 {
141 struct skge_port *skge = netdev_priv(dev);
142
143 wol->supported = wol_supported(skge->hw) ? WAKE_MAGIC : 0;
144 wol->wolopts = skge->wol ? WAKE_MAGIC : 0;
145 }
146
147 static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
148 {
149 struct skge_port *skge = netdev_priv(dev);
150 struct skge_hw *hw = skge->hw;
151
152 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
153 return -EOPNOTSUPP;
154
155 if (wol->wolopts == WAKE_MAGIC && !wol_supported(hw))
156 return -EOPNOTSUPP;
157
158 skge->wol = wol->wolopts == WAKE_MAGIC;
159
160 if (skge->wol) {
161 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
162
163 skge_write16(hw, WOL_CTRL_STAT,
164 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
165 WOL_CTL_ENA_MAGIC_PKT_UNIT);
166 } else
167 skge_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
168
169 return 0;
170 }
171
172 /* Determine supported/adverised modes based on hardware.
173 * Note: ethtoool ADVERTISED_xxx == SUPPORTED_xxx
174 */
175 static u32 skge_supported_modes(const struct skge_hw *hw)
176 {
177 u32 supported;
178
179 if (hw->copper) {
180 supported = SUPPORTED_10baseT_Half
181 | SUPPORTED_10baseT_Full
182 | SUPPORTED_100baseT_Half
183 | SUPPORTED_100baseT_Full
184 | SUPPORTED_1000baseT_Half
185 | SUPPORTED_1000baseT_Full
186 | SUPPORTED_Autoneg| SUPPORTED_TP;
187
188 if (hw->chip_id == CHIP_ID_GENESIS)
189 supported &= ~(SUPPORTED_10baseT_Half
190 | SUPPORTED_10baseT_Full
191 | SUPPORTED_100baseT_Half
192 | SUPPORTED_100baseT_Full);
193
194 else if (hw->chip_id == CHIP_ID_YUKON)
195 supported &= ~SUPPORTED_1000baseT_Half;
196 } else
197 supported = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
198 | SUPPORTED_Autoneg;
199
200 return supported;
201 }
202
203 static int skge_get_settings(struct net_device *dev,
204 struct ethtool_cmd *ecmd)
205 {
206 struct skge_port *skge = netdev_priv(dev);
207 struct skge_hw *hw = skge->hw;
208
209 ecmd->transceiver = XCVR_INTERNAL;
210 ecmd->supported = skge_supported_modes(hw);
211
212 if (hw->copper) {
213 ecmd->port = PORT_TP;
214 ecmd->phy_address = hw->phy_addr;
215 } else
216 ecmd->port = PORT_FIBRE;
217
218 ecmd->advertising = skge->advertising;
219 ecmd->autoneg = skge->autoneg;
220 ecmd->speed = skge->speed;
221 ecmd->duplex = skge->duplex;
222 return 0;
223 }
224
225 static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
226 {
227 struct skge_port *skge = netdev_priv(dev);
228 const struct skge_hw *hw = skge->hw;
229 u32 supported = skge_supported_modes(hw);
230
231 if (ecmd->autoneg == AUTONEG_ENABLE) {
232 ecmd->advertising = supported;
233 skge->duplex = -1;
234 skge->speed = -1;
235 } else {
236 u32 setting;
237
238 switch (ecmd->speed) {
239 case SPEED_1000:
240 if (ecmd->duplex == DUPLEX_FULL)
241 setting = SUPPORTED_1000baseT_Full;
242 else if (ecmd->duplex == DUPLEX_HALF)
243 setting = SUPPORTED_1000baseT_Half;
244 else
245 return -EINVAL;
246 break;
247 case SPEED_100:
248 if (ecmd->duplex == DUPLEX_FULL)
249 setting = SUPPORTED_100baseT_Full;
250 else if (ecmd->duplex == DUPLEX_HALF)
251 setting = SUPPORTED_100baseT_Half;
252 else
253 return -EINVAL;
254 break;
255
256 case SPEED_10:
257 if (ecmd->duplex == DUPLEX_FULL)
258 setting = SUPPORTED_10baseT_Full;
259 else if (ecmd->duplex == DUPLEX_HALF)
260 setting = SUPPORTED_10baseT_Half;
261 else
262 return -EINVAL;
263 break;
264 default:
265 return -EINVAL;
266 }
267
268 if ((setting & supported) == 0)
269 return -EINVAL;
270
271 skge->speed = ecmd->speed;
272 skge->duplex = ecmd->duplex;
273 }
274
275 skge->autoneg = ecmd->autoneg;
276 skge->advertising = ecmd->advertising;
277
278 if (netif_running(dev)) {
279 skge_down(dev);
280 skge_up(dev);
281 }
282 return (0);
283 }
284
285 static void skge_get_drvinfo(struct net_device *dev,
286 struct ethtool_drvinfo *info)
287 {
288 struct skge_port *skge = netdev_priv(dev);
289
290 strcpy(info->driver, DRV_NAME);
291 strcpy(info->version, DRV_VERSION);
292 strcpy(info->fw_version, "N/A");
293 strcpy(info->bus_info, pci_name(skge->hw->pdev));
294 }
295
296 static const struct skge_stat {
297 char name[ETH_GSTRING_LEN];
298 u16 xmac_offset;
299 u16 gma_offset;
300 } skge_stats[] = {
301 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
302 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
303
304 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
305 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
306 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
307 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
308 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
309 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
310 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
311 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
312
313 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
314 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
315 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
316 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
317 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
318 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
319
320 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
321 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
322 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
323 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
324 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
325 };
326
327 static int skge_get_stats_count(struct net_device *dev)
328 {
329 return ARRAY_SIZE(skge_stats);
330 }
331
332 static void skge_get_ethtool_stats(struct net_device *dev,
333 struct ethtool_stats *stats, u64 *data)
334 {
335 struct skge_port *skge = netdev_priv(dev);
336
337 if (skge->hw->chip_id == CHIP_ID_GENESIS)
338 genesis_get_stats(skge, data);
339 else
340 yukon_get_stats(skge, data);
341 }
342
343 /* Use hardware MIB variables for critical path statistics and
344 * transmit feedback not reported at interrupt.
345 * Other errors are accounted for in interrupt handler.
346 */
347 static struct net_device_stats *skge_get_stats(struct net_device *dev)
348 {
349 struct skge_port *skge = netdev_priv(dev);
350 u64 data[ARRAY_SIZE(skge_stats)];
351
352 if (skge->hw->chip_id == CHIP_ID_GENESIS)
353 genesis_get_stats(skge, data);
354 else
355 yukon_get_stats(skge, data);
356
357 skge->net_stats.tx_bytes = data[0];
358 skge->net_stats.rx_bytes = data[1];
359 skge->net_stats.tx_packets = data[2] + data[4] + data[6];
360 skge->net_stats.rx_packets = data[3] + data[5] + data[7];
361 skge->net_stats.multicast = data[5] + data[7];
362 skge->net_stats.collisions = data[10];
363 skge->net_stats.tx_aborted_errors = data[12];
364
365 return &skge->net_stats;
366 }
367
368 static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
369 {
370 int i;
371
372 switch (stringset) {
373 case ETH_SS_STATS:
374 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
375 memcpy(data + i * ETH_GSTRING_LEN,
376 skge_stats[i].name, ETH_GSTRING_LEN);
377 break;
378 }
379 }
380
381 static void skge_get_ring_param(struct net_device *dev,
382 struct ethtool_ringparam *p)
383 {
384 struct skge_port *skge = netdev_priv(dev);
385
386 p->rx_max_pending = MAX_RX_RING_SIZE;
387 p->tx_max_pending = MAX_TX_RING_SIZE;
388 p->rx_mini_max_pending = 0;
389 p->rx_jumbo_max_pending = 0;
390
391 p->rx_pending = skge->rx_ring.count;
392 p->tx_pending = skge->tx_ring.count;
393 p->rx_mini_pending = 0;
394 p->rx_jumbo_pending = 0;
395 }
396
397 static int skge_set_ring_param(struct net_device *dev,
398 struct ethtool_ringparam *p)
399 {
400 struct skge_port *skge = netdev_priv(dev);
401
402 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
403 p->tx_pending == 0 || p->tx_pending > MAX_TX_RING_SIZE)
404 return -EINVAL;
405
406 skge->rx_ring.count = p->rx_pending;
407 skge->tx_ring.count = p->tx_pending;
408
409 if (netif_running(dev)) {
410 skge_down(dev);
411 skge_up(dev);
412 }
413
414 return 0;
415 }
416
417 static u32 skge_get_msglevel(struct net_device *netdev)
418 {
419 struct skge_port *skge = netdev_priv(netdev);
420 return skge->msg_enable;
421 }
422
423 static void skge_set_msglevel(struct net_device *netdev, u32 value)
424 {
425 struct skge_port *skge = netdev_priv(netdev);
426 skge->msg_enable = value;
427 }
428
429 static int skge_nway_reset(struct net_device *dev)
430 {
431 struct skge_port *skge = netdev_priv(dev);
432 struct skge_hw *hw = skge->hw;
433 int port = skge->port;
434
435 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
436 return -EINVAL;
437
438 spin_lock_bh(&hw->phy_lock);
439 if (hw->chip_id == CHIP_ID_GENESIS) {
440 genesis_reset(hw, port);
441 genesis_mac_init(hw, port);
442 } else {
443 yukon_reset(hw, port);
444 yukon_init(hw, port);
445 }
446 spin_unlock_bh(&hw->phy_lock);
447 return 0;
448 }
449
450 static int skge_set_sg(struct net_device *dev, u32 data)
451 {
452 struct skge_port *skge = netdev_priv(dev);
453 struct skge_hw *hw = skge->hw;
454
455 if (hw->chip_id == CHIP_ID_GENESIS && data)
456 return -EOPNOTSUPP;
457 return ethtool_op_set_sg(dev, data);
458 }
459
460 static int skge_set_tx_csum(struct net_device *dev, u32 data)
461 {
462 struct skge_port *skge = netdev_priv(dev);
463 struct skge_hw *hw = skge->hw;
464
465 if (hw->chip_id == CHIP_ID_GENESIS && data)
466 return -EOPNOTSUPP;
467
468 return ethtool_op_set_tx_csum(dev, data);
469 }
470
471 static u32 skge_get_rx_csum(struct net_device *dev)
472 {
473 struct skge_port *skge = netdev_priv(dev);
474
475 return skge->rx_csum;
476 }
477
478 /* Only Yukon supports checksum offload. */
479 static int skge_set_rx_csum(struct net_device *dev, u32 data)
480 {
481 struct skge_port *skge = netdev_priv(dev);
482
483 if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
484 return -EOPNOTSUPP;
485
486 skge->rx_csum = data;
487 return 0;
488 }
489
490 static void skge_get_pauseparam(struct net_device *dev,
491 struct ethtool_pauseparam *ecmd)
492 {
493 struct skge_port *skge = netdev_priv(dev);
494
495 ecmd->tx_pause = (skge->flow_control == FLOW_MODE_LOC_SEND)
496 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
497 ecmd->rx_pause = (skge->flow_control == FLOW_MODE_REM_SEND)
498 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
499
500 ecmd->autoneg = skge->autoneg;
501 }
502
503 static int skge_set_pauseparam(struct net_device *dev,
504 struct ethtool_pauseparam *ecmd)
505 {
506 struct skge_port *skge = netdev_priv(dev);
507
508 skge->autoneg = ecmd->autoneg;
509 if (ecmd->rx_pause && ecmd->tx_pause)
510 skge->flow_control = FLOW_MODE_SYMMETRIC;
511 else if (ecmd->rx_pause && !ecmd->tx_pause)
512 skge->flow_control = FLOW_MODE_REM_SEND;
513 else if (!ecmd->rx_pause && ecmd->tx_pause)
514 skge->flow_control = FLOW_MODE_LOC_SEND;
515 else
516 skge->flow_control = FLOW_MODE_NONE;
517
518 if (netif_running(dev)) {
519 skge_down(dev);
520 skge_up(dev);
521 }
522 return 0;
523 }
524
525 /* Chip internal frequency for clock calculations */
526 static inline u32 hwkhz(const struct skge_hw *hw)
527 {
528 if (hw->chip_id == CHIP_ID_GENESIS)
529 return 53215; /* or: 53.125 MHz */
530 else
531 return 78215; /* or: 78.125 MHz */
532 }
533
534 /* Chip hz to microseconds */
535 static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
536 {
537 return (ticks * 1000) / hwkhz(hw);
538 }
539
540 /* Microseconds to chip hz */
541 static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
542 {
543 return hwkhz(hw) * usec / 1000;
544 }
545
546 static int skge_get_coalesce(struct net_device *dev,
547 struct ethtool_coalesce *ecmd)
548 {
549 struct skge_port *skge = netdev_priv(dev);
550 struct skge_hw *hw = skge->hw;
551 int port = skge->port;
552
553 ecmd->rx_coalesce_usecs = 0;
554 ecmd->tx_coalesce_usecs = 0;
555
556 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
557 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
558 u32 msk = skge_read32(hw, B2_IRQM_MSK);
559
560 if (msk & rxirqmask[port])
561 ecmd->rx_coalesce_usecs = delay;
562 if (msk & txirqmask[port])
563 ecmd->tx_coalesce_usecs = delay;
564 }
565
566 return 0;
567 }
568
569 /* Note: interrupt timer is per board, but can turn on/off per port */
570 static int skge_set_coalesce(struct net_device *dev,
571 struct ethtool_coalesce *ecmd)
572 {
573 struct skge_port *skge = netdev_priv(dev);
574 struct skge_hw *hw = skge->hw;
575 int port = skge->port;
576 u32 msk = skge_read32(hw, B2_IRQM_MSK);
577 u32 delay = 25;
578
579 if (ecmd->rx_coalesce_usecs == 0)
580 msk &= ~rxirqmask[port];
581 else if (ecmd->rx_coalesce_usecs < 25 ||
582 ecmd->rx_coalesce_usecs > 33333)
583 return -EINVAL;
584 else {
585 msk |= rxirqmask[port];
586 delay = ecmd->rx_coalesce_usecs;
587 }
588
589 if (ecmd->tx_coalesce_usecs == 0)
590 msk &= ~txirqmask[port];
591 else if (ecmd->tx_coalesce_usecs < 25 ||
592 ecmd->tx_coalesce_usecs > 33333)
593 return -EINVAL;
594 else {
595 msk |= txirqmask[port];
596 delay = min(delay, ecmd->rx_coalesce_usecs);
597 }
598
599 skge_write32(hw, B2_IRQM_MSK, msk);
600 if (msk == 0)
601 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
602 else {
603 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
604 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
605 }
606 return 0;
607 }
608
609 enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
610 static void skge_led(struct skge_port *skge, enum led_mode mode)
611 {
612 struct skge_hw *hw = skge->hw;
613 int port = skge->port;
614
615 spin_lock_bh(&hw->phy_lock);
616 if (hw->chip_id == CHIP_ID_GENESIS) {
617 switch (mode) {
618 case LED_MODE_OFF:
619 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
620 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
621 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
622 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
623 break;
624
625 case LED_MODE_ON:
626 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
627 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
628
629 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
630 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
631
632 break;
633
634 case LED_MODE_TST:
635 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
636 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
637 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
638
639 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
640 break;
641 }
642 } else {
643 switch (mode) {
644 case LED_MODE_OFF:
645 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
646 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
647 PHY_M_LED_MO_DUP(MO_LED_OFF) |
648 PHY_M_LED_MO_10(MO_LED_OFF) |
649 PHY_M_LED_MO_100(MO_LED_OFF) |
650 PHY_M_LED_MO_1000(MO_LED_OFF) |
651 PHY_M_LED_MO_RX(MO_LED_OFF));
652 break;
653 case LED_MODE_ON:
654 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
655 PHY_M_LED_PULS_DUR(PULS_170MS) |
656 PHY_M_LED_BLINK_RT(BLINK_84MS) |
657 PHY_M_LEDC_TX_CTRL |
658 PHY_M_LEDC_DP_CTRL);
659
660 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
661 PHY_M_LED_MO_RX(MO_LED_OFF) |
662 (skge->speed == SPEED_100 ?
663 PHY_M_LED_MO_100(MO_LED_ON) : 0));
664 break;
665 case LED_MODE_TST:
666 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
667 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
668 PHY_M_LED_MO_DUP(MO_LED_ON) |
669 PHY_M_LED_MO_10(MO_LED_ON) |
670 PHY_M_LED_MO_100(MO_LED_ON) |
671 PHY_M_LED_MO_1000(MO_LED_ON) |
672 PHY_M_LED_MO_RX(MO_LED_ON));
673 }
674 }
675 spin_unlock_bh(&hw->phy_lock);
676 }
677
678 /* blink LED's for finding board */
679 static int skge_phys_id(struct net_device *dev, u32 data)
680 {
681 struct skge_port *skge = netdev_priv(dev);
682 unsigned long ms;
683 enum led_mode mode = LED_MODE_TST;
684
685 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
686 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT / HZ) * 1000;
687 else
688 ms = data * 1000;
689
690 while (ms > 0) {
691 skge_led(skge, mode);
692 mode ^= LED_MODE_TST;
693
694 if (msleep_interruptible(BLINK_MS))
695 break;
696 ms -= BLINK_MS;
697 }
698
699 /* back to regular LED state */
700 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
701
702 return 0;
703 }
704
705 static struct ethtool_ops skge_ethtool_ops = {
706 .get_settings = skge_get_settings,
707 .set_settings = skge_set_settings,
708 .get_drvinfo = skge_get_drvinfo,
709 .get_regs_len = skge_get_regs_len,
710 .get_regs = skge_get_regs,
711 .get_wol = skge_get_wol,
712 .set_wol = skge_set_wol,
713 .get_msglevel = skge_get_msglevel,
714 .set_msglevel = skge_set_msglevel,
715 .nway_reset = skge_nway_reset,
716 .get_link = ethtool_op_get_link,
717 .get_ringparam = skge_get_ring_param,
718 .set_ringparam = skge_set_ring_param,
719 .get_pauseparam = skge_get_pauseparam,
720 .set_pauseparam = skge_set_pauseparam,
721 .get_coalesce = skge_get_coalesce,
722 .set_coalesce = skge_set_coalesce,
723 .get_sg = ethtool_op_get_sg,
724 .set_sg = skge_set_sg,
725 .get_tx_csum = ethtool_op_get_tx_csum,
726 .set_tx_csum = skge_set_tx_csum,
727 .get_rx_csum = skge_get_rx_csum,
728 .set_rx_csum = skge_set_rx_csum,
729 .get_strings = skge_get_strings,
730 .phys_id = skge_phys_id,
731 .get_stats_count = skge_get_stats_count,
732 .get_ethtool_stats = skge_get_ethtool_stats,
733 };
734
735 /*
736 * Allocate ring elements and chain them together
737 * One-to-one association of board descriptors with ring elements
738 */
739 static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u64 base)
740 {
741 struct skge_tx_desc *d;
742 struct skge_element *e;
743 int i;
744
745 ring->start = kmalloc(sizeof(*e)*ring->count, GFP_KERNEL);
746 if (!ring->start)
747 return -ENOMEM;
748
749 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
750 e->desc = d;
751 e->skb = NULL;
752 if (i == ring->count - 1) {
753 e->next = ring->start;
754 d->next_offset = base;
755 } else {
756 e->next = e + 1;
757 d->next_offset = base + (i+1) * sizeof(*d);
758 }
759 }
760 ring->to_use = ring->to_clean = ring->start;
761
762 return 0;
763 }
764
765 /* Allocate and setup a new buffer for receiving */
766 static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
767 struct sk_buff *skb, unsigned int bufsize)
768 {
769 struct skge_rx_desc *rd = e->desc;
770 u64 map;
771
772 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
773 PCI_DMA_FROMDEVICE);
774
775 rd->dma_lo = map;
776 rd->dma_hi = map >> 32;
777 e->skb = skb;
778 rd->csum1_start = ETH_HLEN;
779 rd->csum2_start = ETH_HLEN;
780 rd->csum1 = 0;
781 rd->csum2 = 0;
782
783 wmb();
784
785 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
786 pci_unmap_addr_set(e, mapaddr, map);
787 pci_unmap_len_set(e, maplen, bufsize);
788 }
789
790 /* Resume receiving using existing skb,
791 * Note: DMA address is not changed by chip.
792 * MTU not changed while receiver active.
793 */
794 static void skge_rx_reuse(struct skge_element *e, unsigned int size)
795 {
796 struct skge_rx_desc *rd = e->desc;
797
798 rd->csum2 = 0;
799 rd->csum2_start = ETH_HLEN;
800
801 wmb();
802
803 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
804 }
805
806
807 /* Free all buffers in receive ring, assumes receiver stopped */
808 static void skge_rx_clean(struct skge_port *skge)
809 {
810 struct skge_hw *hw = skge->hw;
811 struct skge_ring *ring = &skge->rx_ring;
812 struct skge_element *e;
813
814 e = ring->start;
815 do {
816 struct skge_rx_desc *rd = e->desc;
817 rd->control = 0;
818 if (e->skb) {
819 pci_unmap_single(hw->pdev,
820 pci_unmap_addr(e, mapaddr),
821 pci_unmap_len(e, maplen),
822 PCI_DMA_FROMDEVICE);
823 dev_kfree_skb(e->skb);
824 e->skb = NULL;
825 }
826 } while ((e = e->next) != ring->start);
827 }
828
829
830 /* Allocate buffers for receive ring
831 * For receive: to_clean is next received frame.
832 */
833 static int skge_rx_fill(struct skge_port *skge)
834 {
835 struct skge_ring *ring = &skge->rx_ring;
836 struct skge_element *e;
837
838 e = ring->start;
839 do {
840 struct sk_buff *skb;
841
842 skb = dev_alloc_skb(skge->rx_buf_size + NET_IP_ALIGN);
843 if (!skb)
844 return -ENOMEM;
845
846 skb_reserve(skb, NET_IP_ALIGN);
847 skge_rx_setup(skge, e, skb, skge->rx_buf_size);
848 } while ( (e = e->next) != ring->start);
849
850 ring->to_clean = ring->start;
851 return 0;
852 }
853
854 static void skge_link_up(struct skge_port *skge)
855 {
856 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
857 LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
858
859 netif_carrier_on(skge->netdev);
860 if (skge->tx_avail > MAX_SKB_FRAGS + 1)
861 netif_wake_queue(skge->netdev);
862
863 if (netif_msg_link(skge))
864 printk(KERN_INFO PFX
865 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
866 skge->netdev->name, skge->speed,
867 skge->duplex == DUPLEX_FULL ? "full" : "half",
868 (skge->flow_control == FLOW_MODE_NONE) ? "none" :
869 (skge->flow_control == FLOW_MODE_LOC_SEND) ? "tx only" :
870 (skge->flow_control == FLOW_MODE_REM_SEND) ? "rx only" :
871 (skge->flow_control == FLOW_MODE_SYMMETRIC) ? "tx and rx" :
872 "unknown");
873 }
874
875 static void skge_link_down(struct skge_port *skge)
876 {
877 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
878 netif_carrier_off(skge->netdev);
879 netif_stop_queue(skge->netdev);
880
881 if (netif_msg_link(skge))
882 printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
883 }
884
885 static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
886 {
887 int i;
888 u16 v;
889
890 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
891 v = xm_read16(hw, port, XM_PHY_DATA);
892
893 /* Need to wait for external PHY */
894 for (i = 0; i < PHY_RETRIES; i++) {
895 udelay(1);
896 if (xm_read16(hw, port, XM_MMU_CMD)
897 & XM_MMU_PHY_RDY)
898 goto ready;
899 }
900
901 printk(KERN_WARNING PFX "%s: phy read timed out\n",
902 hw->dev[port]->name);
903 return 0;
904 ready:
905 v = xm_read16(hw, port, XM_PHY_DATA);
906
907 return v;
908 }
909
910 static void xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
911 {
912 int i;
913
914 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
915 for (i = 0; i < PHY_RETRIES; i++) {
916 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
917 goto ready;
918 udelay(1);
919 }
920 printk(KERN_WARNING PFX "%s: phy write failed to come ready\n",
921 hw->dev[port]->name);
922
923
924 ready:
925 xm_write16(hw, port, XM_PHY_DATA, val);
926 for (i = 0; i < PHY_RETRIES; i++) {
927 udelay(1);
928 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
929 return;
930 }
931 printk(KERN_WARNING PFX "%s: phy write timed out\n",
932 hw->dev[port]->name);
933 }
934
935 static void genesis_init(struct skge_hw *hw)
936 {
937 /* set blink source counter */
938 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
939 skge_write8(hw, B2_BSC_CTRL, BSC_START);
940
941 /* configure mac arbiter */
942 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
943
944 /* configure mac arbiter timeout values */
945 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
946 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
947 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
948 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
949
950 skge_write8(hw, B3_MA_RCINI_RX1, 0);
951 skge_write8(hw, B3_MA_RCINI_RX2, 0);
952 skge_write8(hw, B3_MA_RCINI_TX1, 0);
953 skge_write8(hw, B3_MA_RCINI_TX2, 0);
954
955 /* configure packet arbiter timeout */
956 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
957 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
958 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
959 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
960 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
961 }
962
963 static void genesis_reset(struct skge_hw *hw, int port)
964 {
965 const u8 zero[8] = { 0 };
966
967 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
968
969 /* reset the statistics module */
970 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
971 xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */
972 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
973 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
974 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
975
976 /* disable Broadcom PHY IRQ */
977 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
978
979 xm_outhash(hw, port, XM_HSM, zero);
980 }
981
982
983 /* Convert mode to MII values */
984 static const u16 phy_pause_map[] = {
985 [FLOW_MODE_NONE] = 0,
986 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
987 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
988 [FLOW_MODE_REM_SEND] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
989 };
990
991
992 /* Check status of Broadcom phy link */
993 static void bcom_check_link(struct skge_hw *hw, int port)
994 {
995 struct net_device *dev = hw->dev[port];
996 struct skge_port *skge = netdev_priv(dev);
997 u16 status;
998
999 /* read twice because of latch */
1000 (void) xm_phy_read(hw, port, PHY_BCOM_STAT);
1001 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
1002
1003 if ((status & PHY_ST_LSYNC) == 0) {
1004 u16 cmd = xm_read16(hw, port, XM_MMU_CMD);
1005 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1006 xm_write16(hw, port, XM_MMU_CMD, cmd);
1007 /* dummy read to ensure writing */
1008 (void) xm_read16(hw, port, XM_MMU_CMD);
1009
1010 if (netif_carrier_ok(dev))
1011 skge_link_down(skge);
1012 } else {
1013 if (skge->autoneg == AUTONEG_ENABLE &&
1014 (status & PHY_ST_AN_OVER)) {
1015 u16 lpa = xm_phy_read(hw, port, PHY_BCOM_AUNE_LP);
1016 u16 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1017
1018 if (lpa & PHY_B_AN_RF) {
1019 printk(KERN_NOTICE PFX "%s: remote fault\n",
1020 dev->name);
1021 return;
1022 }
1023
1024 /* Check Duplex mismatch */
1025 switch (aux & PHY_B_AS_AN_RES_MSK) {
1026 case PHY_B_RES_1000FD:
1027 skge->duplex = DUPLEX_FULL;
1028 break;
1029 case PHY_B_RES_1000HD:
1030 skge->duplex = DUPLEX_HALF;
1031 break;
1032 default:
1033 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1034 dev->name);
1035 return;
1036 }
1037
1038
1039 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1040 switch (aux & PHY_B_AS_PAUSE_MSK) {
1041 case PHY_B_AS_PAUSE_MSK:
1042 skge->flow_control = FLOW_MODE_SYMMETRIC;
1043 break;
1044 case PHY_B_AS_PRR:
1045 skge->flow_control = FLOW_MODE_REM_SEND;
1046 break;
1047 case PHY_B_AS_PRT:
1048 skge->flow_control = FLOW_MODE_LOC_SEND;
1049 break;
1050 default:
1051 skge->flow_control = FLOW_MODE_NONE;
1052 }
1053
1054 skge->speed = SPEED_1000;
1055 }
1056
1057 if (!netif_carrier_ok(dev))
1058 genesis_link_up(skge);
1059 }
1060 }
1061
1062 /* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1063 * Phy on for 100 or 10Mbit operation
1064 */
1065 static void bcom_phy_init(struct skge_port *skge, int jumbo)
1066 {
1067 struct skge_hw *hw = skge->hw;
1068 int port = skge->port;
1069 int i;
1070 u16 id1, r, ext, ctl;
1071
1072 /* magic workaround patterns for Broadcom */
1073 static const struct {
1074 u16 reg;
1075 u16 val;
1076 } A1hack[] = {
1077 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1078 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1079 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1080 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1081 }, C0hack[] = {
1082 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1083 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1084 };
1085
1086 /* read Id from external PHY (all have the same address) */
1087 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1088
1089 /* Optimize MDIO transfer by suppressing preamble. */
1090 r = xm_read16(hw, port, XM_MMU_CMD);
1091 r |= XM_MMU_NO_PRE;
1092 xm_write16(hw, port, XM_MMU_CMD,r);
1093
1094 switch (id1) {
1095 case PHY_BCOM_ID1_C0:
1096 /*
1097 * Workaround BCOM Errata for the C0 type.
1098 * Write magic patterns to reserved registers.
1099 */
1100 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1101 xm_phy_write(hw, port,
1102 C0hack[i].reg, C0hack[i].val);
1103
1104 break;
1105 case PHY_BCOM_ID1_A1:
1106 /*
1107 * Workaround BCOM Errata for the A1 type.
1108 * Write magic patterns to reserved registers.
1109 */
1110 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1111 xm_phy_write(hw, port,
1112 A1hack[i].reg, A1hack[i].val);
1113 break;
1114 }
1115
1116 /*
1117 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1118 * Disable Power Management after reset.
1119 */
1120 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1121 r |= PHY_B_AC_DIS_PM;
1122 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1123
1124 /* Dummy read */
1125 xm_read16(hw, port, XM_ISRC);
1126
1127 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1128 ctl = PHY_CT_SP1000; /* always 1000mbit */
1129
1130 if (skge->autoneg == AUTONEG_ENABLE) {
1131 /*
1132 * Workaround BCOM Errata #1 for the C5 type.
1133 * 1000Base-T Link Acquisition Failure in Slave Mode
1134 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1135 */
1136 u16 adv = PHY_B_1000C_RD;
1137 if (skge->advertising & ADVERTISED_1000baseT_Half)
1138 adv |= PHY_B_1000C_AHD;
1139 if (skge->advertising & ADVERTISED_1000baseT_Full)
1140 adv |= PHY_B_1000C_AFD;
1141 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1142
1143 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1144 } else {
1145 if (skge->duplex == DUPLEX_FULL)
1146 ctl |= PHY_CT_DUP_MD;
1147 /* Force to slave */
1148 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1149 }
1150
1151 /* Set autonegotiation pause parameters */
1152 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1153 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1154
1155 /* Handle Jumbo frames */
1156 if (jumbo) {
1157 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1158 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1159
1160 ext |= PHY_B_PEC_HIGH_LA;
1161
1162 }
1163
1164 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1165 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1166
1167 /* Use link status change interrrupt */
1168 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1169
1170 bcom_check_link(hw, port);
1171 }
1172
1173 static void genesis_mac_init(struct skge_hw *hw, int port)
1174 {
1175 struct net_device *dev = hw->dev[port];
1176 struct skge_port *skge = netdev_priv(dev);
1177 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1178 int i;
1179 u32 r;
1180 const u8 zero[6] = { 0 };
1181
1182 /* Clear MIB counters */
1183 xm_write16(hw, port, XM_STAT_CMD,
1184 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1185 /* Clear two times according to Errata #3 */
1186 xm_write16(hw, port, XM_STAT_CMD,
1187 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1188
1189 /* Unreset the XMAC. */
1190 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1191
1192 /*
1193 * Perform additional initialization for external PHYs,
1194 * namely for the 1000baseTX cards that use the XMAC's
1195 * GMII mode.
1196 */
1197 /* Take external Phy out of reset */
1198 r = skge_read32(hw, B2_GP_IO);
1199 if (port == 0)
1200 r |= GP_DIR_0|GP_IO_0;
1201 else
1202 r |= GP_DIR_2|GP_IO_2;
1203
1204 skge_write32(hw, B2_GP_IO, r);
1205 skge_read32(hw, B2_GP_IO);
1206
1207 /* Enable GMII interfac */
1208 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1209
1210 bcom_phy_init(skge, jumbo);
1211
1212 /* Set Station Address */
1213 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
1214
1215 /* We don't use match addresses so clear */
1216 for (i = 1; i < 16; i++)
1217 xm_outaddr(hw, port, XM_EXM(i), zero);
1218
1219 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1220 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1221
1222 /* We don't need the FCS appended to the packet. */
1223 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1224 if (jumbo)
1225 r |= XM_RX_BIG_PK_OK;
1226
1227 if (skge->duplex == DUPLEX_HALF) {
1228 /*
1229 * If in manual half duplex mode the other side might be in
1230 * full duplex mode, so ignore if a carrier extension is not seen
1231 * on frames received
1232 */
1233 r |= XM_RX_DIS_CEXT;
1234 }
1235 xm_write16(hw, port, XM_RX_CMD, r);
1236
1237
1238 /* We want short frames padded to 60 bytes. */
1239 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1240
1241 /*
1242 * Bump up the transmit threshold. This helps hold off transmit
1243 * underruns when we're blasting traffic from both ports at once.
1244 */
1245 xm_write16(hw, port, XM_TX_THR, 512);
1246
1247 /*
1248 * Enable the reception of all error frames. This is is
1249 * a necessary evil due to the design of the XMAC. The
1250 * XMAC's receive FIFO is only 8K in size, however jumbo
1251 * frames can be up to 9000 bytes in length. When bad
1252 * frame filtering is enabled, the XMAC's RX FIFO operates
1253 * in 'store and forward' mode. For this to work, the
1254 * entire frame has to fit into the FIFO, but that means
1255 * that jumbo frames larger than 8192 bytes will be
1256 * truncated. Disabling all bad frame filtering causes
1257 * the RX FIFO to operate in streaming mode, in which
1258 * case the XMAC will start transfering frames out of the
1259 * RX FIFO as soon as the FIFO threshold is reached.
1260 */
1261 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
1262
1263
1264 /*
1265 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1266 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1267 * and 'Octets Rx OK Hi Cnt Ov'.
1268 */
1269 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1270
1271 /*
1272 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1273 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1274 * and 'Octets Tx OK Hi Cnt Ov'.
1275 */
1276 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
1277
1278 /* Configure MAC arbiter */
1279 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1280
1281 /* configure timeout values */
1282 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1283 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1284 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1285 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1286
1287 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1288 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1289 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1290 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1291
1292 /* Configure Rx MAC FIFO */
1293 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1294 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1295 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
1296
1297 /* Configure Tx MAC FIFO */
1298 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1299 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1300 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
1301
1302 if (jumbo) {
1303 /* Enable frame flushing if jumbo frames used */
1304 skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
1305 } else {
1306 /* enable timeout timers if normal frames */
1307 skge_write16(hw, B3_PA_CTRL,
1308 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
1309 }
1310 }
1311
1312 static void genesis_stop(struct skge_port *skge)
1313 {
1314 struct skge_hw *hw = skge->hw;
1315 int port = skge->port;
1316 u32 reg;
1317
1318 genesis_reset(hw, port);
1319
1320 /* Clear Tx packet arbiter timeout IRQ */
1321 skge_write16(hw, B3_PA_CTRL,
1322 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1323
1324 /*
1325 * If the transfer stucks at the MAC the STOP command will not
1326 * terminate if we don't flush the XMAC's transmit FIFO !
1327 */
1328 xm_write32(hw, port, XM_MODE,
1329 xm_read32(hw, port, XM_MODE)|XM_MD_FTF);
1330
1331
1332 /* Reset the MAC */
1333 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
1334
1335 /* For external PHYs there must be special handling */
1336 reg = skge_read32(hw, B2_GP_IO);
1337 if (port == 0) {
1338 reg |= GP_DIR_0;
1339 reg &= ~GP_IO_0;
1340 } else {
1341 reg |= GP_DIR_2;
1342 reg &= ~GP_IO_2;
1343 }
1344 skge_write32(hw, B2_GP_IO, reg);
1345 skge_read32(hw, B2_GP_IO);
1346
1347 xm_write16(hw, port, XM_MMU_CMD,
1348 xm_read16(hw, port, XM_MMU_CMD)
1349 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1350
1351 xm_read16(hw, port, XM_MMU_CMD);
1352 }
1353
1354
1355 static void genesis_get_stats(struct skge_port *skge, u64 *data)
1356 {
1357 struct skge_hw *hw = skge->hw;
1358 int port = skge->port;
1359 int i;
1360 unsigned long timeout = jiffies + HZ;
1361
1362 xm_write16(hw, port,
1363 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1364
1365 /* wait for update to complete */
1366 while (xm_read16(hw, port, XM_STAT_CMD)
1367 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1368 if (time_after(jiffies, timeout))
1369 break;
1370 udelay(10);
1371 }
1372
1373 /* special case for 64 bit octet counter */
1374 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1375 | xm_read32(hw, port, XM_TXO_OK_LO);
1376 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1377 | xm_read32(hw, port, XM_RXO_OK_LO);
1378
1379 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1380 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
1381 }
1382
1383 static void genesis_mac_intr(struct skge_hw *hw, int port)
1384 {
1385 struct skge_port *skge = netdev_priv(hw->dev[port]);
1386 u16 status = xm_read16(hw, port, XM_ISRC);
1387
1388 if (netif_msg_intr(skge))
1389 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1390 skge->netdev->name, status);
1391
1392 if (status & XM_IS_TXF_UR) {
1393 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
1394 ++skge->net_stats.tx_fifo_errors;
1395 }
1396 if (status & XM_IS_RXF_OV) {
1397 xm_write32(hw, port, XM_MODE, XM_MD_FRF);
1398 ++skge->net_stats.rx_fifo_errors;
1399 }
1400 }
1401
1402 static void gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1403 {
1404 int i;
1405
1406 gma_write16(hw, port, GM_SMI_DATA, val);
1407 gma_write16(hw, port, GM_SMI_CTRL,
1408 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1409 for (i = 0; i < PHY_RETRIES; i++) {
1410 udelay(1);
1411
1412 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1413 break;
1414 }
1415 }
1416
1417 static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1418 {
1419 int i;
1420
1421 gma_write16(hw, port, GM_SMI_CTRL,
1422 GM_SMI_CT_PHY_AD(hw->phy_addr)
1423 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1424
1425 for (i = 0; i < PHY_RETRIES; i++) {
1426 udelay(1);
1427 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1428 goto ready;
1429 }
1430
1431 printk(KERN_WARNING PFX "%s: phy read timeout\n",
1432 hw->dev[port]->name);
1433 return 0;
1434 ready:
1435 return gma_read16(hw, port, GM_SMI_DATA);
1436 }
1437
1438 static void genesis_link_up(struct skge_port *skge)
1439 {
1440 struct skge_hw *hw = skge->hw;
1441 int port = skge->port;
1442 u16 cmd;
1443 u32 mode, msk;
1444
1445 cmd = xm_read16(hw, port, XM_MMU_CMD);
1446
1447 /*
1448 * enabling pause frame reception is required for 1000BT
1449 * because the XMAC is not reset if the link is going down
1450 */
1451 if (skge->flow_control == FLOW_MODE_NONE ||
1452 skge->flow_control == FLOW_MODE_LOC_SEND)
1453 /* Disable Pause Frame Reception */
1454 cmd |= XM_MMU_IGN_PF;
1455 else
1456 /* Enable Pause Frame Reception */
1457 cmd &= ~XM_MMU_IGN_PF;
1458
1459 xm_write16(hw, port, XM_MMU_CMD, cmd);
1460
1461 mode = xm_read32(hw, port, XM_MODE);
1462 if (skge->flow_control == FLOW_MODE_SYMMETRIC ||
1463 skge->flow_control == FLOW_MODE_LOC_SEND) {
1464 /*
1465 * Configure Pause Frame Generation
1466 * Use internal and external Pause Frame Generation.
1467 * Sending pause frames is edge triggered.
1468 * Send a Pause frame with the maximum pause time if
1469 * internal oder external FIFO full condition occurs.
1470 * Send a zero pause time frame to re-start transmission.
1471 */
1472 /* XM_PAUSE_DA = '010000C28001' (default) */
1473 /* XM_MAC_PTIME = 0xffff (maximum) */
1474 /* remember this value is defined in big endian (!) */
1475 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
1476
1477 mode |= XM_PAUSE_MODE;
1478 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
1479 } else {
1480 /*
1481 * disable pause frame generation is required for 1000BT
1482 * because the XMAC is not reset if the link is going down
1483 */
1484 /* Disable Pause Mode in Mode Register */
1485 mode &= ~XM_PAUSE_MODE;
1486
1487 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
1488 }
1489
1490 xm_write32(hw, port, XM_MODE, mode);
1491
1492 msk = XM_DEF_MSK;
1493 /* disable GP0 interrupt bit for external Phy */
1494 msk |= XM_IS_INP_ASS;
1495
1496 xm_write16(hw, port, XM_IMSK, msk);
1497 xm_read16(hw, port, XM_ISRC);
1498
1499 /* get MMU Command Reg. */
1500 cmd = xm_read16(hw, port, XM_MMU_CMD);
1501 if (skge->duplex == DUPLEX_FULL)
1502 cmd |= XM_MMU_GMII_FD;
1503
1504 /*
1505 * Workaround BCOM Errata (#10523) for all BCom Phys
1506 * Enable Power Management after link up
1507 */
1508 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1509 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1510 & ~PHY_B_AC_DIS_PM);
1511 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1512
1513 /* enable Rx/Tx */
1514 xm_write16(hw, port, XM_MMU_CMD,
1515 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1516 skge_link_up(skge);
1517 }
1518
1519
1520 static inline void bcom_phy_intr(struct skge_port *skge)
1521 {
1522 struct skge_hw *hw = skge->hw;
1523 int port = skge->port;
1524 u16 isrc;
1525
1526 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
1527 if (netif_msg_intr(skge))
1528 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n",
1529 skge->netdev->name, isrc);
1530
1531 if (isrc & PHY_B_IS_PSE)
1532 printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",
1533 hw->dev[port]->name);
1534
1535 /* Workaround BCom Errata:
1536 * enable and disable loopback mode if "NO HCD" occurs.
1537 */
1538 if (isrc & PHY_B_IS_NO_HDCL) {
1539 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1540 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1541 ctrl | PHY_CT_LOOP);
1542 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1543 ctrl & ~PHY_CT_LOOP);
1544 }
1545
1546 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1547 bcom_check_link(hw, port);
1548
1549 }
1550
1551 /* Marvell Phy Initailization */
1552 static void yukon_init(struct skge_hw *hw, int port)
1553 {
1554 struct skge_port *skge = netdev_priv(hw->dev[port]);
1555 u16 ctrl, ct1000, adv;
1556
1557 if (skge->autoneg == AUTONEG_ENABLE) {
1558 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
1559
1560 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1561 PHY_M_EC_MAC_S_MSK);
1562 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1563
1564 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
1565
1566 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
1567 }
1568
1569 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1570 if (skge->autoneg == AUTONEG_DISABLE)
1571 ctrl &= ~PHY_CT_ANE;
1572
1573 ctrl |= PHY_CT_RESET;
1574 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1575
1576 ctrl = 0;
1577 ct1000 = 0;
1578 adv = PHY_AN_CSMA;
1579
1580 if (skge->autoneg == AUTONEG_ENABLE) {
1581 if (hw->copper) {
1582 if (skge->advertising & ADVERTISED_1000baseT_Full)
1583 ct1000 |= PHY_M_1000C_AFD;
1584 if (skge->advertising & ADVERTISED_1000baseT_Half)
1585 ct1000 |= PHY_M_1000C_AHD;
1586 if (skge->advertising & ADVERTISED_100baseT_Full)
1587 adv |= PHY_M_AN_100_FD;
1588 if (skge->advertising & ADVERTISED_100baseT_Half)
1589 adv |= PHY_M_AN_100_HD;
1590 if (skge->advertising & ADVERTISED_10baseT_Full)
1591 adv |= PHY_M_AN_10_FD;
1592 if (skge->advertising & ADVERTISED_10baseT_Half)
1593 adv |= PHY_M_AN_10_HD;
1594 } else /* special defines for FIBER (88E1011S only) */
1595 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
1596
1597 /* Set Flow-control capabilities */
1598 adv |= phy_pause_map[skge->flow_control];
1599
1600 /* Restart Auto-negotiation */
1601 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1602 } else {
1603 /* forced speed/duplex settings */
1604 ct1000 = PHY_M_1000C_MSE;
1605
1606 if (skge->duplex == DUPLEX_FULL)
1607 ctrl |= PHY_CT_DUP_MD;
1608
1609 switch (skge->speed) {
1610 case SPEED_1000:
1611 ctrl |= PHY_CT_SP1000;
1612 break;
1613 case SPEED_100:
1614 ctrl |= PHY_CT_SP100;
1615 break;
1616 }
1617
1618 ctrl |= PHY_CT_RESET;
1619 }
1620
1621 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
1622
1623 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
1624 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1625
1626 /* Enable phy interrupt on autonegotiation complete (or link up) */
1627 if (skge->autoneg == AUTONEG_ENABLE)
1628 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
1629 else
1630 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
1631 }
1632
1633 static void yukon_reset(struct skge_hw *hw, int port)
1634 {
1635 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
1636 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
1637 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
1638 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
1639 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
1640
1641 gma_write16(hw, port, GM_RX_CTRL,
1642 gma_read16(hw, port, GM_RX_CTRL)
1643 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
1644 }
1645
1646 /* Apparently, early versions of Yukon-Lite had wrong chip_id? */
1647 static int is_yukon_lite_a0(struct skge_hw *hw)
1648 {
1649 u32 reg;
1650 int ret;
1651
1652 if (hw->chip_id != CHIP_ID_YUKON)
1653 return 0;
1654
1655 reg = skge_read32(hw, B2_FAR);
1656 skge_write8(hw, B2_FAR + 3, 0xff);
1657 ret = (skge_read8(hw, B2_FAR + 3) != 0);
1658 skge_write32(hw, B2_FAR, reg);
1659 return ret;
1660 }
1661
1662 static void yukon_mac_init(struct skge_hw *hw, int port)
1663 {
1664 struct skge_port *skge = netdev_priv(hw->dev[port]);
1665 int i;
1666 u32 reg;
1667 const u8 *addr = hw->dev[port]->dev_addr;
1668
1669 /* WA code for COMA mode -- set PHY reset */
1670 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1671 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1672 reg = skge_read32(hw, B2_GP_IO);
1673 reg |= GP_DIR_9 | GP_IO_9;
1674 skge_write32(hw, B2_GP_IO, reg);
1675 }
1676
1677 /* hard reset */
1678 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1679 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1680
1681 /* WA code for COMA mode -- clear PHY reset */
1682 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1683 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1684 reg = skge_read32(hw, B2_GP_IO);
1685 reg |= GP_DIR_9;
1686 reg &= ~GP_IO_9;
1687 skge_write32(hw, B2_GP_IO, reg);
1688 }
1689
1690 /* Set hardware config mode */
1691 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
1692 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
1693 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
1694
1695 /* Clear GMC reset */
1696 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
1697 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
1698 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
1699 if (skge->autoneg == AUTONEG_DISABLE) {
1700 reg = GM_GPCR_AU_ALL_DIS;
1701 gma_write16(hw, port, GM_GP_CTRL,
1702 gma_read16(hw, port, GM_GP_CTRL) | reg);
1703
1704 switch (skge->speed) {
1705 case SPEED_1000:
1706 reg |= GM_GPCR_SPEED_1000;
1707 /* fallthru */
1708 case SPEED_100:
1709 reg |= GM_GPCR_SPEED_100;
1710 }
1711
1712 if (skge->duplex == DUPLEX_FULL)
1713 reg |= GM_GPCR_DUP_FULL;
1714 } else
1715 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
1716 switch (skge->flow_control) {
1717 case FLOW_MODE_NONE:
1718 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1719 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1720 break;
1721 case FLOW_MODE_LOC_SEND:
1722 /* disable Rx flow-control */
1723 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1724 }
1725
1726 gma_write16(hw, port, GM_GP_CTRL, reg);
1727 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
1728
1729 yukon_init(hw, port);
1730
1731 /* MIB clear */
1732 reg = gma_read16(hw, port, GM_PHY_ADDR);
1733 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
1734
1735 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
1736 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
1737 gma_write16(hw, port, GM_PHY_ADDR, reg);
1738
1739 /* transmit control */
1740 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
1741
1742 /* receive control reg: unicast + multicast + no FCS */
1743 gma_write16(hw, port, GM_RX_CTRL,
1744 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
1745
1746 /* transmit flow control */
1747 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
1748
1749 /* transmit parameter */
1750 gma_write16(hw, port, GM_TX_PARAM,
1751 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
1752 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
1753 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
1754
1755 /* serial mode register */
1756 reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1757 if (hw->dev[port]->mtu > 1500)
1758 reg |= GM_SMOD_JUMBO_ENA;
1759
1760 gma_write16(hw, port, GM_SERIAL_MODE, reg);
1761
1762 /* physical address: used for pause frames */
1763 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
1764 /* virtual address for data */
1765 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
1766
1767 /* enable interrupt mask for counter overflows */
1768 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
1769 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
1770 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
1771
1772 /* Initialize Mac Fifo */
1773
1774 /* Configure Rx MAC FIFO */
1775 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
1776 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
1777
1778 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
1779 if (is_yukon_lite_a0(hw))
1780 reg &= ~GMF_RX_F_FL_ON;
1781
1782 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
1783 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
1784 /*
1785 * because Pause Packet Truncation in GMAC is not working
1786 * we have to increase the Flush Threshold to 64 bytes
1787 * in order to flush pause packets in Rx FIFO on Yukon-1
1788 */
1789 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
1790
1791 /* Configure Tx MAC FIFO */
1792 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
1793 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
1794 }
1795
1796 static void yukon_stop(struct skge_port *skge)
1797 {
1798 struct skge_hw *hw = skge->hw;
1799 int port = skge->port;
1800
1801 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1802 yukon_reset(hw, port);
1803
1804 gma_write16(hw, port, GM_GP_CTRL,
1805 gma_read16(hw, port, GM_GP_CTRL)
1806 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
1807 gma_read16(hw, port, GM_GP_CTRL);
1808
1809 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1810 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1811 u32 io = skge_read32(hw, B2_GP_IO);
1812
1813 io |= GP_DIR_9 | GP_IO_9;
1814 skge_write32(hw, B2_GP_IO, io);
1815 skge_read32(hw, B2_GP_IO);
1816 }
1817
1818 /* set GPHY Control reset */
1819 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1820 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1821 }
1822
1823 static void yukon_get_stats(struct skge_port *skge, u64 *data)
1824 {
1825 struct skge_hw *hw = skge->hw;
1826 int port = skge->port;
1827 int i;
1828
1829 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
1830 | gma_read32(hw, port, GM_TXO_OK_LO);
1831 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
1832 | gma_read32(hw, port, GM_RXO_OK_LO);
1833
1834 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1835 data[i] = gma_read32(hw, port,
1836 skge_stats[i].gma_offset);
1837 }
1838
1839 static void yukon_mac_intr(struct skge_hw *hw, int port)
1840 {
1841 struct net_device *dev = hw->dev[port];
1842 struct skge_port *skge = netdev_priv(dev);
1843 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
1844
1845 if (netif_msg_intr(skge))
1846 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1847 dev->name, status);
1848
1849 if (status & GM_IS_RX_FF_OR) {
1850 ++skge->net_stats.rx_fifo_errors;
1851 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
1852 }
1853
1854 if (status & GM_IS_TX_FF_UR) {
1855 ++skge->net_stats.tx_fifo_errors;
1856 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
1857 }
1858
1859 }
1860
1861 static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
1862 {
1863 switch (aux & PHY_M_PS_SPEED_MSK) {
1864 case PHY_M_PS_SPEED_1000:
1865 return SPEED_1000;
1866 case PHY_M_PS_SPEED_100:
1867 return SPEED_100;
1868 default:
1869 return SPEED_10;
1870 }
1871 }
1872
1873 static void yukon_link_up(struct skge_port *skge)
1874 {
1875 struct skge_hw *hw = skge->hw;
1876 int port = skge->port;
1877 u16 reg;
1878
1879 /* Enable Transmit FIFO Underrun */
1880 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
1881
1882 reg = gma_read16(hw, port, GM_GP_CTRL);
1883 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
1884 reg |= GM_GPCR_DUP_FULL;
1885
1886 /* enable Rx/Tx */
1887 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1888 gma_write16(hw, port, GM_GP_CTRL, reg);
1889
1890 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
1891 skge_link_up(skge);
1892 }
1893
1894 static void yukon_link_down(struct skge_port *skge)
1895 {
1896 struct skge_hw *hw = skge->hw;
1897 int port = skge->port;
1898 u16 ctrl;
1899
1900 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1901
1902 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1903 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1904 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1905
1906 if (skge->flow_control == FLOW_MODE_REM_SEND) {
1907 /* restore Asymmetric Pause bit */
1908 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1909 gm_phy_read(hw, port,
1910 PHY_MARV_AUNE_ADV)
1911 | PHY_M_AN_ASP);
1912
1913 }
1914
1915 yukon_reset(hw, port);
1916 skge_link_down(skge);
1917
1918 yukon_init(hw, port);
1919 }
1920
1921 static void yukon_phy_intr(struct skge_port *skge)
1922 {
1923 struct skge_hw *hw = skge->hw;
1924 int port = skge->port;
1925 const char *reason = NULL;
1926 u16 istatus, phystat;
1927
1928 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1929 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1930
1931 if (netif_msg_intr(skge))
1932 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n",
1933 skge->netdev->name, istatus, phystat);
1934
1935 if (istatus & PHY_M_IS_AN_COMPL) {
1936 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
1937 & PHY_M_AN_RF) {
1938 reason = "remote fault";
1939 goto failed;
1940 }
1941
1942 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1943 reason = "master/slave fault";
1944 goto failed;
1945 }
1946
1947 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
1948 reason = "speed/duplex";
1949 goto failed;
1950 }
1951
1952 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
1953 ? DUPLEX_FULL : DUPLEX_HALF;
1954 skge->speed = yukon_speed(hw, phystat);
1955
1956 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1957 switch (phystat & PHY_M_PS_PAUSE_MSK) {
1958 case PHY_M_PS_PAUSE_MSK:
1959 skge->flow_control = FLOW_MODE_SYMMETRIC;
1960 break;
1961 case PHY_M_PS_RX_P_EN:
1962 skge->flow_control = FLOW_MODE_REM_SEND;
1963 break;
1964 case PHY_M_PS_TX_P_EN:
1965 skge->flow_control = FLOW_MODE_LOC_SEND;
1966 break;
1967 default:
1968 skge->flow_control = FLOW_MODE_NONE;
1969 }
1970
1971 if (skge->flow_control == FLOW_MODE_NONE ||
1972 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
1973 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1974 else
1975 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1976 yukon_link_up(skge);
1977 return;
1978 }
1979
1980 if (istatus & PHY_M_IS_LSP_CHANGE)
1981 skge->speed = yukon_speed(hw, phystat);
1982
1983 if (istatus & PHY_M_IS_DUP_CHANGE)
1984 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1985 if (istatus & PHY_M_IS_LST_CHANGE) {
1986 if (phystat & PHY_M_PS_LINK_UP)
1987 yukon_link_up(skge);
1988 else
1989 yukon_link_down(skge);
1990 }
1991 return;
1992 failed:
1993 printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",
1994 skge->netdev->name, reason);
1995
1996 /* XXX restart autonegotiation? */
1997 }
1998
1999 static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
2000 {
2001 u32 end;
2002
2003 start /= 8;
2004 len /= 8;
2005 end = start + len - 1;
2006
2007 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2008 skge_write32(hw, RB_ADDR(q, RB_START), start);
2009 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2010 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2011 skge_write32(hw, RB_ADDR(q, RB_END), end);
2012
2013 if (q == Q_R1 || q == Q_R2) {
2014 /* Set thresholds on receive queue's */
2015 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2016 start + (2*len)/3);
2017 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2018 start + (len/3));
2019 } else {
2020 /* Enable store & forward on Tx queue's because
2021 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2022 */
2023 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2024 }
2025
2026 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2027 }
2028
2029 /* Setup Bus Memory Interface */
2030 static void skge_qset(struct skge_port *skge, u16 q,
2031 const struct skge_element *e)
2032 {
2033 struct skge_hw *hw = skge->hw;
2034 u32 watermark = 0x600;
2035 u64 base = skge->dma + (e->desc - skge->mem);
2036
2037 /* optimization to reduce window on 32bit/33mhz */
2038 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2039 watermark /= 2;
2040
2041 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2042 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2043 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2044 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2045 }
2046
2047 static int skge_up(struct net_device *dev)
2048 {
2049 struct skge_port *skge = netdev_priv(dev);
2050 struct skge_hw *hw = skge->hw;
2051 int port = skge->port;
2052 u32 chunk, ram_addr;
2053 size_t rx_size, tx_size;
2054 int err;
2055
2056 if (netif_msg_ifup(skge))
2057 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
2058
2059 if (dev->mtu > RX_BUF_SIZE)
2060 skge->rx_buf_size = dev->mtu + ETH_HLEN + NET_IP_ALIGN;
2061 else
2062 skge->rx_buf_size = RX_BUF_SIZE;
2063
2064
2065 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2066 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2067 skge->mem_size = tx_size + rx_size;
2068 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2069 if (!skge->mem)
2070 return -ENOMEM;
2071
2072 memset(skge->mem, 0, skge->mem_size);
2073
2074 if ((err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma)))
2075 goto free_pci_mem;
2076
2077 err = skge_rx_fill(skge);
2078 if (err)
2079 goto free_rx_ring;
2080
2081 if ((err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2082 skge->dma + rx_size)))
2083 goto free_rx_ring;
2084
2085 skge->tx_avail = skge->tx_ring.count - 1;
2086
2087 /* Enable IRQ from port */
2088 hw->intr_mask |= portirqmask[port];
2089 skge_write32(hw, B0_IMSK, hw->intr_mask);
2090
2091 /* Initialze MAC */
2092 spin_lock_bh(&hw->phy_lock);
2093 if (hw->chip_id == CHIP_ID_GENESIS)
2094 genesis_mac_init(hw, port);
2095 else
2096 yukon_mac_init(hw, port);
2097 spin_unlock_bh(&hw->phy_lock);
2098
2099 /* Configure RAMbuffers */
2100 chunk = hw->ram_size / ((hw->ports + 1)*2);
2101 ram_addr = hw->ram_offset + 2 * chunk * port;
2102
2103 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2104 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2105
2106 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2107 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2108 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2109
2110 /* Start receiver BMU */
2111 wmb();
2112 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2113 skge_led(skge, LED_MODE_ON);
2114
2115 return 0;
2116
2117 free_rx_ring:
2118 skge_rx_clean(skge);
2119 kfree(skge->rx_ring.start);
2120 free_pci_mem:
2121 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2122
2123 return err;
2124 }
2125
2126 static int skge_down(struct net_device *dev)
2127 {
2128 struct skge_port *skge = netdev_priv(dev);
2129 struct skge_hw *hw = skge->hw;
2130 int port = skge->port;
2131
2132 if (netif_msg_ifdown(skge))
2133 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
2134
2135 netif_stop_queue(dev);
2136
2137 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
2138 if (hw->chip_id == CHIP_ID_GENESIS)
2139 genesis_stop(skge);
2140 else
2141 yukon_stop(skge);
2142
2143 hw->intr_mask &= ~portirqmask[skge->port];
2144 skge_write32(hw, B0_IMSK, hw->intr_mask);
2145
2146 /* Stop transmitter */
2147 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2148 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2149 RB_RST_SET|RB_DIS_OP_MD);
2150
2151
2152 /* Disable Force Sync bit and Enable Alloc bit */
2153 skge_write8(hw, SK_REG(port, TXA_CTRL),
2154 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2155
2156 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2157 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2158 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2159
2160 /* Reset PCI FIFO */
2161 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2162 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2163
2164 /* Reset the RAM Buffer async Tx queue */
2165 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2166 /* stop receiver */
2167 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2168 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2169 RB_RST_SET|RB_DIS_OP_MD);
2170 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2171
2172 if (hw->chip_id == CHIP_ID_GENESIS) {
2173 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2174 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
2175 } else {
2176 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2177 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2178 }
2179
2180 skge_led(skge, LED_MODE_OFF);
2181
2182 skge_tx_clean(skge);
2183 skge_rx_clean(skge);
2184
2185 kfree(skge->rx_ring.start);
2186 kfree(skge->tx_ring.start);
2187 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2188 return 0;
2189 }
2190
2191 static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2192 {
2193 struct skge_port *skge = netdev_priv(dev);
2194 struct skge_hw *hw = skge->hw;
2195 struct skge_ring *ring = &skge->tx_ring;
2196 struct skge_element *e;
2197 struct skge_tx_desc *td;
2198 int i;
2199 u32 control, len;
2200 u64 map;
2201 unsigned long flags;
2202
2203 skb = skb_padto(skb, ETH_ZLEN);
2204 if (!skb)
2205 return NETDEV_TX_OK;
2206
2207 local_irq_save(flags);
2208 if (!spin_trylock(&skge->tx_lock)) {
2209 /* Collision - tell upper layer to requeue */
2210 local_irq_restore(flags);
2211 return NETDEV_TX_LOCKED;
2212 }
2213
2214 if (unlikely(skge->tx_avail < skb_shinfo(skb)->nr_frags +1)) {
2215 netif_stop_queue(dev);
2216 spin_unlock_irqrestore(&skge->tx_lock, flags);
2217
2218 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
2219 dev->name);
2220 return NETDEV_TX_BUSY;
2221 }
2222
2223 e = ring->to_use;
2224 td = e->desc;
2225 e->skb = skb;
2226 len = skb_headlen(skb);
2227 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2228 pci_unmap_addr_set(e, mapaddr, map);
2229 pci_unmap_len_set(e, maplen, len);
2230
2231 td->dma_lo = map;
2232 td->dma_hi = map >> 32;
2233
2234 if (skb->ip_summed == CHECKSUM_HW) {
2235 const struct iphdr *ip
2236 = (const struct iphdr *) (skb->data + ETH_HLEN);
2237 int offset = skb->h.raw - skb->data;
2238
2239 /* This seems backwards, but it is what the sk98lin
2240 * does. Looks like hardware is wrong?
2241 */
2242 if (ip->protocol == IPPROTO_UDP
2243 && hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
2244 control = BMU_TCP_CHECK;
2245 else
2246 control = BMU_UDP_CHECK;
2247
2248 td->csum_offs = 0;
2249 td->csum_start = offset;
2250 td->csum_write = offset + skb->csum;
2251 } else
2252 control = BMU_CHECK;
2253
2254 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2255 control |= BMU_EOF| BMU_IRQ_EOF;
2256 else {
2257 struct skge_tx_desc *tf = td;
2258
2259 control |= BMU_STFWD;
2260 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2261 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2262
2263 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2264 frag->size, PCI_DMA_TODEVICE);
2265
2266 e = e->next;
2267 e->skb = NULL;
2268 tf = e->desc;
2269 tf->dma_lo = map;
2270 tf->dma_hi = (u64) map >> 32;
2271 pci_unmap_addr_set(e, mapaddr, map);
2272 pci_unmap_len_set(e, maplen, frag->size);
2273
2274 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2275 }
2276 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2277 }
2278 /* Make sure all the descriptors written */
2279 wmb();
2280 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2281 wmb();
2282
2283 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2284
2285 if (netif_msg_tx_queued(skge))
2286 printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n",
2287 dev->name, e - ring->start, skb->len);
2288
2289 ring->to_use = e->next;
2290 skge->tx_avail -= skb_shinfo(skb)->nr_frags + 1;
2291 if (skge->tx_avail <= MAX_SKB_FRAGS + 1) {
2292 pr_debug("%s: transmit queue full\n", dev->name);
2293 netif_stop_queue(dev);
2294 }
2295
2296 dev->trans_start = jiffies;
2297 spin_unlock_irqrestore(&skge->tx_lock, flags);
2298
2299 return NETDEV_TX_OK;
2300 }
2301
2302 static inline void skge_tx_free(struct skge_hw *hw, struct skge_element *e)
2303 {
2304 /* This ring element can be skb or fragment */
2305 if (e->skb) {
2306 pci_unmap_single(hw->pdev,
2307 pci_unmap_addr(e, mapaddr),
2308 pci_unmap_len(e, maplen),
2309 PCI_DMA_TODEVICE);
2310 dev_kfree_skb_any(e->skb);
2311 e->skb = NULL;
2312 } else {
2313 pci_unmap_page(hw->pdev,
2314 pci_unmap_addr(e, mapaddr),
2315 pci_unmap_len(e, maplen),
2316 PCI_DMA_TODEVICE);
2317 }
2318 }
2319
2320 static void skge_tx_clean(struct skge_port *skge)
2321 {
2322 struct skge_ring *ring = &skge->tx_ring;
2323 struct skge_element *e;
2324 unsigned long flags;
2325
2326 spin_lock_irqsave(&skge->tx_lock, flags);
2327 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
2328 ++skge->tx_avail;
2329 skge_tx_free(skge->hw, e);
2330 }
2331 ring->to_clean = e;
2332 spin_unlock_irqrestore(&skge->tx_lock, flags);
2333 }
2334
2335 static void skge_tx_timeout(struct net_device *dev)
2336 {
2337 struct skge_port *skge = netdev_priv(dev);
2338
2339 if (netif_msg_timer(skge))
2340 printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);
2341
2342 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
2343 skge_tx_clean(skge);
2344 }
2345
2346 static int skge_change_mtu(struct net_device *dev, int new_mtu)
2347 {
2348 int err = 0;
2349 int running = netif_running(dev);
2350
2351 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2352 return -EINVAL;
2353
2354
2355 if (running)
2356 skge_down(dev);
2357 dev->mtu = new_mtu;
2358 if (running)
2359 skge_up(dev);
2360
2361 return err;
2362 }
2363
2364 static void genesis_set_multicast(struct net_device *dev)
2365 {
2366 struct skge_port *skge = netdev_priv(dev);
2367 struct skge_hw *hw = skge->hw;
2368 int port = skge->port;
2369 int i, count = dev->mc_count;
2370 struct dev_mc_list *list = dev->mc_list;
2371 u32 mode;
2372 u8 filter[8];
2373
2374 mode = xm_read32(hw, port, XM_MODE);
2375 mode |= XM_MD_ENA_HASH;
2376 if (dev->flags & IFF_PROMISC)
2377 mode |= XM_MD_ENA_PROM;
2378 else
2379 mode &= ~XM_MD_ENA_PROM;
2380
2381 if (dev->flags & IFF_ALLMULTI)
2382 memset(filter, 0xff, sizeof(filter));
2383 else {
2384 memset(filter, 0, sizeof(filter));
2385 for (i = 0; list && i < count; i++, list = list->next) {
2386 u32 crc, bit;
2387 crc = ether_crc_le(ETH_ALEN, list->dmi_addr);
2388 bit = ~crc & 0x3f;
2389 filter[bit/8] |= 1 << (bit%8);
2390 }
2391 }
2392
2393 xm_write32(hw, port, XM_MODE, mode);
2394 xm_outhash(hw, port, XM_HSM, filter);
2395 }
2396
2397 static void yukon_set_multicast(struct net_device *dev)
2398 {
2399 struct skge_port *skge = netdev_priv(dev);
2400 struct skge_hw *hw = skge->hw;
2401 int port = skge->port;
2402 struct dev_mc_list *list = dev->mc_list;
2403 u16 reg;
2404 u8 filter[8];
2405
2406 memset(filter, 0, sizeof(filter));
2407
2408 reg = gma_read16(hw, port, GM_RX_CTRL);
2409 reg |= GM_RXCR_UCF_ENA;
2410
2411 if (dev->flags & IFF_PROMISC) /* promiscious */
2412 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2413 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2414 memset(filter, 0xff, sizeof(filter));
2415 else if (dev->mc_count == 0) /* no multicast */
2416 reg &= ~GM_RXCR_MCF_ENA;
2417 else {
2418 int i;
2419 reg |= GM_RXCR_MCF_ENA;
2420
2421 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2422 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2423 filter[bit/8] |= 1 << (bit%8);
2424 }
2425 }
2426
2427
2428 gma_write16(hw, port, GM_MC_ADDR_H1,
2429 (u16)filter[0] | ((u16)filter[1] << 8));
2430 gma_write16(hw, port, GM_MC_ADDR_H2,
2431 (u16)filter[2] | ((u16)filter[3] << 8));
2432 gma_write16(hw, port, GM_MC_ADDR_H3,
2433 (u16)filter[4] | ((u16)filter[5] << 8));
2434 gma_write16(hw, port, GM_MC_ADDR_H4,
2435 (u16)filter[6] | ((u16)filter[7] << 8));
2436
2437 gma_write16(hw, port, GM_RX_CTRL, reg);
2438 }
2439
2440 static inline u16 phy_length(const struct skge_hw *hw, u32 status)
2441 {
2442 if (hw->chip_id == CHIP_ID_GENESIS)
2443 return status >> XMR_FS_LEN_SHIFT;
2444 else
2445 return status >> GMR_FS_LEN_SHIFT;
2446 }
2447
2448 static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
2449 {
2450 if (hw->chip_id == CHIP_ID_GENESIS)
2451 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
2452 else
2453 return (status & GMR_FS_ANY_ERR) ||
2454 (status & GMR_FS_RX_OK) == 0;
2455 }
2456
2457
2458 /* Get receive buffer from descriptor.
2459 * Handles copy of small buffers and reallocation failures
2460 */
2461 static inline struct sk_buff *skge_rx_get(struct skge_port *skge,
2462 struct skge_element *e,
2463 u32 control, u32 status, u16 csum)
2464 {
2465 struct sk_buff *skb;
2466 u16 len = control & BMU_BBC;
2467
2468 if (unlikely(netif_msg_rx_status(skge)))
2469 printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",
2470 skge->netdev->name, e - skge->rx_ring.start,
2471 status, len);
2472
2473 if (len > skge->rx_buf_size)
2474 goto error;
2475
2476 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
2477 goto error;
2478
2479 if (bad_phy_status(skge->hw, status))
2480 goto error;
2481
2482 if (phy_length(skge->hw, status) != len)
2483 goto error;
2484
2485 if (len < RX_COPY_THRESHOLD) {
2486 skb = dev_alloc_skb(len + 2);
2487 if (!skb)
2488 goto resubmit;
2489
2490 skb_reserve(skb, 2);
2491 pci_dma_sync_single_for_cpu(skge->hw->pdev,
2492 pci_unmap_addr(e, mapaddr),
2493 len, PCI_DMA_FROMDEVICE);
2494 memcpy(skb->data, e->skb->data, len);
2495 pci_dma_sync_single_for_device(skge->hw->pdev,
2496 pci_unmap_addr(e, mapaddr),
2497 len, PCI_DMA_FROMDEVICE);
2498 skge_rx_reuse(e, skge->rx_buf_size);
2499 } else {
2500 struct sk_buff *nskb;
2501 nskb = dev_alloc_skb(skge->rx_buf_size + NET_IP_ALIGN);
2502 if (!nskb)
2503 goto resubmit;
2504
2505 pci_unmap_single(skge->hw->pdev,
2506 pci_unmap_addr(e, mapaddr),
2507 pci_unmap_len(e, maplen),
2508 PCI_DMA_FROMDEVICE);
2509 skb = e->skb;
2510 prefetch(skb->data);
2511 skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
2512 }
2513
2514 skb_put(skb, len);
2515 skb->dev = skge->netdev;
2516 if (skge->rx_csum) {
2517 skb->csum = csum;
2518 skb->ip_summed = CHECKSUM_HW;
2519 }
2520
2521 skb->protocol = eth_type_trans(skb, skge->netdev);
2522
2523 return skb;
2524 error:
2525
2526 if (netif_msg_rx_err(skge))
2527 printk(KERN_DEBUG PFX "%s: rx err, slot %td control 0x%x status 0x%x\n",
2528 skge->netdev->name, e - skge->rx_ring.start,
2529 control, status);
2530
2531 if (skge->hw->chip_id == CHIP_ID_GENESIS) {
2532 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
2533 skge->net_stats.rx_length_errors++;
2534 if (status & XMR_FS_FRA_ERR)
2535 skge->net_stats.rx_frame_errors++;
2536 if (status & XMR_FS_FCS_ERR)
2537 skge->net_stats.rx_crc_errors++;
2538 } else {
2539 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
2540 skge->net_stats.rx_length_errors++;
2541 if (status & GMR_FS_FRAGMENT)
2542 skge->net_stats.rx_frame_errors++;
2543 if (status & GMR_FS_CRC_ERR)
2544 skge->net_stats.rx_crc_errors++;
2545 }
2546
2547 resubmit:
2548 skge_rx_reuse(e, skge->rx_buf_size);
2549 return NULL;
2550 }
2551
2552
2553 static int skge_poll(struct net_device *dev, int *budget)
2554 {
2555 struct skge_port *skge = netdev_priv(dev);
2556 struct skge_hw *hw = skge->hw;
2557 struct skge_ring *ring = &skge->rx_ring;
2558 struct skge_element *e;
2559 unsigned int to_do = min(dev->quota, *budget);
2560 unsigned int work_done = 0;
2561
2562 for (e = ring->to_clean; work_done < to_do; e = e->next) {
2563 struct skge_rx_desc *rd = e->desc;
2564 struct sk_buff *skb;
2565 u32 control;
2566
2567 rmb();
2568 control = rd->control;
2569 if (control & BMU_OWN)
2570 break;
2571
2572 skb = skge_rx_get(skge, e, control, rd->status,
2573 le16_to_cpu(rd->csum2));
2574 if (likely(skb)) {
2575 dev->last_rx = jiffies;
2576 netif_receive_skb(skb);
2577
2578 ++work_done;
2579 } else
2580 skge_rx_reuse(e, skge->rx_buf_size);
2581 }
2582 ring->to_clean = e;
2583
2584 /* restart receiver */
2585 wmb();
2586 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR),
2587 CSR_START | CSR_IRQ_CL_F);
2588
2589 *budget -= work_done;
2590 dev->quota -= work_done;
2591
2592 if (work_done >= to_do)
2593 return 1; /* not done */
2594
2595 local_irq_disable();
2596 __netif_rx_complete(dev);
2597 hw->intr_mask |= portirqmask[skge->port];
2598 skge_write32(hw, B0_IMSK, hw->intr_mask);
2599 local_irq_enable();
2600 return 0;
2601 }
2602
2603 static inline void skge_tx_intr(struct net_device *dev)
2604 {
2605 struct skge_port *skge = netdev_priv(dev);
2606 struct skge_hw *hw = skge->hw;
2607 struct skge_ring *ring = &skge->tx_ring;
2608 struct skge_element *e;
2609
2610 spin_lock(&skge->tx_lock);
2611 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
2612 struct skge_tx_desc *td = e->desc;
2613 u32 control;
2614
2615 rmb();
2616 control = td->control;
2617 if (control & BMU_OWN)
2618 break;
2619
2620 if (unlikely(netif_msg_tx_done(skge)))
2621 printk(KERN_DEBUG PFX "%s: tx done slot %td status 0x%x\n",
2622 dev->name, e - ring->start, td->status);
2623
2624 skge_tx_free(hw, e);
2625 e->skb = NULL;
2626 ++skge->tx_avail;
2627 }
2628 ring->to_clean = e;
2629 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
2630
2631 if (skge->tx_avail > MAX_SKB_FRAGS + 1)
2632 netif_wake_queue(dev);
2633
2634 spin_unlock(&skge->tx_lock);
2635 }
2636
2637 /* Parity errors seem to happen when Genesis is connected to a switch
2638 * with no other ports present. Heartbeat error??
2639 */
2640 static void skge_mac_parity(struct skge_hw *hw, int port)
2641 {
2642 struct net_device *dev = hw->dev[port];
2643
2644 if (dev) {
2645 struct skge_port *skge = netdev_priv(dev);
2646 ++skge->net_stats.tx_heartbeat_errors;
2647 }
2648
2649 if (hw->chip_id == CHIP_ID_GENESIS)
2650 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
2651 MFF_CLR_PERR);
2652 else
2653 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
2654 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
2655 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
2656 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
2657 }
2658
2659 static void skge_pci_clear(struct skge_hw *hw)
2660 {
2661 u16 status;
2662
2663 pci_read_config_word(hw->pdev, PCI_STATUS, &status);
2664 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2665 pci_write_config_word(hw->pdev, PCI_STATUS,
2666 status | PCI_STATUS_ERROR_BITS);
2667 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2668 }
2669
2670 static void skge_mac_intr(struct skge_hw *hw, int port)
2671 {
2672 if (hw->chip_id == CHIP_ID_GENESIS)
2673 genesis_mac_intr(hw, port);
2674 else
2675 yukon_mac_intr(hw, port);
2676 }
2677
2678 /* Handle device specific framing and timeout interrupts */
2679 static void skge_error_irq(struct skge_hw *hw)
2680 {
2681 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2682
2683 if (hw->chip_id == CHIP_ID_GENESIS) {
2684 /* clear xmac errors */
2685 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
2686 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
2687 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
2688 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
2689 } else {
2690 /* Timestamp (unused) overflow */
2691 if (hwstatus & IS_IRQ_TIST_OV)
2692 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2693 }
2694
2695 if (hwstatus & IS_RAM_RD_PAR) {
2696 printk(KERN_ERR PFX "Ram read data parity error\n");
2697 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
2698 }
2699
2700 if (hwstatus & IS_RAM_WR_PAR) {
2701 printk(KERN_ERR PFX "Ram write data parity error\n");
2702 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
2703 }
2704
2705 if (hwstatus & IS_M1_PAR_ERR)
2706 skge_mac_parity(hw, 0);
2707
2708 if (hwstatus & IS_M2_PAR_ERR)
2709 skge_mac_parity(hw, 1);
2710
2711 if (hwstatus & IS_R1_PAR_ERR)
2712 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
2713
2714 if (hwstatus & IS_R2_PAR_ERR)
2715 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
2716
2717 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
2718 printk(KERN_ERR PFX "hardware error detected (status 0x%x)\n",
2719 hwstatus);
2720
2721 skge_pci_clear(hw);
2722
2723 /* if error still set then just ignore it */
2724 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2725 if (hwstatus & IS_IRQ_STAT) {
2726 pr_debug("IRQ status %x: still set ignoring hardware errors\n",
2727 hwstatus);
2728 hw->intr_mask &= ~IS_HW_ERR;
2729 }
2730 }
2731 }
2732
2733 /*
2734 * Interrrupt from PHY are handled in tasklet (soft irq)
2735 * because accessing phy registers requires spin wait which might
2736 * cause excess interrupt latency.
2737 */
2738 static void skge_extirq(unsigned long data)
2739 {
2740 struct skge_hw *hw = (struct skge_hw *) data;
2741 int port;
2742
2743 spin_lock(&hw->phy_lock);
2744 for (port = 0; port < 2; port++) {
2745 struct net_device *dev = hw->dev[port];
2746
2747 if (dev && netif_running(dev)) {
2748 struct skge_port *skge = netdev_priv(dev);
2749
2750 if (hw->chip_id != CHIP_ID_GENESIS)
2751 yukon_phy_intr(skge);
2752 else
2753 bcom_phy_intr(skge);
2754 }
2755 }
2756 spin_unlock(&hw->phy_lock);
2757
2758 local_irq_disable();
2759 hw->intr_mask |= IS_EXT_REG;
2760 skge_write32(hw, B0_IMSK, hw->intr_mask);
2761 local_irq_enable();
2762 }
2763
2764 static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)
2765 {
2766 struct skge_hw *hw = dev_id;
2767 u32 status = skge_read32(hw, B0_SP_ISRC);
2768
2769 if (status == 0 || status == ~0) /* hotplug or shared irq */
2770 return IRQ_NONE;
2771
2772 status &= hw->intr_mask;
2773 if (status & IS_R1_F) {
2774 hw->intr_mask &= ~IS_R1_F;
2775 netif_rx_schedule(hw->dev[0]);
2776 }
2777
2778 if (status & IS_R2_F) {
2779 hw->intr_mask &= ~IS_R2_F;
2780 netif_rx_schedule(hw->dev[1]);
2781 }
2782
2783 if (status & IS_XA1_F)
2784 skge_tx_intr(hw->dev[0]);
2785
2786 if (status & IS_XA2_F)
2787 skge_tx_intr(hw->dev[1]);
2788
2789 if (status & IS_PA_TO_RX1) {
2790 struct skge_port *skge = netdev_priv(hw->dev[0]);
2791 ++skge->net_stats.rx_over_errors;
2792 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
2793 }
2794
2795 if (status & IS_PA_TO_RX2) {
2796 struct skge_port *skge = netdev_priv(hw->dev[1]);
2797 ++skge->net_stats.rx_over_errors;
2798 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
2799 }
2800
2801 if (status & IS_PA_TO_TX1)
2802 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
2803
2804 if (status & IS_PA_TO_TX2)
2805 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
2806
2807 if (status & IS_MAC1)
2808 skge_mac_intr(hw, 0);
2809
2810 if (status & IS_MAC2)
2811 skge_mac_intr(hw, 1);
2812
2813 if (status & IS_HW_ERR)
2814 skge_error_irq(hw);
2815
2816 if (status & IS_EXT_REG) {
2817 hw->intr_mask &= ~IS_EXT_REG;
2818 tasklet_schedule(&hw->ext_tasklet);
2819 }
2820
2821 skge_write32(hw, B0_IMSK, hw->intr_mask);
2822
2823 return IRQ_HANDLED;
2824 }
2825
2826 #ifdef CONFIG_NET_POLL_CONTROLLER
2827 static void skge_netpoll(struct net_device *dev)
2828 {
2829 struct skge_port *skge = netdev_priv(dev);
2830
2831 disable_irq(dev->irq);
2832 skge_intr(dev->irq, skge->hw, NULL);
2833 enable_irq(dev->irq);
2834 }
2835 #endif
2836
2837 static int skge_set_mac_address(struct net_device *dev, void *p)
2838 {
2839 struct skge_port *skge = netdev_priv(dev);
2840 struct skge_hw *hw = skge->hw;
2841 unsigned port = skge->port;
2842 const struct sockaddr *addr = p;
2843
2844 if (!is_valid_ether_addr(addr->sa_data))
2845 return -EADDRNOTAVAIL;
2846
2847 spin_lock_bh(&hw->phy_lock);
2848 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2849 memcpy_toio(hw->regs + B2_MAC_1 + port*8,
2850 dev->dev_addr, ETH_ALEN);
2851 memcpy_toio(hw->regs + B2_MAC_2 + port*8,
2852 dev->dev_addr, ETH_ALEN);
2853
2854 if (hw->chip_id == CHIP_ID_GENESIS)
2855 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
2856 else {
2857 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
2858 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2859 }
2860 spin_unlock_bh(&hw->phy_lock);
2861
2862 return 0;
2863 }
2864
2865 static const struct {
2866 u8 id;
2867 const char *name;
2868 } skge_chips[] = {
2869 { CHIP_ID_GENESIS, "Genesis" },
2870 { CHIP_ID_YUKON, "Yukon" },
2871 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
2872 { CHIP_ID_YUKON_LP, "Yukon-LP"},
2873 };
2874
2875 static const char *skge_board_name(const struct skge_hw *hw)
2876 {
2877 int i;
2878 static char buf[16];
2879
2880 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
2881 if (skge_chips[i].id == hw->chip_id)
2882 return skge_chips[i].name;
2883
2884 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
2885 return buf;
2886 }
2887
2888
2889 /*
2890 * Setup the board data structure, but don't bring up
2891 * the port(s)
2892 */
2893 static int skge_reset(struct skge_hw *hw)
2894 {
2895 u16 ctst;
2896 u8 t8, mac_cfg, pmd_type, phy_type;
2897 int i;
2898
2899 ctst = skge_read16(hw, B0_CTST);
2900
2901 /* do a SW reset */
2902 skge_write8(hw, B0_CTST, CS_RST_SET);
2903 skge_write8(hw, B0_CTST, CS_RST_CLR);
2904
2905 /* clear PCI errors, if any */
2906 skge_pci_clear(hw);
2907
2908 skge_write8(hw, B0_CTST, CS_MRST_CLR);
2909
2910 /* restore CLK_RUN bits (for Yukon-Lite) */
2911 skge_write16(hw, B0_CTST,
2912 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
2913
2914 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
2915 phy_type = skge_read8(hw, B2_E_1) & 0xf;
2916 pmd_type = skge_read8(hw, B2_PMD_TYP);
2917 hw->copper = (pmd_type == 'T' || pmd_type == '1');
2918
2919 switch (hw->chip_id) {
2920 case CHIP_ID_GENESIS:
2921 switch (phy_type) {
2922 case SK_PHY_BCOM:
2923 hw->phy_addr = PHY_ADDR_BCOM;
2924 break;
2925 default:
2926 printk(KERN_ERR PFX "%s: unsupported phy type 0x%x\n",
2927 pci_name(hw->pdev), phy_type);
2928 return -EOPNOTSUPP;
2929 }
2930 break;
2931
2932 case CHIP_ID_YUKON:
2933 case CHIP_ID_YUKON_LITE:
2934 case CHIP_ID_YUKON_LP:
2935 if (phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
2936 hw->copper = 1;
2937
2938 hw->phy_addr = PHY_ADDR_MARV;
2939 break;
2940
2941 default:
2942 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2943 pci_name(hw->pdev), hw->chip_id);
2944 return -EOPNOTSUPP;
2945 }
2946
2947 mac_cfg = skge_read8(hw, B2_MAC_CFG);
2948 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
2949 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
2950
2951 /* read the adapters RAM size */
2952 t8 = skge_read8(hw, B2_E_0);
2953 if (hw->chip_id == CHIP_ID_GENESIS) {
2954 if (t8 == 3) {
2955 /* special case: 4 x 64k x 36, offset = 0x80000 */
2956 hw->ram_size = 0x100000;
2957 hw->ram_offset = 0x80000;
2958 } else
2959 hw->ram_size = t8 * 512;
2960 }
2961 else if (t8 == 0)
2962 hw->ram_size = 0x20000;
2963 else
2964 hw->ram_size = t8 * 4096;
2965
2966 hw->intr_mask = IS_HW_ERR | IS_EXT_REG;
2967 if (hw->chip_id == CHIP_ID_GENESIS)
2968 genesis_init(hw);
2969 else {
2970 /* switch power to VCC (WA for VAUX problem) */
2971 skge_write8(hw, B0_POWER_CTRL,
2972 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
2973 /* avoid boards with stuck Hardware error bits */
2974 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
2975 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
2976 printk(KERN_WARNING PFX "stuck hardware sensor bit\n");
2977 hw->intr_mask &= ~IS_HW_ERR;
2978 }
2979
2980 for (i = 0; i < hw->ports; i++) {
2981 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2982 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2983 }
2984 }
2985
2986 /* turn off hardware timer (unused) */
2987 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
2988 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2989 skge_write8(hw, B0_LED, LED_STAT_ON);
2990
2991 /* enable the Tx Arbiters */
2992 for (i = 0; i < hw->ports; i++)
2993 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2994
2995 /* Initialize ram interface */
2996 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
2997
2998 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
2999 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3000 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3001 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3002 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3003 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3004 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3005 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3006 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3007 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3008 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3009 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3010
3011 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3012
3013 /* Set interrupt moderation for Transmit only
3014 * Receive interrupts avoided by NAPI
3015 */
3016 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3017 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3018 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3019
3020 skge_write32(hw, B0_IMSK, hw->intr_mask);
3021
3022 spin_lock_bh(&hw->phy_lock);
3023 for (i = 0; i < hw->ports; i++) {
3024 if (hw->chip_id == CHIP_ID_GENESIS)
3025 genesis_reset(hw, i);
3026 else
3027 yukon_reset(hw, i);
3028 }
3029 spin_unlock_bh(&hw->phy_lock);
3030
3031 return 0;
3032 }
3033
3034 /* Initialize network device */
3035 static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3036 int highmem)
3037 {
3038 struct skge_port *skge;
3039 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3040
3041 if (!dev) {
3042 printk(KERN_ERR "skge etherdev alloc failed");
3043 return NULL;
3044 }
3045
3046 SET_MODULE_OWNER(dev);
3047 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3048 dev->open = skge_up;
3049 dev->stop = skge_down;
3050 dev->hard_start_xmit = skge_xmit_frame;
3051 dev->get_stats = skge_get_stats;
3052 if (hw->chip_id == CHIP_ID_GENESIS)
3053 dev->set_multicast_list = genesis_set_multicast;
3054 else
3055 dev->set_multicast_list = yukon_set_multicast;
3056
3057 dev->set_mac_address = skge_set_mac_address;
3058 dev->change_mtu = skge_change_mtu;
3059 SET_ETHTOOL_OPS(dev, &skge_ethtool_ops);
3060 dev->tx_timeout = skge_tx_timeout;
3061 dev->watchdog_timeo = TX_WATCHDOG;
3062 dev->poll = skge_poll;
3063 dev->weight = NAPI_WEIGHT;
3064 #ifdef CONFIG_NET_POLL_CONTROLLER
3065 dev->poll_controller = skge_netpoll;
3066 #endif
3067 dev->irq = hw->pdev->irq;
3068 dev->features = NETIF_F_LLTX;
3069 if (highmem)
3070 dev->features |= NETIF_F_HIGHDMA;
3071
3072 skge = netdev_priv(dev);
3073 skge->netdev = dev;
3074 skge->hw = hw;
3075 skge->msg_enable = netif_msg_init(debug, default_msg);
3076 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3077 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3078
3079 /* Auto speed and flow control */
3080 skge->autoneg = AUTONEG_ENABLE;
3081 skge->flow_control = FLOW_MODE_SYMMETRIC;
3082 skge->duplex = -1;
3083 skge->speed = -1;
3084 skge->advertising = skge_supported_modes(hw);
3085
3086 hw->dev[port] = dev;
3087
3088 skge->port = port;
3089
3090 spin_lock_init(&skge->tx_lock);
3091
3092 if (hw->chip_id != CHIP_ID_GENESIS) {
3093 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3094 skge->rx_csum = 1;
3095 }
3096
3097 /* read the mac address */
3098 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
3099
3100 /* device is off until link detection */
3101 netif_carrier_off(dev);
3102 netif_stop_queue(dev);
3103
3104 return dev;
3105 }
3106
3107 static void __devinit skge_show_addr(struct net_device *dev)
3108 {
3109 const struct skge_port *skge = netdev_priv(dev);
3110
3111 if (netif_msg_probe(skge))
3112 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3113 dev->name,
3114 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3115 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3116 }
3117
3118 static int __devinit skge_probe(struct pci_dev *pdev,
3119 const struct pci_device_id *ent)
3120 {
3121 struct net_device *dev, *dev1;
3122 struct skge_hw *hw;
3123 int err, using_dac = 0;
3124
3125 if ((err = pci_enable_device(pdev))) {
3126 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3127 pci_name(pdev));
3128 goto err_out;
3129 }
3130
3131 if ((err = pci_request_regions(pdev, DRV_NAME))) {
3132 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3133 pci_name(pdev));
3134 goto err_out_disable_pdev;
3135 }
3136
3137 pci_set_master(pdev);
3138
3139 if (!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK)))
3140 using_dac = 1;
3141 else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3142 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3143 pci_name(pdev));
3144 goto err_out_free_regions;
3145 }
3146
3147 #ifdef __BIG_ENDIAN
3148 /* byte swap decriptors in hardware */
3149 {
3150 u32 reg;
3151
3152 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3153 reg |= PCI_REV_DESC;
3154 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3155 }
3156 #endif
3157
3158 err = -ENOMEM;
3159 hw = kmalloc(sizeof(*hw), GFP_KERNEL);
3160 if (!hw) {
3161 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3162 pci_name(pdev));
3163 goto err_out_free_regions;
3164 }
3165
3166 memset(hw, 0, sizeof(*hw));
3167 hw->pdev = pdev;
3168 spin_lock_init(&hw->phy_lock);
3169 tasklet_init(&hw->ext_tasklet, skge_extirq, (unsigned long) hw);
3170
3171 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3172 if (!hw->regs) {
3173 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3174 pci_name(pdev));
3175 goto err_out_free_hw;
3176 }
3177
3178 if ((err = request_irq(pdev->irq, skge_intr, SA_SHIRQ, DRV_NAME, hw))) {
3179 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3180 pci_name(pdev), pdev->irq);
3181 goto err_out_iounmap;
3182 }
3183 pci_set_drvdata(pdev, hw);
3184
3185 err = skge_reset(hw);
3186 if (err)
3187 goto err_out_free_irq;
3188
3189 printk(KERN_INFO PFX "addr 0x%lx irq %d chip %s rev %d\n",
3190 pci_resource_start(pdev, 0), pdev->irq,
3191 skge_board_name(hw), hw->chip_rev);
3192
3193 if ((dev = skge_devinit(hw, 0, using_dac)) == NULL)
3194 goto err_out_led_off;
3195
3196 if ((err = register_netdev(dev))) {
3197 printk(KERN_ERR PFX "%s: cannot register net device\n",
3198 pci_name(pdev));
3199 goto err_out_free_netdev;
3200 }
3201
3202 skge_show_addr(dev);
3203
3204 if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
3205 if (register_netdev(dev1) == 0)
3206 skge_show_addr(dev1);
3207 else {
3208 /* Failure to register second port need not be fatal */
3209 printk(KERN_WARNING PFX "register of second port failed\n");
3210 hw->dev[1] = NULL;
3211 free_netdev(dev1);
3212 }
3213 }
3214
3215 return 0;
3216
3217 err_out_free_netdev:
3218 free_netdev(dev);
3219 err_out_led_off:
3220 skge_write16(hw, B0_LED, LED_STAT_OFF);
3221 err_out_free_irq:
3222 free_irq(pdev->irq, hw);
3223 err_out_iounmap:
3224 iounmap(hw->regs);
3225 err_out_free_hw:
3226 kfree(hw);
3227 err_out_free_regions:
3228 pci_release_regions(pdev);
3229 err_out_disable_pdev:
3230 pci_disable_device(pdev);
3231 pci_set_drvdata(pdev, NULL);
3232 err_out:
3233 return err;
3234 }
3235
3236 static void __devexit skge_remove(struct pci_dev *pdev)
3237 {
3238 struct skge_hw *hw = pci_get_drvdata(pdev);
3239 struct net_device *dev0, *dev1;
3240
3241 if (!hw)
3242 return;
3243
3244 if ((dev1 = hw->dev[1]))
3245 unregister_netdev(dev1);
3246 dev0 = hw->dev[0];
3247 unregister_netdev(dev0);
3248
3249 skge_write32(hw, B0_IMSK, 0);
3250 skge_write16(hw, B0_LED, LED_STAT_OFF);
3251 skge_pci_clear(hw);
3252 skge_write8(hw, B0_CTST, CS_RST_SET);
3253
3254 tasklet_kill(&hw->ext_tasklet);
3255
3256 free_irq(pdev->irq, hw);
3257 pci_release_regions(pdev);
3258 pci_disable_device(pdev);
3259 if (dev1)
3260 free_netdev(dev1);
3261 free_netdev(dev0);
3262
3263 iounmap(hw->regs);
3264 kfree(hw);
3265 pci_set_drvdata(pdev, NULL);
3266 }
3267
3268 #ifdef CONFIG_PM
3269 static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
3270 {
3271 struct skge_hw *hw = pci_get_drvdata(pdev);
3272 int i, wol = 0;
3273
3274 for (i = 0; i < 2; i++) {
3275 struct net_device *dev = hw->dev[i];
3276
3277 if (dev) {
3278 struct skge_port *skge = netdev_priv(dev);
3279 if (netif_running(dev)) {
3280 netif_carrier_off(dev);
3281 if (skge->wol)
3282 netif_stop_queue(dev);
3283 else
3284 skge_down(dev);
3285 }
3286 netif_device_detach(dev);
3287 wol |= skge->wol;
3288 }
3289 }
3290
3291 pci_save_state(pdev);
3292 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
3293 pci_disable_device(pdev);
3294 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3295
3296 return 0;
3297 }
3298
3299 static int skge_resume(struct pci_dev *pdev)
3300 {
3301 struct skge_hw *hw = pci_get_drvdata(pdev);
3302 int i;
3303
3304 pci_set_power_state(pdev, PCI_D0);
3305 pci_restore_state(pdev);
3306 pci_enable_wake(pdev, PCI_D0, 0);
3307
3308 skge_reset(hw);
3309
3310 for (i = 0; i < 2; i++) {
3311 struct net_device *dev = hw->dev[i];
3312 if (dev) {
3313 netif_device_attach(dev);
3314 if (netif_running(dev))
3315 skge_up(dev);
3316 }
3317 }
3318 return 0;
3319 }
3320 #endif
3321
3322 static struct pci_driver skge_driver = {
3323 .name = DRV_NAME,
3324 .id_table = skge_id_table,
3325 .probe = skge_probe,
3326 .remove = __devexit_p(skge_remove),
3327 #ifdef CONFIG_PM
3328 .suspend = skge_suspend,
3329 .resume = skge_resume,
3330 #endif
3331 };
3332
3333 static int __init skge_init_module(void)
3334 {
3335 return pci_module_init(&skge_driver);
3336 }
3337
3338 static void __exit skge_cleanup_module(void)
3339 {
3340 pci_unregister_driver(&skge_driver);
3341 }
3342
3343 module_init(skge_init_module);
3344 module_exit(skge_cleanup_module);
Linux 2.6 libata-dev (mirror)