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ppc64: Minor compilation fixes
[linux-2.6/libata-dev.git] / drivers / net / bnx2.c
blob3a2ace01e444d082daaa31dc30de97c542d19054
1 /* bnx2.c: Broadcom NX2 network driver.
2 *
3 * Copyright (c) 2004, 2005 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Written by: Michael Chan (mchan@broadcom.com)
10 */
11
12 #include "bnx2.h"
13 #include "bnx2_fw.h"
14
15 #define DRV_MODULE_NAME "bnx2"
16 #define PFX DRV_MODULE_NAME ": "
17 #define DRV_MODULE_VERSION "1.2.21"
18 #define DRV_MODULE_RELDATE "September 7, 2005"
19
20 #define RUN_AT(x) (jiffies + (x))
21
22 /* Time in jiffies before concluding the transmitter is hung. */
23 #define TX_TIMEOUT (5*HZ)
24
25 static char version[] __devinitdata =
26 "Broadcom NetXtreme II Gigabit Ethernet Driver " DRV_MODULE_NAME " v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
27
28 MODULE_AUTHOR("Michael Chan <mchan@broadcom.com>");
29 MODULE_DESCRIPTION("Broadcom NetXtreme II BCM5706 Driver");
30 MODULE_LICENSE("GPL");
31 MODULE_VERSION(DRV_MODULE_VERSION);
32
33 static int disable_msi = 0;
34
35 module_param(disable_msi, int, 0);
36 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
37
38 typedef enum {
39 BCM5706 = 0,
40 NC370T,
41 NC370I,
42 BCM5706S,
43 NC370F,
44 } board_t;
45
46 /* indexed by board_t, above */
47 static struct {
48 char *name;
49 } board_info[] __devinitdata = {
50 { "Broadcom NetXtreme II BCM5706 1000Base-T" },
51 { "HP NC370T Multifunction Gigabit Server Adapter" },
52 { "HP NC370i Multifunction Gigabit Server Adapter" },
53 { "Broadcom NetXtreme II BCM5706 1000Base-SX" },
54 { "HP NC370F Multifunction Gigabit Server Adapter" },
55 };
56
57 static struct pci_device_id bnx2_pci_tbl[] = {
58 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
59 PCI_VENDOR_ID_HP, 0x3101, 0, 0, NC370T },
60 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
61 PCI_VENDOR_ID_HP, 0x3106, 0, 0, NC370I },
62 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706,
63 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706 },
64 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
65 PCI_VENDOR_ID_HP, 0x3102, 0, 0, NC370F },
66 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_NX2_5706S,
67 PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5706S },
68 { 0, }
69 };
70
71 static struct flash_spec flash_table[] =
72 {
73 /* Slow EEPROM */
74 {0x00000000, 0x40030380, 0x009f0081, 0xa184a053, 0xaf000400,
75 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
76 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
77 "EEPROM - slow"},
78 /* Fast EEPROM */
79 {0x02000000, 0x62008380, 0x009f0081, 0xa184a053, 0xaf000400,
80 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
81 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
82 "EEPROM - fast"},
83 /* ATMEL AT45DB011B (buffered flash) */
84 {0x02000003, 0x6e008173, 0x00570081, 0x68848353, 0xaf000400,
85 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
86 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
87 "Buffered flash"},
88 /* Saifun SA25F005 (non-buffered flash) */
89 /* strap, cfg1, & write1 need updates */
90 {0x01000003, 0x5f008081, 0x00050081, 0x03840253, 0xaf020406,
91 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
92 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
93 "Non-buffered flash (64kB)"},
94 /* Saifun SA25F010 (non-buffered flash) */
95 /* strap, cfg1, & write1 need updates */
96 {0x00000001, 0x47008081, 0x00050081, 0x03840253, 0xaf020406,
97 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
98 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
99 "Non-buffered flash (128kB)"},
100 /* Saifun SA25F020 (non-buffered flash) */
101 /* strap, cfg1, & write1 need updates */
102 {0x00000003, 0x4f008081, 0x00050081, 0x03840253, 0xaf020406,
103 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
104 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
105 "Non-buffered flash (256kB)"},
106 };
107
108 MODULE_DEVICE_TABLE(pci, bnx2_pci_tbl);
109
110 static inline u32 bnx2_tx_avail(struct bnx2 *bp)
111 {
112 u32 diff = TX_RING_IDX(bp->tx_prod) - TX_RING_IDX(bp->tx_cons);
113
114 if (diff > MAX_TX_DESC_CNT)
115 diff = (diff & MAX_TX_DESC_CNT) - 1;
116 return (bp->tx_ring_size - diff);
117 }
118
119 static u32
120 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset)
121 {
122 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
123 return (REG_RD(bp, BNX2_PCICFG_REG_WINDOW));
124 }
125
126 static void
127 bnx2_reg_wr_ind(struct bnx2 *bp, u32 offset, u32 val)
128 {
129 REG_WR(bp, BNX2_PCICFG_REG_WINDOW_ADDRESS, offset);
130 REG_WR(bp, BNX2_PCICFG_REG_WINDOW, val);
131 }
132
133 static void
134 bnx2_ctx_wr(struct bnx2 *bp, u32 cid_addr, u32 offset, u32 val)
135 {
136 offset += cid_addr;
137 REG_WR(bp, BNX2_CTX_DATA_ADR, offset);
138 REG_WR(bp, BNX2_CTX_DATA, val);
139 }
140
141 static int
142 bnx2_read_phy(struct bnx2 *bp, u32 reg, u32 *val)
143 {
144 u32 val1;
145 int i, ret;
146
147 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
148 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
149 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
150
151 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
152 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
153
154 udelay(40);
155 }
156
157 val1 = (bp->phy_addr << 21) | (reg << 16) |
158 BNX2_EMAC_MDIO_COMM_COMMAND_READ | BNX2_EMAC_MDIO_COMM_DISEXT |
159 BNX2_EMAC_MDIO_COMM_START_BUSY;
160 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
161
162 for (i = 0; i < 50; i++) {
163 udelay(10);
164
165 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
166 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
167 udelay(5);
168
169 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
170 val1 &= BNX2_EMAC_MDIO_COMM_DATA;
171
172 break;
173 }
174 }
175
176 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY) {
177 *val = 0x0;
178 ret = -EBUSY;
179 }
180 else {
181 *val = val1;
182 ret = 0;
183 }
184
185 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
186 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
187 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
188
189 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
190 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
191
192 udelay(40);
193 }
194
195 return ret;
196 }
197
198 static int
199 bnx2_write_phy(struct bnx2 *bp, u32 reg, u32 val)
200 {
201 u32 val1;
202 int i, ret;
203
204 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
205 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
206 val1 &= ~BNX2_EMAC_MDIO_MODE_AUTO_POLL;
207
208 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
209 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
210
211 udelay(40);
212 }
213
214 val1 = (bp->phy_addr << 21) | (reg << 16) | val |
215 BNX2_EMAC_MDIO_COMM_COMMAND_WRITE |
216 BNX2_EMAC_MDIO_COMM_START_BUSY | BNX2_EMAC_MDIO_COMM_DISEXT;
217 REG_WR(bp, BNX2_EMAC_MDIO_COMM, val1);
218
219 for (i = 0; i < 50; i++) {
220 udelay(10);
221
222 val1 = REG_RD(bp, BNX2_EMAC_MDIO_COMM);
223 if (!(val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)) {
224 udelay(5);
225 break;
226 }
227 }
228
229 if (val1 & BNX2_EMAC_MDIO_COMM_START_BUSY)
230 ret = -EBUSY;
231 else
232 ret = 0;
233
234 if (bp->phy_flags & PHY_INT_MODE_AUTO_POLLING_FLAG) {
235 val1 = REG_RD(bp, BNX2_EMAC_MDIO_MODE);
236 val1 |= BNX2_EMAC_MDIO_MODE_AUTO_POLL;
237
238 REG_WR(bp, BNX2_EMAC_MDIO_MODE, val1);
239 REG_RD(bp, BNX2_EMAC_MDIO_MODE);
240
241 udelay(40);
242 }
243
244 return ret;
245 }
246
247 static void
248 bnx2_disable_int(struct bnx2 *bp)
249 {
250 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
251 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
252 REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD);
253 }
254
255 static void
256 bnx2_enable_int(struct bnx2 *bp)
257 {
258 u32 val;
259
260 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
261 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | bp->last_status_idx);
262
263 val = REG_RD(bp, BNX2_HC_COMMAND);
264 REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW);
265 }
266
267 static void
268 bnx2_disable_int_sync(struct bnx2 *bp)
269 {
270 atomic_inc(&bp->intr_sem);
271 bnx2_disable_int(bp);
272 synchronize_irq(bp->pdev->irq);
273 }
274
275 static void
276 bnx2_netif_stop(struct bnx2 *bp)
277 {
278 bnx2_disable_int_sync(bp);
279 if (netif_running(bp->dev)) {
280 netif_poll_disable(bp->dev);
281 netif_tx_disable(bp->dev);
282 bp->dev->trans_start = jiffies; /* prevent tx timeout */
283 }
284 }
285
286 static void
287 bnx2_netif_start(struct bnx2 *bp)
288 {
289 if (atomic_dec_and_test(&bp->intr_sem)) {
290 if (netif_running(bp->dev)) {
291 netif_wake_queue(bp->dev);
292 netif_poll_enable(bp->dev);
293 bnx2_enable_int(bp);
294 }
295 }
296 }
297
298 static void
299 bnx2_free_mem(struct bnx2 *bp)
300 {
301 if (bp->stats_blk) {
302 pci_free_consistent(bp->pdev, sizeof(struct statistics_block),
303 bp->stats_blk, bp->stats_blk_mapping);
304 bp->stats_blk = NULL;
305 }
306 if (bp->status_blk) {
307 pci_free_consistent(bp->pdev, sizeof(struct status_block),
308 bp->status_blk, bp->status_blk_mapping);
309 bp->status_blk = NULL;
310 }
311 if (bp->tx_desc_ring) {
312 pci_free_consistent(bp->pdev,
313 sizeof(struct tx_bd) * TX_DESC_CNT,
314 bp->tx_desc_ring, bp->tx_desc_mapping);
315 bp->tx_desc_ring = NULL;
316 }
317 if (bp->tx_buf_ring) {
318 kfree(bp->tx_buf_ring);
319 bp->tx_buf_ring = NULL;
320 }
321 if (bp->rx_desc_ring) {
322 pci_free_consistent(bp->pdev,
323 sizeof(struct rx_bd) * RX_DESC_CNT,
324 bp->rx_desc_ring, bp->rx_desc_mapping);
325 bp->rx_desc_ring = NULL;
326 }
327 if (bp->rx_buf_ring) {
328 kfree(bp->rx_buf_ring);
329 bp->rx_buf_ring = NULL;
330 }
331 }
332
333 static int
334 bnx2_alloc_mem(struct bnx2 *bp)
335 {
336 bp->tx_buf_ring = kmalloc(sizeof(struct sw_bd) * TX_DESC_CNT,
337 GFP_KERNEL);
338 if (bp->tx_buf_ring == NULL)
339 return -ENOMEM;
340
341 memset(bp->tx_buf_ring, 0, sizeof(struct sw_bd) * TX_DESC_CNT);
342 bp->tx_desc_ring = pci_alloc_consistent(bp->pdev,
343 sizeof(struct tx_bd) *
344 TX_DESC_CNT,
345 &bp->tx_desc_mapping);
346 if (bp->tx_desc_ring == NULL)
347 goto alloc_mem_err;
348
349 bp->rx_buf_ring = kmalloc(sizeof(struct sw_bd) * RX_DESC_CNT,
350 GFP_KERNEL);
351 if (bp->rx_buf_ring == NULL)
352 goto alloc_mem_err;
353
354 memset(bp->rx_buf_ring, 0, sizeof(struct sw_bd) * RX_DESC_CNT);
355 bp->rx_desc_ring = pci_alloc_consistent(bp->pdev,
356 sizeof(struct rx_bd) *
357 RX_DESC_CNT,
358 &bp->rx_desc_mapping);
359 if (bp->rx_desc_ring == NULL)
360 goto alloc_mem_err;
361
362 bp->status_blk = pci_alloc_consistent(bp->pdev,
363 sizeof(struct status_block),
364 &bp->status_blk_mapping);
365 if (bp->status_blk == NULL)
366 goto alloc_mem_err;
367
368 memset(bp->status_blk, 0, sizeof(struct status_block));
369
370 bp->stats_blk = pci_alloc_consistent(bp->pdev,
371 sizeof(struct statistics_block),
372 &bp->stats_blk_mapping);
373 if (bp->stats_blk == NULL)
374 goto alloc_mem_err;
375
376 memset(bp->stats_blk, 0, sizeof(struct statistics_block));
377
378 return 0;
379
380 alloc_mem_err:
381 bnx2_free_mem(bp);
382 return -ENOMEM;
383 }
384
385 static void
386 bnx2_report_link(struct bnx2 *bp)
387 {
388 if (bp->link_up) {
389 netif_carrier_on(bp->dev);
390 printk(KERN_INFO PFX "%s NIC Link is Up, ", bp->dev->name);
391
392 printk("%d Mbps ", bp->line_speed);
393
394 if (bp->duplex == DUPLEX_FULL)
395 printk("full duplex");
396 else
397 printk("half duplex");
398
399 if (bp->flow_ctrl) {
400 if (bp->flow_ctrl & FLOW_CTRL_RX) {
401 printk(", receive ");
402 if (bp->flow_ctrl & FLOW_CTRL_TX)
403 printk("& transmit ");
404 }
405 else {
406 printk(", transmit ");
407 }
408 printk("flow control ON");
409 }
410 printk("\n");
411 }
412 else {
413 netif_carrier_off(bp->dev);
414 printk(KERN_ERR PFX "%s NIC Link is Down\n", bp->dev->name);
415 }
416 }
417
418 static void
419 bnx2_resolve_flow_ctrl(struct bnx2 *bp)
420 {
421 u32 local_adv, remote_adv;
422
423 bp->flow_ctrl = 0;
424 if ((bp->autoneg & (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) !=
425 (AUTONEG_SPEED | AUTONEG_FLOW_CTRL)) {
426
427 if (bp->duplex == DUPLEX_FULL) {
428 bp->flow_ctrl = bp->req_flow_ctrl;
429 }
430 return;
431 }
432
433 if (bp->duplex != DUPLEX_FULL) {
434 return;
435 }
436
437 bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
438 bnx2_read_phy(bp, MII_LPA, &remote_adv);
439
440 if (bp->phy_flags & PHY_SERDES_FLAG) {
441 u32 new_local_adv = 0;
442 u32 new_remote_adv = 0;
443
444 if (local_adv & ADVERTISE_1000XPAUSE)
445 new_local_adv |= ADVERTISE_PAUSE_CAP;
446 if (local_adv & ADVERTISE_1000XPSE_ASYM)
447 new_local_adv |= ADVERTISE_PAUSE_ASYM;
448 if (remote_adv & ADVERTISE_1000XPAUSE)
449 new_remote_adv |= ADVERTISE_PAUSE_CAP;
450 if (remote_adv & ADVERTISE_1000XPSE_ASYM)
451 new_remote_adv |= ADVERTISE_PAUSE_ASYM;
452
453 local_adv = new_local_adv;
454 remote_adv = new_remote_adv;
455 }
456
457 /* See Table 28B-3 of 802.3ab-1999 spec. */
458 if (local_adv & ADVERTISE_PAUSE_CAP) {
459 if(local_adv & ADVERTISE_PAUSE_ASYM) {
460 if (remote_adv & ADVERTISE_PAUSE_CAP) {
461 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
462 }
463 else if (remote_adv & ADVERTISE_PAUSE_ASYM) {
464 bp->flow_ctrl = FLOW_CTRL_RX;
465 }
466 }
467 else {
468 if (remote_adv & ADVERTISE_PAUSE_CAP) {
469 bp->flow_ctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
470 }
471 }
472 }
473 else if (local_adv & ADVERTISE_PAUSE_ASYM) {
474 if ((remote_adv & ADVERTISE_PAUSE_CAP) &&
475 (remote_adv & ADVERTISE_PAUSE_ASYM)) {
476
477 bp->flow_ctrl = FLOW_CTRL_TX;
478 }
479 }
480 }
481
482 static int
483 bnx2_serdes_linkup(struct bnx2 *bp)
484 {
485 u32 bmcr, local_adv, remote_adv, common;
486
487 bp->link_up = 1;
488 bp->line_speed = SPEED_1000;
489
490 bnx2_read_phy(bp, MII_BMCR, &bmcr);
491 if (bmcr & BMCR_FULLDPLX) {
492 bp->duplex = DUPLEX_FULL;
493 }
494 else {
495 bp->duplex = DUPLEX_HALF;
496 }
497
498 if (!(bmcr & BMCR_ANENABLE)) {
499 return 0;
500 }
501
502 bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
503 bnx2_read_phy(bp, MII_LPA, &remote_adv);
504
505 common = local_adv & remote_adv;
506 if (common & (ADVERTISE_1000XHALF | ADVERTISE_1000XFULL)) {
507
508 if (common & ADVERTISE_1000XFULL) {
509 bp->duplex = DUPLEX_FULL;
510 }
511 else {
512 bp->duplex = DUPLEX_HALF;
513 }
514 }
515
516 return 0;
517 }
518
519 static int
520 bnx2_copper_linkup(struct bnx2 *bp)
521 {
522 u32 bmcr;
523
524 bnx2_read_phy(bp, MII_BMCR, &bmcr);
525 if (bmcr & BMCR_ANENABLE) {
526 u32 local_adv, remote_adv, common;
527
528 bnx2_read_phy(bp, MII_CTRL1000, &local_adv);
529 bnx2_read_phy(bp, MII_STAT1000, &remote_adv);
530
531 common = local_adv & (remote_adv >> 2);
532 if (common & ADVERTISE_1000FULL) {
533 bp->line_speed = SPEED_1000;
534 bp->duplex = DUPLEX_FULL;
535 }
536 else if (common & ADVERTISE_1000HALF) {
537 bp->line_speed = SPEED_1000;
538 bp->duplex = DUPLEX_HALF;
539 }
540 else {
541 bnx2_read_phy(bp, MII_ADVERTISE, &local_adv);
542 bnx2_read_phy(bp, MII_LPA, &remote_adv);
543
544 common = local_adv & remote_adv;
545 if (common & ADVERTISE_100FULL) {
546 bp->line_speed = SPEED_100;
547 bp->duplex = DUPLEX_FULL;
548 }
549 else if (common & ADVERTISE_100HALF) {
550 bp->line_speed = SPEED_100;
551 bp->duplex = DUPLEX_HALF;
552 }
553 else if (common & ADVERTISE_10FULL) {
554 bp->line_speed = SPEED_10;
555 bp->duplex = DUPLEX_FULL;
556 }
557 else if (common & ADVERTISE_10HALF) {
558 bp->line_speed = SPEED_10;
559 bp->duplex = DUPLEX_HALF;
560 }
561 else {
562 bp->line_speed = 0;
563 bp->link_up = 0;
564 }
565 }
566 }
567 else {
568 if (bmcr & BMCR_SPEED100) {
569 bp->line_speed = SPEED_100;
570 }
571 else {
572 bp->line_speed = SPEED_10;
573 }
574 if (bmcr & BMCR_FULLDPLX) {
575 bp->duplex = DUPLEX_FULL;
576 }
577 else {
578 bp->duplex = DUPLEX_HALF;
579 }
580 }
581
582 return 0;
583 }
584
585 static int
586 bnx2_set_mac_link(struct bnx2 *bp)
587 {
588 u32 val;
589
590 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x2620);
591 if (bp->link_up && (bp->line_speed == SPEED_1000) &&
592 (bp->duplex == DUPLEX_HALF)) {
593 REG_WR(bp, BNX2_EMAC_TX_LENGTHS, 0x26ff);
594 }
595
596 /* Configure the EMAC mode register. */
597 val = REG_RD(bp, BNX2_EMAC_MODE);
598
599 val &= ~(BNX2_EMAC_MODE_PORT | BNX2_EMAC_MODE_HALF_DUPLEX |
600 BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK);
601
602 if (bp->link_up) {
603 if (bp->line_speed != SPEED_1000)
604 val |= BNX2_EMAC_MODE_PORT_MII;
605 else
606 val |= BNX2_EMAC_MODE_PORT_GMII;
607 }
608 else {
609 val |= BNX2_EMAC_MODE_PORT_GMII;
610 }
611
612 /* Set the MAC to operate in the appropriate duplex mode. */
613 if (bp->duplex == DUPLEX_HALF)
614 val |= BNX2_EMAC_MODE_HALF_DUPLEX;
615 REG_WR(bp, BNX2_EMAC_MODE, val);
616
617 /* Enable/disable rx PAUSE. */
618 bp->rx_mode &= ~BNX2_EMAC_RX_MODE_FLOW_EN;
619
620 if (bp->flow_ctrl & FLOW_CTRL_RX)
621 bp->rx_mode |= BNX2_EMAC_RX_MODE_FLOW_EN;
622 REG_WR(bp, BNX2_EMAC_RX_MODE, bp->rx_mode);
623
624 /* Enable/disable tx PAUSE. */
625 val = REG_RD(bp, BNX2_EMAC_TX_MODE);
626 val &= ~BNX2_EMAC_TX_MODE_FLOW_EN;
627
628 if (bp->flow_ctrl & FLOW_CTRL_TX)
629 val |= BNX2_EMAC_TX_MODE_FLOW_EN;
630 REG_WR(bp, BNX2_EMAC_TX_MODE, val);
631
632 /* Acknowledge the interrupt. */
633 REG_WR(bp, BNX2_EMAC_STATUS, BNX2_EMAC_STATUS_LINK_CHANGE);
634
635 return 0;
636 }
637
638 static int
639 bnx2_set_link(struct bnx2 *bp)
640 {
641 u32 bmsr;
642 u8 link_up;
643
644 if (bp->loopback == MAC_LOOPBACK) {
645 bp->link_up = 1;
646 return 0;
647 }
648
649 link_up = bp->link_up;
650
651 bnx2_read_phy(bp, MII_BMSR, &bmsr);
652 bnx2_read_phy(bp, MII_BMSR, &bmsr);
653
654 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
655 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
656 u32 val;
657
658 val = REG_RD(bp, BNX2_EMAC_STATUS);
659 if (val & BNX2_EMAC_STATUS_LINK)
660 bmsr |= BMSR_LSTATUS;
661 else
662 bmsr &= ~BMSR_LSTATUS;
663 }
664
665 if (bmsr & BMSR_LSTATUS) {
666 bp->link_up = 1;
667
668 if (bp->phy_flags & PHY_SERDES_FLAG) {
669 bnx2_serdes_linkup(bp);
670 }
671 else {
672 bnx2_copper_linkup(bp);
673 }
674 bnx2_resolve_flow_ctrl(bp);
675 }
676 else {
677 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
678 (bp->autoneg & AUTONEG_SPEED)) {
679
680 u32 bmcr;
681
682 bnx2_read_phy(bp, MII_BMCR, &bmcr);
683 if (!(bmcr & BMCR_ANENABLE)) {
684 bnx2_write_phy(bp, MII_BMCR, bmcr |
685 BMCR_ANENABLE);
686 }
687 }
688 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
689 bp->link_up = 0;
690 }
691
692 if (bp->link_up != link_up) {
693 bnx2_report_link(bp);
694 }
695
696 bnx2_set_mac_link(bp);
697
698 return 0;
699 }
700
701 static int
702 bnx2_reset_phy(struct bnx2 *bp)
703 {
704 int i;
705 u32 reg;
706
707 bnx2_write_phy(bp, MII_BMCR, BMCR_RESET);
708
709 #define PHY_RESET_MAX_WAIT 100
710 for (i = 0; i < PHY_RESET_MAX_WAIT; i++) {
711 udelay(10);
712
713 bnx2_read_phy(bp, MII_BMCR, &reg);
714 if (!(reg & BMCR_RESET)) {
715 udelay(20);
716 break;
717 }
718 }
719 if (i == PHY_RESET_MAX_WAIT) {
720 return -EBUSY;
721 }
722 return 0;
723 }
724
725 static u32
726 bnx2_phy_get_pause_adv(struct bnx2 *bp)
727 {
728 u32 adv = 0;
729
730 if ((bp->req_flow_ctrl & (FLOW_CTRL_RX | FLOW_CTRL_TX)) ==
731 (FLOW_CTRL_RX | FLOW_CTRL_TX)) {
732
733 if (bp->phy_flags & PHY_SERDES_FLAG) {
734 adv = ADVERTISE_1000XPAUSE;
735 }
736 else {
737 adv = ADVERTISE_PAUSE_CAP;
738 }
739 }
740 else if (bp->req_flow_ctrl & FLOW_CTRL_TX) {
741 if (bp->phy_flags & PHY_SERDES_FLAG) {
742 adv = ADVERTISE_1000XPSE_ASYM;
743 }
744 else {
745 adv = ADVERTISE_PAUSE_ASYM;
746 }
747 }
748 else if (bp->req_flow_ctrl & FLOW_CTRL_RX) {
749 if (bp->phy_flags & PHY_SERDES_FLAG) {
750 adv = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
751 }
752 else {
753 adv = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
754 }
755 }
756 return adv;
757 }
758
759 static int
760 bnx2_setup_serdes_phy(struct bnx2 *bp)
761 {
762 u32 adv, bmcr;
763 u32 new_adv = 0;
764
765 if (!(bp->autoneg & AUTONEG_SPEED)) {
766 u32 new_bmcr;
767
768 bnx2_read_phy(bp, MII_BMCR, &bmcr);
769 new_bmcr = bmcr & ~BMCR_ANENABLE;
770 new_bmcr |= BMCR_SPEED1000;
771 if (bp->req_duplex == DUPLEX_FULL) {
772 new_bmcr |= BMCR_FULLDPLX;
773 }
774 else {
775 new_bmcr &= ~BMCR_FULLDPLX;
776 }
777 if (new_bmcr != bmcr) {
778 /* Force a link down visible on the other side */
779 if (bp->link_up) {
780 bnx2_read_phy(bp, MII_ADVERTISE, &adv);
781 adv &= ~(ADVERTISE_1000XFULL |
782 ADVERTISE_1000XHALF);
783 bnx2_write_phy(bp, MII_ADVERTISE, adv);
784 bnx2_write_phy(bp, MII_BMCR, bmcr |
785 BMCR_ANRESTART | BMCR_ANENABLE);
786
787 bp->link_up = 0;
788 netif_carrier_off(bp->dev);
789 }
790 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
791 }
792 return 0;
793 }
794
795 if (bp->advertising & ADVERTISED_1000baseT_Full)
796 new_adv |= ADVERTISE_1000XFULL;
797
798 new_adv |= bnx2_phy_get_pause_adv(bp);
799
800 bnx2_read_phy(bp, MII_ADVERTISE, &adv);
801 bnx2_read_phy(bp, MII_BMCR, &bmcr);
802
803 bp->serdes_an_pending = 0;
804 if ((adv != new_adv) || ((bmcr & BMCR_ANENABLE) == 0)) {
805 /* Force a link down visible on the other side */
806 if (bp->link_up) {
807 int i;
808
809 bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
810 for (i = 0; i < 110; i++) {
811 udelay(100);
812 }
813 }
814
815 bnx2_write_phy(bp, MII_ADVERTISE, new_adv);
816 bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART |
817 BMCR_ANENABLE);
818 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
819 /* Speed up link-up time when the link partner
820 * does not autonegotiate which is very common
821 * in blade servers. Some blade servers use
822 * IPMI for kerboard input and it's important
823 * to minimize link disruptions. Autoneg. involves
824 * exchanging base pages plus 3 next pages and
825 * normally completes in about 120 msec.
826 */
827 bp->current_interval = SERDES_AN_TIMEOUT;
828 bp->serdes_an_pending = 1;
829 mod_timer(&bp->timer, jiffies + bp->current_interval);
830 }
831 }
832
833 return 0;
834 }
835
836 #define ETHTOOL_ALL_FIBRE_SPEED \
837 (ADVERTISED_1000baseT_Full)
838
839 #define ETHTOOL_ALL_COPPER_SPEED \
840 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | \
841 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | \
842 ADVERTISED_1000baseT_Full)
843
844 #define PHY_ALL_10_100_SPEED (ADVERTISE_10HALF | ADVERTISE_10FULL | \
845 ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_CSMA)
846
847 #define PHY_ALL_1000_SPEED (ADVERTISE_1000HALF | ADVERTISE_1000FULL)
848
849 static int
850 bnx2_setup_copper_phy(struct bnx2 *bp)
851 {
852 u32 bmcr;
853 u32 new_bmcr;
854
855 bnx2_read_phy(bp, MII_BMCR, &bmcr);
856
857 if (bp->autoneg & AUTONEG_SPEED) {
858 u32 adv_reg, adv1000_reg;
859 u32 new_adv_reg = 0;
860 u32 new_adv1000_reg = 0;
861
862 bnx2_read_phy(bp, MII_ADVERTISE, &adv_reg);
863 adv_reg &= (PHY_ALL_10_100_SPEED | ADVERTISE_PAUSE_CAP |
864 ADVERTISE_PAUSE_ASYM);
865
866 bnx2_read_phy(bp, MII_CTRL1000, &adv1000_reg);
867 adv1000_reg &= PHY_ALL_1000_SPEED;
868
869 if (bp->advertising & ADVERTISED_10baseT_Half)
870 new_adv_reg |= ADVERTISE_10HALF;
871 if (bp->advertising & ADVERTISED_10baseT_Full)
872 new_adv_reg |= ADVERTISE_10FULL;
873 if (bp->advertising & ADVERTISED_100baseT_Half)
874 new_adv_reg |= ADVERTISE_100HALF;
875 if (bp->advertising & ADVERTISED_100baseT_Full)
876 new_adv_reg |= ADVERTISE_100FULL;
877 if (bp->advertising & ADVERTISED_1000baseT_Full)
878 new_adv1000_reg |= ADVERTISE_1000FULL;
879
880 new_adv_reg |= ADVERTISE_CSMA;
881
882 new_adv_reg |= bnx2_phy_get_pause_adv(bp);
883
884 if ((adv1000_reg != new_adv1000_reg) ||
885 (adv_reg != new_adv_reg) ||
886 ((bmcr & BMCR_ANENABLE) == 0)) {
887
888 bnx2_write_phy(bp, MII_ADVERTISE, new_adv_reg);
889 bnx2_write_phy(bp, MII_CTRL1000, new_adv1000_reg);
890 bnx2_write_phy(bp, MII_BMCR, BMCR_ANRESTART |
891 BMCR_ANENABLE);
892 }
893 else if (bp->link_up) {
894 /* Flow ctrl may have changed from auto to forced */
895 /* or vice-versa. */
896
897 bnx2_resolve_flow_ctrl(bp);
898 bnx2_set_mac_link(bp);
899 }
900 return 0;
901 }
902
903 new_bmcr = 0;
904 if (bp->req_line_speed == SPEED_100) {
905 new_bmcr |= BMCR_SPEED100;
906 }
907 if (bp->req_duplex == DUPLEX_FULL) {
908 new_bmcr |= BMCR_FULLDPLX;
909 }
910 if (new_bmcr != bmcr) {
911 u32 bmsr;
912 int i = 0;
913
914 bnx2_read_phy(bp, MII_BMSR, &bmsr);
915 bnx2_read_phy(bp, MII_BMSR, &bmsr);
916
917 if (bmsr & BMSR_LSTATUS) {
918 /* Force link down */
919 bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
920 do {
921 udelay(100);
922 bnx2_read_phy(bp, MII_BMSR, &bmsr);
923 bnx2_read_phy(bp, MII_BMSR, &bmsr);
924 i++;
925 } while ((bmsr & BMSR_LSTATUS) && (i < 620));
926 }
927
928 bnx2_write_phy(bp, MII_BMCR, new_bmcr);
929
930 /* Normally, the new speed is setup after the link has
931 * gone down and up again. In some cases, link will not go
932 * down so we need to set up the new speed here.
933 */
934 if (bmsr & BMSR_LSTATUS) {
935 bp->line_speed = bp->req_line_speed;
936 bp->duplex = bp->req_duplex;
937 bnx2_resolve_flow_ctrl(bp);
938 bnx2_set_mac_link(bp);
939 }
940 }
941 return 0;
942 }
943
944 static int
945 bnx2_setup_phy(struct bnx2 *bp)
946 {
947 if (bp->loopback == MAC_LOOPBACK)
948 return 0;
949
950 if (bp->phy_flags & PHY_SERDES_FLAG) {
951 return (bnx2_setup_serdes_phy(bp));
952 }
953 else {
954 return (bnx2_setup_copper_phy(bp));
955 }
956 }
957
958 static int
959 bnx2_init_serdes_phy(struct bnx2 *bp)
960 {
961 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
962
963 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
964 REG_WR(bp, BNX2_MISC_UNUSED0, 0x300);
965 }
966
967 if (bp->dev->mtu > 1500) {
968 u32 val;
969
970 /* Set extended packet length bit */
971 bnx2_write_phy(bp, 0x18, 0x7);
972 bnx2_read_phy(bp, 0x18, &val);
973 bnx2_write_phy(bp, 0x18, (val & 0xfff8) | 0x4000);
974
975 bnx2_write_phy(bp, 0x1c, 0x6c00);
976 bnx2_read_phy(bp, 0x1c, &val);
977 bnx2_write_phy(bp, 0x1c, (val & 0x3ff) | 0xec02);
978 }
979 else {
980 u32 val;
981
982 bnx2_write_phy(bp, 0x18, 0x7);
983 bnx2_read_phy(bp, 0x18, &val);
984 bnx2_write_phy(bp, 0x18, val & ~0x4007);
985
986 bnx2_write_phy(bp, 0x1c, 0x6c00);
987 bnx2_read_phy(bp, 0x1c, &val);
988 bnx2_write_phy(bp, 0x1c, (val & 0x3fd) | 0xec00);
989 }
990
991 return 0;
992 }
993
994 static int
995 bnx2_init_copper_phy(struct bnx2 *bp)
996 {
997 bp->phy_flags |= PHY_CRC_FIX_FLAG;
998
999 if (bp->phy_flags & PHY_CRC_FIX_FLAG) {
1000 bnx2_write_phy(bp, 0x18, 0x0c00);
1001 bnx2_write_phy(bp, 0x17, 0x000a);
1002 bnx2_write_phy(bp, 0x15, 0x310b);
1003 bnx2_write_phy(bp, 0x17, 0x201f);
1004 bnx2_write_phy(bp, 0x15, 0x9506);
1005 bnx2_write_phy(bp, 0x17, 0x401f);
1006 bnx2_write_phy(bp, 0x15, 0x14e2);
1007 bnx2_write_phy(bp, 0x18, 0x0400);
1008 }
1009
1010 if (bp->dev->mtu > 1500) {
1011 u32 val;
1012
1013 /* Set extended packet length bit */
1014 bnx2_write_phy(bp, 0x18, 0x7);
1015 bnx2_read_phy(bp, 0x18, &val);
1016 bnx2_write_phy(bp, 0x18, val | 0x4000);
1017
1018 bnx2_read_phy(bp, 0x10, &val);
1019 bnx2_write_phy(bp, 0x10, val | 0x1);
1020 }
1021 else {
1022 u32 val;
1023
1024 bnx2_write_phy(bp, 0x18, 0x7);
1025 bnx2_read_phy(bp, 0x18, &val);
1026 bnx2_write_phy(bp, 0x18, val & ~0x4007);
1027
1028 bnx2_read_phy(bp, 0x10, &val);
1029 bnx2_write_phy(bp, 0x10, val & ~0x1);
1030 }
1031
1032 return 0;
1033 }
1034
1035
1036 static int
1037 bnx2_init_phy(struct bnx2 *bp)
1038 {
1039 u32 val;
1040 int rc = 0;
1041
1042 bp->phy_flags &= ~PHY_INT_MODE_MASK_FLAG;
1043 bp->phy_flags |= PHY_INT_MODE_LINK_READY_FLAG;
1044
1045 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
1046
1047 bnx2_reset_phy(bp);
1048
1049 bnx2_read_phy(bp, MII_PHYSID1, &val);
1050 bp->phy_id = val << 16;
1051 bnx2_read_phy(bp, MII_PHYSID2, &val);
1052 bp->phy_id |= val & 0xffff;
1053
1054 if (bp->phy_flags & PHY_SERDES_FLAG) {
1055 rc = bnx2_init_serdes_phy(bp);
1056 }
1057 else {
1058 rc = bnx2_init_copper_phy(bp);
1059 }
1060
1061 bnx2_setup_phy(bp);
1062
1063 return rc;
1064 }
1065
1066 static int
1067 bnx2_set_mac_loopback(struct bnx2 *bp)
1068 {
1069 u32 mac_mode;
1070
1071 mac_mode = REG_RD(bp, BNX2_EMAC_MODE);
1072 mac_mode &= ~BNX2_EMAC_MODE_PORT;
1073 mac_mode |= BNX2_EMAC_MODE_MAC_LOOP | BNX2_EMAC_MODE_FORCE_LINK;
1074 REG_WR(bp, BNX2_EMAC_MODE, mac_mode);
1075 bp->link_up = 1;
1076 return 0;
1077 }
1078
1079 static int
1080 bnx2_fw_sync(struct bnx2 *bp, u32 msg_data)
1081 {
1082 int i;
1083 u32 val;
1084
1085 if (bp->fw_timed_out)
1086 return -EBUSY;
1087
1088 bp->fw_wr_seq++;
1089 msg_data |= bp->fw_wr_seq;
1090
1091 REG_WR_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DRV_MB, msg_data);
1092
1093 /* wait for an acknowledgement. */
1094 for (i = 0; i < (FW_ACK_TIME_OUT_MS * 1000)/5; i++) {
1095 udelay(5);
1096
1097 val = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_FW_MB);
1098
1099 if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
1100 break;
1101 }
1102
1103 /* If we timed out, inform the firmware that this is the case. */
1104 if (((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) &&
1105 ((msg_data & BNX2_DRV_MSG_DATA) != BNX2_DRV_MSG_DATA_WAIT0)) {
1106
1107 msg_data &= ~BNX2_DRV_MSG_CODE;
1108 msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
1109
1110 REG_WR_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DRV_MB, msg_data);
1111
1112 bp->fw_timed_out = 1;
1113
1114 return -EBUSY;
1115 }
1116
1117 return 0;
1118 }
1119
1120 static void
1121 bnx2_init_context(struct bnx2 *bp)
1122 {
1123 u32 vcid;
1124
1125 vcid = 96;
1126 while (vcid) {
1127 u32 vcid_addr, pcid_addr, offset;
1128
1129 vcid--;
1130
1131 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
1132 u32 new_vcid;
1133
1134 vcid_addr = GET_PCID_ADDR(vcid);
1135 if (vcid & 0x8) {
1136 new_vcid = 0x60 + (vcid & 0xf0) + (vcid & 0x7);
1137 }
1138 else {
1139 new_vcid = vcid;
1140 }
1141 pcid_addr = GET_PCID_ADDR(new_vcid);
1142 }
1143 else {
1144 vcid_addr = GET_CID_ADDR(vcid);
1145 pcid_addr = vcid_addr;
1146 }
1147
1148 REG_WR(bp, BNX2_CTX_VIRT_ADDR, 0x00);
1149 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
1150
1151 /* Zero out the context. */
1152 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4) {
1153 CTX_WR(bp, 0x00, offset, 0);
1154 }
1155
1156 REG_WR(bp, BNX2_CTX_VIRT_ADDR, vcid_addr);
1157 REG_WR(bp, BNX2_CTX_PAGE_TBL, pcid_addr);
1158 }
1159 }
1160
1161 static int
1162 bnx2_alloc_bad_rbuf(struct bnx2 *bp)
1163 {
1164 u16 *good_mbuf;
1165 u32 good_mbuf_cnt;
1166 u32 val;
1167
1168 good_mbuf = kmalloc(512 * sizeof(u16), GFP_KERNEL);
1169 if (good_mbuf == NULL) {
1170 printk(KERN_ERR PFX "Failed to allocate memory in "
1171 "bnx2_alloc_bad_rbuf\n");
1172 return -ENOMEM;
1173 }
1174
1175 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
1176 BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE);
1177
1178 good_mbuf_cnt = 0;
1179
1180 /* Allocate a bunch of mbufs and save the good ones in an array. */
1181 val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
1182 while (val & BNX2_RBUF_STATUS1_FREE_COUNT) {
1183 REG_WR_IND(bp, BNX2_RBUF_COMMAND, BNX2_RBUF_COMMAND_ALLOC_REQ);
1184
1185 val = REG_RD_IND(bp, BNX2_RBUF_FW_BUF_ALLOC);
1186
1187 val &= BNX2_RBUF_FW_BUF_ALLOC_VALUE;
1188
1189 /* The addresses with Bit 9 set are bad memory blocks. */
1190 if (!(val & (1 << 9))) {
1191 good_mbuf[good_mbuf_cnt] = (u16) val;
1192 good_mbuf_cnt++;
1193 }
1194
1195 val = REG_RD_IND(bp, BNX2_RBUF_STATUS1);
1196 }
1197
1198 /* Free the good ones back to the mbuf pool thus discarding
1199 * all the bad ones. */
1200 while (good_mbuf_cnt) {
1201 good_mbuf_cnt--;
1202
1203 val = good_mbuf[good_mbuf_cnt];
1204 val = (val << 9) | val | 1;
1205
1206 REG_WR_IND(bp, BNX2_RBUF_FW_BUF_FREE, val);
1207 }
1208 kfree(good_mbuf);
1209 return 0;
1210 }
1211
1212 static void
1213 bnx2_set_mac_addr(struct bnx2 *bp)
1214 {
1215 u32 val;
1216 u8 *mac_addr = bp->dev->dev_addr;
1217
1218 val = (mac_addr[0] << 8) | mac_addr[1];
1219
1220 REG_WR(bp, BNX2_EMAC_MAC_MATCH0, val);
1221
1222 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
1223 (mac_addr[4] << 8) | mac_addr[5];
1224
1225 REG_WR(bp, BNX2_EMAC_MAC_MATCH1, val);
1226 }
1227
1228 static inline int
1229 bnx2_alloc_rx_skb(struct bnx2 *bp, u16 index)
1230 {
1231 struct sk_buff *skb;
1232 struct sw_bd *rx_buf = &bp->rx_buf_ring[index];
1233 dma_addr_t mapping;
1234 struct rx_bd *rxbd = &bp->rx_desc_ring[index];
1235 unsigned long align;
1236
1237 skb = dev_alloc_skb(bp->rx_buf_size);
1238 if (skb == NULL) {
1239 return -ENOMEM;
1240 }
1241
1242 if (unlikely((align = (unsigned long) skb->data & 0x7))) {
1243 skb_reserve(skb, 8 - align);
1244 }
1245
1246 skb->dev = bp->dev;
1247 mapping = pci_map_single(bp->pdev, skb->data, bp->rx_buf_use_size,
1248 PCI_DMA_FROMDEVICE);
1249
1250 rx_buf->skb = skb;
1251 pci_unmap_addr_set(rx_buf, mapping, mapping);
1252
1253 rxbd->rx_bd_haddr_hi = (u64) mapping >> 32;
1254 rxbd->rx_bd_haddr_lo = (u64) mapping & 0xffffffff;
1255
1256 bp->rx_prod_bseq += bp->rx_buf_use_size;
1257
1258 return 0;
1259 }
1260
1261 static void
1262 bnx2_phy_int(struct bnx2 *bp)
1263 {
1264 u32 new_link_state, old_link_state;
1265
1266 new_link_state = bp->status_blk->status_attn_bits &
1267 STATUS_ATTN_BITS_LINK_STATE;
1268 old_link_state = bp->status_blk->status_attn_bits_ack &
1269 STATUS_ATTN_BITS_LINK_STATE;
1270 if (new_link_state != old_link_state) {
1271 if (new_link_state) {
1272 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_SET_CMD,
1273 STATUS_ATTN_BITS_LINK_STATE);
1274 }
1275 else {
1276 REG_WR(bp, BNX2_PCICFG_STATUS_BIT_CLEAR_CMD,
1277 STATUS_ATTN_BITS_LINK_STATE);
1278 }
1279 bnx2_set_link(bp);
1280 }
1281 }
1282
1283 static void
1284 bnx2_tx_int(struct bnx2 *bp)
1285 {
1286 u16 hw_cons, sw_cons, sw_ring_cons;
1287 int tx_free_bd = 0;
1288
1289 hw_cons = bp->status_blk->status_tx_quick_consumer_index0;
1290 if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
1291 hw_cons++;
1292 }
1293 sw_cons = bp->tx_cons;
1294
1295 while (sw_cons != hw_cons) {
1296 struct sw_bd *tx_buf;
1297 struct sk_buff *skb;
1298 int i, last;
1299
1300 sw_ring_cons = TX_RING_IDX(sw_cons);
1301
1302 tx_buf = &bp->tx_buf_ring[sw_ring_cons];
1303 skb = tx_buf->skb;
1304 #ifdef BCM_TSO
1305 /* partial BD completions possible with TSO packets */
1306 if (skb_shinfo(skb)->tso_size) {
1307 u16 last_idx, last_ring_idx;
1308
1309 last_idx = sw_cons +
1310 skb_shinfo(skb)->nr_frags + 1;
1311 last_ring_idx = sw_ring_cons +
1312 skb_shinfo(skb)->nr_frags + 1;
1313 if (unlikely(last_ring_idx >= MAX_TX_DESC_CNT)) {
1314 last_idx++;
1315 }
1316 if (((s16) ((s16) last_idx - (s16) hw_cons)) > 0) {
1317 break;
1318 }
1319 }
1320 #endif
1321 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
1322 skb_headlen(skb), PCI_DMA_TODEVICE);
1323
1324 tx_buf->skb = NULL;
1325 last = skb_shinfo(skb)->nr_frags;
1326
1327 for (i = 0; i < last; i++) {
1328 sw_cons = NEXT_TX_BD(sw_cons);
1329
1330 pci_unmap_page(bp->pdev,
1331 pci_unmap_addr(
1332 &bp->tx_buf_ring[TX_RING_IDX(sw_cons)],
1333 mapping),
1334 skb_shinfo(skb)->frags[i].size,
1335 PCI_DMA_TODEVICE);
1336 }
1337
1338 sw_cons = NEXT_TX_BD(sw_cons);
1339
1340 tx_free_bd += last + 1;
1341
1342 dev_kfree_skb_irq(skb);
1343
1344 hw_cons = bp->status_blk->status_tx_quick_consumer_index0;
1345 if ((hw_cons & MAX_TX_DESC_CNT) == MAX_TX_DESC_CNT) {
1346 hw_cons++;
1347 }
1348 }
1349
1350 bp->tx_cons = sw_cons;
1351
1352 if (unlikely(netif_queue_stopped(bp->dev))) {
1353 spin_lock(&bp->tx_lock);
1354 if ((netif_queue_stopped(bp->dev)) &&
1355 (bnx2_tx_avail(bp) > MAX_SKB_FRAGS)) {
1356
1357 netif_wake_queue(bp->dev);
1358 }
1359 spin_unlock(&bp->tx_lock);
1360 }
1361 }
1362
1363 static inline void
1364 bnx2_reuse_rx_skb(struct bnx2 *bp, struct sk_buff *skb,
1365 u16 cons, u16 prod)
1366 {
1367 struct sw_bd *cons_rx_buf = &bp->rx_buf_ring[cons];
1368 struct sw_bd *prod_rx_buf = &bp->rx_buf_ring[prod];
1369 struct rx_bd *cons_bd = &bp->rx_desc_ring[cons];
1370 struct rx_bd *prod_bd = &bp->rx_desc_ring[prod];
1371
1372 pci_dma_sync_single_for_device(bp->pdev,
1373 pci_unmap_addr(cons_rx_buf, mapping),
1374 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
1375
1376 prod_rx_buf->skb = cons_rx_buf->skb;
1377 pci_unmap_addr_set(prod_rx_buf, mapping,
1378 pci_unmap_addr(cons_rx_buf, mapping));
1379
1380 memcpy(prod_bd, cons_bd, 8);
1381
1382 bp->rx_prod_bseq += bp->rx_buf_use_size;
1383
1384 }
1385
1386 static int
1387 bnx2_rx_int(struct bnx2 *bp, int budget)
1388 {
1389 u16 hw_cons, sw_cons, sw_ring_cons, sw_prod, sw_ring_prod;
1390 struct l2_fhdr *rx_hdr;
1391 int rx_pkt = 0;
1392
1393 hw_cons = bp->status_blk->status_rx_quick_consumer_index0;
1394 if ((hw_cons & MAX_RX_DESC_CNT) == MAX_RX_DESC_CNT) {
1395 hw_cons++;
1396 }
1397 sw_cons = bp->rx_cons;
1398 sw_prod = bp->rx_prod;
1399
1400 /* Memory barrier necessary as speculative reads of the rx
1401 * buffer can be ahead of the index in the status block
1402 */
1403 rmb();
1404 while (sw_cons != hw_cons) {
1405 unsigned int len;
1406 u16 status;
1407 struct sw_bd *rx_buf;
1408 struct sk_buff *skb;
1409
1410 sw_ring_cons = RX_RING_IDX(sw_cons);
1411 sw_ring_prod = RX_RING_IDX(sw_prod);
1412
1413 rx_buf = &bp->rx_buf_ring[sw_ring_cons];
1414 skb = rx_buf->skb;
1415 pci_dma_sync_single_for_cpu(bp->pdev,
1416 pci_unmap_addr(rx_buf, mapping),
1417 bp->rx_offset + RX_COPY_THRESH, PCI_DMA_FROMDEVICE);
1418
1419 rx_hdr = (struct l2_fhdr *) skb->data;
1420 len = rx_hdr->l2_fhdr_pkt_len - 4;
1421
1422 if (rx_hdr->l2_fhdr_errors &
1423 (L2_FHDR_ERRORS_BAD_CRC |
1424 L2_FHDR_ERRORS_PHY_DECODE |
1425 L2_FHDR_ERRORS_ALIGNMENT |
1426 L2_FHDR_ERRORS_TOO_SHORT |
1427 L2_FHDR_ERRORS_GIANT_FRAME)) {
1428
1429 goto reuse_rx;
1430 }
1431
1432 /* Since we don't have a jumbo ring, copy small packets
1433 * if mtu > 1500
1434 */
1435 if ((bp->dev->mtu > 1500) && (len <= RX_COPY_THRESH)) {
1436 struct sk_buff *new_skb;
1437
1438 new_skb = dev_alloc_skb(len + 2);
1439 if (new_skb == NULL)
1440 goto reuse_rx;
1441
1442 /* aligned copy */
1443 memcpy(new_skb->data,
1444 skb->data + bp->rx_offset - 2,
1445 len + 2);
1446
1447 skb_reserve(new_skb, 2);
1448 skb_put(new_skb, len);
1449 new_skb->dev = bp->dev;
1450
1451 bnx2_reuse_rx_skb(bp, skb,
1452 sw_ring_cons, sw_ring_prod);
1453
1454 skb = new_skb;
1455 }
1456 else if (bnx2_alloc_rx_skb(bp, sw_ring_prod) == 0) {
1457 pci_unmap_single(bp->pdev,
1458 pci_unmap_addr(rx_buf, mapping),
1459 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
1460
1461 skb_reserve(skb, bp->rx_offset);
1462 skb_put(skb, len);
1463 }
1464 else {
1465 reuse_rx:
1466 bnx2_reuse_rx_skb(bp, skb,
1467 sw_ring_cons, sw_ring_prod);
1468 goto next_rx;
1469 }
1470
1471 skb->protocol = eth_type_trans(skb, bp->dev);
1472
1473 if ((len > (bp->dev->mtu + ETH_HLEN)) &&
1474 (htons(skb->protocol) != 0x8100)) {
1475
1476 dev_kfree_skb_irq(skb);
1477 goto next_rx;
1478
1479 }
1480
1481 status = rx_hdr->l2_fhdr_status;
1482 skb->ip_summed = CHECKSUM_NONE;
1483 if (bp->rx_csum &&
1484 (status & (L2_FHDR_STATUS_TCP_SEGMENT |
1485 L2_FHDR_STATUS_UDP_DATAGRAM))) {
1486
1487 u16 cksum = rx_hdr->l2_fhdr_tcp_udp_xsum;
1488
1489 if (cksum == 0xffff)
1490 skb->ip_summed = CHECKSUM_UNNECESSARY;
1491 }
1492
1493 #ifdef BCM_VLAN
1494 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) && (bp->vlgrp != 0)) {
1495 vlan_hwaccel_receive_skb(skb, bp->vlgrp,
1496 rx_hdr->l2_fhdr_vlan_tag);
1497 }
1498 else
1499 #endif
1500 netif_receive_skb(skb);
1501
1502 bp->dev->last_rx = jiffies;
1503 rx_pkt++;
1504
1505 next_rx:
1506 rx_buf->skb = NULL;
1507
1508 sw_cons = NEXT_RX_BD(sw_cons);
1509 sw_prod = NEXT_RX_BD(sw_prod);
1510
1511 if ((rx_pkt == budget))
1512 break;
1513 }
1514 bp->rx_cons = sw_cons;
1515 bp->rx_prod = sw_prod;
1516
1517 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, sw_prod);
1518
1519 REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
1520
1521 mmiowb();
1522
1523 return rx_pkt;
1524
1525 }
1526
1527 /* MSI ISR - The only difference between this and the INTx ISR
1528 * is that the MSI interrupt is always serviced.
1529 */
1530 static irqreturn_t
1531 bnx2_msi(int irq, void *dev_instance, struct pt_regs *regs)
1532 {
1533 struct net_device *dev = dev_instance;
1534 struct bnx2 *bp = dev->priv;
1535
1536 prefetch(bp->status_blk);
1537 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1538 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
1539 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
1540
1541 /* Return here if interrupt is disabled. */
1542 if (unlikely(atomic_read(&bp->intr_sem) != 0))
1543 return IRQ_HANDLED;
1544
1545 netif_rx_schedule(dev);
1546
1547 return IRQ_HANDLED;
1548 }
1549
1550 static irqreturn_t
1551 bnx2_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
1552 {
1553 struct net_device *dev = dev_instance;
1554 struct bnx2 *bp = dev->priv;
1555
1556 /* When using INTx, it is possible for the interrupt to arrive
1557 * at the CPU before the status block posted prior to the
1558 * interrupt. Reading a register will flush the status block.
1559 * When using MSI, the MSI message will always complete after
1560 * the status block write.
1561 */
1562 if ((bp->status_blk->status_idx == bp->last_status_idx) &&
1563 (REG_RD(bp, BNX2_PCICFG_MISC_STATUS) &
1564 BNX2_PCICFG_MISC_STATUS_INTA_VALUE))
1565 return IRQ_NONE;
1566
1567 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1568 BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
1569 BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
1570
1571 /* Return here if interrupt is shared and is disabled. */
1572 if (unlikely(atomic_read(&bp->intr_sem) != 0))
1573 return IRQ_HANDLED;
1574
1575 netif_rx_schedule(dev);
1576
1577 return IRQ_HANDLED;
1578 }
1579
1580 static int
1581 bnx2_poll(struct net_device *dev, int *budget)
1582 {
1583 struct bnx2 *bp = dev->priv;
1584 int rx_done = 1;
1585
1586 bp->last_status_idx = bp->status_blk->status_idx;
1587
1588 rmb();
1589 if ((bp->status_blk->status_attn_bits &
1590 STATUS_ATTN_BITS_LINK_STATE) !=
1591 (bp->status_blk->status_attn_bits_ack &
1592 STATUS_ATTN_BITS_LINK_STATE)) {
1593
1594 spin_lock(&bp->phy_lock);
1595 bnx2_phy_int(bp);
1596 spin_unlock(&bp->phy_lock);
1597 }
1598
1599 if (bp->status_blk->status_tx_quick_consumer_index0 != bp->tx_cons) {
1600 bnx2_tx_int(bp);
1601 }
1602
1603 if (bp->status_blk->status_rx_quick_consumer_index0 != bp->rx_cons) {
1604 int orig_budget = *budget;
1605 int work_done;
1606
1607 if (orig_budget > dev->quota)
1608 orig_budget = dev->quota;
1609
1610 work_done = bnx2_rx_int(bp, orig_budget);
1611 *budget -= work_done;
1612 dev->quota -= work_done;
1613
1614 if (work_done >= orig_budget) {
1615 rx_done = 0;
1616 }
1617 }
1618
1619 if (rx_done) {
1620 netif_rx_complete(dev);
1621 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD,
1622 BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID |
1623 bp->last_status_idx);
1624 return 0;
1625 }
1626
1627 return 1;
1628 }
1629
1630 /* Called with rtnl_lock from vlan functions and also dev->xmit_lock
1631 * from set_multicast.
1632 */
1633 static void
1634 bnx2_set_rx_mode(struct net_device *dev)
1635 {
1636 struct bnx2 *bp = dev->priv;
1637 u32 rx_mode, sort_mode;
1638 int i;
1639
1640 spin_lock_bh(&bp->phy_lock);
1641
1642 rx_mode = bp->rx_mode & ~(BNX2_EMAC_RX_MODE_PROMISCUOUS |
1643 BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG);
1644 sort_mode = 1 | BNX2_RPM_SORT_USER0_BC_EN;
1645 #ifdef BCM_VLAN
1646 if (!bp->vlgrp) {
1647 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
1648 }
1649 #else
1650 rx_mode |= BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG;
1651 #endif
1652 if (dev->flags & IFF_PROMISC) {
1653 /* Promiscuous mode. */
1654 rx_mode |= BNX2_EMAC_RX_MODE_PROMISCUOUS;
1655 sort_mode |= BNX2_RPM_SORT_USER0_PROM_EN;
1656 }
1657 else if (dev->flags & IFF_ALLMULTI) {
1658 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
1659 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
1660 0xffffffff);
1661 }
1662 sort_mode |= BNX2_RPM_SORT_USER0_MC_EN;
1663 }
1664 else {
1665 /* Accept one or more multicast(s). */
1666 struct dev_mc_list *mclist;
1667 u32 mc_filter[NUM_MC_HASH_REGISTERS];
1668 u32 regidx;
1669 u32 bit;
1670 u32 crc;
1671
1672 memset(mc_filter, 0, 4 * NUM_MC_HASH_REGISTERS);
1673
1674 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1675 i++, mclist = mclist->next) {
1676
1677 crc = ether_crc_le(ETH_ALEN, mclist->dmi_addr);
1678 bit = crc & 0xff;
1679 regidx = (bit & 0xe0) >> 5;
1680 bit &= 0x1f;
1681 mc_filter[regidx] |= (1 << bit);
1682 }
1683
1684 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
1685 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
1686 mc_filter[i]);
1687 }
1688
1689 sort_mode |= BNX2_RPM_SORT_USER0_MC_HSH_EN;
1690 }
1691
1692 if (rx_mode != bp->rx_mode) {
1693 bp->rx_mode = rx_mode;
1694 REG_WR(bp, BNX2_EMAC_RX_MODE, rx_mode);
1695 }
1696
1697 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
1698 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode);
1699 REG_WR(bp, BNX2_RPM_SORT_USER0, sort_mode | BNX2_RPM_SORT_USER0_ENA);
1700
1701 spin_unlock_bh(&bp->phy_lock);
1702 }
1703
1704 static void
1705 load_rv2p_fw(struct bnx2 *bp, u32 *rv2p_code, u32 rv2p_code_len,
1706 u32 rv2p_proc)
1707 {
1708 int i;
1709 u32 val;
1710
1711
1712 for (i = 0; i < rv2p_code_len; i += 8) {
1713 REG_WR(bp, BNX2_RV2P_INSTR_HIGH, *rv2p_code);
1714 rv2p_code++;
1715 REG_WR(bp, BNX2_RV2P_INSTR_LOW, *rv2p_code);
1716 rv2p_code++;
1717
1718 if (rv2p_proc == RV2P_PROC1) {
1719 val = (i / 8) | BNX2_RV2P_PROC1_ADDR_CMD_RDWR;
1720 REG_WR(bp, BNX2_RV2P_PROC1_ADDR_CMD, val);
1721 }
1722 else {
1723 val = (i / 8) | BNX2_RV2P_PROC2_ADDR_CMD_RDWR;
1724 REG_WR(bp, BNX2_RV2P_PROC2_ADDR_CMD, val);
1725 }
1726 }
1727
1728 /* Reset the processor, un-stall is done later. */
1729 if (rv2p_proc == RV2P_PROC1) {
1730 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC1_RESET);
1731 }
1732 else {
1733 REG_WR(bp, BNX2_RV2P_COMMAND, BNX2_RV2P_COMMAND_PROC2_RESET);
1734 }
1735 }
1736
1737 static void
1738 load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw)
1739 {
1740 u32 offset;
1741 u32 val;
1742
1743 /* Halt the CPU. */
1744 val = REG_RD_IND(bp, cpu_reg->mode);
1745 val |= cpu_reg->mode_value_halt;
1746 REG_WR_IND(bp, cpu_reg->mode, val);
1747 REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
1748
1749 /* Load the Text area. */
1750 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
1751 if (fw->text) {
1752 int j;
1753
1754 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
1755 REG_WR_IND(bp, offset, fw->text[j]);
1756 }
1757 }
1758
1759 /* Load the Data area. */
1760 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
1761 if (fw->data) {
1762 int j;
1763
1764 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
1765 REG_WR_IND(bp, offset, fw->data[j]);
1766 }
1767 }
1768
1769 /* Load the SBSS area. */
1770 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
1771 if (fw->sbss) {
1772 int j;
1773
1774 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
1775 REG_WR_IND(bp, offset, fw->sbss[j]);
1776 }
1777 }
1778
1779 /* Load the BSS area. */
1780 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
1781 if (fw->bss) {
1782 int j;
1783
1784 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
1785 REG_WR_IND(bp, offset, fw->bss[j]);
1786 }
1787 }
1788
1789 /* Load the Read-Only area. */
1790 offset = cpu_reg->spad_base +
1791 (fw->rodata_addr - cpu_reg->mips_view_base);
1792 if (fw->rodata) {
1793 int j;
1794
1795 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
1796 REG_WR_IND(bp, offset, fw->rodata[j]);
1797 }
1798 }
1799
1800 /* Clear the pre-fetch instruction. */
1801 REG_WR_IND(bp, cpu_reg->inst, 0);
1802 REG_WR_IND(bp, cpu_reg->pc, fw->start_addr);
1803
1804 /* Start the CPU. */
1805 val = REG_RD_IND(bp, cpu_reg->mode);
1806 val &= ~cpu_reg->mode_value_halt;
1807 REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear);
1808 REG_WR_IND(bp, cpu_reg->mode, val);
1809 }
1810
1811 static void
1812 bnx2_init_cpus(struct bnx2 *bp)
1813 {
1814 struct cpu_reg cpu_reg;
1815 struct fw_info fw;
1816
1817 /* Initialize the RV2P processor. */
1818 load_rv2p_fw(bp, bnx2_rv2p_proc1, sizeof(bnx2_rv2p_proc1), RV2P_PROC1);
1819 load_rv2p_fw(bp, bnx2_rv2p_proc2, sizeof(bnx2_rv2p_proc2), RV2P_PROC2);
1820
1821 /* Initialize the RX Processor. */
1822 cpu_reg.mode = BNX2_RXP_CPU_MODE;
1823 cpu_reg.mode_value_halt = BNX2_RXP_CPU_MODE_SOFT_HALT;
1824 cpu_reg.mode_value_sstep = BNX2_RXP_CPU_MODE_STEP_ENA;
1825 cpu_reg.state = BNX2_RXP_CPU_STATE;
1826 cpu_reg.state_value_clear = 0xffffff;
1827 cpu_reg.gpr0 = BNX2_RXP_CPU_REG_FILE;
1828 cpu_reg.evmask = BNX2_RXP_CPU_EVENT_MASK;
1829 cpu_reg.pc = BNX2_RXP_CPU_PROGRAM_COUNTER;
1830 cpu_reg.inst = BNX2_RXP_CPU_INSTRUCTION;
1831 cpu_reg.bp = BNX2_RXP_CPU_HW_BREAKPOINT;
1832 cpu_reg.spad_base = BNX2_RXP_SCRATCH;
1833 cpu_reg.mips_view_base = 0x8000000;
1834
1835 fw.ver_major = bnx2_RXP_b06FwReleaseMajor;
1836 fw.ver_minor = bnx2_RXP_b06FwReleaseMinor;
1837 fw.ver_fix = bnx2_RXP_b06FwReleaseFix;
1838 fw.start_addr = bnx2_RXP_b06FwStartAddr;
1839
1840 fw.text_addr = bnx2_RXP_b06FwTextAddr;
1841 fw.text_len = bnx2_RXP_b06FwTextLen;
1842 fw.text_index = 0;
1843 fw.text = bnx2_RXP_b06FwText;
1844
1845 fw.data_addr = bnx2_RXP_b06FwDataAddr;
1846 fw.data_len = bnx2_RXP_b06FwDataLen;
1847 fw.data_index = 0;
1848 fw.data = bnx2_RXP_b06FwData;
1849
1850 fw.sbss_addr = bnx2_RXP_b06FwSbssAddr;
1851 fw.sbss_len = bnx2_RXP_b06FwSbssLen;
1852 fw.sbss_index = 0;
1853 fw.sbss = bnx2_RXP_b06FwSbss;
1854
1855 fw.bss_addr = bnx2_RXP_b06FwBssAddr;
1856 fw.bss_len = bnx2_RXP_b06FwBssLen;
1857 fw.bss_index = 0;
1858 fw.bss = bnx2_RXP_b06FwBss;
1859
1860 fw.rodata_addr = bnx2_RXP_b06FwRodataAddr;
1861 fw.rodata_len = bnx2_RXP_b06FwRodataLen;
1862 fw.rodata_index = 0;
1863 fw.rodata = bnx2_RXP_b06FwRodata;
1864
1865 load_cpu_fw(bp, &cpu_reg, &fw);
1866
1867 /* Initialize the TX Processor. */
1868 cpu_reg.mode = BNX2_TXP_CPU_MODE;
1869 cpu_reg.mode_value_halt = BNX2_TXP_CPU_MODE_SOFT_HALT;
1870 cpu_reg.mode_value_sstep = BNX2_TXP_CPU_MODE_STEP_ENA;
1871 cpu_reg.state = BNX2_TXP_CPU_STATE;
1872 cpu_reg.state_value_clear = 0xffffff;
1873 cpu_reg.gpr0 = BNX2_TXP_CPU_REG_FILE;
1874 cpu_reg.evmask = BNX2_TXP_CPU_EVENT_MASK;
1875 cpu_reg.pc = BNX2_TXP_CPU_PROGRAM_COUNTER;
1876 cpu_reg.inst = BNX2_TXP_CPU_INSTRUCTION;
1877 cpu_reg.bp = BNX2_TXP_CPU_HW_BREAKPOINT;
1878 cpu_reg.spad_base = BNX2_TXP_SCRATCH;
1879 cpu_reg.mips_view_base = 0x8000000;
1880
1881 fw.ver_major = bnx2_TXP_b06FwReleaseMajor;
1882 fw.ver_minor = bnx2_TXP_b06FwReleaseMinor;
1883 fw.ver_fix = bnx2_TXP_b06FwReleaseFix;
1884 fw.start_addr = bnx2_TXP_b06FwStartAddr;
1885
1886 fw.text_addr = bnx2_TXP_b06FwTextAddr;
1887 fw.text_len = bnx2_TXP_b06FwTextLen;
1888 fw.text_index = 0;
1889 fw.text = bnx2_TXP_b06FwText;
1890
1891 fw.data_addr = bnx2_TXP_b06FwDataAddr;
1892 fw.data_len = bnx2_TXP_b06FwDataLen;
1893 fw.data_index = 0;
1894 fw.data = bnx2_TXP_b06FwData;
1895
1896 fw.sbss_addr = bnx2_TXP_b06FwSbssAddr;
1897 fw.sbss_len = bnx2_TXP_b06FwSbssLen;
1898 fw.sbss_index = 0;
1899 fw.sbss = bnx2_TXP_b06FwSbss;
1900
1901 fw.bss_addr = bnx2_TXP_b06FwBssAddr;
1902 fw.bss_len = bnx2_TXP_b06FwBssLen;
1903 fw.bss_index = 0;
1904 fw.bss = bnx2_TXP_b06FwBss;
1905
1906 fw.rodata_addr = bnx2_TXP_b06FwRodataAddr;
1907 fw.rodata_len = bnx2_TXP_b06FwRodataLen;
1908 fw.rodata_index = 0;
1909 fw.rodata = bnx2_TXP_b06FwRodata;
1910
1911 load_cpu_fw(bp, &cpu_reg, &fw);
1912
1913 /* Initialize the TX Patch-up Processor. */
1914 cpu_reg.mode = BNX2_TPAT_CPU_MODE;
1915 cpu_reg.mode_value_halt = BNX2_TPAT_CPU_MODE_SOFT_HALT;
1916 cpu_reg.mode_value_sstep = BNX2_TPAT_CPU_MODE_STEP_ENA;
1917 cpu_reg.state = BNX2_TPAT_CPU_STATE;
1918 cpu_reg.state_value_clear = 0xffffff;
1919 cpu_reg.gpr0 = BNX2_TPAT_CPU_REG_FILE;
1920 cpu_reg.evmask = BNX2_TPAT_CPU_EVENT_MASK;
1921 cpu_reg.pc = BNX2_TPAT_CPU_PROGRAM_COUNTER;
1922 cpu_reg.inst = BNX2_TPAT_CPU_INSTRUCTION;
1923 cpu_reg.bp = BNX2_TPAT_CPU_HW_BREAKPOINT;
1924 cpu_reg.spad_base = BNX2_TPAT_SCRATCH;
1925 cpu_reg.mips_view_base = 0x8000000;
1926
1927 fw.ver_major = bnx2_TPAT_b06FwReleaseMajor;
1928 fw.ver_minor = bnx2_TPAT_b06FwReleaseMinor;
1929 fw.ver_fix = bnx2_TPAT_b06FwReleaseFix;
1930 fw.start_addr = bnx2_TPAT_b06FwStartAddr;
1931
1932 fw.text_addr = bnx2_TPAT_b06FwTextAddr;
1933 fw.text_len = bnx2_TPAT_b06FwTextLen;
1934 fw.text_index = 0;
1935 fw.text = bnx2_TPAT_b06FwText;
1936
1937 fw.data_addr = bnx2_TPAT_b06FwDataAddr;
1938 fw.data_len = bnx2_TPAT_b06FwDataLen;
1939 fw.data_index = 0;
1940 fw.data = bnx2_TPAT_b06FwData;
1941
1942 fw.sbss_addr = bnx2_TPAT_b06FwSbssAddr;
1943 fw.sbss_len = bnx2_TPAT_b06FwSbssLen;
1944 fw.sbss_index = 0;
1945 fw.sbss = bnx2_TPAT_b06FwSbss;
1946
1947 fw.bss_addr = bnx2_TPAT_b06FwBssAddr;
1948 fw.bss_len = bnx2_TPAT_b06FwBssLen;
1949 fw.bss_index = 0;
1950 fw.bss = bnx2_TPAT_b06FwBss;
1951
1952 fw.rodata_addr = bnx2_TPAT_b06FwRodataAddr;
1953 fw.rodata_len = bnx2_TPAT_b06FwRodataLen;
1954 fw.rodata_index = 0;
1955 fw.rodata = bnx2_TPAT_b06FwRodata;
1956
1957 load_cpu_fw(bp, &cpu_reg, &fw);
1958
1959 /* Initialize the Completion Processor. */
1960 cpu_reg.mode = BNX2_COM_CPU_MODE;
1961 cpu_reg.mode_value_halt = BNX2_COM_CPU_MODE_SOFT_HALT;
1962 cpu_reg.mode_value_sstep = BNX2_COM_CPU_MODE_STEP_ENA;
1963 cpu_reg.state = BNX2_COM_CPU_STATE;
1964 cpu_reg.state_value_clear = 0xffffff;
1965 cpu_reg.gpr0 = BNX2_COM_CPU_REG_FILE;
1966 cpu_reg.evmask = BNX2_COM_CPU_EVENT_MASK;
1967 cpu_reg.pc = BNX2_COM_CPU_PROGRAM_COUNTER;
1968 cpu_reg.inst = BNX2_COM_CPU_INSTRUCTION;
1969 cpu_reg.bp = BNX2_COM_CPU_HW_BREAKPOINT;
1970 cpu_reg.spad_base = BNX2_COM_SCRATCH;
1971 cpu_reg.mips_view_base = 0x8000000;
1972
1973 fw.ver_major = bnx2_COM_b06FwReleaseMajor;
1974 fw.ver_minor = bnx2_COM_b06FwReleaseMinor;
1975 fw.ver_fix = bnx2_COM_b06FwReleaseFix;
1976 fw.start_addr = bnx2_COM_b06FwStartAddr;
1977
1978 fw.text_addr = bnx2_COM_b06FwTextAddr;
1979 fw.text_len = bnx2_COM_b06FwTextLen;
1980 fw.text_index = 0;
1981 fw.text = bnx2_COM_b06FwText;
1982
1983 fw.data_addr = bnx2_COM_b06FwDataAddr;
1984 fw.data_len = bnx2_COM_b06FwDataLen;
1985 fw.data_index = 0;
1986 fw.data = bnx2_COM_b06FwData;
1987
1988 fw.sbss_addr = bnx2_COM_b06FwSbssAddr;
1989 fw.sbss_len = bnx2_COM_b06FwSbssLen;
1990 fw.sbss_index = 0;
1991 fw.sbss = bnx2_COM_b06FwSbss;
1992
1993 fw.bss_addr = bnx2_COM_b06FwBssAddr;
1994 fw.bss_len = bnx2_COM_b06FwBssLen;
1995 fw.bss_index = 0;
1996 fw.bss = bnx2_COM_b06FwBss;
1997
1998 fw.rodata_addr = bnx2_COM_b06FwRodataAddr;
1999 fw.rodata_len = bnx2_COM_b06FwRodataLen;
2000 fw.rodata_index = 0;
2001 fw.rodata = bnx2_COM_b06FwRodata;
2002
2003 load_cpu_fw(bp, &cpu_reg, &fw);
2004
2005 }
2006
2007 static int
2008 bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
2009 {
2010 u16 pmcsr;
2011
2012 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
2013
2014 switch (state) {
2015 case PCI_D0: {
2016 u32 val;
2017
2018 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
2019 (pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
2020 PCI_PM_CTRL_PME_STATUS);
2021
2022 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
2023 /* delay required during transition out of D3hot */
2024 msleep(20);
2025
2026 val = REG_RD(bp, BNX2_EMAC_MODE);
2027 val |= BNX2_EMAC_MODE_MPKT_RCVD | BNX2_EMAC_MODE_ACPI_RCVD;
2028 val &= ~BNX2_EMAC_MODE_MPKT;
2029 REG_WR(bp, BNX2_EMAC_MODE, val);
2030
2031 val = REG_RD(bp, BNX2_RPM_CONFIG);
2032 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
2033 REG_WR(bp, BNX2_RPM_CONFIG, val);
2034 break;
2035 }
2036 case PCI_D3hot: {
2037 int i;
2038 u32 val, wol_msg;
2039
2040 if (bp->wol) {
2041 u32 advertising;
2042 u8 autoneg;
2043
2044 autoneg = bp->autoneg;
2045 advertising = bp->advertising;
2046
2047 bp->autoneg = AUTONEG_SPEED;
2048 bp->advertising = ADVERTISED_10baseT_Half |
2049 ADVERTISED_10baseT_Full |
2050 ADVERTISED_100baseT_Half |
2051 ADVERTISED_100baseT_Full |
2052 ADVERTISED_Autoneg;
2053
2054 bnx2_setup_copper_phy(bp);
2055
2056 bp->autoneg = autoneg;
2057 bp->advertising = advertising;
2058
2059 bnx2_set_mac_addr(bp);
2060
2061 val = REG_RD(bp, BNX2_EMAC_MODE);
2062
2063 /* Enable port mode. */
2064 val &= ~BNX2_EMAC_MODE_PORT;
2065 val |= BNX2_EMAC_MODE_PORT_MII |
2066 BNX2_EMAC_MODE_MPKT_RCVD |
2067 BNX2_EMAC_MODE_ACPI_RCVD |
2068 BNX2_EMAC_MODE_FORCE_LINK |
2069 BNX2_EMAC_MODE_MPKT;
2070
2071 REG_WR(bp, BNX2_EMAC_MODE, val);
2072
2073 /* receive all multicast */
2074 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
2075 REG_WR(bp, BNX2_EMAC_MULTICAST_HASH0 + (i * 4),
2076 0xffffffff);
2077 }
2078 REG_WR(bp, BNX2_EMAC_RX_MODE,
2079 BNX2_EMAC_RX_MODE_SORT_MODE);
2080
2081 val = 1 | BNX2_RPM_SORT_USER0_BC_EN |
2082 BNX2_RPM_SORT_USER0_MC_EN;
2083 REG_WR(bp, BNX2_RPM_SORT_USER0, 0x0);
2084 REG_WR(bp, BNX2_RPM_SORT_USER0, val);
2085 REG_WR(bp, BNX2_RPM_SORT_USER0, val |
2086 BNX2_RPM_SORT_USER0_ENA);
2087
2088 /* Need to enable EMAC and RPM for WOL. */
2089 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2090 BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE |
2091 BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE |
2092 BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE);
2093
2094 val = REG_RD(bp, BNX2_RPM_CONFIG);
2095 val &= ~BNX2_RPM_CONFIG_ACPI_ENA;
2096 REG_WR(bp, BNX2_RPM_CONFIG, val);
2097
2098 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
2099 }
2100 else {
2101 wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
2102 }
2103
2104 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg);
2105
2106 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
2107 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
2108 (CHIP_ID(bp) == CHIP_ID_5706_A1)) {
2109
2110 if (bp->wol)
2111 pmcsr |= 3;
2112 }
2113 else {
2114 pmcsr |= 3;
2115 }
2116 if (bp->wol) {
2117 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
2118 }
2119 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
2120 pmcsr);
2121
2122 /* No more memory access after this point until
2123 * device is brought back to D0.
2124 */
2125 udelay(50);
2126 break;
2127 }
2128 default:
2129 return -EINVAL;
2130 }
2131 return 0;
2132 }
2133
2134 static int
2135 bnx2_acquire_nvram_lock(struct bnx2 *bp)
2136 {
2137 u32 val;
2138 int j;
2139
2140 /* Request access to the flash interface. */
2141 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_SET2);
2142 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2143 val = REG_RD(bp, BNX2_NVM_SW_ARB);
2144 if (val & BNX2_NVM_SW_ARB_ARB_ARB2)
2145 break;
2146
2147 udelay(5);
2148 }
2149
2150 if (j >= NVRAM_TIMEOUT_COUNT)
2151 return -EBUSY;
2152
2153 return 0;
2154 }
2155
2156 static int
2157 bnx2_release_nvram_lock(struct bnx2 *bp)
2158 {
2159 int j;
2160 u32 val;
2161
2162 /* Relinquish nvram interface. */
2163 REG_WR(bp, BNX2_NVM_SW_ARB, BNX2_NVM_SW_ARB_ARB_REQ_CLR2);
2164
2165 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2166 val = REG_RD(bp, BNX2_NVM_SW_ARB);
2167 if (!(val & BNX2_NVM_SW_ARB_ARB_ARB2))
2168 break;
2169
2170 udelay(5);
2171 }
2172
2173 if (j >= NVRAM_TIMEOUT_COUNT)
2174 return -EBUSY;
2175
2176 return 0;
2177 }
2178
2179
2180 static int
2181 bnx2_enable_nvram_write(struct bnx2 *bp)
2182 {
2183 u32 val;
2184
2185 val = REG_RD(bp, BNX2_MISC_CFG);
2186 REG_WR(bp, BNX2_MISC_CFG, val | BNX2_MISC_CFG_NVM_WR_EN_PCI);
2187
2188 if (!bp->flash_info->buffered) {
2189 int j;
2190
2191 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2192 REG_WR(bp, BNX2_NVM_COMMAND,
2193 BNX2_NVM_COMMAND_WREN | BNX2_NVM_COMMAND_DOIT);
2194
2195 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2196 udelay(5);
2197
2198 val = REG_RD(bp, BNX2_NVM_COMMAND);
2199 if (val & BNX2_NVM_COMMAND_DONE)
2200 break;
2201 }
2202
2203 if (j >= NVRAM_TIMEOUT_COUNT)
2204 return -EBUSY;
2205 }
2206 return 0;
2207 }
2208
2209 static void
2210 bnx2_disable_nvram_write(struct bnx2 *bp)
2211 {
2212 u32 val;
2213
2214 val = REG_RD(bp, BNX2_MISC_CFG);
2215 REG_WR(bp, BNX2_MISC_CFG, val & ~BNX2_MISC_CFG_NVM_WR_EN);
2216 }
2217
2218
2219 static void
2220 bnx2_enable_nvram_access(struct bnx2 *bp)
2221 {
2222 u32 val;
2223
2224 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
2225 /* Enable both bits, even on read. */
2226 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
2227 val | BNX2_NVM_ACCESS_ENABLE_EN | BNX2_NVM_ACCESS_ENABLE_WR_EN);
2228 }
2229
2230 static void
2231 bnx2_disable_nvram_access(struct bnx2 *bp)
2232 {
2233 u32 val;
2234
2235 val = REG_RD(bp, BNX2_NVM_ACCESS_ENABLE);
2236 /* Disable both bits, even after read. */
2237 REG_WR(bp, BNX2_NVM_ACCESS_ENABLE,
2238 val & ~(BNX2_NVM_ACCESS_ENABLE_EN |
2239 BNX2_NVM_ACCESS_ENABLE_WR_EN));
2240 }
2241
2242 static int
2243 bnx2_nvram_erase_page(struct bnx2 *bp, u32 offset)
2244 {
2245 u32 cmd;
2246 int j;
2247
2248 if (bp->flash_info->buffered)
2249 /* Buffered flash, no erase needed */
2250 return 0;
2251
2252 /* Build an erase command */
2253 cmd = BNX2_NVM_COMMAND_ERASE | BNX2_NVM_COMMAND_WR |
2254 BNX2_NVM_COMMAND_DOIT;
2255
2256 /* Need to clear DONE bit separately. */
2257 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2258
2259 /* Address of the NVRAM to read from. */
2260 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2261
2262 /* Issue an erase command. */
2263 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2264
2265 /* Wait for completion. */
2266 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2267 u32 val;
2268
2269 udelay(5);
2270
2271 val = REG_RD(bp, BNX2_NVM_COMMAND);
2272 if (val & BNX2_NVM_COMMAND_DONE)
2273 break;
2274 }
2275
2276 if (j >= NVRAM_TIMEOUT_COUNT)
2277 return -EBUSY;
2278
2279 return 0;
2280 }
2281
2282 static int
2283 bnx2_nvram_read_dword(struct bnx2 *bp, u32 offset, u8 *ret_val, u32 cmd_flags)
2284 {
2285 u32 cmd;
2286 int j;
2287
2288 /* Build the command word. */
2289 cmd = BNX2_NVM_COMMAND_DOIT | cmd_flags;
2290
2291 /* Calculate an offset of a buffered flash. */
2292 if (bp->flash_info->buffered) {
2293 offset = ((offset / bp->flash_info->page_size) <<
2294 bp->flash_info->page_bits) +
2295 (offset % bp->flash_info->page_size);
2296 }
2297
2298 /* Need to clear DONE bit separately. */
2299 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2300
2301 /* Address of the NVRAM to read from. */
2302 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2303
2304 /* Issue a read command. */
2305 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2306
2307 /* Wait for completion. */
2308 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2309 u32 val;
2310
2311 udelay(5);
2312
2313 val = REG_RD(bp, BNX2_NVM_COMMAND);
2314 if (val & BNX2_NVM_COMMAND_DONE) {
2315 val = REG_RD(bp, BNX2_NVM_READ);
2316
2317 val = be32_to_cpu(val);
2318 memcpy(ret_val, &val, 4);
2319 break;
2320 }
2321 }
2322 if (j >= NVRAM_TIMEOUT_COUNT)
2323 return -EBUSY;
2324
2325 return 0;
2326 }
2327
2328
2329 static int
2330 bnx2_nvram_write_dword(struct bnx2 *bp, u32 offset, u8 *val, u32 cmd_flags)
2331 {
2332 u32 cmd, val32;
2333 int j;
2334
2335 /* Build the command word. */
2336 cmd = BNX2_NVM_COMMAND_DOIT | BNX2_NVM_COMMAND_WR | cmd_flags;
2337
2338 /* Calculate an offset of a buffered flash. */
2339 if (bp->flash_info->buffered) {
2340 offset = ((offset / bp->flash_info->page_size) <<
2341 bp->flash_info->page_bits) +
2342 (offset % bp->flash_info->page_size);
2343 }
2344
2345 /* Need to clear DONE bit separately. */
2346 REG_WR(bp, BNX2_NVM_COMMAND, BNX2_NVM_COMMAND_DONE);
2347
2348 memcpy(&val32, val, 4);
2349 val32 = cpu_to_be32(val32);
2350
2351 /* Write the data. */
2352 REG_WR(bp, BNX2_NVM_WRITE, val32);
2353
2354 /* Address of the NVRAM to write to. */
2355 REG_WR(bp, BNX2_NVM_ADDR, offset & BNX2_NVM_ADDR_NVM_ADDR_VALUE);
2356
2357 /* Issue the write command. */
2358 REG_WR(bp, BNX2_NVM_COMMAND, cmd);
2359
2360 /* Wait for completion. */
2361 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2362 udelay(5);
2363
2364 if (REG_RD(bp, BNX2_NVM_COMMAND) & BNX2_NVM_COMMAND_DONE)
2365 break;
2366 }
2367 if (j >= NVRAM_TIMEOUT_COUNT)
2368 return -EBUSY;
2369
2370 return 0;
2371 }
2372
2373 static int
2374 bnx2_init_nvram(struct bnx2 *bp)
2375 {
2376 u32 val;
2377 int j, entry_count, rc;
2378 struct flash_spec *flash;
2379
2380 /* Determine the selected interface. */
2381 val = REG_RD(bp, BNX2_NVM_CFG1);
2382
2383 entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
2384
2385 rc = 0;
2386 if (val & 0x40000000) {
2387
2388 /* Flash interface has been reconfigured */
2389 for (j = 0, flash = &flash_table[0]; j < entry_count;
2390 j++, flash++) {
2391
2392 if (val == flash->config1) {
2393 bp->flash_info = flash;
2394 break;
2395 }
2396 }
2397 }
2398 else {
2399 /* Not yet been reconfigured */
2400
2401 for (j = 0, flash = &flash_table[0]; j < entry_count;
2402 j++, flash++) {
2403
2404 if ((val & FLASH_STRAP_MASK) == flash->strapping) {
2405 bp->flash_info = flash;
2406
2407 /* Request access to the flash interface. */
2408 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
2409 return rc;
2410
2411 /* Enable access to flash interface */
2412 bnx2_enable_nvram_access(bp);
2413
2414 /* Reconfigure the flash interface */
2415 REG_WR(bp, BNX2_NVM_CFG1, flash->config1);
2416 REG_WR(bp, BNX2_NVM_CFG2, flash->config2);
2417 REG_WR(bp, BNX2_NVM_CFG3, flash->config3);
2418 REG_WR(bp, BNX2_NVM_WRITE1, flash->write1);
2419
2420 /* Disable access to flash interface */
2421 bnx2_disable_nvram_access(bp);
2422 bnx2_release_nvram_lock(bp);
2423
2424 break;
2425 }
2426 }
2427 } /* if (val & 0x40000000) */
2428
2429 if (j == entry_count) {
2430 bp->flash_info = NULL;
2431 printk(KERN_ALERT "Unknown flash/EEPROM type.\n");
2432 rc = -ENODEV;
2433 }
2434
2435 return rc;
2436 }
2437
2438 static int
2439 bnx2_nvram_read(struct bnx2 *bp, u32 offset, u8 *ret_buf,
2440 int buf_size)
2441 {
2442 int rc = 0;
2443 u32 cmd_flags, offset32, len32, extra;
2444
2445 if (buf_size == 0)
2446 return 0;
2447
2448 /* Request access to the flash interface. */
2449 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
2450 return rc;
2451
2452 /* Enable access to flash interface */
2453 bnx2_enable_nvram_access(bp);
2454
2455 len32 = buf_size;
2456 offset32 = offset;
2457 extra = 0;
2458
2459 cmd_flags = 0;
2460
2461 if (offset32 & 3) {
2462 u8 buf[4];
2463 u32 pre_len;
2464
2465 offset32 &= ~3;
2466 pre_len = 4 - (offset & 3);
2467
2468 if (pre_len >= len32) {
2469 pre_len = len32;
2470 cmd_flags = BNX2_NVM_COMMAND_FIRST |
2471 BNX2_NVM_COMMAND_LAST;
2472 }
2473 else {
2474 cmd_flags = BNX2_NVM_COMMAND_FIRST;
2475 }
2476
2477 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
2478
2479 if (rc)
2480 return rc;
2481
2482 memcpy(ret_buf, buf + (offset & 3), pre_len);
2483
2484 offset32 += 4;
2485 ret_buf += pre_len;
2486 len32 -= pre_len;
2487 }
2488 if (len32 & 3) {
2489 extra = 4 - (len32 & 3);
2490 len32 = (len32 + 4) & ~3;
2491 }
2492
2493 if (len32 == 4) {
2494 u8 buf[4];
2495
2496 if (cmd_flags)
2497 cmd_flags = BNX2_NVM_COMMAND_LAST;
2498 else
2499 cmd_flags = BNX2_NVM_COMMAND_FIRST |
2500 BNX2_NVM_COMMAND_LAST;
2501
2502 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
2503
2504 memcpy(ret_buf, buf, 4 - extra);
2505 }
2506 else if (len32 > 0) {
2507 u8 buf[4];
2508
2509 /* Read the first word. */
2510 if (cmd_flags)
2511 cmd_flags = 0;
2512 else
2513 cmd_flags = BNX2_NVM_COMMAND_FIRST;
2514
2515 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, cmd_flags);
2516
2517 /* Advance to the next dword. */
2518 offset32 += 4;
2519 ret_buf += 4;
2520 len32 -= 4;
2521
2522 while (len32 > 4 && rc == 0) {
2523 rc = bnx2_nvram_read_dword(bp, offset32, ret_buf, 0);
2524
2525 /* Advance to the next dword. */
2526 offset32 += 4;
2527 ret_buf += 4;
2528 len32 -= 4;
2529 }
2530
2531 if (rc)
2532 return rc;
2533
2534 cmd_flags = BNX2_NVM_COMMAND_LAST;
2535 rc = bnx2_nvram_read_dword(bp, offset32, buf, cmd_flags);
2536
2537 memcpy(ret_buf, buf, 4 - extra);
2538 }
2539
2540 /* Disable access to flash interface */
2541 bnx2_disable_nvram_access(bp);
2542
2543 bnx2_release_nvram_lock(bp);
2544
2545 return rc;
2546 }
2547
2548 static int
2549 bnx2_nvram_write(struct bnx2 *bp, u32 offset, u8 *data_buf,
2550 int buf_size)
2551 {
2552 u32 written, offset32, len32;
2553 u8 *buf, start[4], end[4];
2554 int rc = 0;
2555 int align_start, align_end;
2556
2557 buf = data_buf;
2558 offset32 = offset;
2559 len32 = buf_size;
2560 align_start = align_end = 0;
2561
2562 if ((align_start = (offset32 & 3))) {
2563 offset32 &= ~3;
2564 len32 += align_start;
2565 if ((rc = bnx2_nvram_read(bp, offset32, start, 4)))
2566 return rc;
2567 }
2568
2569 if (len32 & 3) {
2570 if ((len32 > 4) || !align_start) {
2571 align_end = 4 - (len32 & 3);
2572 len32 += align_end;
2573 if ((rc = bnx2_nvram_read(bp, offset32 + len32 - 4,
2574 end, 4))) {
2575 return rc;
2576 }
2577 }
2578 }
2579
2580 if (align_start || align_end) {
2581 buf = kmalloc(len32, GFP_KERNEL);
2582 if (buf == 0)
2583 return -ENOMEM;
2584 if (align_start) {
2585 memcpy(buf, start, 4);
2586 }
2587 if (align_end) {
2588 memcpy(buf + len32 - 4, end, 4);
2589 }
2590 memcpy(buf + align_start, data_buf, buf_size);
2591 }
2592
2593 written = 0;
2594 while ((written < len32) && (rc == 0)) {
2595 u32 page_start, page_end, data_start, data_end;
2596 u32 addr, cmd_flags;
2597 int i;
2598 u8 flash_buffer[264];
2599
2600 /* Find the page_start addr */
2601 page_start = offset32 + written;
2602 page_start -= (page_start % bp->flash_info->page_size);
2603 /* Find the page_end addr */
2604 page_end = page_start + bp->flash_info->page_size;
2605 /* Find the data_start addr */
2606 data_start = (written == 0) ? offset32 : page_start;
2607 /* Find the data_end addr */
2608 data_end = (page_end > offset32 + len32) ?
2609 (offset32 + len32) : page_end;
2610
2611 /* Request access to the flash interface. */
2612 if ((rc = bnx2_acquire_nvram_lock(bp)) != 0)
2613 goto nvram_write_end;
2614
2615 /* Enable access to flash interface */
2616 bnx2_enable_nvram_access(bp);
2617
2618 cmd_flags = BNX2_NVM_COMMAND_FIRST;
2619 if (bp->flash_info->buffered == 0) {
2620 int j;
2621
2622 /* Read the whole page into the buffer
2623 * (non-buffer flash only) */
2624 for (j = 0; j < bp->flash_info->page_size; j += 4) {
2625 if (j == (bp->flash_info->page_size - 4)) {
2626 cmd_flags |= BNX2_NVM_COMMAND_LAST;
2627 }
2628 rc = bnx2_nvram_read_dword(bp,
2629 page_start + j,
2630 &flash_buffer[j],
2631 cmd_flags);
2632
2633 if (rc)
2634 goto nvram_write_end;
2635
2636 cmd_flags = 0;
2637 }
2638 }
2639
2640 /* Enable writes to flash interface (unlock write-protect) */
2641 if ((rc = bnx2_enable_nvram_write(bp)) != 0)
2642 goto nvram_write_end;
2643
2644 /* Erase the page */
2645 if ((rc = bnx2_nvram_erase_page(bp, page_start)) != 0)
2646 goto nvram_write_end;
2647
2648 /* Re-enable the write again for the actual write */
2649 bnx2_enable_nvram_write(bp);
2650
2651 /* Loop to write back the buffer data from page_start to
2652 * data_start */
2653 i = 0;
2654 if (bp->flash_info->buffered == 0) {
2655 for (addr = page_start; addr < data_start;
2656 addr += 4, i += 4) {
2657
2658 rc = bnx2_nvram_write_dword(bp, addr,
2659 &flash_buffer[i], cmd_flags);
2660
2661 if (rc != 0)
2662 goto nvram_write_end;
2663
2664 cmd_flags = 0;
2665 }
2666 }
2667
2668 /* Loop to write the new data from data_start to data_end */
2669 for (addr = data_start; addr < data_end; addr += 4, i++) {
2670 if ((addr == page_end - 4) ||
2671 ((bp->flash_info->buffered) &&
2672 (addr == data_end - 4))) {
2673
2674 cmd_flags |= BNX2_NVM_COMMAND_LAST;
2675 }
2676 rc = bnx2_nvram_write_dword(bp, addr, buf,
2677 cmd_flags);
2678
2679 if (rc != 0)
2680 goto nvram_write_end;
2681
2682 cmd_flags = 0;
2683 buf += 4;
2684 }
2685
2686 /* Loop to write back the buffer data from data_end
2687 * to page_end */
2688 if (bp->flash_info->buffered == 0) {
2689 for (addr = data_end; addr < page_end;
2690 addr += 4, i += 4) {
2691
2692 if (addr == page_end-4) {
2693 cmd_flags = BNX2_NVM_COMMAND_LAST;
2694 }
2695 rc = bnx2_nvram_write_dword(bp, addr,
2696 &flash_buffer[i], cmd_flags);
2697
2698 if (rc != 0)
2699 goto nvram_write_end;
2700
2701 cmd_flags = 0;
2702 }
2703 }
2704
2705 /* Disable writes to flash interface (lock write-protect) */
2706 bnx2_disable_nvram_write(bp);
2707
2708 /* Disable access to flash interface */
2709 bnx2_disable_nvram_access(bp);
2710 bnx2_release_nvram_lock(bp);
2711
2712 /* Increment written */
2713 written += data_end - data_start;
2714 }
2715
2716 nvram_write_end:
2717 if (align_start || align_end)
2718 kfree(buf);
2719 return rc;
2720 }
2721
2722 static int
2723 bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
2724 {
2725 u32 val;
2726 int i, rc = 0;
2727
2728 /* Wait for the current PCI transaction to complete before
2729 * issuing a reset. */
2730 REG_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
2731 BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
2732 BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
2733 BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
2734 BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
2735 val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
2736 udelay(5);
2737
2738 /* Deposit a driver reset signature so the firmware knows that
2739 * this is a soft reset. */
2740 REG_WR_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DRV_RESET_SIGNATURE,
2741 BNX2_DRV_RESET_SIGNATURE_MAGIC);
2742
2743 bp->fw_timed_out = 0;
2744
2745 /* Wait for the firmware to tell us it is ok to issue a reset. */
2746 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code);
2747
2748 /* Do a dummy read to force the chip to complete all current transaction
2749 * before we issue a reset. */
2750 val = REG_RD(bp, BNX2_MISC_ID);
2751
2752 val = BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
2753 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
2754 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
2755
2756 /* Chip reset. */
2757 REG_WR(bp, BNX2_PCICFG_MISC_CONFIG, val);
2758
2759 if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
2760 (CHIP_ID(bp) == CHIP_ID_5706_A1))
2761 msleep(15);
2762
2763 /* Reset takes approximate 30 usec */
2764 for (i = 0; i < 10; i++) {
2765 val = REG_RD(bp, BNX2_PCICFG_MISC_CONFIG);
2766 if ((val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
2767 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) {
2768 break;
2769 }
2770 udelay(10);
2771 }
2772
2773 if (val & (BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ |
2774 BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
2775 printk(KERN_ERR PFX "Chip reset did not complete\n");
2776 return -EBUSY;
2777 }
2778
2779 /* Make sure byte swapping is properly configured. */
2780 val = REG_RD(bp, BNX2_PCI_SWAP_DIAG0);
2781 if (val != 0x01020304) {
2782 printk(KERN_ERR PFX "Chip not in correct endian mode\n");
2783 return -ENODEV;
2784 }
2785
2786 bp->fw_timed_out = 0;
2787
2788 /* Wait for the firmware to finish its initialization. */
2789 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code);
2790
2791 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2792 /* Adjust the voltage regular to two steps lower. The default
2793 * of this register is 0x0000000e. */
2794 REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa);
2795
2796 /* Remove bad rbuf memory from the free pool. */
2797 rc = bnx2_alloc_bad_rbuf(bp);
2798 }
2799
2800 return rc;
2801 }
2802
2803 static int
2804 bnx2_init_chip(struct bnx2 *bp)
2805 {
2806 u32 val;
2807
2808 /* Make sure the interrupt is not active. */
2809 REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
2810
2811 val = BNX2_DMA_CONFIG_DATA_BYTE_SWAP |
2812 BNX2_DMA_CONFIG_DATA_WORD_SWAP |
2813 #ifdef __BIG_ENDIAN
2814 BNX2_DMA_CONFIG_CNTL_BYTE_SWAP |
2815 #endif
2816 BNX2_DMA_CONFIG_CNTL_WORD_SWAP |
2817 DMA_READ_CHANS << 12 |
2818 DMA_WRITE_CHANS << 16;
2819
2820 val |= (0x2 << 20) | (1 << 11);
2821
2822 if ((bp->flags & PCIX_FLAG) && (bp->bus_speed_mhz = 133))
2823 val |= (1 << 23);
2824
2825 if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
2826 (CHIP_ID(bp) != CHIP_ID_5706_A0) && !(bp->flags & PCIX_FLAG))
2827 val |= BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA;
2828
2829 REG_WR(bp, BNX2_DMA_CONFIG, val);
2830
2831 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
2832 val = REG_RD(bp, BNX2_TDMA_CONFIG);
2833 val |= BNX2_TDMA_CONFIG_ONE_DMA;
2834 REG_WR(bp, BNX2_TDMA_CONFIG, val);
2835 }
2836
2837 if (bp->flags & PCIX_FLAG) {
2838 u16 val16;
2839
2840 pci_read_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
2841 &val16);
2842 pci_write_config_word(bp->pdev, bp->pcix_cap + PCI_X_CMD,
2843 val16 & ~PCI_X_CMD_ERO);
2844 }
2845
2846 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS,
2847 BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
2848 BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
2849 BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
2850
2851 /* Initialize context mapping and zero out the quick contexts. The
2852 * context block must have already been enabled. */
2853 bnx2_init_context(bp);
2854
2855 bnx2_init_cpus(bp);
2856 bnx2_init_nvram(bp);
2857
2858 bnx2_set_mac_addr(bp);
2859
2860 val = REG_RD(bp, BNX2_MQ_CONFIG);
2861 val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
2862 val |= BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
2863 REG_WR(bp, BNX2_MQ_CONFIG, val);
2864
2865 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
2866 REG_WR(bp, BNX2_MQ_KNL_BYP_WIND_START, val);
2867 REG_WR(bp, BNX2_MQ_KNL_WIND_END, val);
2868
2869 val = (BCM_PAGE_BITS - 8) << 24;
2870 REG_WR(bp, BNX2_RV2P_CONFIG, val);
2871
2872 /* Configure page size. */
2873 val = REG_RD(bp, BNX2_TBDR_CONFIG);
2874 val &= ~BNX2_TBDR_CONFIG_PAGE_SIZE;
2875 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
2876 REG_WR(bp, BNX2_TBDR_CONFIG, val);
2877
2878 val = bp->mac_addr[0] +
2879 (bp->mac_addr[1] << 8) +
2880 (bp->mac_addr[2] << 16) +
2881 bp->mac_addr[3] +
2882 (bp->mac_addr[4] << 8) +
2883 (bp->mac_addr[5] << 16);
2884 REG_WR(bp, BNX2_EMAC_BACKOFF_SEED, val);
2885
2886 /* Program the MTU. Also include 4 bytes for CRC32. */
2887 val = bp->dev->mtu + ETH_HLEN + 4;
2888 if (val > (MAX_ETHERNET_PACKET_SIZE + 4))
2889 val |= BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA;
2890 REG_WR(bp, BNX2_EMAC_RX_MTU_SIZE, val);
2891
2892 bp->last_status_idx = 0;
2893 bp->rx_mode = BNX2_EMAC_RX_MODE_SORT_MODE;
2894
2895 /* Set up how to generate a link change interrupt. */
2896 REG_WR(bp, BNX2_EMAC_ATTENTION_ENA, BNX2_EMAC_ATTENTION_ENA_LINK);
2897
2898 REG_WR(bp, BNX2_HC_STATUS_ADDR_L,
2899 (u64) bp->status_blk_mapping & 0xffffffff);
2900 REG_WR(bp, BNX2_HC_STATUS_ADDR_H, (u64) bp->status_blk_mapping >> 32);
2901
2902 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_L,
2903 (u64) bp->stats_blk_mapping & 0xffffffff);
2904 REG_WR(bp, BNX2_HC_STATISTICS_ADDR_H,
2905 (u64) bp->stats_blk_mapping >> 32);
2906
2907 REG_WR(bp, BNX2_HC_TX_QUICK_CONS_TRIP,
2908 (bp->tx_quick_cons_trip_int << 16) | bp->tx_quick_cons_trip);
2909
2910 REG_WR(bp, BNX2_HC_RX_QUICK_CONS_TRIP,
2911 (bp->rx_quick_cons_trip_int << 16) | bp->rx_quick_cons_trip);
2912
2913 REG_WR(bp, BNX2_HC_COMP_PROD_TRIP,
2914 (bp->comp_prod_trip_int << 16) | bp->comp_prod_trip);
2915
2916 REG_WR(bp, BNX2_HC_TX_TICKS, (bp->tx_ticks_int << 16) | bp->tx_ticks);
2917
2918 REG_WR(bp, BNX2_HC_RX_TICKS, (bp->rx_ticks_int << 16) | bp->rx_ticks);
2919
2920 REG_WR(bp, BNX2_HC_COM_TICKS,
2921 (bp->com_ticks_int << 16) | bp->com_ticks);
2922
2923 REG_WR(bp, BNX2_HC_CMD_TICKS,
2924 (bp->cmd_ticks_int << 16) | bp->cmd_ticks);
2925
2926 REG_WR(bp, BNX2_HC_STATS_TICKS, bp->stats_ticks & 0xffff00);
2927 REG_WR(bp, BNX2_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
2928
2929 if (CHIP_ID(bp) == CHIP_ID_5706_A1)
2930 REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_COLLECT_STATS);
2931 else {
2932 REG_WR(bp, BNX2_HC_CONFIG, BNX2_HC_CONFIG_RX_TMR_MODE |
2933 BNX2_HC_CONFIG_TX_TMR_MODE |
2934 BNX2_HC_CONFIG_COLLECT_STATS);
2935 }
2936
2937 /* Clear internal stats counters. */
2938 REG_WR(bp, BNX2_HC_COMMAND, BNX2_HC_COMMAND_CLR_STAT_NOW);
2939
2940 REG_WR(bp, BNX2_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
2941
2942 /* Initialize the receive filter. */
2943 bnx2_set_rx_mode(bp->dev);
2944
2945 bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET);
2946
2947 REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, 0x5ffffff);
2948 REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
2949
2950 udelay(20);
2951
2952 return 0;
2953 }
2954
2955
2956 static void
2957 bnx2_init_tx_ring(struct bnx2 *bp)
2958 {
2959 struct tx_bd *txbd;
2960 u32 val;
2961
2962 txbd = &bp->tx_desc_ring[MAX_TX_DESC_CNT];
2963
2964 txbd->tx_bd_haddr_hi = (u64) bp->tx_desc_mapping >> 32;
2965 txbd->tx_bd_haddr_lo = (u64) bp->tx_desc_mapping & 0xffffffff;
2966
2967 bp->tx_prod = 0;
2968 bp->tx_cons = 0;
2969 bp->tx_prod_bseq = 0;
2970
2971 val = BNX2_L2CTX_TYPE_TYPE_L2;
2972 val |= BNX2_L2CTX_TYPE_SIZE_L2;
2973 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TYPE, val);
2974
2975 val = BNX2_L2CTX_CMD_TYPE_TYPE_L2;
2976 val |= 8 << 16;
2977 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_CMD_TYPE, val);
2978
2979 val = (u64) bp->tx_desc_mapping >> 32;
2980 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_HI, val);
2981
2982 val = (u64) bp->tx_desc_mapping & 0xffffffff;
2983 CTX_WR(bp, GET_CID_ADDR(TX_CID), BNX2_L2CTX_TBDR_BHADDR_LO, val);
2984 }
2985
2986 static void
2987 bnx2_init_rx_ring(struct bnx2 *bp)
2988 {
2989 struct rx_bd *rxbd;
2990 int i;
2991 u16 prod, ring_prod;
2992 u32 val;
2993
2994 /* 8 for CRC and VLAN */
2995 bp->rx_buf_use_size = bp->dev->mtu + ETH_HLEN + bp->rx_offset + 8;
2996 /* 8 for alignment */
2997 bp->rx_buf_size = bp->rx_buf_use_size + 8;
2998
2999 ring_prod = prod = bp->rx_prod = 0;
3000 bp->rx_cons = 0;
3001 bp->rx_prod_bseq = 0;
3002
3003 rxbd = &bp->rx_desc_ring[0];
3004 for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
3005 rxbd->rx_bd_len = bp->rx_buf_use_size;
3006 rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
3007 }
3008
3009 rxbd->rx_bd_haddr_hi = (u64) bp->rx_desc_mapping >> 32;
3010 rxbd->rx_bd_haddr_lo = (u64) bp->rx_desc_mapping & 0xffffffff;
3011
3012 val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
3013 val |= BNX2_L2CTX_CTX_TYPE_SIZE_L2;
3014 val |= 0x02 << 8;
3015 CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_CTX_TYPE, val);
3016
3017 val = (u64) bp->rx_desc_mapping >> 32;
3018 CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_HI, val);
3019
3020 val = (u64) bp->rx_desc_mapping & 0xffffffff;
3021 CTX_WR(bp, GET_CID_ADDR(RX_CID), BNX2_L2CTX_NX_BDHADDR_LO, val);
3022
3023 for ( ;ring_prod < bp->rx_ring_size; ) {
3024 if (bnx2_alloc_rx_skb(bp, ring_prod) < 0) {
3025 break;
3026 }
3027 prod = NEXT_RX_BD(prod);
3028 ring_prod = RX_RING_IDX(prod);
3029 }
3030 bp->rx_prod = prod;
3031
3032 REG_WR16(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BDIDX, prod);
3033
3034 REG_WR(bp, MB_RX_CID_ADDR + BNX2_L2CTX_HOST_BSEQ, bp->rx_prod_bseq);
3035 }
3036
3037 static void
3038 bnx2_free_tx_skbs(struct bnx2 *bp)
3039 {
3040 int i;
3041
3042 if (bp->tx_buf_ring == NULL)
3043 return;
3044
3045 for (i = 0; i < TX_DESC_CNT; ) {
3046 struct sw_bd *tx_buf = &bp->tx_buf_ring[i];
3047 struct sk_buff *skb = tx_buf->skb;
3048 int j, last;
3049
3050 if (skb == NULL) {
3051 i++;
3052 continue;
3053 }
3054
3055 pci_unmap_single(bp->pdev, pci_unmap_addr(tx_buf, mapping),
3056 skb_headlen(skb), PCI_DMA_TODEVICE);
3057
3058 tx_buf->skb = NULL;
3059
3060 last = skb_shinfo(skb)->nr_frags;
3061 for (j = 0; j < last; j++) {
3062 tx_buf = &bp->tx_buf_ring[i + j + 1];
3063 pci_unmap_page(bp->pdev,
3064 pci_unmap_addr(tx_buf, mapping),
3065 skb_shinfo(skb)->frags[j].size,
3066 PCI_DMA_TODEVICE);
3067 }
3068 dev_kfree_skb_any(skb);
3069 i += j + 1;
3070 }
3071
3072 }
3073
3074 static void
3075 bnx2_free_rx_skbs(struct bnx2 *bp)
3076 {
3077 int i;
3078
3079 if (bp->rx_buf_ring == NULL)
3080 return;
3081
3082 for (i = 0; i < RX_DESC_CNT; i++) {
3083 struct sw_bd *rx_buf = &bp->rx_buf_ring[i];
3084 struct sk_buff *skb = rx_buf->skb;
3085
3086 if (skb == 0)
3087 continue;
3088
3089 pci_unmap_single(bp->pdev, pci_unmap_addr(rx_buf, mapping),
3090 bp->rx_buf_use_size, PCI_DMA_FROMDEVICE);
3091
3092 rx_buf->skb = NULL;
3093
3094 dev_kfree_skb_any(skb);
3095 }
3096 }
3097
3098 static void
3099 bnx2_free_skbs(struct bnx2 *bp)
3100 {
3101 bnx2_free_tx_skbs(bp);
3102 bnx2_free_rx_skbs(bp);
3103 }
3104
3105 static int
3106 bnx2_reset_nic(struct bnx2 *bp, u32 reset_code)
3107 {
3108 int rc;
3109
3110 rc = bnx2_reset_chip(bp, reset_code);
3111 bnx2_free_skbs(bp);
3112 if (rc)
3113 return rc;
3114
3115 bnx2_init_chip(bp);
3116 bnx2_init_tx_ring(bp);
3117 bnx2_init_rx_ring(bp);
3118 return 0;
3119 }
3120
3121 static int
3122 bnx2_init_nic(struct bnx2 *bp)
3123 {
3124 int rc;
3125
3126 if ((rc = bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_RESET)) != 0)
3127 return rc;
3128
3129 bnx2_init_phy(bp);
3130 bnx2_set_link(bp);
3131 return 0;
3132 }
3133
3134 static int
3135 bnx2_test_registers(struct bnx2 *bp)
3136 {
3137 int ret;
3138 int i;
3139 static struct {
3140 u16 offset;
3141 u16 flags;
3142 u32 rw_mask;
3143 u32 ro_mask;
3144 } reg_tbl[] = {
3145 { 0x006c, 0, 0x00000000, 0x0000003f },
3146 { 0x0090, 0, 0xffffffff, 0x00000000 },
3147 { 0x0094, 0, 0x00000000, 0x00000000 },
3148
3149 { 0x0404, 0, 0x00003f00, 0x00000000 },
3150 { 0x0418, 0, 0x00000000, 0xffffffff },
3151 { 0x041c, 0, 0x00000000, 0xffffffff },
3152 { 0x0420, 0, 0x00000000, 0x80ffffff },
3153 { 0x0424, 0, 0x00000000, 0x00000000 },
3154 { 0x0428, 0, 0x00000000, 0x00000001 },
3155 { 0x0450, 0, 0x00000000, 0x0000ffff },
3156 { 0x0454, 0, 0x00000000, 0xffffffff },
3157 { 0x0458, 0, 0x00000000, 0xffffffff },
3158
3159 { 0x0808, 0, 0x00000000, 0xffffffff },
3160 { 0x0854, 0, 0x00000000, 0xffffffff },
3161 { 0x0868, 0, 0x00000000, 0x77777777 },
3162 { 0x086c, 0, 0x00000000, 0x77777777 },
3163 { 0x0870, 0, 0x00000000, 0x77777777 },
3164 { 0x0874, 0, 0x00000000, 0x77777777 },
3165
3166 { 0x0c00, 0, 0x00000000, 0x00000001 },
3167 { 0x0c04, 0, 0x00000000, 0x03ff0001 },
3168 { 0x0c08, 0, 0x0f0ff073, 0x00000000 },
3169 { 0x0c0c, 0, 0x00ffffff, 0x00000000 },
3170 { 0x0c30, 0, 0x00000000, 0xffffffff },
3171 { 0x0c34, 0, 0x00000000, 0xffffffff },
3172 { 0x0c38, 0, 0x00000000, 0xffffffff },
3173 { 0x0c3c, 0, 0x00000000, 0xffffffff },
3174 { 0x0c40, 0, 0x00000000, 0xffffffff },
3175 { 0x0c44, 0, 0x00000000, 0xffffffff },
3176 { 0x0c48, 0, 0x00000000, 0x0007ffff },
3177 { 0x0c4c, 0, 0x00000000, 0xffffffff },
3178 { 0x0c50, 0, 0x00000000, 0xffffffff },
3179 { 0x0c54, 0, 0x00000000, 0xffffffff },
3180 { 0x0c58, 0, 0x00000000, 0xffffffff },
3181 { 0x0c5c, 0, 0x00000000, 0xffffffff },
3182 { 0x0c60, 0, 0x00000000, 0xffffffff },
3183 { 0x0c64, 0, 0x00000000, 0xffffffff },
3184 { 0x0c68, 0, 0x00000000, 0xffffffff },
3185 { 0x0c6c, 0, 0x00000000, 0xffffffff },
3186 { 0x0c70, 0, 0x00000000, 0xffffffff },
3187 { 0x0c74, 0, 0x00000000, 0xffffffff },
3188 { 0x0c78, 0, 0x00000000, 0xffffffff },
3189 { 0x0c7c, 0, 0x00000000, 0xffffffff },
3190 { 0x0c80, 0, 0x00000000, 0xffffffff },
3191 { 0x0c84, 0, 0x00000000, 0xffffffff },
3192 { 0x0c88, 0, 0x00000000, 0xffffffff },
3193 { 0x0c8c, 0, 0x00000000, 0xffffffff },
3194 { 0x0c90, 0, 0x00000000, 0xffffffff },
3195 { 0x0c94, 0, 0x00000000, 0xffffffff },
3196 { 0x0c98, 0, 0x00000000, 0xffffffff },
3197 { 0x0c9c, 0, 0x00000000, 0xffffffff },
3198 { 0x0ca0, 0, 0x00000000, 0xffffffff },
3199 { 0x0ca4, 0, 0x00000000, 0xffffffff },
3200 { 0x0ca8, 0, 0x00000000, 0x0007ffff },
3201 { 0x0cac, 0, 0x00000000, 0xffffffff },
3202 { 0x0cb0, 0, 0x00000000, 0xffffffff },
3203 { 0x0cb4, 0, 0x00000000, 0xffffffff },
3204 { 0x0cb8, 0, 0x00000000, 0xffffffff },
3205 { 0x0cbc, 0, 0x00000000, 0xffffffff },
3206 { 0x0cc0, 0, 0x00000000, 0xffffffff },
3207 { 0x0cc4, 0, 0x00000000, 0xffffffff },
3208 { 0x0cc8, 0, 0x00000000, 0xffffffff },
3209 { 0x0ccc, 0, 0x00000000, 0xffffffff },
3210 { 0x0cd0, 0, 0x00000000, 0xffffffff },
3211 { 0x0cd4, 0, 0x00000000, 0xffffffff },
3212 { 0x0cd8, 0, 0x00000000, 0xffffffff },
3213 { 0x0cdc, 0, 0x00000000, 0xffffffff },
3214 { 0x0ce0, 0, 0x00000000, 0xffffffff },
3215 { 0x0ce4, 0, 0x00000000, 0xffffffff },
3216 { 0x0ce8, 0, 0x00000000, 0xffffffff },
3217 { 0x0cec, 0, 0x00000000, 0xffffffff },
3218 { 0x0cf0, 0, 0x00000000, 0xffffffff },
3219 { 0x0cf4, 0, 0x00000000, 0xffffffff },
3220 { 0x0cf8, 0, 0x00000000, 0xffffffff },
3221 { 0x0cfc, 0, 0x00000000, 0xffffffff },
3222 { 0x0d00, 0, 0x00000000, 0xffffffff },
3223 { 0x0d04, 0, 0x00000000, 0xffffffff },
3224
3225 { 0x1000, 0, 0x00000000, 0x00000001 },
3226 { 0x1004, 0, 0x00000000, 0x000f0001 },
3227 { 0x1044, 0, 0x00000000, 0xffc003ff },
3228 { 0x1080, 0, 0x00000000, 0x0001ffff },
3229 { 0x1084, 0, 0x00000000, 0xffffffff },
3230 { 0x1088, 0, 0x00000000, 0xffffffff },
3231 { 0x108c, 0, 0x00000000, 0xffffffff },
3232 { 0x1090, 0, 0x00000000, 0xffffffff },
3233 { 0x1094, 0, 0x00000000, 0xffffffff },
3234 { 0x1098, 0, 0x00000000, 0xffffffff },
3235 { 0x109c, 0, 0x00000000, 0xffffffff },
3236 { 0x10a0, 0, 0x00000000, 0xffffffff },
3237
3238 { 0x1408, 0, 0x01c00800, 0x00000000 },
3239 { 0x149c, 0, 0x8000ffff, 0x00000000 },
3240 { 0x14a8, 0, 0x00000000, 0x000001ff },
3241 { 0x14ac, 0, 0x4fffffff, 0x10000000 },
3242 { 0x14b0, 0, 0x00000002, 0x00000001 },
3243 { 0x14b8, 0, 0x00000000, 0x00000000 },
3244 { 0x14c0, 0, 0x00000000, 0x00000009 },
3245 { 0x14c4, 0, 0x00003fff, 0x00000000 },
3246 { 0x14cc, 0, 0x00000000, 0x00000001 },
3247 { 0x14d0, 0, 0xffffffff, 0x00000000 },
3248 { 0x1500, 0, 0x00000000, 0xffffffff },
3249 { 0x1504, 0, 0x00000000, 0xffffffff },
3250 { 0x1508, 0, 0x00000000, 0xffffffff },
3251 { 0x150c, 0, 0x00000000, 0xffffffff },
3252 { 0x1510, 0, 0x00000000, 0xffffffff },
3253 { 0x1514, 0, 0x00000000, 0xffffffff },
3254 { 0x1518, 0, 0x00000000, 0xffffffff },
3255 { 0x151c, 0, 0x00000000, 0xffffffff },
3256 { 0x1520, 0, 0x00000000, 0xffffffff },
3257 { 0x1524, 0, 0x00000000, 0xffffffff },
3258 { 0x1528, 0, 0x00000000, 0xffffffff },
3259 { 0x152c, 0, 0x00000000, 0xffffffff },
3260 { 0x1530, 0, 0x00000000, 0xffffffff },
3261 { 0x1534, 0, 0x00000000, 0xffffffff },
3262 { 0x1538, 0, 0x00000000, 0xffffffff },
3263 { 0x153c, 0, 0x00000000, 0xffffffff },
3264 { 0x1540, 0, 0x00000000, 0xffffffff },
3265 { 0x1544, 0, 0x00000000, 0xffffffff },
3266 { 0x1548, 0, 0x00000000, 0xffffffff },
3267 { 0x154c, 0, 0x00000000, 0xffffffff },
3268 { 0x1550, 0, 0x00000000, 0xffffffff },
3269 { 0x1554, 0, 0x00000000, 0xffffffff },
3270 { 0x1558, 0, 0x00000000, 0xffffffff },
3271 { 0x1600, 0, 0x00000000, 0xffffffff },
3272 { 0x1604, 0, 0x00000000, 0xffffffff },
3273 { 0x1608, 0, 0x00000000, 0xffffffff },
3274 { 0x160c, 0, 0x00000000, 0xffffffff },
3275 { 0x1610, 0, 0x00000000, 0xffffffff },
3276 { 0x1614, 0, 0x00000000, 0xffffffff },
3277 { 0x1618, 0, 0x00000000, 0xffffffff },
3278 { 0x161c, 0, 0x00000000, 0xffffffff },
3279 { 0x1620, 0, 0x00000000, 0xffffffff },
3280 { 0x1624, 0, 0x00000000, 0xffffffff },
3281 { 0x1628, 0, 0x00000000, 0xffffffff },
3282 { 0x162c, 0, 0x00000000, 0xffffffff },
3283 { 0x1630, 0, 0x00000000, 0xffffffff },
3284 { 0x1634, 0, 0x00000000, 0xffffffff },
3285 { 0x1638, 0, 0x00000000, 0xffffffff },
3286 { 0x163c, 0, 0x00000000, 0xffffffff },
3287 { 0x1640, 0, 0x00000000, 0xffffffff },
3288 { 0x1644, 0, 0x00000000, 0xffffffff },
3289 { 0x1648, 0, 0x00000000, 0xffffffff },
3290 { 0x164c, 0, 0x00000000, 0xffffffff },
3291 { 0x1650, 0, 0x00000000, 0xffffffff },
3292 { 0x1654, 0, 0x00000000, 0xffffffff },
3293
3294 { 0x1800, 0, 0x00000000, 0x00000001 },
3295 { 0x1804, 0, 0x00000000, 0x00000003 },
3296 { 0x1840, 0, 0x00000000, 0xffffffff },
3297 { 0x1844, 0, 0x00000000, 0xffffffff },
3298 { 0x1848, 0, 0x00000000, 0xffffffff },
3299 { 0x184c, 0, 0x00000000, 0xffffffff },
3300 { 0x1850, 0, 0x00000000, 0xffffffff },
3301 { 0x1900, 0, 0x7ffbffff, 0x00000000 },
3302 { 0x1904, 0, 0xffffffff, 0x00000000 },
3303 { 0x190c, 0, 0xffffffff, 0x00000000 },
3304 { 0x1914, 0, 0xffffffff, 0x00000000 },
3305 { 0x191c, 0, 0xffffffff, 0x00000000 },
3306 { 0x1924, 0, 0xffffffff, 0x00000000 },
3307 { 0x192c, 0, 0xffffffff, 0x00000000 },
3308 { 0x1934, 0, 0xffffffff, 0x00000000 },
3309 { 0x193c, 0, 0xffffffff, 0x00000000 },
3310 { 0x1944, 0, 0xffffffff, 0x00000000 },
3311 { 0x194c, 0, 0xffffffff, 0x00000000 },
3312 { 0x1954, 0, 0xffffffff, 0x00000000 },
3313 { 0x195c, 0, 0xffffffff, 0x00000000 },
3314 { 0x1964, 0, 0xffffffff, 0x00000000 },
3315 { 0x196c, 0, 0xffffffff, 0x00000000 },
3316 { 0x1974, 0, 0xffffffff, 0x00000000 },
3317 { 0x197c, 0, 0xffffffff, 0x00000000 },
3318 { 0x1980, 0, 0x0700ffff, 0x00000000 },
3319
3320 { 0x1c00, 0, 0x00000000, 0x00000001 },
3321 { 0x1c04, 0, 0x00000000, 0x00000003 },
3322 { 0x1c08, 0, 0x0000000f, 0x00000000 },
3323 { 0x1c40, 0, 0x00000000, 0xffffffff },
3324 { 0x1c44, 0, 0x00000000, 0xffffffff },
3325 { 0x1c48, 0, 0x00000000, 0xffffffff },
3326 { 0x1c4c, 0, 0x00000000, 0xffffffff },
3327 { 0x1c50, 0, 0x00000000, 0xffffffff },
3328 { 0x1d00, 0, 0x7ffbffff, 0x00000000 },
3329 { 0x1d04, 0, 0xffffffff, 0x00000000 },
3330 { 0x1d0c, 0, 0xffffffff, 0x00000000 },
3331 { 0x1d14, 0, 0xffffffff, 0x00000000 },
3332 { 0x1d1c, 0, 0xffffffff, 0x00000000 },
3333 { 0x1d24, 0, 0xffffffff, 0x00000000 },
3334 { 0x1d2c, 0, 0xffffffff, 0x00000000 },
3335 { 0x1d34, 0, 0xffffffff, 0x00000000 },
3336 { 0x1d3c, 0, 0xffffffff, 0x00000000 },
3337 { 0x1d44, 0, 0xffffffff, 0x00000000 },
3338 { 0x1d4c, 0, 0xffffffff, 0x00000000 },
3339 { 0x1d54, 0, 0xffffffff, 0x00000000 },
3340 { 0x1d5c, 0, 0xffffffff, 0x00000000 },
3341 { 0x1d64, 0, 0xffffffff, 0x00000000 },
3342 { 0x1d6c, 0, 0xffffffff, 0x00000000 },
3343 { 0x1d74, 0, 0xffffffff, 0x00000000 },
3344 { 0x1d7c, 0, 0xffffffff, 0x00000000 },
3345 { 0x1d80, 0, 0x0700ffff, 0x00000000 },
3346
3347 { 0x2004, 0, 0x00000000, 0x0337000f },
3348 { 0x2008, 0, 0xffffffff, 0x00000000 },
3349 { 0x200c, 0, 0xffffffff, 0x00000000 },
3350 { 0x2010, 0, 0xffffffff, 0x00000000 },
3351 { 0x2014, 0, 0x801fff80, 0x00000000 },
3352 { 0x2018, 0, 0x000003ff, 0x00000000 },
3353
3354 { 0x2800, 0, 0x00000000, 0x00000001 },
3355 { 0x2804, 0, 0x00000000, 0x00003f01 },
3356 { 0x2808, 0, 0x0f3f3f03, 0x00000000 },
3357 { 0x2810, 0, 0xffff0000, 0x00000000 },
3358 { 0x2814, 0, 0xffff0000, 0x00000000 },
3359 { 0x2818, 0, 0xffff0000, 0x00000000 },
3360 { 0x281c, 0, 0xffff0000, 0x00000000 },
3361 { 0x2834, 0, 0xffffffff, 0x00000000 },
3362 { 0x2840, 0, 0x00000000, 0xffffffff },
3363 { 0x2844, 0, 0x00000000, 0xffffffff },
3364 { 0x2848, 0, 0xffffffff, 0x00000000 },
3365 { 0x284c, 0, 0xf800f800, 0x07ff07ff },
3366
3367 { 0x2c00, 0, 0x00000000, 0x00000011 },
3368 { 0x2c04, 0, 0x00000000, 0x00030007 },
3369
3370 { 0x3000, 0, 0x00000000, 0x00000001 },
3371 { 0x3004, 0, 0x00000000, 0x007007ff },
3372 { 0x3008, 0, 0x00000003, 0x00000000 },
3373 { 0x300c, 0, 0xffffffff, 0x00000000 },
3374 { 0x3010, 0, 0xffffffff, 0x00000000 },
3375 { 0x3014, 0, 0xffffffff, 0x00000000 },
3376 { 0x3034, 0, 0xffffffff, 0x00000000 },
3377 { 0x3038, 0, 0xffffffff, 0x00000000 },
3378 { 0x3050, 0, 0x00000001, 0x00000000 },
3379
3380 { 0x3c00, 0, 0x00000000, 0x00000001 },
3381 { 0x3c04, 0, 0x00000000, 0x00070000 },
3382 { 0x3c08, 0, 0x00007f71, 0x07f00000 },
3383 { 0x3c0c, 0, 0x1f3ffffc, 0x00000000 },
3384 { 0x3c10, 0, 0xffffffff, 0x00000000 },
3385 { 0x3c14, 0, 0x00000000, 0xffffffff },
3386 { 0x3c18, 0, 0x00000000, 0xffffffff },
3387 { 0x3c1c, 0, 0xfffff000, 0x00000000 },
3388 { 0x3c20, 0, 0xffffff00, 0x00000000 },
3389 { 0x3c24, 0, 0xffffffff, 0x00000000 },
3390 { 0x3c28, 0, 0xffffffff, 0x00000000 },
3391 { 0x3c2c, 0, 0xffffffff, 0x00000000 },
3392 { 0x3c30, 0, 0xffffffff, 0x00000000 },
3393 { 0x3c34, 0, 0xffffffff, 0x00000000 },
3394 { 0x3c38, 0, 0xffffffff, 0x00000000 },
3395 { 0x3c3c, 0, 0xffffffff, 0x00000000 },
3396 { 0x3c40, 0, 0xffffffff, 0x00000000 },
3397 { 0x3c44, 0, 0xffffffff, 0x00000000 },
3398 { 0x3c48, 0, 0xffffffff, 0x00000000 },
3399 { 0x3c4c, 0, 0xffffffff, 0x00000000 },
3400 { 0x3c50, 0, 0xffffffff, 0x00000000 },
3401 { 0x3c54, 0, 0xffffffff, 0x00000000 },
3402 { 0x3c58, 0, 0xffffffff, 0x00000000 },
3403 { 0x3c5c, 0, 0xffffffff, 0x00000000 },
3404 { 0x3c60, 0, 0xffffffff, 0x00000000 },
3405 { 0x3c64, 0, 0xffffffff, 0x00000000 },
3406 { 0x3c68, 0, 0xffffffff, 0x00000000 },
3407 { 0x3c6c, 0, 0xffffffff, 0x00000000 },
3408 { 0x3c70, 0, 0xffffffff, 0x00000000 },
3409 { 0x3c74, 0, 0x0000003f, 0x00000000 },
3410 { 0x3c78, 0, 0x00000000, 0x00000000 },
3411 { 0x3c7c, 0, 0x00000000, 0x00000000 },
3412 { 0x3c80, 0, 0x3fffffff, 0x00000000 },
3413 { 0x3c84, 0, 0x0000003f, 0x00000000 },
3414 { 0x3c88, 0, 0x00000000, 0xffffffff },
3415 { 0x3c8c, 0, 0x00000000, 0xffffffff },
3416
3417 { 0x4000, 0, 0x00000000, 0x00000001 },
3418 { 0x4004, 0, 0x00000000, 0x00030000 },
3419 { 0x4008, 0, 0x00000ff0, 0x00000000 },
3420 { 0x400c, 0, 0xffffffff, 0x00000000 },
3421 { 0x4088, 0, 0x00000000, 0x00070303 },
3422
3423 { 0x4400, 0, 0x00000000, 0x00000001 },
3424 { 0x4404, 0, 0x00000000, 0x00003f01 },
3425 { 0x4408, 0, 0x7fff00ff, 0x00000000 },
3426 { 0x440c, 0, 0xffffffff, 0x00000000 },
3427 { 0x4410, 0, 0xffff, 0x0000 },
3428 { 0x4414, 0, 0xffff, 0x0000 },
3429 { 0x4418, 0, 0xffff, 0x0000 },
3430 { 0x441c, 0, 0xffff, 0x0000 },
3431 { 0x4428, 0, 0xffffffff, 0x00000000 },
3432 { 0x442c, 0, 0xffffffff, 0x00000000 },
3433 { 0x4430, 0, 0xffffffff, 0x00000000 },
3434 { 0x4434, 0, 0xffffffff, 0x00000000 },
3435 { 0x4438, 0, 0xffffffff, 0x00000000 },
3436 { 0x443c, 0, 0xffffffff, 0x00000000 },
3437 { 0x4440, 0, 0xffffffff, 0x00000000 },
3438 { 0x4444, 0, 0xffffffff, 0x00000000 },
3439
3440 { 0x4c00, 0, 0x00000000, 0x00000001 },
3441 { 0x4c04, 0, 0x00000000, 0x0000003f },
3442 { 0x4c08, 0, 0xffffffff, 0x00000000 },
3443 { 0x4c0c, 0, 0x0007fc00, 0x00000000 },
3444 { 0x4c10, 0, 0x80003fe0, 0x00000000 },
3445 { 0x4c14, 0, 0xffffffff, 0x00000000 },
3446 { 0x4c44, 0, 0x00000000, 0x9fff9fff },
3447 { 0x4c48, 0, 0x00000000, 0xb3009fff },
3448 { 0x4c4c, 0, 0x00000000, 0x77f33b30 },
3449 { 0x4c50, 0, 0x00000000, 0xffffffff },
3450
3451 { 0x5004, 0, 0x00000000, 0x0000007f },
3452 { 0x5008, 0, 0x0f0007ff, 0x00000000 },
3453 { 0x500c, 0, 0xf800f800, 0x07ff07ff },
3454
3455 { 0x5400, 0, 0x00000008, 0x00000001 },
3456 { 0x5404, 0, 0x00000000, 0x0000003f },
3457 { 0x5408, 0, 0x0000001f, 0x00000000 },
3458 { 0x540c, 0, 0xffffffff, 0x00000000 },
3459 { 0x5410, 0, 0xffffffff, 0x00000000 },
3460 { 0x5414, 0, 0x0000ffff, 0x00000000 },
3461 { 0x5418, 0, 0x0000ffff, 0x00000000 },
3462 { 0x541c, 0, 0x0000ffff, 0x00000000 },
3463 { 0x5420, 0, 0x0000ffff, 0x00000000 },
3464 { 0x5428, 0, 0x000000ff, 0x00000000 },
3465 { 0x542c, 0, 0xff00ffff, 0x00000000 },
3466 { 0x5430, 0, 0x001fff80, 0x00000000 },
3467 { 0x5438, 0, 0xffffffff, 0x00000000 },
3468 { 0x543c, 0, 0xffffffff, 0x00000000 },
3469 { 0x5440, 0, 0xf800f800, 0x07ff07ff },
3470
3471 { 0x5c00, 0, 0x00000000, 0x00000001 },
3472 { 0x5c04, 0, 0x00000000, 0x0003000f },
3473 { 0x5c08, 0, 0x00000003, 0x00000000 },
3474 { 0x5c0c, 0, 0x0000fff8, 0x00000000 },
3475 { 0x5c10, 0, 0x00000000, 0xffffffff },
3476 { 0x5c80, 0, 0x00000000, 0x0f7113f1 },
3477 { 0x5c84, 0, 0x00000000, 0x0000f333 },
3478 { 0x5c88, 0, 0x00000000, 0x00077373 },
3479 { 0x5c8c, 0, 0x00000000, 0x0007f737 },
3480
3481 { 0x6808, 0, 0x0000ff7f, 0x00000000 },
3482 { 0x680c, 0, 0xffffffff, 0x00000000 },
3483 { 0x6810, 0, 0xffffffff, 0x00000000 },
3484 { 0x6814, 0, 0xffffffff, 0x00000000 },
3485 { 0x6818, 0, 0xffffffff, 0x00000000 },
3486 { 0x681c, 0, 0xffffffff, 0x00000000 },
3487 { 0x6820, 0, 0x00ff00ff, 0x00000000 },
3488 { 0x6824, 0, 0x00ff00ff, 0x00000000 },
3489 { 0x6828, 0, 0x00ff00ff, 0x00000000 },
3490 { 0x682c, 0, 0x03ff03ff, 0x00000000 },
3491 { 0x6830, 0, 0x03ff03ff, 0x00000000 },
3492 { 0x6834, 0, 0x03ff03ff, 0x00000000 },
3493 { 0x6838, 0, 0x03ff03ff, 0x00000000 },
3494 { 0x683c, 0, 0x0000ffff, 0x00000000 },
3495 { 0x6840, 0, 0x00000ff0, 0x00000000 },
3496 { 0x6844, 0, 0x00ffff00, 0x00000000 },
3497 { 0x684c, 0, 0xffffffff, 0x00000000 },
3498 { 0x6850, 0, 0x7f7f7f7f, 0x00000000 },
3499 { 0x6854, 0, 0x7f7f7f7f, 0x00000000 },
3500 { 0x6858, 0, 0x7f7f7f7f, 0x00000000 },
3501 { 0x685c, 0, 0x7f7f7f7f, 0x00000000 },
3502 { 0x6908, 0, 0x00000000, 0x0001ff0f },
3503 { 0x690c, 0, 0x00000000, 0x0ffe00f0 },
3504
3505 { 0xffff, 0, 0x00000000, 0x00000000 },
3506 };
3507
3508 ret = 0;
3509 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
3510 u32 offset, rw_mask, ro_mask, save_val, val;
3511
3512 offset = (u32) reg_tbl[i].offset;
3513 rw_mask = reg_tbl[i].rw_mask;
3514 ro_mask = reg_tbl[i].ro_mask;
3515
3516 save_val = readl(bp->regview + offset);
3517
3518 writel(0, bp->regview + offset);
3519
3520 val = readl(bp->regview + offset);
3521 if ((val & rw_mask) != 0) {
3522 goto reg_test_err;
3523 }
3524
3525 if ((val & ro_mask) != (save_val & ro_mask)) {
3526 goto reg_test_err;
3527 }
3528
3529 writel(0xffffffff, bp->regview + offset);
3530
3531 val = readl(bp->regview + offset);
3532 if ((val & rw_mask) != rw_mask) {
3533 goto reg_test_err;
3534 }
3535
3536 if ((val & ro_mask) != (save_val & ro_mask)) {
3537 goto reg_test_err;
3538 }
3539
3540 writel(save_val, bp->regview + offset);
3541 continue;
3542
3543 reg_test_err:
3544 writel(save_val, bp->regview + offset);
3545 ret = -ENODEV;
3546 break;
3547 }
3548 return ret;
3549 }
3550
3551 static int
3552 bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
3553 {
3554 static u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
3555 0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
3556 int i;
3557
3558 for (i = 0; i < sizeof(test_pattern) / 4; i++) {
3559 u32 offset;
3560
3561 for (offset = 0; offset < size; offset += 4) {
3562
3563 REG_WR_IND(bp, start + offset, test_pattern[i]);
3564
3565 if (REG_RD_IND(bp, start + offset) !=
3566 test_pattern[i]) {
3567 return -ENODEV;
3568 }
3569 }
3570 }
3571 return 0;
3572 }
3573
3574 static int
3575 bnx2_test_memory(struct bnx2 *bp)
3576 {
3577 int ret = 0;
3578 int i;
3579 static struct {
3580 u32 offset;
3581 u32 len;
3582 } mem_tbl[] = {
3583 { 0x60000, 0x4000 },
3584 { 0xa0000, 0x4000 },
3585 { 0xe0000, 0x4000 },
3586 { 0x120000, 0x4000 },
3587 { 0x1a0000, 0x4000 },
3588 { 0x160000, 0x4000 },
3589 { 0xffffffff, 0 },
3590 };
3591
3592 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
3593 if ((ret = bnx2_do_mem_test(bp, mem_tbl[i].offset,
3594 mem_tbl[i].len)) != 0) {
3595 return ret;
3596 }
3597 }
3598
3599 return ret;
3600 }
3601
3602 static int
3603 bnx2_test_loopback(struct bnx2 *bp)
3604 {
3605 unsigned int pkt_size, num_pkts, i;
3606 struct sk_buff *skb, *rx_skb;
3607 unsigned char *packet;
3608 u16 rx_start_idx, rx_idx, send_idx;
3609 u32 send_bseq, val;
3610 dma_addr_t map;
3611 struct tx_bd *txbd;
3612 struct sw_bd *rx_buf;
3613 struct l2_fhdr *rx_hdr;
3614 int ret = -ENODEV;
3615
3616 if (!netif_running(bp->dev))
3617 return -ENODEV;
3618
3619 bp->loopback = MAC_LOOPBACK;
3620 bnx2_reset_nic(bp, BNX2_DRV_MSG_CODE_DIAG);
3621 bnx2_set_mac_loopback(bp);
3622
3623 pkt_size = 1514;
3624 skb = dev_alloc_skb(pkt_size);
3625 packet = skb_put(skb, pkt_size);
3626 memcpy(packet, bp->mac_addr, 6);
3627 memset(packet + 6, 0x0, 8);
3628 for (i = 14; i < pkt_size; i++)
3629 packet[i] = (unsigned char) (i & 0xff);
3630
3631 map = pci_map_single(bp->pdev, skb->data, pkt_size,
3632 PCI_DMA_TODEVICE);
3633
3634 val = REG_RD(bp, BNX2_HC_COMMAND);
3635 REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3636 REG_RD(bp, BNX2_HC_COMMAND);
3637
3638 udelay(5);
3639 rx_start_idx = bp->status_blk->status_rx_quick_consumer_index0;
3640
3641 send_idx = 0;
3642 send_bseq = 0;
3643 num_pkts = 0;
3644
3645 txbd = &bp->tx_desc_ring[send_idx];
3646
3647 txbd->tx_bd_haddr_hi = (u64) map >> 32;
3648 txbd->tx_bd_haddr_lo = (u64) map & 0xffffffff;
3649 txbd->tx_bd_mss_nbytes = pkt_size;
3650 txbd->tx_bd_vlan_tag_flags = TX_BD_FLAGS_START | TX_BD_FLAGS_END;
3651
3652 num_pkts++;
3653 send_idx = NEXT_TX_BD(send_idx);
3654
3655 send_bseq += pkt_size;
3656
3657 REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, send_idx);
3658 REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, send_bseq);
3659
3660
3661 udelay(100);
3662
3663 val = REG_RD(bp, BNX2_HC_COMMAND);
3664 REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
3665 REG_RD(bp, BNX2_HC_COMMAND);
3666
3667 udelay(5);
3668
3669 pci_unmap_single(bp->pdev, map, pkt_size, PCI_DMA_TODEVICE);
3670 dev_kfree_skb_irq(skb);
3671
3672 if (bp->status_blk->status_tx_quick_consumer_index0 != send_idx) {
3673 goto loopback_test_done;
3674 }
3675
3676 rx_idx = bp->status_blk->status_rx_quick_consumer_index0;
3677 if (rx_idx != rx_start_idx + num_pkts) {
3678 goto loopback_test_done;
3679 }
3680
3681 rx_buf = &bp->rx_buf_ring[rx_start_idx];
3682 rx_skb = rx_buf->skb;
3683
3684 rx_hdr = (struct l2_fhdr *) rx_skb->data;
3685 skb_reserve(rx_skb, bp->rx_offset);
3686
3687 pci_dma_sync_single_for_cpu(bp->pdev,
3688 pci_unmap_addr(rx_buf, mapping),
3689 bp->rx_buf_size, PCI_DMA_FROMDEVICE);
3690
3691 if (rx_hdr->l2_fhdr_errors &
3692 (L2_FHDR_ERRORS_BAD_CRC |
3693 L2_FHDR_ERRORS_PHY_DECODE |
3694 L2_FHDR_ERRORS_ALIGNMENT |
3695 L2_FHDR_ERRORS_TOO_SHORT |
3696 L2_FHDR_ERRORS_GIANT_FRAME)) {
3697
3698 goto loopback_test_done;
3699 }
3700
3701 if ((rx_hdr->l2_fhdr_pkt_len - 4) != pkt_size) {
3702 goto loopback_test_done;
3703 }
3704
3705 for (i = 14; i < pkt_size; i++) {
3706 if (*(rx_skb->data + i) != (unsigned char) (i & 0xff)) {
3707 goto loopback_test_done;
3708 }
3709 }
3710
3711 ret = 0;
3712
3713 loopback_test_done:
3714 bp->loopback = 0;
3715 return ret;
3716 }
3717
3718 #define NVRAM_SIZE 0x200
3719 #define CRC32_RESIDUAL 0xdebb20e3
3720
3721 static int
3722 bnx2_test_nvram(struct bnx2 *bp)
3723 {
3724 u32 buf[NVRAM_SIZE / 4];
3725 u8 *data = (u8 *) buf;
3726 int rc = 0;
3727 u32 magic, csum;
3728
3729 if ((rc = bnx2_nvram_read(bp, 0, data, 4)) != 0)
3730 goto test_nvram_done;
3731
3732 magic = be32_to_cpu(buf[0]);
3733 if (magic != 0x669955aa) {
3734 rc = -ENODEV;
3735 goto test_nvram_done;
3736 }
3737
3738 if ((rc = bnx2_nvram_read(bp, 0x100, data, NVRAM_SIZE)) != 0)
3739 goto test_nvram_done;
3740
3741 csum = ether_crc_le(0x100, data);
3742 if (csum != CRC32_RESIDUAL) {
3743 rc = -ENODEV;
3744 goto test_nvram_done;
3745 }
3746
3747 csum = ether_crc_le(0x100, data + 0x100);
3748 if (csum != CRC32_RESIDUAL) {
3749 rc = -ENODEV;
3750 }
3751
3752 test_nvram_done:
3753 return rc;
3754 }
3755
3756 static int
3757 bnx2_test_link(struct bnx2 *bp)
3758 {
3759 u32 bmsr;
3760
3761 spin_lock_bh(&bp->phy_lock);
3762 bnx2_read_phy(bp, MII_BMSR, &bmsr);
3763 bnx2_read_phy(bp, MII_BMSR, &bmsr);
3764 spin_unlock_bh(&bp->phy_lock);
3765
3766 if (bmsr & BMSR_LSTATUS) {
3767 return 0;
3768 }
3769 return -ENODEV;
3770 }
3771
3772 static int
3773 bnx2_test_intr(struct bnx2 *bp)
3774 {
3775 int i;
3776 u32 val;
3777 u16 status_idx;
3778
3779 if (!netif_running(bp->dev))
3780 return -ENODEV;
3781
3782 status_idx = REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff;
3783
3784 /* This register is not touched during run-time. */
3785 val = REG_RD(bp, BNX2_HC_COMMAND);
3786 REG_WR(bp, BNX2_HC_COMMAND, val | BNX2_HC_COMMAND_COAL_NOW);
3787 REG_RD(bp, BNX2_HC_COMMAND);
3788
3789 for (i = 0; i < 10; i++) {
3790 if ((REG_RD(bp, BNX2_PCICFG_INT_ACK_CMD) & 0xffff) !=
3791 status_idx) {
3792
3793 break;
3794 }
3795
3796 msleep_interruptible(10);
3797 }
3798 if (i < 10)
3799 return 0;
3800
3801 return -ENODEV;
3802 }
3803
3804 static void
3805 bnx2_timer(unsigned long data)
3806 {
3807 struct bnx2 *bp = (struct bnx2 *) data;
3808 u32 msg;
3809
3810 if (!netif_running(bp->dev))
3811 return;
3812
3813 if (atomic_read(&bp->intr_sem) != 0)
3814 goto bnx2_restart_timer;
3815
3816 msg = (u32) ++bp->fw_drv_pulse_wr_seq;
3817 REG_WR_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DRV_PULSE_MB, msg);
3818
3819 if ((bp->phy_flags & PHY_SERDES_FLAG) &&
3820 (CHIP_NUM(bp) == CHIP_NUM_5706)) {
3821
3822 spin_lock(&bp->phy_lock);
3823 if (bp->serdes_an_pending) {
3824 bp->serdes_an_pending--;
3825 }
3826 else if ((bp->link_up == 0) && (bp->autoneg & AUTONEG_SPEED)) {
3827 u32 bmcr;
3828
3829 bp->current_interval = bp->timer_interval;
3830
3831 bnx2_read_phy(bp, MII_BMCR, &bmcr);
3832
3833 if (bmcr & BMCR_ANENABLE) {
3834 u32 phy1, phy2;
3835
3836 bnx2_write_phy(bp, 0x1c, 0x7c00);
3837 bnx2_read_phy(bp, 0x1c, &phy1);
3838
3839 bnx2_write_phy(bp, 0x17, 0x0f01);
3840 bnx2_read_phy(bp, 0x15, &phy2);
3841 bnx2_write_phy(bp, 0x17, 0x0f01);
3842 bnx2_read_phy(bp, 0x15, &phy2);
3843
3844 if ((phy1 & 0x10) && /* SIGNAL DETECT */
3845 !(phy2 & 0x20)) { /* no CONFIG */
3846
3847 bmcr &= ~BMCR_ANENABLE;
3848 bmcr |= BMCR_SPEED1000 |
3849 BMCR_FULLDPLX;
3850 bnx2_write_phy(bp, MII_BMCR, bmcr);
3851 bp->phy_flags |=
3852 PHY_PARALLEL_DETECT_FLAG;
3853 }
3854 }
3855 }
3856 else if ((bp->link_up) && (bp->autoneg & AUTONEG_SPEED) &&
3857 (bp->phy_flags & PHY_PARALLEL_DETECT_FLAG)) {
3858 u32 phy2;
3859
3860 bnx2_write_phy(bp, 0x17, 0x0f01);
3861 bnx2_read_phy(bp, 0x15, &phy2);
3862 if (phy2 & 0x20) {
3863 u32 bmcr;
3864
3865 bnx2_read_phy(bp, MII_BMCR, &bmcr);
3866 bmcr |= BMCR_ANENABLE;
3867 bnx2_write_phy(bp, MII_BMCR, bmcr);
3868
3869 bp->phy_flags &= ~PHY_PARALLEL_DETECT_FLAG;
3870
3871 }
3872 }
3873 else
3874 bp->current_interval = bp->timer_interval;
3875
3876 spin_unlock(&bp->phy_lock);
3877 }
3878
3879 bnx2_restart_timer:
3880 mod_timer(&bp->timer, jiffies + bp->current_interval);
3881 }
3882
3883 /* Called with rtnl_lock */
3884 static int
3885 bnx2_open(struct net_device *dev)
3886 {
3887 struct bnx2 *bp = dev->priv;
3888 int rc;
3889
3890 bnx2_set_power_state(bp, PCI_D0);
3891 bnx2_disable_int(bp);
3892
3893 rc = bnx2_alloc_mem(bp);
3894 if (rc)
3895 return rc;
3896
3897 if ((CHIP_ID(bp) != CHIP_ID_5706_A0) &&
3898 (CHIP_ID(bp) != CHIP_ID_5706_A1) &&
3899 !disable_msi) {
3900
3901 if (pci_enable_msi(bp->pdev) == 0) {
3902 bp->flags |= USING_MSI_FLAG;
3903 rc = request_irq(bp->pdev->irq, bnx2_msi, 0, dev->name,
3904 dev);
3905 }
3906 else {
3907 rc = request_irq(bp->pdev->irq, bnx2_interrupt,
3908 SA_SHIRQ, dev->name, dev);
3909 }
3910 }
3911 else {
3912 rc = request_irq(bp->pdev->irq, bnx2_interrupt, SA_SHIRQ,
3913 dev->name, dev);
3914 }
3915 if (rc) {
3916 bnx2_free_mem(bp);
3917 return rc;
3918 }
3919
3920 rc = bnx2_init_nic(bp);
3921
3922 if (rc) {
3923 free_irq(bp->pdev->irq, dev);
3924 if (bp->flags & USING_MSI_FLAG) {
3925 pci_disable_msi(bp->pdev);
3926 bp->flags &= ~USING_MSI_FLAG;
3927 }
3928 bnx2_free_skbs(bp);
3929 bnx2_free_mem(bp);
3930 return rc;
3931 }
3932
3933 mod_timer(&bp->timer, jiffies + bp->current_interval);
3934
3935 atomic_set(&bp->intr_sem, 0);
3936
3937 bnx2_enable_int(bp);
3938
3939 if (bp->flags & USING_MSI_FLAG) {
3940 /* Test MSI to make sure it is working
3941 * If MSI test fails, go back to INTx mode
3942 */
3943 if (bnx2_test_intr(bp) != 0) {
3944 printk(KERN_WARNING PFX "%s: No interrupt was generated"
3945 " using MSI, switching to INTx mode. Please"
3946 " report this failure to the PCI maintainer"
3947 " and include system chipset information.\n",
3948 bp->dev->name);
3949
3950 bnx2_disable_int(bp);
3951 free_irq(bp->pdev->irq, dev);
3952 pci_disable_msi(bp->pdev);
3953 bp->flags &= ~USING_MSI_FLAG;
3954
3955 rc = bnx2_init_nic(bp);
3956
3957 if (!rc) {
3958 rc = request_irq(bp->pdev->irq, bnx2_interrupt,
3959 SA_SHIRQ, dev->name, dev);
3960 }
3961 if (rc) {
3962 bnx2_free_skbs(bp);
3963 bnx2_free_mem(bp);
3964 del_timer_sync(&bp->timer);
3965 return rc;
3966 }
3967 bnx2_enable_int(bp);
3968 }
3969 }
3970 if (bp->flags & USING_MSI_FLAG) {
3971 printk(KERN_INFO PFX "%s: using MSI\n", dev->name);
3972 }
3973
3974 netif_start_queue(dev);
3975
3976 return 0;
3977 }
3978
3979 static void
3980 bnx2_reset_task(void *data)
3981 {
3982 struct bnx2 *bp = data;
3983
3984 if (!netif_running(bp->dev))
3985 return;
3986
3987 bp->in_reset_task = 1;
3988 bnx2_netif_stop(bp);
3989
3990 bnx2_init_nic(bp);
3991
3992 atomic_set(&bp->intr_sem, 1);
3993 bnx2_netif_start(bp);
3994 bp->in_reset_task = 0;
3995 }
3996
3997 static void
3998 bnx2_tx_timeout(struct net_device *dev)
3999 {
4000 struct bnx2 *bp = dev->priv;
4001
4002 /* This allows the netif to be shutdown gracefully before resetting */
4003 schedule_work(&bp->reset_task);
4004 }
4005
4006 #ifdef BCM_VLAN
4007 /* Called with rtnl_lock */
4008 static void
4009 bnx2_vlan_rx_register(struct net_device *dev, struct vlan_group *vlgrp)
4010 {
4011 struct bnx2 *bp = dev->priv;
4012
4013 bnx2_netif_stop(bp);
4014
4015 bp->vlgrp = vlgrp;
4016 bnx2_set_rx_mode(dev);
4017
4018 bnx2_netif_start(bp);
4019 }
4020
4021 /* Called with rtnl_lock */
4022 static void
4023 bnx2_vlan_rx_kill_vid(struct net_device *dev, uint16_t vid)
4024 {
4025 struct bnx2 *bp = dev->priv;
4026
4027 bnx2_netif_stop(bp);
4028
4029 if (bp->vlgrp)
4030 bp->vlgrp->vlan_devices[vid] = NULL;
4031 bnx2_set_rx_mode(dev);
4032
4033 bnx2_netif_start(bp);
4034 }
4035 #endif
4036
4037 /* Called with dev->xmit_lock.
4038 * hard_start_xmit is pseudo-lockless - a lock is only required when
4039 * the tx queue is full. This way, we get the benefit of lockless
4040 * operations most of the time without the complexities to handle
4041 * netif_stop_queue/wake_queue race conditions.
4042 */
4043 static int
4044 bnx2_start_xmit(struct sk_buff *skb, struct net_device *dev)
4045 {
4046 struct bnx2 *bp = dev->priv;
4047 dma_addr_t mapping;
4048 struct tx_bd *txbd;
4049 struct sw_bd *tx_buf;
4050 u32 len, vlan_tag_flags, last_frag, mss;
4051 u16 prod, ring_prod;
4052 int i;
4053
4054 if (unlikely(bnx2_tx_avail(bp) < (skb_shinfo(skb)->nr_frags + 1))) {
4055 netif_stop_queue(dev);
4056 printk(KERN_ERR PFX "%s: BUG! Tx ring full when queue awake!\n",
4057 dev->name);
4058
4059 return NETDEV_TX_BUSY;
4060 }
4061 len = skb_headlen(skb);
4062 prod = bp->tx_prod;
4063 ring_prod = TX_RING_IDX(prod);
4064
4065 vlan_tag_flags = 0;
4066 if (skb->ip_summed == CHECKSUM_HW) {
4067 vlan_tag_flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
4068 }
4069
4070 if (bp->vlgrp != 0 && vlan_tx_tag_present(skb)) {
4071 vlan_tag_flags |=
4072 (TX_BD_FLAGS_VLAN_TAG | (vlan_tx_tag_get(skb) << 16));
4073 }
4074 #ifdef BCM_TSO
4075 if ((mss = skb_shinfo(skb)->tso_size) &&
4076 (skb->len > (bp->dev->mtu + ETH_HLEN))) {
4077 u32 tcp_opt_len, ip_tcp_len;
4078
4079 if (skb_header_cloned(skb) &&
4080 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4081 dev_kfree_skb(skb);
4082 return NETDEV_TX_OK;
4083 }
4084
4085 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
4086 vlan_tag_flags |= TX_BD_FLAGS_SW_LSO;
4087
4088 tcp_opt_len = 0;
4089 if (skb->h.th->doff > 5) {
4090 tcp_opt_len = (skb->h.th->doff - 5) << 2;
4091 }
4092 ip_tcp_len = (skb->nh.iph->ihl << 2) + sizeof(struct tcphdr);
4093
4094 skb->nh.iph->check = 0;
4095 skb->nh.iph->tot_len = ntohs(mss + ip_tcp_len + tcp_opt_len);
4096 skb->h.th->check =
4097 ~csum_tcpudp_magic(skb->nh.iph->saddr,
4098 skb->nh.iph->daddr,
4099 0, IPPROTO_TCP, 0);
4100
4101 if (tcp_opt_len || (skb->nh.iph->ihl > 5)) {
4102 vlan_tag_flags |= ((skb->nh.iph->ihl - 5) +
4103 (tcp_opt_len >> 2)) << 8;
4104 }
4105 }
4106 else
4107 #endif
4108 {
4109 mss = 0;
4110 }
4111
4112 mapping = pci_map_single(bp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4113
4114 tx_buf = &bp->tx_buf_ring[ring_prod];
4115 tx_buf->skb = skb;
4116 pci_unmap_addr_set(tx_buf, mapping, mapping);
4117
4118 txbd = &bp->tx_desc_ring[ring_prod];
4119
4120 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
4121 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
4122 txbd->tx_bd_mss_nbytes = len | (mss << 16);
4123 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags | TX_BD_FLAGS_START;
4124
4125 last_frag = skb_shinfo(skb)->nr_frags;
4126
4127 for (i = 0; i < last_frag; i++) {
4128 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4129
4130 prod = NEXT_TX_BD(prod);
4131 ring_prod = TX_RING_IDX(prod);
4132 txbd = &bp->tx_desc_ring[ring_prod];
4133
4134 len = frag->size;
4135 mapping = pci_map_page(bp->pdev, frag->page, frag->page_offset,
4136 len, PCI_DMA_TODEVICE);
4137 pci_unmap_addr_set(&bp->tx_buf_ring[ring_prod],
4138 mapping, mapping);
4139
4140 txbd->tx_bd_haddr_hi = (u64) mapping >> 32;
4141 txbd->tx_bd_haddr_lo = (u64) mapping & 0xffffffff;
4142 txbd->tx_bd_mss_nbytes = len | (mss << 16);
4143 txbd->tx_bd_vlan_tag_flags = vlan_tag_flags;
4144
4145 }
4146 txbd->tx_bd_vlan_tag_flags |= TX_BD_FLAGS_END;
4147
4148 prod = NEXT_TX_BD(prod);
4149 bp->tx_prod_bseq += skb->len;
4150
4151 REG_WR16(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BIDX, prod);
4152 REG_WR(bp, MB_TX_CID_ADDR + BNX2_L2CTX_TX_HOST_BSEQ, bp->tx_prod_bseq);
4153
4154 mmiowb();
4155
4156 bp->tx_prod = prod;
4157 dev->trans_start = jiffies;
4158
4159 if (unlikely(bnx2_tx_avail(bp) <= MAX_SKB_FRAGS)) {
4160 spin_lock(&bp->tx_lock);
4161 netif_stop_queue(dev);
4162
4163 if (bnx2_tx_avail(bp) > MAX_SKB_FRAGS)
4164 netif_wake_queue(dev);
4165 spin_unlock(&bp->tx_lock);
4166 }
4167
4168 return NETDEV_TX_OK;
4169 }
4170
4171 /* Called with rtnl_lock */
4172 static int
4173 bnx2_close(struct net_device *dev)
4174 {
4175 struct bnx2 *bp = dev->priv;
4176 u32 reset_code;
4177
4178 /* Calling flush_scheduled_work() may deadlock because
4179 * linkwatch_event() may be on the workqueue and it will try to get
4180 * the rtnl_lock which we are holding.
4181 */
4182 while (bp->in_reset_task)
4183 msleep(1);
4184
4185 bnx2_netif_stop(bp);
4186 del_timer_sync(&bp->timer);
4187 if (bp->wol)
4188 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
4189 else
4190 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
4191 bnx2_reset_chip(bp, reset_code);
4192 free_irq(bp->pdev->irq, dev);
4193 if (bp->flags & USING_MSI_FLAG) {
4194 pci_disable_msi(bp->pdev);
4195 bp->flags &= ~USING_MSI_FLAG;
4196 }
4197 bnx2_free_skbs(bp);
4198 bnx2_free_mem(bp);
4199 bp->link_up = 0;
4200 netif_carrier_off(bp->dev);
4201 bnx2_set_power_state(bp, PCI_D3hot);
4202 return 0;
4203 }
4204
4205 #define GET_NET_STATS64(ctr) \
4206 (unsigned long) ((unsigned long) (ctr##_hi) << 32) + \
4207 (unsigned long) (ctr##_lo)
4208
4209 #define GET_NET_STATS32(ctr) \
4210 (ctr##_lo)
4211
4212 #if (BITS_PER_LONG == 64)
4213 #define GET_NET_STATS GET_NET_STATS64
4214 #else
4215 #define GET_NET_STATS GET_NET_STATS32
4216 #endif
4217
4218 static struct net_device_stats *
4219 bnx2_get_stats(struct net_device *dev)
4220 {
4221 struct bnx2 *bp = dev->priv;
4222 struct statistics_block *stats_blk = bp->stats_blk;
4223 struct net_device_stats *net_stats = &bp->net_stats;
4224
4225 if (bp->stats_blk == NULL) {
4226 return net_stats;
4227 }
4228 net_stats->rx_packets =
4229 GET_NET_STATS(stats_blk->stat_IfHCInUcastPkts) +
4230 GET_NET_STATS(stats_blk->stat_IfHCInMulticastPkts) +
4231 GET_NET_STATS(stats_blk->stat_IfHCInBroadcastPkts);
4232
4233 net_stats->tx_packets =
4234 GET_NET_STATS(stats_blk->stat_IfHCOutUcastPkts) +
4235 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts) +
4236 GET_NET_STATS(stats_blk->stat_IfHCOutBroadcastPkts);
4237
4238 net_stats->rx_bytes =
4239 GET_NET_STATS(stats_blk->stat_IfHCInOctets);
4240
4241 net_stats->tx_bytes =
4242 GET_NET_STATS(stats_blk->stat_IfHCOutOctets);
4243
4244 net_stats->multicast =
4245 GET_NET_STATS(stats_blk->stat_IfHCOutMulticastPkts);
4246
4247 net_stats->collisions =
4248 (unsigned long) stats_blk->stat_EtherStatsCollisions;
4249
4250 net_stats->rx_length_errors =
4251 (unsigned long) (stats_blk->stat_EtherStatsUndersizePkts +
4252 stats_blk->stat_EtherStatsOverrsizePkts);
4253
4254 net_stats->rx_over_errors =
4255 (unsigned long) stats_blk->stat_IfInMBUFDiscards;
4256
4257 net_stats->rx_frame_errors =
4258 (unsigned long) stats_blk->stat_Dot3StatsAlignmentErrors;
4259
4260 net_stats->rx_crc_errors =
4261 (unsigned long) stats_blk->stat_Dot3StatsFCSErrors;
4262
4263 net_stats->rx_errors = net_stats->rx_length_errors +
4264 net_stats->rx_over_errors + net_stats->rx_frame_errors +
4265 net_stats->rx_crc_errors;
4266
4267 net_stats->tx_aborted_errors =
4268 (unsigned long) (stats_blk->stat_Dot3StatsExcessiveCollisions +
4269 stats_blk->stat_Dot3StatsLateCollisions);
4270
4271 if (CHIP_NUM(bp) == CHIP_NUM_5706)
4272 net_stats->tx_carrier_errors = 0;
4273 else {
4274 net_stats->tx_carrier_errors =
4275 (unsigned long)
4276 stats_blk->stat_Dot3StatsCarrierSenseErrors;
4277 }
4278
4279 net_stats->tx_errors =
4280 (unsigned long)
4281 stats_blk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors
4282 +
4283 net_stats->tx_aborted_errors +
4284 net_stats->tx_carrier_errors;
4285
4286 return net_stats;
4287 }
4288
4289 /* All ethtool functions called with rtnl_lock */
4290
4291 static int
4292 bnx2_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4293 {
4294 struct bnx2 *bp = dev->priv;
4295
4296 cmd->supported = SUPPORTED_Autoneg;
4297 if (bp->phy_flags & PHY_SERDES_FLAG) {
4298 cmd->supported |= SUPPORTED_1000baseT_Full |
4299 SUPPORTED_FIBRE;
4300
4301 cmd->port = PORT_FIBRE;
4302 }
4303 else {
4304 cmd->supported |= SUPPORTED_10baseT_Half |
4305 SUPPORTED_10baseT_Full |
4306 SUPPORTED_100baseT_Half |
4307 SUPPORTED_100baseT_Full |
4308 SUPPORTED_1000baseT_Full |
4309 SUPPORTED_TP;
4310
4311 cmd->port = PORT_TP;
4312 }
4313
4314 cmd->advertising = bp->advertising;
4315
4316 if (bp->autoneg & AUTONEG_SPEED) {
4317 cmd->autoneg = AUTONEG_ENABLE;
4318 }
4319 else {
4320 cmd->autoneg = AUTONEG_DISABLE;
4321 }
4322
4323 if (netif_carrier_ok(dev)) {
4324 cmd->speed = bp->line_speed;
4325 cmd->duplex = bp->duplex;
4326 }
4327 else {
4328 cmd->speed = -1;
4329 cmd->duplex = -1;
4330 }
4331
4332 cmd->transceiver = XCVR_INTERNAL;
4333 cmd->phy_address = bp->phy_addr;
4334
4335 return 0;
4336 }
4337
4338 static int
4339 bnx2_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
4340 {
4341 struct bnx2 *bp = dev->priv;
4342 u8 autoneg = bp->autoneg;
4343 u8 req_duplex = bp->req_duplex;
4344 u16 req_line_speed = bp->req_line_speed;
4345 u32 advertising = bp->advertising;
4346
4347 if (cmd->autoneg == AUTONEG_ENABLE) {
4348 autoneg |= AUTONEG_SPEED;
4349
4350 cmd->advertising &= ETHTOOL_ALL_COPPER_SPEED;
4351
4352 /* allow advertising 1 speed */
4353 if ((cmd->advertising == ADVERTISED_10baseT_Half) ||
4354 (cmd->advertising == ADVERTISED_10baseT_Full) ||
4355 (cmd->advertising == ADVERTISED_100baseT_Half) ||
4356 (cmd->advertising == ADVERTISED_100baseT_Full)) {
4357
4358 if (bp->phy_flags & PHY_SERDES_FLAG)
4359 return -EINVAL;
4360
4361 advertising = cmd->advertising;
4362
4363 }
4364 else if (cmd->advertising == ADVERTISED_1000baseT_Full) {
4365 advertising = cmd->advertising;
4366 }
4367 else if (cmd->advertising == ADVERTISED_1000baseT_Half) {
4368 return -EINVAL;
4369 }
4370 else {
4371 if (bp->phy_flags & PHY_SERDES_FLAG) {
4372 advertising = ETHTOOL_ALL_FIBRE_SPEED;
4373 }
4374 else {
4375 advertising = ETHTOOL_ALL_COPPER_SPEED;
4376 }
4377 }
4378 advertising |= ADVERTISED_Autoneg;
4379 }
4380 else {
4381 if (bp->phy_flags & PHY_SERDES_FLAG) {
4382 if ((cmd->speed != SPEED_1000) ||
4383 (cmd->duplex != DUPLEX_FULL)) {
4384 return -EINVAL;
4385 }
4386 }
4387 else if (cmd->speed == SPEED_1000) {
4388 return -EINVAL;
4389 }
4390 autoneg &= ~AUTONEG_SPEED;
4391 req_line_speed = cmd->speed;
4392 req_duplex = cmd->duplex;
4393 advertising = 0;
4394 }
4395
4396 bp->autoneg = autoneg;
4397 bp->advertising = advertising;
4398 bp->req_line_speed = req_line_speed;
4399 bp->req_duplex = req_duplex;
4400
4401 spin_lock_bh(&bp->phy_lock);
4402
4403 bnx2_setup_phy(bp);
4404
4405 spin_unlock_bh(&bp->phy_lock);
4406
4407 return 0;
4408 }
4409
4410 static void
4411 bnx2_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4412 {
4413 struct bnx2 *bp = dev->priv;
4414
4415 strcpy(info->driver, DRV_MODULE_NAME);
4416 strcpy(info->version, DRV_MODULE_VERSION);
4417 strcpy(info->bus_info, pci_name(bp->pdev));
4418 info->fw_version[0] = ((bp->fw_ver & 0xff000000) >> 24) + '0';
4419 info->fw_version[2] = ((bp->fw_ver & 0xff0000) >> 16) + '0';
4420 info->fw_version[4] = ((bp->fw_ver & 0xff00) >> 8) + '0';
4421 info->fw_version[6] = (bp->fw_ver & 0xff) + '0';
4422 info->fw_version[1] = info->fw_version[3] = info->fw_version[5] = '.';
4423 info->fw_version[7] = 0;
4424 }
4425
4426 static void
4427 bnx2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4428 {
4429 struct bnx2 *bp = dev->priv;
4430
4431 if (bp->flags & NO_WOL_FLAG) {
4432 wol->supported = 0;
4433 wol->wolopts = 0;
4434 }
4435 else {
4436 wol->supported = WAKE_MAGIC;
4437 if (bp->wol)
4438 wol->wolopts = WAKE_MAGIC;
4439 else
4440 wol->wolopts = 0;
4441 }
4442 memset(&wol->sopass, 0, sizeof(wol->sopass));
4443 }
4444
4445 static int
4446 bnx2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4447 {
4448 struct bnx2 *bp = dev->priv;
4449
4450 if (wol->wolopts & ~WAKE_MAGIC)
4451 return -EINVAL;
4452
4453 if (wol->wolopts & WAKE_MAGIC) {
4454 if (bp->flags & NO_WOL_FLAG)
4455 return -EINVAL;
4456
4457 bp->wol = 1;
4458 }
4459 else {
4460 bp->wol = 0;
4461 }
4462 return 0;
4463 }
4464
4465 static int
4466 bnx2_nway_reset(struct net_device *dev)
4467 {
4468 struct bnx2 *bp = dev->priv;
4469 u32 bmcr;
4470
4471 if (!(bp->autoneg & AUTONEG_SPEED)) {
4472 return -EINVAL;
4473 }
4474
4475 spin_lock_bh(&bp->phy_lock);
4476
4477 /* Force a link down visible on the other side */
4478 if (bp->phy_flags & PHY_SERDES_FLAG) {
4479 bnx2_write_phy(bp, MII_BMCR, BMCR_LOOPBACK);
4480 spin_unlock_bh(&bp->phy_lock);
4481
4482 msleep(20);
4483
4484 spin_lock_bh(&bp->phy_lock);
4485 if (CHIP_NUM(bp) == CHIP_NUM_5706) {
4486 bp->current_interval = SERDES_AN_TIMEOUT;
4487 bp->serdes_an_pending = 1;
4488 mod_timer(&bp->timer, jiffies + bp->current_interval);
4489 }
4490 }
4491
4492 bnx2_read_phy(bp, MII_BMCR, &bmcr);
4493 bmcr &= ~BMCR_LOOPBACK;
4494 bnx2_write_phy(bp, MII_BMCR, bmcr | BMCR_ANRESTART | BMCR_ANENABLE);
4495
4496 spin_unlock_bh(&bp->phy_lock);
4497
4498 return 0;
4499 }
4500
4501 static int
4502 bnx2_get_eeprom_len(struct net_device *dev)
4503 {
4504 struct bnx2 *bp = dev->priv;
4505
4506 if (bp->flash_info == 0)
4507 return 0;
4508
4509 return (int) bp->flash_info->total_size;
4510 }
4511
4512 static int
4513 bnx2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4514 u8 *eebuf)
4515 {
4516 struct bnx2 *bp = dev->priv;
4517 int rc;
4518
4519 if (eeprom->offset > bp->flash_info->total_size)
4520 return -EINVAL;
4521
4522 if ((eeprom->offset + eeprom->len) > bp->flash_info->total_size)
4523 eeprom->len = bp->flash_info->total_size - eeprom->offset;
4524
4525 rc = bnx2_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
4526
4527 return rc;
4528 }
4529
4530 static int
4531 bnx2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4532 u8 *eebuf)
4533 {
4534 struct bnx2 *bp = dev->priv;
4535 int rc;
4536
4537 if (eeprom->offset > bp->flash_info->total_size)
4538 return -EINVAL;
4539
4540 if ((eeprom->offset + eeprom->len) > bp->flash_info->total_size)
4541 eeprom->len = bp->flash_info->total_size - eeprom->offset;
4542
4543 rc = bnx2_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
4544
4545 return rc;
4546 }
4547
4548 static int
4549 bnx2_get_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
4550 {
4551 struct bnx2 *bp = dev->priv;
4552
4553 memset(coal, 0, sizeof(struct ethtool_coalesce));
4554
4555 coal->rx_coalesce_usecs = bp->rx_ticks;
4556 coal->rx_max_coalesced_frames = bp->rx_quick_cons_trip;
4557 coal->rx_coalesce_usecs_irq = bp->rx_ticks_int;
4558 coal->rx_max_coalesced_frames_irq = bp->rx_quick_cons_trip_int;
4559
4560 coal->tx_coalesce_usecs = bp->tx_ticks;
4561 coal->tx_max_coalesced_frames = bp->tx_quick_cons_trip;
4562 coal->tx_coalesce_usecs_irq = bp->tx_ticks_int;
4563 coal->tx_max_coalesced_frames_irq = bp->tx_quick_cons_trip_int;
4564
4565 coal->stats_block_coalesce_usecs = bp->stats_ticks;
4566
4567 return 0;
4568 }
4569
4570 static int
4571 bnx2_set_coalesce(struct net_device *dev, struct ethtool_coalesce *coal)
4572 {
4573 struct bnx2 *bp = dev->priv;
4574
4575 bp->rx_ticks = (u16) coal->rx_coalesce_usecs;
4576 if (bp->rx_ticks > 0x3ff) bp->rx_ticks = 0x3ff;
4577
4578 bp->rx_quick_cons_trip = (u16) coal->rx_max_coalesced_frames;
4579 if (bp->rx_quick_cons_trip > 0xff) bp->rx_quick_cons_trip = 0xff;
4580
4581 bp->rx_ticks_int = (u16) coal->rx_coalesce_usecs_irq;
4582 if (bp->rx_ticks_int > 0x3ff) bp->rx_ticks_int = 0x3ff;
4583
4584 bp->rx_quick_cons_trip_int = (u16) coal->rx_max_coalesced_frames_irq;
4585 if (bp->rx_quick_cons_trip_int > 0xff)
4586 bp->rx_quick_cons_trip_int = 0xff;
4587
4588 bp->tx_ticks = (u16) coal->tx_coalesce_usecs;
4589 if (bp->tx_ticks > 0x3ff) bp->tx_ticks = 0x3ff;
4590
4591 bp->tx_quick_cons_trip = (u16) coal->tx_max_coalesced_frames;
4592 if (bp->tx_quick_cons_trip > 0xff) bp->tx_quick_cons_trip = 0xff;
4593
4594 bp->tx_ticks_int = (u16) coal->tx_coalesce_usecs_irq;
4595 if (bp->tx_ticks_int > 0x3ff) bp->tx_ticks_int = 0x3ff;
4596
4597 bp->tx_quick_cons_trip_int = (u16) coal->tx_max_coalesced_frames_irq;
4598 if (bp->tx_quick_cons_trip_int > 0xff) bp->tx_quick_cons_trip_int =
4599 0xff;
4600
4601 bp->stats_ticks = coal->stats_block_coalesce_usecs;
4602 if (bp->stats_ticks > 0xffff00) bp->stats_ticks = 0xffff00;
4603 bp->stats_ticks &= 0xffff00;
4604
4605 if (netif_running(bp->dev)) {
4606 bnx2_netif_stop(bp);
4607 bnx2_init_nic(bp);
4608 bnx2_netif_start(bp);
4609 }
4610
4611 return 0;
4612 }
4613
4614 static void
4615 bnx2_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
4616 {
4617 struct bnx2 *bp = dev->priv;
4618
4619 ering->rx_max_pending = MAX_RX_DESC_CNT;
4620 ering->rx_mini_max_pending = 0;
4621 ering->rx_jumbo_max_pending = 0;
4622
4623 ering->rx_pending = bp->rx_ring_size;
4624 ering->rx_mini_pending = 0;
4625 ering->rx_jumbo_pending = 0;
4626
4627 ering->tx_max_pending = MAX_TX_DESC_CNT;
4628 ering->tx_pending = bp->tx_ring_size;
4629 }
4630
4631 static int
4632 bnx2_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
4633 {
4634 struct bnx2 *bp = dev->priv;
4635
4636 if ((ering->rx_pending > MAX_RX_DESC_CNT) ||
4637 (ering->tx_pending > MAX_TX_DESC_CNT) ||
4638 (ering->tx_pending <= MAX_SKB_FRAGS)) {
4639
4640 return -EINVAL;
4641 }
4642 bp->rx_ring_size = ering->rx_pending;
4643 bp->tx_ring_size = ering->tx_pending;
4644
4645 if (netif_running(bp->dev)) {
4646 bnx2_netif_stop(bp);
4647 bnx2_init_nic(bp);
4648 bnx2_netif_start(bp);
4649 }
4650
4651 return 0;
4652 }
4653
4654 static void
4655 bnx2_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
4656 {
4657 struct bnx2 *bp = dev->priv;
4658
4659 epause->autoneg = ((bp->autoneg & AUTONEG_FLOW_CTRL) != 0);
4660 epause->rx_pause = ((bp->flow_ctrl & FLOW_CTRL_RX) != 0);
4661 epause->tx_pause = ((bp->flow_ctrl & FLOW_CTRL_TX) != 0);
4662 }
4663
4664 static int
4665 bnx2_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
4666 {
4667 struct bnx2 *bp = dev->priv;
4668
4669 bp->req_flow_ctrl = 0;
4670 if (epause->rx_pause)
4671 bp->req_flow_ctrl |= FLOW_CTRL_RX;
4672 if (epause->tx_pause)
4673 bp->req_flow_ctrl |= FLOW_CTRL_TX;
4674
4675 if (epause->autoneg) {
4676 bp->autoneg |= AUTONEG_FLOW_CTRL;
4677 }
4678 else {
4679 bp->autoneg &= ~AUTONEG_FLOW_CTRL;
4680 }
4681
4682 spin_lock_bh(&bp->phy_lock);
4683
4684 bnx2_setup_phy(bp);
4685
4686 spin_unlock_bh(&bp->phy_lock);
4687
4688 return 0;
4689 }
4690
4691 static u32
4692 bnx2_get_rx_csum(struct net_device *dev)
4693 {
4694 struct bnx2 *bp = dev->priv;
4695
4696 return bp->rx_csum;
4697 }
4698
4699 static int
4700 bnx2_set_rx_csum(struct net_device *dev, u32 data)
4701 {
4702 struct bnx2 *bp = dev->priv;
4703
4704 bp->rx_csum = data;
4705 return 0;
4706 }
4707
4708 #define BNX2_NUM_STATS 45
4709
4710 static struct {
4711 char string[ETH_GSTRING_LEN];
4712 } bnx2_stats_str_arr[BNX2_NUM_STATS] = {
4713 { "rx_bytes" },
4714 { "rx_error_bytes" },
4715 { "tx_bytes" },
4716 { "tx_error_bytes" },
4717 { "rx_ucast_packets" },
4718 { "rx_mcast_packets" },
4719 { "rx_bcast_packets" },
4720 { "tx_ucast_packets" },
4721 { "tx_mcast_packets" },
4722 { "tx_bcast_packets" },
4723 { "tx_mac_errors" },
4724 { "tx_carrier_errors" },
4725 { "rx_crc_errors" },
4726 { "rx_align_errors" },
4727 { "tx_single_collisions" },
4728 { "tx_multi_collisions" },
4729 { "tx_deferred" },
4730 { "tx_excess_collisions" },
4731 { "tx_late_collisions" },
4732 { "tx_total_collisions" },
4733 { "rx_fragments" },
4734 { "rx_jabbers" },
4735 { "rx_undersize_packets" },
4736 { "rx_oversize_packets" },
4737 { "rx_64_byte_packets" },
4738 { "rx_65_to_127_byte_packets" },
4739 { "rx_128_to_255_byte_packets" },
4740 { "rx_256_to_511_byte_packets" },
4741 { "rx_512_to_1023_byte_packets" },
4742 { "rx_1024_to_1522_byte_packets" },
4743 { "rx_1523_to_9022_byte_packets" },
4744 { "tx_64_byte_packets" },
4745 { "tx_65_to_127_byte_packets" },
4746 { "tx_128_to_255_byte_packets" },
4747 { "tx_256_to_511_byte_packets" },
4748 { "tx_512_to_1023_byte_packets" },
4749 { "tx_1024_to_1522_byte_packets" },
4750 { "tx_1523_to_9022_byte_packets" },
4751 { "rx_xon_frames" },
4752 { "rx_xoff_frames" },
4753 { "tx_xon_frames" },
4754 { "tx_xoff_frames" },
4755 { "rx_mac_ctrl_frames" },
4756 { "rx_filtered_packets" },
4757 { "rx_discards" },
4758 };
4759
4760 #define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
4761
4762 static unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
4763 STATS_OFFSET32(stat_IfHCInOctets_hi),
4764 STATS_OFFSET32(stat_IfHCInBadOctets_hi),
4765 STATS_OFFSET32(stat_IfHCOutOctets_hi),
4766 STATS_OFFSET32(stat_IfHCOutBadOctets_hi),
4767 STATS_OFFSET32(stat_IfHCInUcastPkts_hi),
4768 STATS_OFFSET32(stat_IfHCInMulticastPkts_hi),
4769 STATS_OFFSET32(stat_IfHCInBroadcastPkts_hi),
4770 STATS_OFFSET32(stat_IfHCOutUcastPkts_hi),
4771 STATS_OFFSET32(stat_IfHCOutMulticastPkts_hi),
4772 STATS_OFFSET32(stat_IfHCOutBroadcastPkts_hi),
4773 STATS_OFFSET32(stat_emac_tx_stat_dot3statsinternalmactransmiterrors),
4774 STATS_OFFSET32(stat_Dot3StatsCarrierSenseErrors),
4775 STATS_OFFSET32(stat_Dot3StatsFCSErrors),
4776 STATS_OFFSET32(stat_Dot3StatsAlignmentErrors),
4777 STATS_OFFSET32(stat_Dot3StatsSingleCollisionFrames),
4778 STATS_OFFSET32(stat_Dot3StatsMultipleCollisionFrames),
4779 STATS_OFFSET32(stat_Dot3StatsDeferredTransmissions),
4780 STATS_OFFSET32(stat_Dot3StatsExcessiveCollisions),
4781 STATS_OFFSET32(stat_Dot3StatsLateCollisions),
4782 STATS_OFFSET32(stat_EtherStatsCollisions),
4783 STATS_OFFSET32(stat_EtherStatsFragments),
4784 STATS_OFFSET32(stat_EtherStatsJabbers),
4785 STATS_OFFSET32(stat_EtherStatsUndersizePkts),
4786 STATS_OFFSET32(stat_EtherStatsOverrsizePkts),
4787 STATS_OFFSET32(stat_EtherStatsPktsRx64Octets),
4788 STATS_OFFSET32(stat_EtherStatsPktsRx65Octetsto127Octets),
4789 STATS_OFFSET32(stat_EtherStatsPktsRx128Octetsto255Octets),
4790 STATS_OFFSET32(stat_EtherStatsPktsRx256Octetsto511Octets),
4791 STATS_OFFSET32(stat_EtherStatsPktsRx512Octetsto1023Octets),
4792 STATS_OFFSET32(stat_EtherStatsPktsRx1024Octetsto1522Octets),
4793 STATS_OFFSET32(stat_EtherStatsPktsRx1523Octetsto9022Octets),
4794 STATS_OFFSET32(stat_EtherStatsPktsTx64Octets),
4795 STATS_OFFSET32(stat_EtherStatsPktsTx65Octetsto127Octets),
4796 STATS_OFFSET32(stat_EtherStatsPktsTx128Octetsto255Octets),
4797 STATS_OFFSET32(stat_EtherStatsPktsTx256Octetsto511Octets),
4798 STATS_OFFSET32(stat_EtherStatsPktsTx512Octetsto1023Octets),
4799 STATS_OFFSET32(stat_EtherStatsPktsTx1024Octetsto1522Octets),
4800 STATS_OFFSET32(stat_EtherStatsPktsTx1523Octetsto9022Octets),
4801 STATS_OFFSET32(stat_XonPauseFramesReceived),
4802 STATS_OFFSET32(stat_XoffPauseFramesReceived),
4803 STATS_OFFSET32(stat_OutXonSent),
4804 STATS_OFFSET32(stat_OutXoffSent),
4805 STATS_OFFSET32(stat_MacControlFramesReceived),
4806 STATS_OFFSET32(stat_IfInFramesL2FilterDiscards),
4807 STATS_OFFSET32(stat_IfInMBUFDiscards),
4808 };
4809
4810 /* stat_IfHCInBadOctets and stat_Dot3StatsCarrierSenseErrors are
4811 * skipped because of errata.
4812 */
4813 static u8 bnx2_5706_stats_len_arr[BNX2_NUM_STATS] = {
4814 8,0,8,8,8,8,8,8,8,8,
4815 4,0,4,4,4,4,4,4,4,4,
4816 4,4,4,4,4,4,4,4,4,4,
4817 4,4,4,4,4,4,4,4,4,4,
4818 4,4,4,4,4,
4819 };
4820
4821 #define BNX2_NUM_TESTS 6
4822
4823 static struct {
4824 char string[ETH_GSTRING_LEN];
4825 } bnx2_tests_str_arr[BNX2_NUM_TESTS] = {
4826 { "register_test (offline)" },
4827 { "memory_test (offline)" },
4828 { "loopback_test (offline)" },
4829 { "nvram_test (online)" },
4830 { "interrupt_test (online)" },
4831 { "link_test (online)" },
4832 };
4833
4834 static int
4835 bnx2_self_test_count(struct net_device *dev)
4836 {
4837 return BNX2_NUM_TESTS;
4838 }
4839
4840 static void
4841 bnx2_self_test(struct net_device *dev, struct ethtool_test *etest, u64 *buf)
4842 {
4843 struct bnx2 *bp = dev->priv;
4844
4845 memset(buf, 0, sizeof(u64) * BNX2_NUM_TESTS);
4846 if (etest->flags & ETH_TEST_FL_OFFLINE) {
4847 bnx2_netif_stop(bp);
4848 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_DIAG);
4849 bnx2_free_skbs(bp);
4850
4851 if (bnx2_test_registers(bp) != 0) {
4852 buf[0] = 1;
4853 etest->flags |= ETH_TEST_FL_FAILED;
4854 }
4855 if (bnx2_test_memory(bp) != 0) {
4856 buf[1] = 1;
4857 etest->flags |= ETH_TEST_FL_FAILED;
4858 }
4859 if (bnx2_test_loopback(bp) != 0) {
4860 buf[2] = 1;
4861 etest->flags |= ETH_TEST_FL_FAILED;
4862 }
4863
4864 if (!netif_running(bp->dev)) {
4865 bnx2_reset_chip(bp, BNX2_DRV_MSG_CODE_RESET);
4866 }
4867 else {
4868 bnx2_init_nic(bp);
4869 bnx2_netif_start(bp);
4870 }
4871
4872 /* wait for link up */
4873 msleep_interruptible(3000);
4874 if ((!bp->link_up) && !(bp->phy_flags & PHY_SERDES_FLAG))
4875 msleep_interruptible(4000);
4876 }
4877
4878 if (bnx2_test_nvram(bp) != 0) {
4879 buf[3] = 1;
4880 etest->flags |= ETH_TEST_FL_FAILED;
4881 }
4882 if (bnx2_test_intr(bp) != 0) {
4883 buf[4] = 1;
4884 etest->flags |= ETH_TEST_FL_FAILED;
4885 }
4886
4887 if (bnx2_test_link(bp) != 0) {
4888 buf[5] = 1;
4889 etest->flags |= ETH_TEST_FL_FAILED;
4890
4891 }
4892 }
4893
4894 static void
4895 bnx2_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
4896 {
4897 switch (stringset) {
4898 case ETH_SS_STATS:
4899 memcpy(buf, bnx2_stats_str_arr,
4900 sizeof(bnx2_stats_str_arr));
4901 break;
4902 case ETH_SS_TEST:
4903 memcpy(buf, bnx2_tests_str_arr,
4904 sizeof(bnx2_tests_str_arr));
4905 break;
4906 }
4907 }
4908
4909 static int
4910 bnx2_get_stats_count(struct net_device *dev)
4911 {
4912 return BNX2_NUM_STATS;
4913 }
4914
4915 static void
4916 bnx2_get_ethtool_stats(struct net_device *dev,
4917 struct ethtool_stats *stats, u64 *buf)
4918 {
4919 struct bnx2 *bp = dev->priv;
4920 int i;
4921 u32 *hw_stats = (u32 *) bp->stats_blk;
4922 u8 *stats_len_arr = NULL;
4923
4924 if (hw_stats == NULL) {
4925 memset(buf, 0, sizeof(u64) * BNX2_NUM_STATS);
4926 return;
4927 }
4928
4929 if (CHIP_NUM(bp) == CHIP_NUM_5706)
4930 stats_len_arr = bnx2_5706_stats_len_arr;
4931
4932 for (i = 0; i < BNX2_NUM_STATS; i++) {
4933 if (stats_len_arr[i] == 0) {
4934 /* skip this counter */
4935 buf[i] = 0;
4936 continue;
4937 }
4938 if (stats_len_arr[i] == 4) {
4939 /* 4-byte counter */
4940 buf[i] = (u64)
4941 *(hw_stats + bnx2_stats_offset_arr[i]);
4942 continue;
4943 }
4944 /* 8-byte counter */
4945 buf[i] = (((u64) *(hw_stats +
4946 bnx2_stats_offset_arr[i])) << 32) +
4947 *(hw_stats + bnx2_stats_offset_arr[i] + 1);
4948 }
4949 }
4950
4951 static int
4952 bnx2_phys_id(struct net_device *dev, u32 data)
4953 {
4954 struct bnx2 *bp = dev->priv;
4955 int i;
4956 u32 save;
4957
4958 if (data == 0)
4959 data = 2;
4960
4961 save = REG_RD(bp, BNX2_MISC_CFG);
4962 REG_WR(bp, BNX2_MISC_CFG, BNX2_MISC_CFG_LEDMODE_MAC);
4963
4964 for (i = 0; i < (data * 2); i++) {
4965 if ((i % 2) == 0) {
4966 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE);
4967 }
4968 else {
4969 REG_WR(bp, BNX2_EMAC_LED, BNX2_EMAC_LED_OVERRIDE |
4970 BNX2_EMAC_LED_1000MB_OVERRIDE |
4971 BNX2_EMAC_LED_100MB_OVERRIDE |
4972 BNX2_EMAC_LED_10MB_OVERRIDE |
4973 BNX2_EMAC_LED_TRAFFIC_OVERRIDE |
4974 BNX2_EMAC_LED_TRAFFIC);
4975 }
4976 msleep_interruptible(500);
4977 if (signal_pending(current))
4978 break;
4979 }
4980 REG_WR(bp, BNX2_EMAC_LED, 0);
4981 REG_WR(bp, BNX2_MISC_CFG, save);
4982 return 0;
4983 }
4984
4985 static struct ethtool_ops bnx2_ethtool_ops = {
4986 .get_settings = bnx2_get_settings,
4987 .set_settings = bnx2_set_settings,
4988 .get_drvinfo = bnx2_get_drvinfo,
4989 .get_wol = bnx2_get_wol,
4990 .set_wol = bnx2_set_wol,
4991 .nway_reset = bnx2_nway_reset,
4992 .get_link = ethtool_op_get_link,
4993 .get_eeprom_len = bnx2_get_eeprom_len,
4994 .get_eeprom = bnx2_get_eeprom,
4995 .set_eeprom = bnx2_set_eeprom,
4996 .get_coalesce = bnx2_get_coalesce,
4997 .set_coalesce = bnx2_set_coalesce,
4998 .get_ringparam = bnx2_get_ringparam,
4999 .set_ringparam = bnx2_set_ringparam,
5000 .get_pauseparam = bnx2_get_pauseparam,
5001 .set_pauseparam = bnx2_set_pauseparam,
5002 .get_rx_csum = bnx2_get_rx_csum,
5003 .set_rx_csum = bnx2_set_rx_csum,
5004 .get_tx_csum = ethtool_op_get_tx_csum,
5005 .set_tx_csum = ethtool_op_set_tx_csum,
5006 .get_sg = ethtool_op_get_sg,
5007 .set_sg = ethtool_op_set_sg,
5008 #ifdef BCM_TSO
5009 .get_tso = ethtool_op_get_tso,
5010 .set_tso = ethtool_op_set_tso,
5011 #endif
5012 .self_test_count = bnx2_self_test_count,
5013 .self_test = bnx2_self_test,
5014 .get_strings = bnx2_get_strings,
5015 .phys_id = bnx2_phys_id,
5016 .get_stats_count = bnx2_get_stats_count,
5017 .get_ethtool_stats = bnx2_get_ethtool_stats,
5018 .get_perm_addr = ethtool_op_get_perm_addr,
5019 };
5020
5021 /* Called with rtnl_lock */
5022 static int
5023 bnx2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
5024 {
5025 struct mii_ioctl_data *data = if_mii(ifr);
5026 struct bnx2 *bp = dev->priv;
5027 int err;
5028
5029 switch(cmd) {
5030 case SIOCGMIIPHY:
5031 data->phy_id = bp->phy_addr;
5032
5033 /* fallthru */
5034 case SIOCGMIIREG: {
5035 u32 mii_regval;
5036
5037 spin_lock_bh(&bp->phy_lock);
5038 err = bnx2_read_phy(bp, data->reg_num & 0x1f, &mii_regval);
5039 spin_unlock_bh(&bp->phy_lock);
5040
5041 data->val_out = mii_regval;
5042
5043 return err;
5044 }
5045
5046 case SIOCSMIIREG:
5047 if (!capable(CAP_NET_ADMIN))
5048 return -EPERM;
5049
5050 spin_lock_bh(&bp->phy_lock);
5051 err = bnx2_write_phy(bp, data->reg_num & 0x1f, data->val_in);
5052 spin_unlock_bh(&bp->phy_lock);
5053
5054 return err;
5055
5056 default:
5057 /* do nothing */
5058 break;
5059 }
5060 return -EOPNOTSUPP;
5061 }
5062
5063 /* Called with rtnl_lock */
5064 static int
5065 bnx2_change_mac_addr(struct net_device *dev, void *p)
5066 {
5067 struct sockaddr *addr = p;
5068 struct bnx2 *bp = dev->priv;
5069
5070 if (!is_valid_ether_addr(addr->sa_data))
5071 return -EINVAL;
5072
5073 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5074 if (netif_running(dev))
5075 bnx2_set_mac_addr(bp);
5076
5077 return 0;
5078 }
5079
5080 /* Called with rtnl_lock */
5081 static int
5082 bnx2_change_mtu(struct net_device *dev, int new_mtu)
5083 {
5084 struct bnx2 *bp = dev->priv;
5085
5086 if (((new_mtu + ETH_HLEN) > MAX_ETHERNET_JUMBO_PACKET_SIZE) ||
5087 ((new_mtu + ETH_HLEN) < MIN_ETHERNET_PACKET_SIZE))
5088 return -EINVAL;
5089
5090 dev->mtu = new_mtu;
5091 if (netif_running(dev)) {
5092 bnx2_netif_stop(bp);
5093
5094 bnx2_init_nic(bp);
5095
5096 bnx2_netif_start(bp);
5097 }
5098 return 0;
5099 }
5100
5101 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
5102 static void
5103 poll_bnx2(struct net_device *dev)
5104 {
5105 struct bnx2 *bp = dev->priv;
5106
5107 disable_irq(bp->pdev->irq);
5108 bnx2_interrupt(bp->pdev->irq, dev, NULL);
5109 enable_irq(bp->pdev->irq);
5110 }
5111 #endif
5112
5113 static int __devinit
5114 bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
5115 {
5116 struct bnx2 *bp;
5117 unsigned long mem_len;
5118 int rc;
5119 u32 reg;
5120
5121 SET_MODULE_OWNER(dev);
5122 SET_NETDEV_DEV(dev, &pdev->dev);
5123 bp = dev->priv;
5124
5125 bp->flags = 0;
5126 bp->phy_flags = 0;
5127
5128 /* enable device (incl. PCI PM wakeup), and bus-mastering */
5129 rc = pci_enable_device(pdev);
5130 if (rc) {
5131 printk(KERN_ERR PFX "Cannot enable PCI device, aborting.");
5132 goto err_out;
5133 }
5134
5135 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
5136 printk(KERN_ERR PFX "Cannot find PCI device base address, "
5137 "aborting.\n");
5138 rc = -ENODEV;
5139 goto err_out_disable;
5140 }
5141
5142 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
5143 if (rc) {
5144 printk(KERN_ERR PFX "Cannot obtain PCI resources, aborting.\n");
5145 goto err_out_disable;
5146 }
5147
5148 pci_set_master(pdev);
5149
5150 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
5151 if (bp->pm_cap == 0) {
5152 printk(KERN_ERR PFX "Cannot find power management capability, "
5153 "aborting.\n");
5154 rc = -EIO;
5155 goto err_out_release;
5156 }
5157
5158 bp->pcix_cap = pci_find_capability(pdev, PCI_CAP_ID_PCIX);
5159 if (bp->pcix_cap == 0) {
5160 printk(KERN_ERR PFX "Cannot find PCIX capability, aborting.\n");
5161 rc = -EIO;
5162 goto err_out_release;
5163 }
5164
5165 if (pci_set_dma_mask(pdev, DMA_64BIT_MASK) == 0) {
5166 bp->flags |= USING_DAC_FLAG;
5167 if (pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK) != 0) {
5168 printk(KERN_ERR PFX "pci_set_consistent_dma_mask "
5169 "failed, aborting.\n");
5170 rc = -EIO;
5171 goto err_out_release;
5172 }
5173 }
5174 else if (pci_set_dma_mask(pdev, DMA_32BIT_MASK) != 0) {
5175 printk(KERN_ERR PFX "System does not support DMA, aborting.\n");
5176 rc = -EIO;
5177 goto err_out_release;
5178 }
5179
5180 bp->dev = dev;
5181 bp->pdev = pdev;
5182
5183 spin_lock_init(&bp->phy_lock);
5184 spin_lock_init(&bp->tx_lock);
5185 INIT_WORK(&bp->reset_task, bnx2_reset_task, bp);
5186
5187 dev->base_addr = dev->mem_start = pci_resource_start(pdev, 0);
5188 mem_len = MB_GET_CID_ADDR(17);
5189 dev->mem_end = dev->mem_start + mem_len;
5190 dev->irq = pdev->irq;
5191
5192 bp->regview = ioremap_nocache(dev->base_addr, mem_len);
5193
5194 if (!bp->regview) {
5195 printk(KERN_ERR PFX "Cannot map register space, aborting.\n");
5196 rc = -ENOMEM;
5197 goto err_out_release;
5198 }
5199
5200 /* Configure byte swap and enable write to the reg_window registers.
5201 * Rely on CPU to do target byte swapping on big endian systems
5202 * The chip's target access swapping will not swap all accesses
5203 */
5204 pci_write_config_dword(bp->pdev, BNX2_PCICFG_MISC_CONFIG,
5205 BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
5206 BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP);
5207
5208 bnx2_set_power_state(bp, PCI_D0);
5209
5210 bp->chip_id = REG_RD(bp, BNX2_MISC_ID);
5211
5212 bp->phy_addr = 1;
5213
5214 /* Get bus information. */
5215 reg = REG_RD(bp, BNX2_PCICFG_MISC_STATUS);
5216 if (reg & BNX2_PCICFG_MISC_STATUS_PCIX_DET) {
5217 u32 clkreg;
5218
5219 bp->flags |= PCIX_FLAG;
5220
5221 clkreg = REG_RD(bp, BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS);
5222
5223 clkreg &= BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
5224 switch (clkreg) {
5225 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
5226 bp->bus_speed_mhz = 133;
5227 break;
5228
5229 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
5230 bp->bus_speed_mhz = 100;
5231 break;
5232
5233 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
5234 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
5235 bp->bus_speed_mhz = 66;
5236 break;
5237
5238 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
5239 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
5240 bp->bus_speed_mhz = 50;
5241 break;
5242
5243 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
5244 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
5245 case BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
5246 bp->bus_speed_mhz = 33;
5247 break;
5248 }
5249 }
5250 else {
5251 if (reg & BNX2_PCICFG_MISC_STATUS_M66EN)
5252 bp->bus_speed_mhz = 66;
5253 else
5254 bp->bus_speed_mhz = 33;
5255 }
5256
5257 if (reg & BNX2_PCICFG_MISC_STATUS_32BIT_DET)
5258 bp->flags |= PCI_32BIT_FLAG;
5259
5260 /* 5706A0 may falsely detect SERR and PERR. */
5261 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
5262 reg = REG_RD(bp, PCI_COMMAND);
5263 reg &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
5264 REG_WR(bp, PCI_COMMAND, reg);
5265 }
5266 else if ((CHIP_ID(bp) == CHIP_ID_5706_A1) &&
5267 !(bp->flags & PCIX_FLAG)) {
5268
5269 printk(KERN_ERR PFX "5706 A1 can only be used in a PCIX bus, "
5270 "aborting.\n");
5271 goto err_out_unmap;
5272 }
5273
5274 bnx2_init_nvram(bp);
5275
5276 /* Get the permanent MAC address. First we need to make sure the
5277 * firmware is actually running.
5278 */
5279 reg = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_DEV_INFO_SIGNATURE);
5280
5281 if ((reg & BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
5282 BNX2_DEV_INFO_SIGNATURE_MAGIC) {
5283 printk(KERN_ERR PFX "Firmware not running, aborting.\n");
5284 rc = -ENODEV;
5285 goto err_out_unmap;
5286 }
5287
5288 bp->fw_ver = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE +
5289 BNX2_DEV_INFO_BC_REV);
5290
5291 reg = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_PORT_HW_CFG_MAC_UPPER);
5292 bp->mac_addr[0] = (u8) (reg >> 8);
5293 bp->mac_addr[1] = (u8) reg;
5294
5295 reg = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE + BNX2_PORT_HW_CFG_MAC_LOWER);
5296 bp->mac_addr[2] = (u8) (reg >> 24);
5297 bp->mac_addr[3] = (u8) (reg >> 16);
5298 bp->mac_addr[4] = (u8) (reg >> 8);
5299 bp->mac_addr[5] = (u8) reg;
5300
5301 bp->tx_ring_size = MAX_TX_DESC_CNT;
5302 bp->rx_ring_size = 100;
5303
5304 bp->rx_csum = 1;
5305
5306 bp->rx_offset = sizeof(struct l2_fhdr) + 2;
5307
5308 bp->tx_quick_cons_trip_int = 20;
5309 bp->tx_quick_cons_trip = 20;
5310 bp->tx_ticks_int = 80;
5311 bp->tx_ticks = 80;
5312
5313 bp->rx_quick_cons_trip_int = 6;
5314 bp->rx_quick_cons_trip = 6;
5315 bp->rx_ticks_int = 18;
5316 bp->rx_ticks = 18;
5317
5318 bp->stats_ticks = 1000000 & 0xffff00;
5319
5320 bp->timer_interval = HZ;
5321 bp->current_interval = HZ;
5322
5323 /* Disable WOL support if we are running on a SERDES chip. */
5324 if (CHIP_BOND_ID(bp) & CHIP_BOND_ID_SERDES_BIT) {
5325 bp->phy_flags |= PHY_SERDES_FLAG;
5326 bp->flags |= NO_WOL_FLAG;
5327 }
5328
5329 if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
5330 bp->tx_quick_cons_trip_int =
5331 bp->tx_quick_cons_trip;
5332 bp->tx_ticks_int = bp->tx_ticks;
5333 bp->rx_quick_cons_trip_int =
5334 bp->rx_quick_cons_trip;
5335 bp->rx_ticks_int = bp->rx_ticks;
5336 bp->comp_prod_trip_int = bp->comp_prod_trip;
5337 bp->com_ticks_int = bp->com_ticks;
5338 bp->cmd_ticks_int = bp->cmd_ticks;
5339 }
5340
5341 bp->autoneg = AUTONEG_SPEED | AUTONEG_FLOW_CTRL;
5342 bp->req_line_speed = 0;
5343 if (bp->phy_flags & PHY_SERDES_FLAG) {
5344 bp->advertising = ETHTOOL_ALL_FIBRE_SPEED | ADVERTISED_Autoneg;
5345
5346 reg = REG_RD_IND(bp, HOST_VIEW_SHMEM_BASE +
5347 BNX2_PORT_HW_CFG_CONFIG);
5348 reg &= BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK;
5349 if (reg == BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G) {
5350 bp->autoneg = 0;
5351 bp->req_line_speed = bp->line_speed = SPEED_1000;
5352 bp->req_duplex = DUPLEX_FULL;
5353 }
5354 }
5355 else {
5356 bp->advertising = ETHTOOL_ALL_COPPER_SPEED | ADVERTISED_Autoneg;
5357 }
5358
5359 bp->req_flow_ctrl = FLOW_CTRL_RX | FLOW_CTRL_TX;
5360
5361 init_timer(&bp->timer);
5362 bp->timer.expires = RUN_AT(bp->timer_interval);
5363 bp->timer.data = (unsigned long) bp;
5364 bp->timer.function = bnx2_timer;
5365
5366 return 0;
5367
5368 err_out_unmap:
5369 if (bp->regview) {
5370 iounmap(bp->regview);
5371 bp->regview = NULL;
5372 }
5373
5374 err_out_release:
5375 pci_release_regions(pdev);
5376
5377 err_out_disable:
5378 pci_disable_device(pdev);
5379 pci_set_drvdata(pdev, NULL);
5380
5381 err_out:
5382 return rc;
5383 }
5384
5385 static int __devinit
5386 bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
5387 {
5388 static int version_printed = 0;
5389 struct net_device *dev = NULL;
5390 struct bnx2 *bp;
5391 int rc, i;
5392
5393 if (version_printed++ == 0)
5394 printk(KERN_INFO "%s", version);
5395
5396 /* dev zeroed in init_etherdev */
5397 dev = alloc_etherdev(sizeof(*bp));
5398
5399 if (!dev)
5400 return -ENOMEM;
5401
5402 rc = bnx2_init_board(pdev, dev);
5403 if (rc < 0) {
5404 free_netdev(dev);
5405 return rc;
5406 }
5407
5408 dev->open = bnx2_open;
5409 dev->hard_start_xmit = bnx2_start_xmit;
5410 dev->stop = bnx2_close;
5411 dev->get_stats = bnx2_get_stats;
5412 dev->set_multicast_list = bnx2_set_rx_mode;
5413 dev->do_ioctl = bnx2_ioctl;
5414 dev->set_mac_address = bnx2_change_mac_addr;
5415 dev->change_mtu = bnx2_change_mtu;
5416 dev->tx_timeout = bnx2_tx_timeout;
5417 dev->watchdog_timeo = TX_TIMEOUT;
5418 #ifdef BCM_VLAN
5419 dev->vlan_rx_register = bnx2_vlan_rx_register;
5420 dev->vlan_rx_kill_vid = bnx2_vlan_rx_kill_vid;
5421 #endif
5422 dev->poll = bnx2_poll;
5423 dev->ethtool_ops = &bnx2_ethtool_ops;
5424 dev->weight = 64;
5425
5426 bp = dev->priv;
5427
5428 #if defined(HAVE_POLL_CONTROLLER) || defined(CONFIG_NET_POLL_CONTROLLER)
5429 dev->poll_controller = poll_bnx2;
5430 #endif
5431
5432 if ((rc = register_netdev(dev))) {
5433 printk(KERN_ERR PFX "Cannot register net device\n");
5434 if (bp->regview)
5435 iounmap(bp->regview);
5436 pci_release_regions(pdev);
5437 pci_disable_device(pdev);
5438 pci_set_drvdata(pdev, NULL);
5439 free_netdev(dev);
5440 return rc;
5441 }
5442
5443 pci_set_drvdata(pdev, dev);
5444
5445 memcpy(dev->dev_addr, bp->mac_addr, 6);
5446 memcpy(dev->perm_addr, bp->mac_addr, 6);
5447 bp->name = board_info[ent->driver_data].name,
5448 printk(KERN_INFO "%s: %s (%c%d) PCI%s %s %dMHz found at mem %lx, "
5449 "IRQ %d, ",
5450 dev->name,
5451 bp->name,
5452 ((CHIP_ID(bp) & 0xf000) >> 12) + 'A',
5453 ((CHIP_ID(bp) & 0x0ff0) >> 4),
5454 ((bp->flags & PCIX_FLAG) ? "-X" : ""),
5455 ((bp->flags & PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
5456 bp->bus_speed_mhz,
5457 dev->base_addr,
5458 bp->pdev->irq);
5459
5460 printk("node addr ");
5461 for (i = 0; i < 6; i++)
5462 printk("%2.2x", dev->dev_addr[i]);
5463 printk("\n");
5464
5465 dev->features |= NETIF_F_SG;
5466 if (bp->flags & USING_DAC_FLAG)
5467 dev->features |= NETIF_F_HIGHDMA;
5468 dev->features |= NETIF_F_IP_CSUM;
5469 #ifdef BCM_VLAN
5470 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
5471 #endif
5472 #ifdef BCM_TSO
5473 dev->features |= NETIF_F_TSO;
5474 #endif
5475
5476 netif_carrier_off(bp->dev);
5477
5478 return 0;
5479 }
5480
5481 static void __devexit
5482 bnx2_remove_one(struct pci_dev *pdev)
5483 {
5484 struct net_device *dev = pci_get_drvdata(pdev);
5485 struct bnx2 *bp = dev->priv;
5486
5487 flush_scheduled_work();
5488
5489 unregister_netdev(dev);
5490
5491 if (bp->regview)
5492 iounmap(bp->regview);
5493
5494 free_netdev(dev);
5495 pci_release_regions(pdev);
5496 pci_disable_device(pdev);
5497 pci_set_drvdata(pdev, NULL);
5498 }
5499
5500 static int
5501 bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
5502 {
5503 struct net_device *dev = pci_get_drvdata(pdev);
5504 struct bnx2 *bp = dev->priv;
5505 u32 reset_code;
5506
5507 if (!netif_running(dev))
5508 return 0;
5509
5510 bnx2_netif_stop(bp);
5511 netif_device_detach(dev);
5512 del_timer_sync(&bp->timer);
5513 if (bp->wol)
5514 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
5515 else
5516 reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
5517 bnx2_reset_chip(bp, reset_code);
5518 bnx2_free_skbs(bp);
5519 bnx2_set_power_state(bp, pci_choose_state(pdev, state));
5520 return 0;
5521 }
5522
5523 static int
5524 bnx2_resume(struct pci_dev *pdev)
5525 {
5526 struct net_device *dev = pci_get_drvdata(pdev);
5527 struct bnx2 *bp = dev->priv;
5528
5529 if (!netif_running(dev))
5530 return 0;
5531
5532 bnx2_set_power_state(bp, PCI_D0);
5533 netif_device_attach(dev);
5534 bnx2_init_nic(bp);
5535 bnx2_netif_start(bp);
5536 return 0;
5537 }
5538
5539 static struct pci_driver bnx2_pci_driver = {
5540 .name = DRV_MODULE_NAME,
5541 .id_table = bnx2_pci_tbl,
5542 .probe = bnx2_init_one,
5543 .remove = __devexit_p(bnx2_remove_one),
5544 .suspend = bnx2_suspend,
5545 .resume = bnx2_resume,
5546 };
5547
5548 static int __init bnx2_init(void)
5549 {
5550 return pci_module_init(&bnx2_pci_driver);
5551 }
5552
5553 static void __exit bnx2_cleanup(void)
5554 {
5555 pci_unregister_driver(&bnx2_pci_driver);
5556 }
5557
5558 module_init(bnx2_init);
5559 module_exit(bnx2_cleanup);
5560
5561
5562
Linux 2.6 libata-dev (mirror)