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Revert "ASoC: ad1836: reset and restore clock control mode in suspend/resume entry"
[linux-2.6/libata-dev.git] / drivers / staging / rtl8192e / r8192E.h
blob61b6f250b91704af94c4fa30ae7358344d0786fd
1 /*
2 This is part of rtl8187 OpenSource driver.
3 Copyright (C) Andrea Merello 2004-2005 <andreamrl@tiscali.it>
4 Released under the terms of GPL (General Public Licence)
5
6 Parts of this driver are based on the GPL part of the
7 official realtek driver
8
9 Parts of this driver are based on the rtl8192 driver skeleton
10 from Patric Schenke & Andres Salomon
11
12 Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver
13
14 We want to tanks the Authors of those projects and the Ndiswrapper
15 project Authors.
16 */
17
18 #ifndef R819xU_H
19 #define R819xU_H
20
21 #include <linux/module.h>
22 #include <linux/kernel.h>
23 //#include <linux/config.h>
24 #include <linux/init.h>
25 #include <linux/ioport.h>
26 #include <linux/sched.h>
27 #include <linux/types.h>
28 #include <linux/slab.h>
29 #include <linux/netdevice.h>
30 #include <linux/pci.h>
31 //#include <linux/usb.h>
32 #include <linux/etherdevice.h>
33 #include <linux/delay.h>
34 #include <linux/rtnetlink.h> //for rtnl_lock()
35 #include <linux/wireless.h>
36 #include <linux/timer.h>
37 #include <linux/proc_fs.h> // Necessary because we use the proc fs
38 #include <linux/if_arp.h>
39 #include <linux/random.h>
40 #include <linux/version.h>
41 #include <asm/io.h>
42 #include "ieee80211.h"
43
44
45
46
47 #define RTL819xE_MODULE_NAME "rtl819xE"
48 //added for HW security, john.0629
49 #define FALSE 0
50 #define TRUE 1
51 #define MAX_KEY_LEN 61
52 #define KEY_BUF_SIZE 5
53
54 #define BIT0 0x00000001
55 #define BIT1 0x00000002
56 #define BIT2 0x00000004
57 #define BIT3 0x00000008
58 #define BIT4 0x00000010
59 #define BIT5 0x00000020
60 #define BIT6 0x00000040
61 #define BIT7 0x00000080
62 #define BIT8 0x00000100
63 #define BIT9 0x00000200
64 #define BIT10 0x00000400
65 #define BIT11 0x00000800
66 #define BIT12 0x00001000
67 #define BIT13 0x00002000
68 #define BIT14 0x00004000
69 #define BIT15 0x00008000
70 #define BIT16 0x00010000
71 #define BIT17 0x00020000
72 #define BIT18 0x00040000
73 #define BIT19 0x00080000
74 #define BIT20 0x00100000
75 #define BIT21 0x00200000
76 #define BIT22 0x00400000
77 #define BIT23 0x00800000
78 #define BIT24 0x01000000
79 #define BIT25 0x02000000
80 #define BIT26 0x04000000
81 #define BIT27 0x08000000
82 #define BIT28 0x10000000
83 #define BIT29 0x20000000
84 #define BIT30 0x40000000
85 #define BIT31 0x80000000
86 // Rx smooth factor
87 #define Rx_Smooth_Factor 20
88 /* 2007/06/04 MH Define sliding window for RSSI history. */
89 #define PHY_RSSI_SLID_WIN_MAX 100
90 #define PHY_Beacon_RSSI_SLID_WIN_MAX 10
91
92 #define IC_VersionCut_D 0x3
93 #define IC_VersionCut_E 0x4
94
95 #if 0 //we need to use RT_TRACE instead DMESG as RT_TRACE will clearly show debug level wb.
96 #define DMESG(x,a...) printk(KERN_INFO RTL819xE_MODULE_NAME ": " x "\n", ## a)
97 #define DMESGW(x,a...) printk(KERN_WARNING RTL819xE_MODULE_NAME ": WW:" x "\n", ## a)
98 #define DMESGE(x,a...) printk(KERN_WARNING RTL819xE_MODULE_NAME ": EE:" x "\n", ## a)
99 #else
100 #define DMESG(x,a...)
101 #define DMESGW(x,a...)
102 #define DMESGE(x,a...)
103 extern u32 rt_global_debug_component;
104 #define RT_TRACE(component, x, args...) \
105 do { if(rt_global_debug_component & component) \
106 printk(KERN_DEBUG RTL819xE_MODULE_NAME ":" x "\n" , \
107 ##args);\
108 }while(0);
109
110 #define COMP_TRACE BIT0 // For function call tracing.
111 #define COMP_DBG BIT1 // Only for temporary debug message.
112 #define COMP_INIT BIT2 // during driver initialization / halt / reset.
113
114
115 #define COMP_RECV BIT3 // Reveive part data path.
116 #define COMP_SEND BIT4 // Send part path.
117 #define COMP_IO BIT5 // I/O Related. Added by Annie, 2006-03-02.
118 #define COMP_POWER BIT6 // 802.11 Power Save mode or System/Device Power state related.
119 #define COMP_EPROM BIT7 // 802.11 link related: join/start BSS, leave BSS.
120 #define COMP_SWBW BIT8 // For bandwidth switch.
121 #define COMP_SEC BIT9// For Security.
122
123
124 #define COMP_TURBO BIT10 // For Turbo Mode related. By Annie, 2005-10-21.
125 #define COMP_QOS BIT11 // For QoS.
126
127 #define COMP_RATE BIT12 // For Rate Adaptive mechanism, 2006.07.02, by rcnjko. #define COMP_EVENTS 0x00000080 // Event handling
128 #define COMP_RXDESC BIT13 // Show Rx desc information for SD3 debug. Added by Annie, 2006-07-15.
129 #define COMP_PHY BIT14
130 #define COMP_DIG BIT15 // For DIG, 2006.09.25, by rcnjko.
131 #define COMP_TXAGC BIT16 // For Tx power, 060928, by rcnjko.
132 #define COMP_HALDM BIT17 // For HW Dynamic Mechanism, 061010, by rcnjko.
133 #define COMP_POWER_TRACKING BIT18 //FOR 8190 TX POWER TRACKING
134 #define COMP_EVENTS BIT19 // Event handling
135
136 #define COMP_RF BIT20 // For RF.
137 //1!!!!!!!!!!!!!!!!!!!!!!!!!!!
138 //1//1Attention Please!!!<11n or 8190 specific code should be put below this line>
139 //1!!!!!!!!!!!!!!!!!!!!!!!!!!!
140
141 #define COMP_FIRMWARE BIT21 //for firmware downloading
142 #define COMP_HT BIT22 // For 802.11n HT related information. by Emily 2006-8-11
143
144 #define COMP_RESET BIT23
145 #define COMP_CMDPKT BIT24
146 #define COMP_SCAN BIT25
147 #define COMP_IPS BIT26
148 #define COMP_DOWN BIT27 // for rm driver module
149 #define COMP_INTR BIT28 // for interrupt
150 #define COMP_ERR BIT31 // for error out, always on
151 #endif
152
153 #define RTL819x_DEBUG
154 #ifdef RTL819x_DEBUG
155 #define assert(expr) \
156 if (!(expr)) { \
157 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
158 #expr,__FILE__,__FUNCTION__,__LINE__); \
159 }
160 //wb added to debug out data buf
161 //if you want print DATA buffer related BA, please set ieee80211_debug_level to DATA|BA
162 #define RT_DEBUG_DATA(level, data, datalen) \
163 do{ if ((rt_global_debug_component & (level)) == (level)) \
164 { \
165 int i; \
166 u8* pdata = (u8*) data; \
167 printk(KERN_DEBUG RTL819xE_MODULE_NAME ": %s()\n", __FUNCTION__); \
168 for(i=0; i<(int)(datalen); i++) \
169 { \
170 printk("%2x ", pdata[i]); \
171 if ((i+1)%16 == 0) printk("\n"); \
172 } \
173 printk("\n"); \
174 } \
175 } while (0)
176 #else
177 #define assert(expr) do {} while (0)
178 #define RT_DEBUG_DATA(level, data, datalen) do {} while(0)
179 #endif /* RTL8169_DEBUG */
180
181
182 //
183 // Queue Select Value in TxDesc
184 //
185 #define QSLT_BK 0x1
186 #define QSLT_BE 0x0
187 #define QSLT_VI 0x4
188 #define QSLT_VO 0x6
189 #define QSLT_BEACON 0x10
190 #define QSLT_HIGH 0x11
191 #define QSLT_MGNT 0x12
192 #define QSLT_CMD 0x13
193
194 #define DESC90_RATE1M 0x00
195 #define DESC90_RATE2M 0x01
196 #define DESC90_RATE5_5M 0x02
197 #define DESC90_RATE11M 0x03
198 #define DESC90_RATE6M 0x04
199 #define DESC90_RATE9M 0x05
200 #define DESC90_RATE12M 0x06
201 #define DESC90_RATE18M 0x07
202 #define DESC90_RATE24M 0x08
203 #define DESC90_RATE36M 0x09
204 #define DESC90_RATE48M 0x0a
205 #define DESC90_RATE54M 0x0b
206 #define DESC90_RATEMCS0 0x00
207 #define DESC90_RATEMCS1 0x01
208 #define DESC90_RATEMCS2 0x02
209 #define DESC90_RATEMCS3 0x03
210 #define DESC90_RATEMCS4 0x04
211 #define DESC90_RATEMCS5 0x05
212 #define DESC90_RATEMCS6 0x06
213 #define DESC90_RATEMCS7 0x07
214 #define DESC90_RATEMCS8 0x08
215 #define DESC90_RATEMCS9 0x09
216 #define DESC90_RATEMCS10 0x0a
217 #define DESC90_RATEMCS11 0x0b
218 #define DESC90_RATEMCS12 0x0c
219 #define DESC90_RATEMCS13 0x0d
220 #define DESC90_RATEMCS14 0x0e
221 #define DESC90_RATEMCS15 0x0f
222 #define DESC90_RATEMCS32 0x20
223
224 #define RTL819X_DEFAULT_RF_TYPE RF_1T2R
225 #define EEPROM_Default_LegacyHTTxPowerDiff 0x4
226 #define IEEE80211_WATCH_DOG_TIME 2000
227
228 /* For rtl819x */
229 typedef struct _tx_desc_819x_pci {
230 //DWORD 0
231 u16 PktSize;
232 u8 Offset;
233 u8 Reserved1:3;
234 u8 CmdInit:1;
235 u8 LastSeg:1;
236 u8 FirstSeg:1;
237 u8 LINIP:1;
238 u8 OWN:1;
239
240 //DWORD 1
241 u8 TxFWInfoSize;
242 u8 RATid:3;
243 u8 DISFB:1;
244 u8 USERATE:1;
245 u8 MOREFRAG:1;
246 u8 NoEnc:1;
247 u8 PIFS:1;
248 u8 QueueSelect:5;
249 u8 NoACM:1;
250 u8 Resv:2;
251 u8 SecCAMID:5;
252 u8 SecDescAssign:1;
253 u8 SecType:2;
254
255 //DWORD 2
256 u16 TxBufferSize;
257 u8 PktId:7;
258 u8 Resv1:1;
259 u8 Reserved2;
260
261 //DWORD 3
262 u32 TxBuffAddr;
263
264 //DWORD 4
265 u32 NextDescAddress;
266
267 //DWORD 5,6,7
268 u32 Reserved5;
269 u32 Reserved6;
270 u32 Reserved7;
271 }tx_desc_819x_pci, *ptx_desc_819x_pci;
272
273
274 typedef struct _tx_desc_cmd_819x_pci {
275 //DWORD 0
276 u16 PktSize;
277 u8 Reserved1;
278 u8 CmdType:3;
279 u8 CmdInit:1;
280 u8 LastSeg:1;
281 u8 FirstSeg:1;
282 u8 LINIP:1;
283 u8 OWN:1;
284
285 //DOWRD 1
286 u16 ElementReport;
287 u16 Reserved2;
288
289 //DOWRD 2
290 u16 TxBufferSize;
291 u16 Reserved3;
292
293 //DWORD 3,4,5
294 u32 TxBufferAddr;
295 u32 NextDescAddress;
296 u32 Reserved4;
297 u32 Reserved5;
298 u32 Reserved6;
299 }tx_desc_cmd_819x_pci, *ptx_desc_cmd_819x_pci;
300
301
302 typedef struct _tx_fwinfo_819x_pci {
303 //DOWRD 0
304 u8 TxRate:7;
305 u8 CtsEnable:1;
306 u8 RtsRate:7;
307 u8 RtsEnable:1;
308 u8 TxHT:1;
309 u8 Short:1; //Short PLCP for CCK, or short GI for 11n MCS
310 u8 TxBandwidth:1; // This is used for HT MCS rate only.
311 u8 TxSubCarrier:2; // This is used for legacy OFDM rate only.
312 u8 STBC:2;
313 u8 AllowAggregation:1;
314 u8 RtsHT:1; //Interpre RtsRate field as high throughput data rate
315 u8 RtsShort:1; //Short PLCP for CCK, or short GI for 11n MCS
316 u8 RtsBandwidth:1; // This is used for HT MCS rate only.
317 u8 RtsSubcarrier:2; // This is used for legacy OFDM rate only.
318 u8 RtsSTBC:2;
319 u8 EnableCPUDur:1; //Enable firmware to recalculate and assign packet duration
320
321 //DWORD 1
322 u8 RxMF:2;
323 u8 RxAMD:3;
324 u8 Reserved1:3;
325 u8 Reserved2;
326 u8 Reserved3;
327 u8 Reserved4;
328
329 //u32 Reserved;
330 }tx_fwinfo_819x_pci, *ptx_fwinfo_819x_pci;
331
332 typedef struct rtl8192_rx_info {
333 struct urb *urb;
334 struct net_device *dev;
335 u8 out_pipe;
336 }rtl8192_rx_info ;
337 typedef struct _rx_desc_819x_pci{
338 //DOWRD 0
339 u16 Length:14;
340 u16 CRC32:1;
341 u16 ICV:1;
342 u8 RxDrvInfoSize;
343 u8 Shift:2;
344 u8 PHYStatus:1;
345 u8 SWDec:1;
346 u8 LastSeg:1;
347 u8 FirstSeg:1;
348 u8 EOR:1;
349 u8 OWN:1;
350
351 //DWORD 1
352 u32 Reserved2;
353
354 //DWORD 2
355 u32 Reserved3;
356
357 //DWORD 3
358 u32 BufferAddress;
359
360 }rx_desc_819x_pci, *prx_desc_819x_pci;
361
362 typedef struct _rx_fwinfo_819x_pci{
363 //DWORD 0
364 u16 Reserved1:12;
365 u16 PartAggr:1;
366 u16 FirstAGGR:1;
367 u16 Reserved2:2;
368
369 u8 RxRate:7;
370 u8 RxHT:1;
371
372 u8 BW:1;
373 u8 SPLCP:1;
374 u8 Reserved3:2;
375 u8 PAM:1;
376 u8 Mcast:1;
377 u8 Bcast:1;
378 u8 Reserved4:1;
379
380 //DWORD 1
381 u32 TSFL;
382
383 }rx_fwinfo_819x_pci, *prx_fwinfo_819x_pci;
384
385 #define MAX_DEV_ADDR_SIZE 8 /* support till 64 bit bus width OS */
386 #define MAX_FIRMWARE_INFORMATION_SIZE 32 /*2006/04/30 by Emily forRTL8190*/
387 #define MAX_802_11_HEADER_LENGTH (40 + MAX_FIRMWARE_INFORMATION_SIZE)
388 #define ENCRYPTION_MAX_OVERHEAD 128
389 //#define USB_HWDESC_HEADER_LEN sizeof(tx_desc_819x_usb)
390 //#define TX_PACKET_SHIFT_BYTES (USB_HWDESC_HEADER_LEN + sizeof(tx_fwinfo_819x_usb))
391 #define MAX_FRAGMENT_COUNT 8
392 #define MAX_TRANSMIT_BUFFER_SIZE (1600+(MAX_802_11_HEADER_LENGTH+ENCRYPTION_MAX_OVERHEAD)*MAX_FRAGMENT_COUNT)
393
394 #define scrclng 4 // octets for crc32 (FCS, ICV)
395 /* 8190 Loopback Mode definition */
396 typedef enum _rtl819x_loopback{
397 RTL819X_NO_LOOPBACK = 0,
398 RTL819X_MAC_LOOPBACK = 1,
399 RTL819X_DMA_LOOPBACK = 2,
400 RTL819X_CCK_LOOPBACK = 3,
401 }rtl819x_loopback_e;
402
403 /* due to rtl8192 firmware */
404 typedef enum _desc_packet_type_e{
405 DESC_PACKET_TYPE_INIT = 0,
406 DESC_PACKET_TYPE_NORMAL = 1,
407 }desc_packet_type_e;
408
409 typedef enum _firmware_source{
410 FW_SOURCE_IMG_FILE = 0,
411 FW_SOURCE_HEADER_FILE = 1, //from header file
412 }firmware_source_e, *pfirmware_source_e;
413
414 typedef enum _firmware_status{
415 FW_STATUS_0_INIT = 0,
416 FW_STATUS_1_MOVE_BOOT_CODE = 1,
417 FW_STATUS_2_MOVE_MAIN_CODE = 2,
418 FW_STATUS_3_TURNON_CPU = 3,
419 FW_STATUS_4_MOVE_DATA_CODE = 4,
420 FW_STATUS_5_READY = 5,
421 }firmware_status_e;
422
423 typedef struct _rt_firmare_seg_container {
424 u16 seg_size;
425 u8 *seg_ptr;
426 }fw_seg_container, *pfw_seg_container;
427
428 typedef struct _rt_firmware{
429 firmware_status_e firmware_status;
430 u16 cmdpacket_frag_thresold;
431 #define RTL8190_MAX_FIRMWARE_CODE_SIZE 64000 //64k
432 #define MAX_FW_INIT_STEP 3
433 u8 firmware_buf[MAX_FW_INIT_STEP][RTL8190_MAX_FIRMWARE_CODE_SIZE];
434 u16 firmware_buf_size[MAX_FW_INIT_STEP];
435 }rt_firmware, *prt_firmware;
436 //+by amy 080507
437 #define MAX_RECEIVE_BUFFER_SIZE 9100 // Add this to 9100 bytes to receive A-MSDU from RT-AP
438
439 /* Firmware Queue Layout */
440 #define NUM_OF_FIRMWARE_QUEUE 10
441 #define NUM_OF_PAGES_IN_FW 0x100
442 #define NUM_OF_PAGE_IN_FW_QUEUE_BE 0x0aa
443 #define NUM_OF_PAGE_IN_FW_QUEUE_BK 0x007
444 #define NUM_OF_PAGE_IN_FW_QUEUE_VI 0x024
445 #define NUM_OF_PAGE_IN_FW_QUEUE_VO 0x007
446 #define NUM_OF_PAGE_IN_FW_QUEUE_HCCA 0
447 #define NUM_OF_PAGE_IN_FW_QUEUE_CMD 0x2
448 #define NUM_OF_PAGE_IN_FW_QUEUE_MGNT 0x10
449 #define NUM_OF_PAGE_IN_FW_QUEUE_HIGH 0
450 #define NUM_OF_PAGE_IN_FW_QUEUE_BCN 0x4
451 #define NUM_OF_PAGE_IN_FW_QUEUE_PUB 0xd
452 #define APPLIED_RESERVED_QUEUE_IN_FW 0x80000000
453 #define RSVD_FW_QUEUE_PAGE_BK_SHIFT 0x00
454 #define RSVD_FW_QUEUE_PAGE_BE_SHIFT 0x08
455 #define RSVD_FW_QUEUE_PAGE_VI_SHIFT 0x10
456 #define RSVD_FW_QUEUE_PAGE_VO_SHIFT 0x18
457 #define RSVD_FW_QUEUE_PAGE_MGNT_SHIFT 0x10
458 #define RSVD_FW_QUEUE_PAGE_CMD_SHIFT 0x08
459 #define RSVD_FW_QUEUE_PAGE_BCN_SHIFT 0x00
460 #define RSVD_FW_QUEUE_PAGE_PUB_SHIFT 0x08
461
462 //8187B Security
463 //#define RWCAM 0xA0 // Software read/write CAM config
464 //#define WCAMI 0xA4 // Software write CAM input content
465 //#define RCAMO 0xA8 // Output value from CAM according to 0xa0 setting
466 #define DCAM 0xAC // Debug CAM Interface
467 #define AESMSK_FC 0xB2 // AES Mask register for frame control (0xB2~0xB3). Added by Annie, 2006-03-06.
468
469
470 #define CAM_CONTENT_COUNT 8
471 //#define CFG_DEFAULT_KEY BIT5
472 #define CFG_VALID BIT15
473 #if 0
474 //----------------------------------------------------------------------------
475 // 8187B WPA Config Register (offset 0xb0, 1 byte)
476 //----------------------------------------------------------------------------
477 #define SCR_UseDK 0x01
478 #define SCR_TxSecEnable 0x02
479 #define SCR_RxSecEnable 0x04
480
481 //----------------------------------------------------------------------------
482 // 8187B CAM Config Setting (offset 0xb0, 1 byte)
483 //----------------------------------------------------------------------------
484 #define CAM_VALID 0x8000
485 #define CAM_NOTVALID 0x0000
486 #define CAM_USEDK 0x0020
487
488
489 #define CAM_NONE 0x0
490 #define CAM_WEP40 0x01
491 #define CAM_TKIP 0x02
492 #define CAM_AES 0x04
493 #define CAM_WEP104 0x05
494
495 //#define CAM_SIZE 16
496 #define TOTAL_CAM_ENTRY 16
497 #define CAM_ENTRY_LEN_IN_DW 6 // 6, unit: in u4byte. Added by Annie, 2006-05-25.
498 #define CAM_ENTRY_LEN_IN_BYTE (CAM_ENTRY_LEN_IN_DW*sizeof(u32)) // 24, unit: in u1byte. Added by Annie, 2006-05-25.
499
500 #define CAM_CONFIG_USEDK 1
501 #define CAM_CONFIG_NO_USEDK 0
502
503 #define CAM_WRITE 0x00010000
504 #define CAM_READ 0x00000000
505 #define CAM_POLLINIG 0x80000000
506
507 //=================================================================
508 //=================================================================
509
510 #endif
511 #define EPROM_93c46 0
512 #define EPROM_93c56 1
513
514 #define DEFAULT_FRAG_THRESHOLD 2342U
515 #define MIN_FRAG_THRESHOLD 256U
516 #define DEFAULT_BEACONINTERVAL 0x64U
517 #define DEFAULT_BEACON_ESSID "Rtl819xU"
518
519 #define DEFAULT_SSID ""
520 #define DEFAULT_RETRY_RTS 7
521 #define DEFAULT_RETRY_DATA 7
522 #define PRISM_HDR_SIZE 64
523
524 #define PHY_RSSI_SLID_WIN_MAX 100
525
526
527 typedef enum _WIRELESS_MODE {
528 WIRELESS_MODE_UNKNOWN = 0x00,
529 WIRELESS_MODE_A = 0x01,
530 WIRELESS_MODE_B = 0x02,
531 WIRELESS_MODE_G = 0x04,
532 WIRELESS_MODE_AUTO = 0x08,
533 WIRELESS_MODE_N_24G = 0x10,
534 WIRELESS_MODE_N_5G = 0x20
535 } WIRELESS_MODE;
536
537 #define RTL_IOCTL_WPA_SUPPLICANT SIOCIWFIRSTPRIV+30
538
539 typedef struct buffer
540 {
541 struct buffer *next;
542 u32 *buf;
543 dma_addr_t dma;
544
545 } buffer;
546
547 typedef struct rtl_reg_debug{
548 unsigned int cmd;
549 struct {
550 unsigned char type;
551 unsigned char addr;
552 unsigned char page;
553 unsigned char length;
554 } head;
555 unsigned char buf[0xff];
556 }rtl_reg_debug;
557
558 #if 0
559
560 typedef struct tx_pendingbuf
561 {
562 struct ieee80211_txb *txb;
563 short ispending;
564 short descfrag;
565 } tx_pendigbuf;
566
567 #endif
568
569 typedef struct _rt_9x_tx_rate_history {
570 u32 cck[4];
571 u32 ofdm[8];
572 // HT_MCS[0][]: BW=0 SG=0
573 // HT_MCS[1][]: BW=1 SG=0
574 // HT_MCS[2][]: BW=0 SG=1
575 // HT_MCS[3][]: BW=1 SG=1
576 u32 ht_mcs[4][16];
577 }rt_tx_rahis_t, *prt_tx_rahis_t;
578
579 typedef struct _RT_SMOOTH_DATA_4RF {
580 char elements[4][100];//array to store values
581 u32 index; //index to current array to store
582 u32 TotalNum; //num of valid elements
583 u32 TotalVal[4]; //sum of valid elements
584 }RT_SMOOTH_DATA_4RF, *PRT_SMOOTH_DATA_4RF;
585
586 typedef enum _tag_TxCmd_Config_Index{
587 TXCMD_TXRA_HISTORY_CTRL = 0xFF900000,
588 TXCMD_RESET_TX_PKT_BUFF = 0xFF900001,
589 TXCMD_RESET_RX_PKT_BUFF = 0xFF900002,
590 TXCMD_SET_TX_DURATION = 0xFF900003,
591 TXCMD_SET_RX_RSSI = 0xFF900004,
592 TXCMD_SET_TX_PWR_TRACKING = 0xFF900005,
593 TXCMD_XXXX_CTRL,
594 }DCMD_TXCMD_OP;
595
596 typedef struct Stats
597 {
598 unsigned long txrdu;
599 unsigned long rxrdu;
600 //unsigned long rxnolast;
601 //unsigned long rxnodata;
602 // unsigned long rxreset;
603 // unsigned long rxnopointer;
604 unsigned long rxok;
605 unsigned long rxframgment;
606 unsigned long rxcmdpkt[4]; //08/05/08 amy rx cmd element txfeedback/bcn report/cfg set/query
607 unsigned long rxurberr;
608 unsigned long rxstaterr;
609 unsigned long rxcrcerrmin;//crc error (0-500)
610 unsigned long rxcrcerrmid;//crc error (500-1000)
611 unsigned long rxcrcerrmax;//crc error (>1000)
612 unsigned long received_rate_histogram[4][32]; //0: Total, 1:OK, 2:CRC, 3:ICV, 2007 07 03 cosa
613 unsigned long received_preamble_GI[2][32]; //0: Long preamble/GI, 1:Short preamble/GI
614 unsigned long rx_AMPDUsize_histogram[5]; // level: (<4K), (4K~8K), (8K~16K), (16K~32K), (32K~64K)
615 unsigned long rx_AMPDUnum_histogram[5]; // level: (<5), (5~10), (10~20), (20~40), (>40)
616 unsigned long numpacket_matchbssid; // debug use only.
617 unsigned long numpacket_toself; // debug use only.
618 unsigned long num_process_phyinfo; // debug use only.
619 unsigned long numqry_phystatus;
620 unsigned long numqry_phystatusCCK;
621 unsigned long numqry_phystatusHT;
622 unsigned long received_bwtype[5]; //0: 20M, 1: funn40M, 2: upper20M, 3: lower20M, 4: duplicate
623 unsigned long txnperr;
624 unsigned long txnpdrop;
625 unsigned long txresumed;
626 // unsigned long rxerr;
627 unsigned long rxoverflow;
628 unsigned long rxint;
629 unsigned long txnpokint;
630 // unsigned long txhpokint;
631 // unsigned long txhperr;
632 unsigned long ints;
633 unsigned long shints;
634 unsigned long txoverflow;
635 // unsigned long rxdmafail;
636 // unsigned long txbeacon;
637 // unsigned long txbeaconerr;
638 unsigned long txlpokint;
639 unsigned long txlpdrop;
640 unsigned long txlperr;
641 unsigned long txbeokint;
642 unsigned long txbedrop;
643 unsigned long txbeerr;
644 unsigned long txbkokint;
645 unsigned long txbkdrop;
646 unsigned long txbkerr;
647 unsigned long txviokint;
648 unsigned long txvidrop;
649 unsigned long txvierr;
650 unsigned long txvookint;
651 unsigned long txvodrop;
652 unsigned long txvoerr;
653 unsigned long txbeaconokint;
654 unsigned long txbeacondrop;
655 unsigned long txbeaconerr;
656 unsigned long txmanageokint;
657 unsigned long txmanagedrop;
658 unsigned long txmanageerr;
659 unsigned long txcmdpktokint;
660 unsigned long txdatapkt;
661 unsigned long txfeedback;
662 unsigned long txfeedbackok;
663 unsigned long txoktotal;
664 unsigned long txokbytestotal;
665 unsigned long txokinperiod;
666 unsigned long txmulticast;
667 unsigned long txbytesmulticast;
668 unsigned long txbroadcast;
669 unsigned long txbytesbroadcast;
670 unsigned long txunicast;
671 unsigned long txbytesunicast;
672 unsigned long rxbytesunicast;
673 unsigned long txfeedbackfail;
674 unsigned long txerrtotal;
675 unsigned long txerrbytestotal;
676 unsigned long txerrmulticast;
677 unsigned long txerrbroadcast;
678 unsigned long txerrunicast;
679 unsigned long txretrycount;
680 unsigned long txfeedbackretry;
681 u8 last_packet_rate;
682 unsigned long slide_signal_strength[100];
683 unsigned long slide_evm[100];
684 unsigned long slide_rssi_total; // For recording sliding window's RSSI value
685 unsigned long slide_evm_total; // For recording sliding window's EVM value
686 long signal_strength; // Transformed, in dbm. Beautified signal strength for UI, not correct.
687 long signal_quality;
688 long last_signal_strength_inpercent;
689 long recv_signal_power; // Correct smoothed ss in Dbm, only used in driver to report real power now.
690 u8 rx_rssi_percentage[4];
691 u8 rx_evm_percentage[2];
692 long rxSNRdB[4];
693 rt_tx_rahis_t txrate;
694 u32 Slide_Beacon_pwdb[100]; //cosa add for beacon rssi
695 u32 Slide_Beacon_Total; //cosa add for beacon rssi
696 RT_SMOOTH_DATA_4RF cck_adc_pwdb;
697 u32 CurrentShowTxate;
698
699
700 } Stats;
701
702
703 // Bandwidth Offset
704 #define HAL_PRIME_CHNL_OFFSET_DONT_CARE 0
705 #define HAL_PRIME_CHNL_OFFSET_LOWER 1
706 #define HAL_PRIME_CHNL_OFFSET_UPPER 2
707
708 //+by amy 080507
709
710 typedef struct ChnlAccessSetting {
711 u16 SIFS_Timer;
712 u16 DIFS_Timer;
713 u16 SlotTimeTimer;
714 u16 EIFS_Timer;
715 u16 CWminIndex;
716 u16 CWmaxIndex;
717 }*PCHANNEL_ACCESS_SETTING,CHANNEL_ACCESS_SETTING;
718
719 typedef struct _BB_REGISTER_DEFINITION{
720 u32 rfintfs; // set software control: // 0x870~0x877[8 bytes]
721 u32 rfintfi; // readback data: // 0x8e0~0x8e7[8 bytes]
722 u32 rfintfo; // output data: // 0x860~0x86f [16 bytes]
723 u32 rfintfe; // output enable: // 0x860~0x86f [16 bytes]
724 u32 rf3wireOffset; // LSSI data: // 0x840~0x84f [16 bytes]
725 u32 rfLSSI_Select; // BB Band Select: // 0x878~0x87f [8 bytes]
726 u32 rfTxGainStage; // Tx gain stage: // 0x80c~0x80f [4 bytes]
727 u32 rfHSSIPara1; // wire parameter control1 : // 0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes]
728 u32 rfHSSIPara2; // wire parameter control2 : // 0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes]
729 u32 rfSwitchControl; //Tx Rx antenna control : // 0x858~0x85f [16 bytes]
730 u32 rfAGCControl1; //AGC parameter control1 : // 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes]
731 u32 rfAGCControl2; //AGC parameter control2 : // 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes]
732 u32 rfRxIQImbalance; //OFDM Rx IQ imbalance matrix : // 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes]
733 u32 rfRxAFE; //Rx IQ DC ofset and Rx digital filter, Rx DC notch filter : // 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes]
734 u32 rfTxIQImbalance; //OFDM Tx IQ imbalance matrix // 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes]
735 u32 rfTxAFE; //Tx IQ DC Offset and Tx DFIR type // 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes]
736 u32 rfLSSIReadBack; //LSSI RF readback data // 0x8a0~0x8af [16 bytes]
737 }BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;
738
739 typedef enum _RT_RF_TYPE_819xU{
740 RF_TYPE_MIN = 0,
741 RF_8225,
742 RF_8256,
743 RF_8258,
744 RF_PSEUDO_11N = 4,
745 }RT_RF_TYPE_819xU, *PRT_RF_TYPE_819xU;
746
747
748 typedef struct _rate_adaptive
749 {
750 u8 rate_adaptive_disabled;
751 u8 ratr_state;
752 u16 reserve;
753
754 u32 high_rssi_thresh_for_ra;
755 u32 high2low_rssi_thresh_for_ra;
756 u8 low2high_rssi_thresh_for_ra40M;
757 u32 low_rssi_thresh_for_ra40M;
758 u8 low2high_rssi_thresh_for_ra20M;
759 u32 low_rssi_thresh_for_ra20M;
760 u32 upper_rssi_threshold_ratr;
761 u32 middle_rssi_threshold_ratr;
762 u32 low_rssi_threshold_ratr;
763 u32 low_rssi_threshold_ratr_40M;
764 u32 low_rssi_threshold_ratr_20M;
765 u8 ping_rssi_enable; //cosa add for test
766 u32 ping_rssi_ratr; //cosa add for test
767 u32 ping_rssi_thresh_for_ra;//cosa add for test
768 u32 last_ratr;
769
770 } rate_adaptive, *prate_adaptive;
771 #define TxBBGainTableLength 37
772 #define CCKTxBBGainTableLength 23
773 typedef struct _txbbgain_struct
774 {
775 long txbb_iq_amplifygain;
776 u32 txbbgain_value;
777 } txbbgain_struct, *ptxbbgain_struct;
778
779 typedef struct _ccktxbbgain_struct
780 {
781 //The Value is from a22 to a29 one Byte one time is much Safer
782 u8 ccktxbb_valuearray[8];
783 } ccktxbbgain_struct,*pccktxbbgain_struct;
784
785
786 typedef struct _init_gain
787 {
788 u8 xaagccore1;
789 u8 xbagccore1;
790 u8 xcagccore1;
791 u8 xdagccore1;
792 u8 cca;
793
794 } init_gain, *pinit_gain;
795
796 /* 2007/11/02 MH Define RF mode temporarily for test. */
797 typedef enum tag_Rf_Operatetion_State
798 {
799 RF_STEP_INIT = 0,
800 RF_STEP_NORMAL,
801 RF_STEP_MAX
802 }RF_STEP_E;
803
804 typedef enum _RT_STATUS{
805 RT_STATUS_SUCCESS,
806 RT_STATUS_FAILURE,
807 RT_STATUS_PENDING,
808 RT_STATUS_RESOURCE
809 }RT_STATUS,*PRT_STATUS;
810
811 typedef enum _RT_CUSTOMER_ID
812 {
813 RT_CID_DEFAULT = 0,
814 RT_CID_8187_ALPHA0 = 1,
815 RT_CID_8187_SERCOMM_PS = 2,
816 RT_CID_8187_HW_LED = 3,
817 RT_CID_8187_NETGEAR = 4,
818 RT_CID_WHQL = 5,
819 RT_CID_819x_CAMEO = 6,
820 RT_CID_819x_RUNTOP = 7,
821 RT_CID_819x_Senao = 8,
822 RT_CID_TOSHIBA = 9, // Merge by Jacken, 2008/01/31.
823 RT_CID_819x_Netcore = 10,
824 RT_CID_Nettronix = 11,
825 RT_CID_DLINK = 12,
826 RT_CID_PRONET = 13,
827 RT_CID_COREGA = 14,
828 }RT_CUSTOMER_ID, *PRT_CUSTOMER_ID;
829
830 //================================================================================
831 // LED customization.
832 //================================================================================
833
834 typedef enum _LED_STRATEGY_8190{
835 SW_LED_MODE0, // SW control 1 LED via GPIO0. It is default option.
836 SW_LED_MODE1, // SW control for PCI Express
837 SW_LED_MODE2, // SW control for Cameo.
838 SW_LED_MODE3, // SW contorl for RunTop.
839 SW_LED_MODE4, // SW control for Netcore
840 SW_LED_MODE5, //added by vivi, for led new mode, DLINK
841 SW_LED_MODE6, //added by vivi, for led new mode, PRONET
842 HW_LED, // HW control 2 LEDs, LED0 and LED1 (there are 4 different control modes)
843 }LED_STRATEGY_8190, *PLED_STRATEGY_8190;
844
845 #define CHANNEL_PLAN_LEN 10
846
847 #define sCrcLng 4
848
849 typedef struct _TX_FWINFO_STRUCUTRE{
850 //DOWRD 0
851 u8 TxRate:7;
852 u8 CtsEnable:1;
853 u8 RtsRate:7;
854 u8 RtsEnable:1;
855 u8 TxHT:1;
856 u8 Short:1;
857 u8 TxBandwidth:1;
858 u8 TxSubCarrier:2;
859 u8 STBC:2;
860 u8 AllowAggregation:1;
861 u8 RtsHT:1;
862 u8 RtsShort:1;
863 u8 RtsBandwidth:1;
864 u8 RtsSubcarrier:2;
865 u8 RtsSTBC:2;
866 u8 EnableCPUDur:1;
867
868 //DWORD 1
869 u32 RxMF:2;
870 u32 RxAMD:3;
871 u32 Reserved1:3;
872 u32 TxAGCOffset:4;
873 u32 TxAGCSign:1;
874 u32 Tx_INFO_RSVD:6;
875 u32 PacketID:13;
876 }TX_FWINFO_T;
877
878
879 typedef struct _TX_FWINFO_8190PCI{
880 //DOWRD 0
881 u8 TxRate:7;
882 u8 CtsEnable:1;
883 u8 RtsRate:7;
884 u8 RtsEnable:1;
885 u8 TxHT:1;
886 u8 Short:1; //Short PLCP for CCK, or short GI for 11n MCS
887 u8 TxBandwidth:1; // This is used for HT MCS rate only.
888 u8 TxSubCarrier:2; // This is used for legacy OFDM rate only.
889 u8 STBC:2;
890 u8 AllowAggregation:1;
891 u8 RtsHT:1; //Interpre RtsRate field as high throughput data rate
892 u8 RtsShort:1; //Short PLCP for CCK, or short GI for 11n MCS
893 u8 RtsBandwidth:1; // This is used for HT MCS rate only.
894 u8 RtsSubcarrier:2; // This is used for legacy OFDM rate only.
895 u8 RtsSTBC:2;
896 u8 EnableCPUDur:1; //Enable firmware to recalculate and assign packet duration
897
898 //DWORD 1
899 u32 RxMF:2;
900 u32 RxAMD:3;
901 u32 TxPerPktInfoFeedback:1; // 1: indicate that the transimission info of this packet should be gathered by Firmware and retured by Rx Cmd.
902 u32 Reserved1:2;
903 u32 TxAGCOffset:4; // Only 90 support
904 u32 TxAGCSign:1; // Only 90 support
905 u32 RAW_TXD:1; // MAC will send data in txpktbuffer without any processing,such as CRC check
906 u32 Retry_Limit:4; // CCX Support relative retry limit FW page only support 4 bits now.
907 u32 Reserved2:1;
908 u32 PacketID:13;
909
910 // DW 2
911
912 }TX_FWINFO_8190PCI, *PTX_FWINFO_8190PCI;
913
914 typedef struct _phy_ofdm_rx_status_report_819xpci
915 {
916 u8 trsw_gain_X[4];
917 u8 pwdb_all;
918 u8 cfosho_X[4];
919 u8 cfotail_X[4];
920 u8 rxevm_X[2];
921 u8 rxsnr_X[4];
922 u8 pdsnr_X[2];
923 u8 csi_current_X[2];
924 u8 csi_target_X[2];
925 u8 sigevm;
926 u8 max_ex_pwr;
927 u8 sgi_en;
928 u8 rxsc_sgien_exflg;
929 }phy_sts_ofdm_819xpci_t;
930
931 typedef struct _phy_cck_rx_status_report_819xpci
932 {
933 /* For CCK rate descriptor. This is a unsigned 8:1 variable. LSB bit presend
934 0.5. And MSB 7 bts presend a signed value. Range from -64~+63.5. */
935 u8 adc_pwdb_X[4];
936 u8 sq_rpt;
937 u8 cck_agc_rpt;
938 }phy_sts_cck_819xpci_t;
939
940 typedef struct _phy_ofdm_rx_status_rxsc_sgien_exintfflag{
941 u8 reserved:4;
942 u8 rxsc:2;
943 u8 sgi_en:1;
944 u8 ex_intf_flag:1;
945 }phy_ofdm_rx_status_rxsc_sgien_exintfflag;
946
947 typedef enum _RT_OP_MODE{
948 RT_OP_MODE_AP,
949 RT_OP_MODE_INFRASTRUCTURE,
950 RT_OP_MODE_IBSS,
951 RT_OP_MODE_NO_LINK,
952 }RT_OP_MODE, *PRT_OP_MODE;
953
954
955 /* 2007/11/02 MH Define RF mode temporarily for test. */
956 typedef enum tag_Rf_OpType
957 {
958 RF_OP_By_SW_3wire = 0,
959 RF_OP_By_FW,
960 RF_OP_MAX
961 }RF_OpType_E;
962
963 typedef enum _RESET_TYPE {
964 RESET_TYPE_NORESET = 0x00,
965 RESET_TYPE_NORMAL = 0x01,
966 RESET_TYPE_SILENT = 0x02
967 } RESET_TYPE;
968
969 typedef struct _tx_ring{
970 u32 * desc;
971 u8 nStuckCount;
972 struct _tx_ring * next;
973 }__attribute__ ((packed)) tx_ring, * ptx_ring;
974
975 struct rtl8192_tx_ring {
976 tx_desc_819x_pci *desc;
977 dma_addr_t dma;
978 unsigned int idx;
979 unsigned int entries;
980 struct sk_buff_head queue;
981 };
982
983 #define NIC_SEND_HANG_THRESHOLD_NORMAL 4
984 #define NIC_SEND_HANG_THRESHOLD_POWERSAVE 8
985 #define MAX_TX_QUEUE 9 // BK, BE, VI, VO, HCCA, MANAGEMENT, COMMAND, HIGH, BEACON.
986
987 #define MAX_RX_COUNT 64
988 #define MAX_TX_QUEUE_COUNT 9
989
990 typedef struct r8192_priv
991 {
992 struct pci_dev *pdev;
993 //added for maintain info from eeprom
994 short epromtype;
995 u16 eeprom_vid;
996 u16 eeprom_did;
997 u8 eeprom_CustomerID;
998 u16 eeprom_ChannelPlan;
999 RT_CUSTOMER_ID CustomerID;
1000 LED_STRATEGY_8190 LedStrategy;
1001 //bool bDcut;
1002 u8 IC_Cut;
1003 int irq;
1004 short irq_enabled;
1005 struct ieee80211_device *ieee80211;
1006 bool being_init_adapter;
1007 u8 Rf_Mode;
1008 short card_8192; /* O: rtl8192, 1:rtl8185 V B/C, 2:rtl8185 V D */
1009 u8 card_8192_version; /* if TCR reports card V B/C this discriminates */
1010 // short phy_ver; /* meaningful for rtl8225 1:A 2:B 3:C */
1011 short enable_gpio0;
1012 enum card_type {PCI,MINIPCI,CARDBUS,USB/*rtl8187*/}card_type;
1013 short hw_plcp_len;
1014 short plcp_preamble_mode;
1015 u8 ScanDelay;
1016 spinlock_t irq_lock;
1017 spinlock_t irq_th_lock;
1018 spinlock_t tx_lock;
1019 spinlock_t rf_ps_lock;
1020 struct mutex mutex;
1021 spinlock_t rf_lock; //used to lock rf write operation added by wb
1022 spinlock_t ps_lock;
1023
1024 u32 irq_mask;
1025 // short irq_enabled;
1026 // struct net_device *dev; //comment this out.
1027 short chan;
1028 short sens;
1029 short max_sens;
1030 u32 rx_prevlen;
1031 /*RX stuff*/
1032 rx_desc_819x_pci *rx_ring;
1033 dma_addr_t rx_ring_dma;
1034 unsigned int rx_idx;
1035 struct sk_buff *rx_buf[MAX_RX_COUNT];
1036 int rxringcount;
1037 u16 rxbuffersize;
1038
1039
1040 struct sk_buff *rx_skb;
1041 u32 *rxring;
1042 u32 *rxringtail;
1043 dma_addr_t rxringdma;
1044 struct buffer *rxbuffer;
1045 struct buffer *rxbufferhead;
1046 short rx_skb_complete;
1047 /*TX stuff*/
1048 struct rtl8192_tx_ring tx_ring[MAX_TX_QUEUE_COUNT];
1049 int txringcount;
1050 //{
1051 int txbuffsize;
1052 int txfwbuffersize;
1053 //struct tx_pendingbuf txnp_pending;
1054 //struct tasklet_struct irq_tx_tasklet;
1055 struct tasklet_struct irq_rx_tasklet;
1056 struct tasklet_struct irq_tx_tasklet;
1057 struct tasklet_struct irq_prepare_beacon_tasklet;
1058 struct buffer *txmapbufs;
1059 struct buffer *txbkpbufs;
1060 struct buffer *txbepbufs;
1061 struct buffer *txvipbufs;
1062 struct buffer *txvopbufs;
1063 struct buffer *txcmdbufs;
1064 struct buffer *txmapbufstail;
1065 struct buffer *txbkpbufstail;
1066 struct buffer *txbepbufstail;
1067 struct buffer *txvipbufstail;
1068 struct buffer *txvopbufstail;
1069 struct buffer *txcmdbufstail;
1070 /* adhoc/master mode stuff */
1071 ptx_ring txbeaconringtail;
1072 dma_addr_t txbeaconringdma;
1073 ptx_ring txbeaconring;
1074 int txbeaconcount;
1075 struct buffer *txbeaconbufs;
1076 struct buffer *txbeaconbufstail;
1077 ptx_ring txmapring;
1078 ptx_ring txbkpring;
1079 ptx_ring txbepring;
1080 ptx_ring txvipring;
1081 ptx_ring txvopring;
1082 ptx_ring txcmdring;
1083 ptx_ring txmapringtail;
1084 ptx_ring txbkpringtail;
1085 ptx_ring txbepringtail;
1086 ptx_ring txvipringtail;
1087 ptx_ring txvopringtail;
1088 ptx_ring txcmdringtail;
1089 ptx_ring txmapringhead;
1090 ptx_ring txbkpringhead;
1091 ptx_ring txbepringhead;
1092 ptx_ring txvipringhead;
1093 ptx_ring txvopringhead;
1094 ptx_ring txcmdringhead;
1095 dma_addr_t txmapringdma;
1096 dma_addr_t txbkpringdma;
1097 dma_addr_t txbepringdma;
1098 dma_addr_t txvipringdma;
1099 dma_addr_t txvopringdma;
1100 dma_addr_t txcmdringdma;
1101 // u8 chtxpwr[15]; //channels from 1 to 14, 0 not used
1102 // u8 chtxpwr_ofdm[15]; //channels from 1 to 14, 0 not used
1103 // u8 cck_txpwr_base;
1104 // u8 ofdm_txpwr_base;
1105 // u8 challow[15]; //channels from 1 to 14, 0 not used
1106 short up;
1107 short crcmon; //if 1 allow bad crc frame reception in monitor mode
1108 // short prism_hdr;
1109
1110 // struct timer_list scan_timer;
1111 /*short scanpending;
1112 short stopscan;*/
1113 // spinlock_t scan_lock;
1114 // u8 active_probe;
1115 //u8 active_scan_num;
1116 struct semaphore wx_sem;
1117 struct semaphore rf_sem; //used to lock rf write operation added by wb, modified by david
1118 // short hw_wep;
1119
1120 // short digphy;
1121 // short antb;
1122 // short diversity;
1123 // u8 cs_treshold;
1124 // short rcr_csense;
1125 u8 rf_type; //0 means 1T2R, 1 means 2T4R
1126 RT_RF_TYPE_819xU rf_chip;
1127
1128 // u32 key0[4];
1129 short (*rf_set_sens)(struct net_device *dev,short sens);
1130 u8 (*rf_set_chan)(struct net_device *dev,u8 ch);
1131 void (*rf_close)(struct net_device *dev);
1132 void (*rf_init)(struct net_device *dev);
1133 //short rate;
1134 short promisc;
1135 /*stats*/
1136 struct Stats stats;
1137 struct iw_statistics wstats;
1138 struct proc_dir_entry *dir_dev;
1139
1140 /*RX stuff*/
1141 // u32 *rxring;
1142 // u32 *rxringtail;
1143 // dma_addr_t rxringdma;
1144
1145 #ifdef THOMAS_BEACON
1146 u32 *oldaddr;
1147 #endif
1148 #ifdef THOMAS_TASKLET
1149 atomic_t irt_counter;//count for irq_rx_tasklet
1150 #endif
1151 #ifdef JACKSON_NEW_RX
1152 struct sk_buff **pp_rxskb;
1153 int rx_inx;
1154 #endif
1155
1156 /* modified by davad for Rx process */
1157 struct sk_buff_head rx_queue;
1158 struct sk_buff_head skb_queue;
1159 struct work_struct qos_activate;
1160 short tx_urb_index;
1161 atomic_t tx_pending[0x10];//UART_PRIORITY+1
1162
1163 struct urb *rxurb_task;
1164
1165 //2 Tx Related variables
1166 u16 ShortRetryLimit;
1167 u16 LongRetryLimit;
1168 u32 TransmitConfig;
1169 u8 RegCWinMin; // For turbo mode CW adaptive. Added by Annie, 2005-10-27.
1170
1171 u32 LastRxDescTSFHigh;
1172 u32 LastRxDescTSFLow;
1173
1174
1175 //2 Rx Related variables
1176 u16 EarlyRxThreshold;
1177 u32 ReceiveConfig;
1178 u8 AcmControl;
1179
1180 u8 RFProgType;
1181
1182 u8 retry_data;
1183 u8 retry_rts;
1184 u16 rts;
1185
1186 struct ChnlAccessSetting ChannelAccessSetting;
1187
1188 struct work_struct reset_wq;
1189
1190 /**********************************************************/
1191 //for rtl819xPci
1192 // Data Rate Config. Added by Annie, 2006-04-13.
1193 u16 basic_rate;
1194 u8 short_preamble;
1195 u8 slot_time;
1196 u16 SifsTime;
1197 /* WirelessMode*/
1198 u8 RegWirelessMode;
1199 /*Firmware*/
1200 prt_firmware pFirmware;
1201 rtl819x_loopback_e LoopbackMode;
1202 firmware_source_e firmware_source;
1203 bool AutoloadFailFlag;
1204 u16 EEPROMTxPowerDiff;
1205 u16 EEPROMAntPwDiff; // Antenna gain offset from B/C/D to A
1206 u8 EEPROMThermalMeter;
1207 u8 EEPROMPwDiff;
1208 u8 EEPROMCrystalCap;
1209 u8 EEPROM_Def_Ver;
1210 u8 EEPROMTxPowerLevelCCK[14];// CCK channel 1~14
1211 // The following definition is for eeprom 93c56
1212 u8 EEPROMRfACCKChnl1TxPwLevel[3]; //RF-A CCK Tx Power Level at channel 7
1213 u8 EEPROMRfAOfdmChnlTxPwLevel[3];//RF-A CCK Tx Power Level at [0],[1],[2] = channel 1,7,13
1214 u8 EEPROMRfCCCKChnl1TxPwLevel[3]; //RF-C CCK Tx Power Level at channel 7
1215 u8 EEPROMRfCOfdmChnlTxPwLevel[3];//RF-C CCK Tx Power Level at [0],[1],[2] = channel 1,7,13
1216 u8 EEPROMTxPowerLevelCCK_V1[3];
1217 u8 EEPROMTxPowerLevelOFDM24G[14]; // OFDM 2.4G channel 1~14
1218 u8 EEPROMTxPowerLevelOFDM5G[24]; // OFDM 5G
1219 u8 EEPROMLegacyHTTxPowerDiff; // Legacy to HT rate power diff
1220 bool bTXPowerDataReadFromEEPORM;
1221 /*channel plan*/
1222 u16 RegChannelPlan; // Channel Plan specifed by user, 15: following setting of EEPROM, 0-14: default channel plan index specified by user.
1223 u16 ChannelPlan;
1224 /*PS related*/
1225 bool RegRfOff;
1226 // Rf off action for power save
1227 u8 bHwRfOffAction; //0:No action, 1:By GPIO, 2:By Disable
1228 /*PHY related*/
1229 BB_REGISTER_DEFINITION_T PHYRegDef[4]; //Radio A/B/C/D
1230 // Read/write are allow for following hardware information variables
1231 u32 MCSTxPowerLevelOriginalOffset[6];
1232 u32 CCKTxPowerLevelOriginalOffset;
1233 u8 TxPowerLevelCCK[14]; // CCK channel 1~14
1234 u8 TxPowerLevelCCK_A[14]; // RF-A, CCK channel 1~14
1235 u8 TxPowerLevelCCK_C[14];
1236 u8 TxPowerLevelOFDM24G[14]; // OFDM 2.4G channel 1~14
1237 u8 TxPowerLevelOFDM5G[14]; // OFDM 5G
1238 u8 TxPowerLevelOFDM24G_A[14]; // RF-A, OFDM 2.4G channel 1~14
1239 u8 TxPowerLevelOFDM24G_C[14]; // RF-C, OFDM 2.4G channel 1~14
1240 u8 LegacyHTTxPowerDiff; // Legacy to HT rate power diff
1241 u8 TxPowerDiff;
1242 char RF_C_TxPwDiff; // Antenna gain offset, rf-c to rf-a
1243 u8 AntennaTxPwDiff[3]; // Antenna gain offset, index 0 for B, 1 for C, and 2 for D
1244 u8 CrystalCap; // CrystalCap.
1245 u8 ThermalMeter[2]; // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1
1246 //05/27/2008 cck power enlarge
1247 u8 CckPwEnl;
1248 u16 TSSI_13dBm;
1249 u32 Pwr_Track;
1250 u8 CCKPresentAttentuation_20Mdefault;
1251 u8 CCKPresentAttentuation_40Mdefault;
1252 char CCKPresentAttentuation_difference;
1253 char CCKPresentAttentuation;
1254 // Use to calculate PWBD.
1255 u8 bCckHighPower;
1256 long undecorated_smoothed_pwdb;
1257 long undecorated_smoothed_cck_adc_pwdb[4];
1258 //for set channel
1259 u8 SwChnlInProgress;
1260 u8 SwChnlStage;
1261 u8 SwChnlStep;
1262 u8 SetBWModeInProgress;
1263 HT_CHANNEL_WIDTH CurrentChannelBW;
1264
1265 // 8190 40MHz mode
1266 //
1267 u8 nCur40MhzPrimeSC; // Control channel sub-carrier
1268 // Joseph test for shorten RF configuration time.
1269 // We save RF reg0 in this variable to reduce RF reading.
1270 //
1271 u32 RfReg0Value[4];
1272 u8 NumTotalRFPath;
1273 bool brfpath_rxenable[4];
1274 //+by amy 080507
1275 struct timer_list watch_dog_timer;
1276
1277 //+by amy 080515 for dynamic mechenism
1278 //Add by amy Tx Power Control for Near/Far Range 2008/05/15
1279 bool bdynamic_txpower; //bDynamicTxPower
1280 bool bDynamicTxHighPower; // Tx high power state
1281 bool bDynamicTxLowPower; // Tx low power state
1282 bool bLastDTPFlag_High;
1283 bool bLastDTPFlag_Low;
1284
1285 bool bstore_last_dtpflag;
1286 bool bstart_txctrl_bydtp; //Define to discriminate on High power State or on sitesuvey to change Tx gain index
1287 //Add by amy for Rate Adaptive
1288 rate_adaptive rate_adaptive;
1289 //Add by amy for TX power tracking
1290 //2008/05/15 Mars OPEN/CLOSE TX POWER TRACKING
1291 txbbgain_struct txbbgain_table[TxBBGainTableLength];
1292 u8 txpower_count;//For 6 sec do tracking again
1293 bool btxpower_trackingInit;
1294 u8 OFDM_index;
1295 u8 CCK_index;
1296 u8 Record_CCK_20Mindex;
1297 u8 Record_CCK_40Mindex;
1298 //2007/09/10 Mars Add CCK TX Power Tracking
1299 ccktxbbgain_struct cck_txbbgain_table[CCKTxBBGainTableLength];
1300 ccktxbbgain_struct cck_txbbgain_ch14_table[CCKTxBBGainTableLength];
1301 u8 rfa_txpowertrackingindex;
1302 u8 rfa_txpowertrackingindex_real;
1303 u8 rfa_txpowertracking_default;
1304 u8 rfc_txpowertrackingindex;
1305 u8 rfc_txpowertrackingindex_real;
1306 u8 rfc_txpowertracking_default;
1307 bool btxpower_tracking;
1308 bool bcck_in_ch14;
1309
1310 //For Backup Initial Gain
1311 init_gain initgain_backup;
1312 u8 DefaultInitialGain[4];
1313 // For EDCA Turbo mode, Added by amy 080515.
1314 bool bis_any_nonbepkts;
1315 bool bcurrent_turbo_EDCA;
1316
1317 bool bis_cur_rdlstate;
1318 struct timer_list fsync_timer;
1319 bool bfsync_processing; // 500ms Fsync timer is active or not
1320 u32 rate_record;
1321 u32 rateCountDiffRecord;
1322 u32 ContiuneDiffCount;
1323 bool bswitch_fsync;
1324
1325 u8 framesync;
1326 u32 framesyncC34;
1327 u8 framesyncMonitor;
1328 //Added by amy 080516 for RX related
1329 u16 nrxAMPDU_size;
1330 u8 nrxAMPDU_aggr_num;
1331
1332 /*Last RxDesc TSF value*/
1333 u32 last_rxdesc_tsf_high;
1334 u32 last_rxdesc_tsf_low;
1335
1336 //by amy for gpio
1337 bool bHwRadioOff;
1338 //by amy for ps
1339 bool RFChangeInProgress; // RF Chnage in progress, by Bruce, 2007-10-30
1340 bool SetRFPowerStateInProgress;
1341 RT_OP_MODE OpMode;
1342 //by amy for reset_count
1343 u32 reset_count;
1344 bool bpbc_pressed;
1345 //by amy for debug
1346 u32 txpower_checkcnt;
1347 u32 txpower_tracking_callback_cnt;
1348 u8 thermal_read_val[40];
1349 u8 thermal_readback_index;
1350 u32 ccktxpower_adjustcnt_not_ch14;
1351 u32 ccktxpower_adjustcnt_ch14;
1352 u8 tx_fwinfo_force_subcarriermode;
1353 u8 tx_fwinfo_force_subcarrierval;
1354
1355 //by amy for silent reset
1356 RESET_TYPE ResetProgress;
1357 bool bForcedSilentReset;
1358 bool bDisableNormalResetCheck;
1359 u16 TxCounter;
1360 u16 RxCounter;
1361 int IrpPendingCount;
1362 bool bResetInProgress;
1363 bool force_reset;
1364 u8 InitialGainOperateType;
1365
1366 //define work item by amy 080526
1367 struct delayed_work update_beacon_wq;
1368 struct delayed_work watch_dog_wq;
1369 struct delayed_work txpower_tracking_wq;
1370 struct delayed_work rfpath_check_wq;
1371 struct delayed_work gpio_change_rf_wq;
1372 struct delayed_work initialgain_operate_wq;
1373 struct workqueue_struct *priv_wq;
1374 }r8192_priv;
1375
1376 // for rtl8187
1377 // now mirging to rtl8187B
1378 /*
1379 typedef enum{
1380 LOW_PRIORITY = 0x02,
1381 NORM_PRIORITY
1382 } priority_t;
1383 */
1384 //for rtl8187B
1385 #if 0
1386 typedef enum{
1387 BULK_PRIORITY = 0x01,
1388 //RSVD0,
1389 //RSVD1,
1390 LOW_PRIORITY,
1391 NORM_PRIORITY,
1392 VO_PRIORITY,
1393 VI_PRIORITY, //0x05
1394 BE_PRIORITY,
1395 BK_PRIORITY,
1396 CMD_PRIORITY,//0x8
1397 RSVD3,
1398 BEACON_PRIORITY, //0x0A
1399 HIGH_PRIORITY,
1400 MANAGE_PRIORITY,
1401 RSVD4,
1402 RSVD5,
1403 UART_PRIORITY //0x0F
1404 } priority_t;
1405 #endif
1406 typedef enum{
1407 NIC_8192E = 1,
1408 } nic_t;
1409
1410
1411 #if 0 //defined in Qos.h
1412 //typedef u32 AC_CODING;
1413 #define AC0_BE 0 // ACI: 0x00 // Best Effort
1414 #define AC1_BK 1 // ACI: 0x01 // Background
1415 #define AC2_VI 2 // ACI: 0x10 // Video
1416 #define AC3_VO 3 // ACI: 0x11 // Voice
1417 #define AC_MAX 4 // Max: define total number; Should not to be used as a real enum.
1418
1419 //
1420 // ECWmin/ECWmax field.
1421 // Ref: WMM spec 2.2.2: WME Parameter Element, p.13.
1422 //
1423 typedef union _ECW{
1424 u8 charData;
1425 struct
1426 {
1427 u8 ECWmin:4;
1428 u8 ECWmax:4;
1429 }f; // Field
1430 }ECW, *PECW;
1431
1432 //
1433 // ACI/AIFSN Field.
1434 // Ref: WMM spec 2.2.2: WME Parameter Element, p.12.
1435 //
1436 typedef union _ACI_AIFSN{
1437 u8 charData;
1438
1439 struct
1440 {
1441 u8 AIFSN:4;
1442 u8 ACM:1;
1443 u8 ACI:2;
1444 u8 Reserved:1;
1445 }f; // Field
1446 }ACI_AIFSN, *PACI_AIFSN;
1447
1448 //
1449 // AC Parameters Record Format.
1450 // Ref: WMM spec 2.2.2: WME Parameter Element, p.12.
1451 //
1452 typedef union _AC_PARAM{
1453 u32 longData;
1454 u8 charData[4];
1455
1456 struct
1457 {
1458 ACI_AIFSN AciAifsn;
1459 ECW Ecw;
1460 u16 TXOPLimit;
1461 }f; // Field
1462 }AC_PARAM, *PAC_PARAM;
1463
1464 #endif
1465 bool init_firmware(struct net_device *dev);
1466 void rtl819xE_tx_cmd(struct net_device *dev, struct sk_buff *skb);
1467 short rtl8192_tx(struct net_device *dev, struct sk_buff* skb);
1468 u32 read_cam(struct net_device *dev, u8 addr);
1469 void write_cam(struct net_device *dev, u8 addr, u32 data);
1470 u8 read_nic_byte(struct net_device *dev, int x);
1471 u8 read_nic_byte_E(struct net_device *dev, int x);
1472 u32 read_nic_dword(struct net_device *dev, int x);
1473 u16 read_nic_word(struct net_device *dev, int x) ;
1474 void write_nic_byte(struct net_device *dev, int x,u8 y);
1475 void write_nic_byte_E(struct net_device *dev, int x,u8 y);
1476 void write_nic_word(struct net_device *dev, int x,u16 y);
1477 void write_nic_dword(struct net_device *dev, int x,u32 y);
1478 void force_pci_posting(struct net_device *dev);
1479
1480 void rtl8192_rtx_disable(struct net_device *);
1481 void rtl8192_rx_enable(struct net_device *);
1482 void rtl8192_tx_enable(struct net_device *);
1483
1484 void rtl8192_disassociate(struct net_device *dev);
1485 //void fix_rx_fifo(struct net_device *dev);
1486 void rtl8185_set_rf_pins_enable(struct net_device *dev,u32 a);
1487
1488 void rtl8192_set_anaparam(struct net_device *dev,u32 a);
1489 void rtl8185_set_anaparam2(struct net_device *dev,u32 a);
1490 void rtl8192_update_msr(struct net_device *dev);
1491 int rtl8192_down(struct net_device *dev);
1492 int rtl8192_up(struct net_device *dev);
1493 void rtl8192_commit(struct net_device *dev);
1494 void rtl8192_set_chan(struct net_device *dev,short ch);
1495 void write_phy(struct net_device *dev, u8 adr, u8 data);
1496 void write_phy_cck(struct net_device *dev, u8 adr, u32 data);
1497 void write_phy_ofdm(struct net_device *dev, u8 adr, u32 data);
1498 void rtl8185_tx_antenna(struct net_device *dev, u8 ant);
1499 void rtl8187_set_rxconf(struct net_device *dev);
1500 //short check_nic_enough_desc(struct net_device *dev, priority_t priority);
1501 void rtl8192_start_beacon(struct net_device *dev);
1502 void CamResetAllEntry(struct net_device* dev);
1503 void EnableHWSecurityConfig8192(struct net_device *dev);
1504 void setKey(struct net_device *dev, u8 EntryNo, u8 KeyIndex, u16 KeyType, u8 *MacAddr, u8 DefaultKey, u32 *KeyContent );
1505 void CamPrintDbgReg(struct net_device* dev);
1506 extern void dm_cck_txpower_adjust(struct net_device *dev,bool binch14);
1507 extern void firmware_init_param(struct net_device *dev);
1508 extern RT_STATUS cmpk_message_handle_tx(struct net_device *dev, u8* codevirtualaddress, u32 packettype, u32 buffer_len);
1509 void rtl8192_hw_wakeup_wq (struct work_struct *work);
1510
1511 short rtl8192_is_tx_queue_empty(struct net_device *dev);
1512 #ifdef ENABLE_IPS
1513 void IPSEnter(struct net_device *dev);
1514 void IPSLeave(struct net_device *dev);
1515 #endif
1516 #endif
Linux 2.6 libata-dev (mirror)