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qlcnic: Code optimization patch
[linux-2.6/libata-dev.git] / drivers / net / qlcnic / qlcnic.h
bloba5b28d1475b114faaae9e02b3813a1c285c427dd
1 /*
2 * QLogic qlcnic NIC Driver
3 * Copyright (c) 2009-2010 QLogic Corporation
4 *
5 * See LICENSE.qlcnic for copyright and licensing details.
6 */
7
8 #ifndef _QLCNIC_H_
9 #define _QLCNIC_H_
10
11 #include <linux/module.h>
12 #include <linux/kernel.h>
13 #include <linux/types.h>
14 #include <linux/ioport.h>
15 #include <linux/pci.h>
16 #include <linux/netdevice.h>
17 #include <linux/etherdevice.h>
18 #include <linux/ip.h>
19 #include <linux/in.h>
20 #include <linux/tcp.h>
21 #include <linux/skbuff.h>
22 #include <linux/firmware.h>
23
24 #include <linux/ethtool.h>
25 #include <linux/mii.h>
26 #include <linux/timer.h>
27
28 #include <linux/vmalloc.h>
29
30 #include <linux/io.h>
31 #include <asm/byteorder.h>
32
33 #include "qlcnic_hdr.h"
34
35 #define _QLCNIC_LINUX_MAJOR 5
36 #define _QLCNIC_LINUX_MINOR 0
37 #define _QLCNIC_LINUX_SUBVERSION 15
38 #define QLCNIC_LINUX_VERSIONID "5.0.15"
39 #define QLCNIC_DRV_IDC_VER 0x01
40 #define QLCNIC_DRIVER_VERSION ((_QLCNIC_LINUX_MAJOR << 16) |\
41 (_QLCNIC_LINUX_MINOR << 8) | (_QLCNIC_LINUX_SUBVERSION))
42
43 #define QLCNIC_VERSION_CODE(a, b, c) (((a) << 24) + ((b) << 16) + (c))
44 #define _major(v) (((v) >> 24) & 0xff)
45 #define _minor(v) (((v) >> 16) & 0xff)
46 #define _build(v) ((v) & 0xffff)
47
48 /* version in image has weird encoding:
49 * 7:0 - major
50 * 15:8 - minor
51 * 31:16 - build (little endian)
52 */
53 #define QLCNIC_DECODE_VERSION(v) \
54 QLCNIC_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16))
55
56 #define QLCNIC_MIN_FW_VERSION QLCNIC_VERSION_CODE(4, 4, 2)
57 #define QLCNIC_NUM_FLASH_SECTORS (64)
58 #define QLCNIC_FLASH_SECTOR_SIZE (64 * 1024)
59 #define QLCNIC_FLASH_TOTAL_SIZE (QLCNIC_NUM_FLASH_SECTORS \
60 * QLCNIC_FLASH_SECTOR_SIZE)
61
62 #define RCV_DESC_RINGSIZE(rds_ring) \
63 (sizeof(struct rcv_desc) * (rds_ring)->num_desc)
64 #define RCV_BUFF_RINGSIZE(rds_ring) \
65 (sizeof(struct qlcnic_rx_buffer) * rds_ring->num_desc)
66 #define STATUS_DESC_RINGSIZE(sds_ring) \
67 (sizeof(struct status_desc) * (sds_ring)->num_desc)
68 #define TX_BUFF_RINGSIZE(tx_ring) \
69 (sizeof(struct qlcnic_cmd_buffer) * tx_ring->num_desc)
70 #define TX_DESC_RINGSIZE(tx_ring) \
71 (sizeof(struct cmd_desc_type0) * tx_ring->num_desc)
72
73 #define QLCNIC_P3P_A0 0x50
74
75 #define QLCNIC_IS_REVISION_P3P(REVISION) (REVISION >= QLCNIC_P3P_A0)
76
77 #define FIRST_PAGE_GROUP_START 0
78 #define FIRST_PAGE_GROUP_END 0x100000
79
80 #define P3P_MAX_MTU (9600)
81 #define P3P_MIN_MTU (68)
82 #define QLCNIC_MAX_ETHERHDR 32 /* This contains some padding */
83
84 #define QLCNIC_P3P_RX_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + ETH_DATA_LEN)
85 #define QLCNIC_P3P_RX_JUMBO_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + P3P_MAX_MTU)
86 #define QLCNIC_CT_DEFAULT_RX_BUF_LEN 2048
87 #define QLCNIC_LRO_BUFFER_EXTRA 2048
88
89 /* Opcodes to be used with the commands */
90 #define TX_ETHER_PKT 0x01
91 #define TX_TCP_PKT 0x02
92 #define TX_UDP_PKT 0x03
93 #define TX_IP_PKT 0x04
94 #define TX_TCP_LSO 0x05
95 #define TX_TCP_LSO6 0x06
96 #define TX_TCPV6_PKT 0x0b
97 #define TX_UDPV6_PKT 0x0c
98
99 /* Tx defines */
100 #define MAX_TSO_HEADER_DESC 2
101 #define MGMT_CMD_DESC_RESV 4
102 #define TX_STOP_THRESH ((MAX_SKB_FRAGS >> 2) + MAX_TSO_HEADER_DESC \
103 + MGMT_CMD_DESC_RESV)
104 #define QLCNIC_MAX_TX_TIMEOUTS 2
105
106 /*
107 * Following are the states of the Phantom. Phantom will set them and
108 * Host will read to check if the fields are correct.
109 */
110 #define PHAN_INITIALIZE_FAILED 0xffff
111 #define PHAN_INITIALIZE_COMPLETE 0xff01
112
113 /* Host writes the following to notify that it has done the init-handshake */
114 #define PHAN_INITIALIZE_ACK 0xf00f
115 #define PHAN_PEG_RCV_INITIALIZED 0xff01
116
117 #define NUM_RCV_DESC_RINGS 3
118 #define NUM_STS_DESC_RINGS 4
119
120 #define RCV_RING_NORMAL 0
121 #define RCV_RING_JUMBO 1
122
123 #define MIN_CMD_DESCRIPTORS 64
124 #define MIN_RCV_DESCRIPTORS 64
125 #define MIN_JUMBO_DESCRIPTORS 32
126
127 #define MAX_CMD_DESCRIPTORS 1024
128 #define MAX_RCV_DESCRIPTORS_1G 4096
129 #define MAX_RCV_DESCRIPTORS_10G 8192
130 #define MAX_RCV_DESCRIPTORS_VF 2048
131 #define MAX_JUMBO_RCV_DESCRIPTORS_1G 512
132 #define MAX_JUMBO_RCV_DESCRIPTORS_10G 1024
133
134 #define DEFAULT_RCV_DESCRIPTORS_1G 2048
135 #define DEFAULT_RCV_DESCRIPTORS_10G 4096
136 #define DEFAULT_RCV_DESCRIPTORS_VF 1024
137 #define MAX_RDS_RINGS 2
138
139 #define get_next_index(index, length) \
140 (((index) + 1) & ((length) - 1))
141
142 /*
143 * Following data structures describe the descriptors that will be used.
144 * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
145 * we are doing LSO (above the 1500 size packet) only.
146 */
147
148 #define FLAGS_VLAN_TAGGED 0x10
149 #define FLAGS_VLAN_OOB 0x40
150
151 #define qlcnic_set_tx_vlan_tci(cmd_desc, v) \
152 (cmd_desc)->vlan_TCI = cpu_to_le16(v);
153 #define qlcnic_set_cmd_desc_port(cmd_desc, var) \
154 ((cmd_desc)->port_ctxid |= ((var) & 0x0F))
155 #define qlcnic_set_cmd_desc_ctxid(cmd_desc, var) \
156 ((cmd_desc)->port_ctxid |= ((var) << 4 & 0xF0))
157
158 #define qlcnic_set_tx_port(_desc, _port) \
159 ((_desc)->port_ctxid = ((_port) & 0xf) | (((_port) << 4) & 0xf0))
160
161 #define qlcnic_set_tx_flags_opcode(_desc, _flags, _opcode) \
162 ((_desc)->flags_opcode |= \
163 cpu_to_le16(((_flags) & 0x7f) | (((_opcode) & 0x3f) << 7)))
164
165 #define qlcnic_set_tx_frags_len(_desc, _frags, _len) \
166 ((_desc)->nfrags__length = \
167 cpu_to_le32(((_frags) & 0xff) | (((_len) & 0xffffff) << 8)))
168
169 struct cmd_desc_type0 {
170 u8 tcp_hdr_offset; /* For LSO only */
171 u8 ip_hdr_offset; /* For LSO only */
172 __le16 flags_opcode; /* 15:13 unused, 12:7 opcode, 6:0 flags */
173 __le32 nfrags__length; /* 31:8 total len, 7:0 frag count */
174
175 __le64 addr_buffer2;
176
177 __le16 reference_handle;
178 __le16 mss;
179 u8 port_ctxid; /* 7:4 ctxid 3:0 port */
180 u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */
181 __le16 conn_id; /* IPSec offoad only */
182
183 __le64 addr_buffer3;
184 __le64 addr_buffer1;
185
186 __le16 buffer_length[4];
187
188 __le64 addr_buffer4;
189
190 u8 eth_addr[ETH_ALEN];
191 __le16 vlan_TCI;
192
193 } __attribute__ ((aligned(64)));
194
195 /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
196 struct rcv_desc {
197 __le16 reference_handle;
198 __le16 reserved;
199 __le32 buffer_length; /* allocated buffer length (usually 2K) */
200 __le64 addr_buffer;
201 } __packed;
202
203 /* opcode field in status_desc */
204 #define QLCNIC_SYN_OFFLOAD 0x03
205 #define QLCNIC_RXPKT_DESC 0x04
206 #define QLCNIC_OLD_RXPKT_DESC 0x3f
207 #define QLCNIC_RESPONSE_DESC 0x05
208 #define QLCNIC_LRO_DESC 0x12
209
210 /* for status field in status_desc */
211 #define STATUS_CKSUM_LOOP 0
212 #define STATUS_CKSUM_OK 2
213
214 /* owner bits of status_desc */
215 #define STATUS_OWNER_HOST (0x1ULL << 56)
216 #define STATUS_OWNER_PHANTOM (0x2ULL << 56)
217
218 /* Status descriptor:
219 0-3 port, 4-7 status, 8-11 type, 12-27 total_length
220 28-43 reference_handle, 44-47 protocol, 48-52 pkt_offset
221 53-55 desc_cnt, 56-57 owner, 58-63 opcode
222 */
223 #define qlcnic_get_sts_port(sts_data) \
224 ((sts_data) & 0x0F)
225 #define qlcnic_get_sts_status(sts_data) \
226 (((sts_data) >> 4) & 0x0F)
227 #define qlcnic_get_sts_type(sts_data) \
228 (((sts_data) >> 8) & 0x0F)
229 #define qlcnic_get_sts_totallength(sts_data) \
230 (((sts_data) >> 12) & 0xFFFF)
231 #define qlcnic_get_sts_refhandle(sts_data) \
232 (((sts_data) >> 28) & 0xFFFF)
233 #define qlcnic_get_sts_prot(sts_data) \
234 (((sts_data) >> 44) & 0x0F)
235 #define qlcnic_get_sts_pkt_offset(sts_data) \
236 (((sts_data) >> 48) & 0x1F)
237 #define qlcnic_get_sts_desc_cnt(sts_data) \
238 (((sts_data) >> 53) & 0x7)
239 #define qlcnic_get_sts_opcode(sts_data) \
240 (((sts_data) >> 58) & 0x03F)
241
242 #define qlcnic_get_lro_sts_refhandle(sts_data) \
243 ((sts_data) & 0x0FFFF)
244 #define qlcnic_get_lro_sts_length(sts_data) \
245 (((sts_data) >> 16) & 0x0FFFF)
246 #define qlcnic_get_lro_sts_l2_hdr_offset(sts_data) \
247 (((sts_data) >> 32) & 0x0FF)
248 #define qlcnic_get_lro_sts_l4_hdr_offset(sts_data) \
249 (((sts_data) >> 40) & 0x0FF)
250 #define qlcnic_get_lro_sts_timestamp(sts_data) \
251 (((sts_data) >> 48) & 0x1)
252 #define qlcnic_get_lro_sts_type(sts_data) \
253 (((sts_data) >> 49) & 0x7)
254 #define qlcnic_get_lro_sts_push_flag(sts_data) \
255 (((sts_data) >> 52) & 0x1)
256 #define qlcnic_get_lro_sts_seq_number(sts_data) \
257 ((sts_data) & 0x0FFFFFFFF)
258
259
260 struct status_desc {
261 __le64 status_desc_data[2];
262 } __attribute__ ((aligned(16)));
263
264 /* UNIFIED ROMIMAGE */
265 #define QLCNIC_UNI_FW_MIN_SIZE 0xc8000
266 #define QLCNIC_UNI_DIR_SECT_PRODUCT_TBL 0x0
267 #define QLCNIC_UNI_DIR_SECT_BOOTLD 0x6
268 #define QLCNIC_UNI_DIR_SECT_FW 0x7
269
270 /*Offsets */
271 #define QLCNIC_UNI_CHIP_REV_OFF 10
272 #define QLCNIC_UNI_FLAGS_OFF 11
273 #define QLCNIC_UNI_BIOS_VERSION_OFF 12
274 #define QLCNIC_UNI_BOOTLD_IDX_OFF 27
275 #define QLCNIC_UNI_FIRMWARE_IDX_OFF 29
276
277 struct uni_table_desc{
278 u32 findex;
279 u32 num_entries;
280 u32 entry_size;
281 u32 reserved[5];
282 };
283
284 struct uni_data_desc{
285 u32 findex;
286 u32 size;
287 u32 reserved[5];
288 };
289
290 /* Flash Defines and Structures */
291 #define QLCNIC_FLT_LOCATION 0x3F1000
292 #define QLCNIC_FW_IMAGE_REGION 0x74
293 struct qlcnic_flt_header {
294 u16 version;
295 u16 len;
296 u16 checksum;
297 u16 reserved;
298 };
299
300 struct qlcnic_flt_entry {
301 u8 region;
302 u8 reserved0;
303 u8 attrib;
304 u8 reserved1;
305 u32 size;
306 u32 start_addr;
307 u32 end_add;
308 };
309
310 /* Magic number to let user know flash is programmed */
311 #define QLCNIC_BDINFO_MAGIC 0x12345678
312
313 #define QLCNIC_BRDTYPE_P3P_REF_QG 0x0021
314 #define QLCNIC_BRDTYPE_P3P_HMEZ 0x0022
315 #define QLCNIC_BRDTYPE_P3P_10G_CX4_LP 0x0023
316 #define QLCNIC_BRDTYPE_P3P_4_GB 0x0024
317 #define QLCNIC_BRDTYPE_P3P_IMEZ 0x0025
318 #define QLCNIC_BRDTYPE_P3P_10G_SFP_PLUS 0x0026
319 #define QLCNIC_BRDTYPE_P3P_10000_BASE_T 0x0027
320 #define QLCNIC_BRDTYPE_P3P_XG_LOM 0x0028
321 #define QLCNIC_BRDTYPE_P3P_4_GB_MM 0x0029
322 #define QLCNIC_BRDTYPE_P3P_10G_SFP_CT 0x002a
323 #define QLCNIC_BRDTYPE_P3P_10G_SFP_QT 0x002b
324 #define QLCNIC_BRDTYPE_P3P_10G_CX4 0x0031
325 #define QLCNIC_BRDTYPE_P3P_10G_XFP 0x0032
326 #define QLCNIC_BRDTYPE_P3P_10G_TP 0x0080
327
328 #define QLCNIC_MSIX_TABLE_OFFSET 0x44
329
330 /* Flash memory map */
331 #define QLCNIC_BRDCFG_START 0x4000 /* board config */
332 #define QLCNIC_BOOTLD_START 0x10000 /* bootld */
333 #define QLCNIC_IMAGE_START 0x43000 /* compressed image */
334 #define QLCNIC_USER_START 0x3E8000 /* Firmare info */
335
336 #define QLCNIC_FW_VERSION_OFFSET (QLCNIC_USER_START+0x408)
337 #define QLCNIC_FW_SIZE_OFFSET (QLCNIC_USER_START+0x40c)
338 #define QLCNIC_FW_SERIAL_NUM_OFFSET (QLCNIC_USER_START+0x81c)
339 #define QLCNIC_BIOS_VERSION_OFFSET (QLCNIC_USER_START+0x83c)
340
341 #define QLCNIC_BRDTYPE_OFFSET (QLCNIC_BRDCFG_START+0x8)
342 #define QLCNIC_FW_MAGIC_OFFSET (QLCNIC_BRDCFG_START+0x128)
343
344 #define QLCNIC_FW_MIN_SIZE (0x3fffff)
345 #define QLCNIC_UNIFIED_ROMIMAGE 0
346 #define QLCNIC_FLASH_ROMIMAGE 1
347 #define QLCNIC_UNKNOWN_ROMIMAGE 0xff
348
349 #define QLCNIC_UNIFIED_ROMIMAGE_NAME "phanfw.bin"
350 #define QLCNIC_FLASH_ROMIMAGE_NAME "flash"
351
352 extern char qlcnic_driver_name[];
353
354 /* Number of status descriptors to handle per interrupt */
355 #define MAX_STATUS_HANDLE (64)
356
357 /*
358 * qlcnic_skb_frag{} is to contain mapping info for each SG list. This
359 * has to be freed when DMA is complete. This is part of qlcnic_tx_buffer{}.
360 */
361 struct qlcnic_skb_frag {
362 u64 dma;
363 u64 length;
364 };
365
366 /* Following defines are for the state of the buffers */
367 #define QLCNIC_BUFFER_FREE 0
368 #define QLCNIC_BUFFER_BUSY 1
369
370 /*
371 * There will be one qlcnic_buffer per skb packet. These will be
372 * used to save the dma info for pci_unmap_page()
373 */
374 struct qlcnic_cmd_buffer {
375 struct sk_buff *skb;
376 struct qlcnic_skb_frag frag_array[MAX_SKB_FRAGS + 1];
377 u32 frag_count;
378 };
379
380 /* In rx_buffer, we do not need multiple fragments as is a single buffer */
381 struct qlcnic_rx_buffer {
382 u16 ref_handle;
383 struct sk_buff *skb;
384 struct list_head list;
385 u64 dma;
386 };
387
388 /* Board types */
389 #define QLCNIC_GBE 0x01
390 #define QLCNIC_XGBE 0x02
391
392 /*
393 * One hardware_context{} per adapter
394 * contains interrupt info as well shared hardware info.
395 */
396 struct qlcnic_hardware_context {
397 void __iomem *pci_base0;
398 void __iomem *ocm_win_crb;
399
400 unsigned long pci_len0;
401
402 rwlock_t crb_lock;
403 struct mutex mem_lock;
404
405 u8 revision_id;
406 u8 pci_func;
407 u8 linkup;
408 u16 port_type;
409 u16 board_type;
410 };
411
412 struct qlcnic_adapter_stats {
413 u64 xmitcalled;
414 u64 xmitfinished;
415 u64 rxdropped;
416 u64 txdropped;
417 u64 csummed;
418 u64 rx_pkts;
419 u64 lro_pkts;
420 u64 rxbytes;
421 u64 txbytes;
422 u64 lrobytes;
423 u64 lso_frames;
424 u64 xmit_on;
425 u64 xmit_off;
426 u64 skb_alloc_failure;
427 u64 null_rxbuf;
428 u64 rx_dma_map_error;
429 u64 tx_dma_map_error;
430 };
431
432 /*
433 * Rcv Descriptor Context. One such per Rcv Descriptor. There may
434 * be one Rcv Descriptor for normal packets, one for jumbo and may be others.
435 */
436 struct qlcnic_host_rds_ring {
437 void __iomem *crb_rcv_producer;
438 struct rcv_desc *desc_head;
439 struct qlcnic_rx_buffer *rx_buf_arr;
440 u32 num_desc;
441 u32 producer;
442 u32 dma_size;
443 u32 skb_size;
444 u32 flags;
445 struct list_head free_list;
446 spinlock_t lock;
447 dma_addr_t phys_addr;
448 } ____cacheline_internodealigned_in_smp;
449
450 struct qlcnic_host_sds_ring {
451 u32 consumer;
452 u32 num_desc;
453 void __iomem *crb_sts_consumer;
454
455 struct status_desc *desc_head;
456 struct qlcnic_adapter *adapter;
457 struct napi_struct napi;
458 struct list_head free_list[NUM_RCV_DESC_RINGS];
459
460 void __iomem *crb_intr_mask;
461 int irq;
462
463 dma_addr_t phys_addr;
464 char name[IFNAMSIZ+4];
465 } ____cacheline_internodealigned_in_smp;
466
467 struct qlcnic_host_tx_ring {
468 u32 producer;
469 u32 sw_consumer;
470 u32 num_desc;
471 void __iomem *crb_cmd_producer;
472 struct cmd_desc_type0 *desc_head;
473 struct qlcnic_cmd_buffer *cmd_buf_arr;
474 __le32 *hw_consumer;
475
476 dma_addr_t phys_addr;
477 dma_addr_t hw_cons_phys_addr;
478 struct netdev_queue *txq;
479 } ____cacheline_internodealigned_in_smp;
480
481 /*
482 * Receive context. There is one such structure per instance of the
483 * receive processing. Any state information that is relevant to
484 * the receive, and is must be in this structure. The global data may be
485 * present elsewhere.
486 */
487 struct qlcnic_recv_context {
488 struct qlcnic_host_rds_ring *rds_rings;
489 struct qlcnic_host_sds_ring *sds_rings;
490 u32 state;
491 u16 context_id;
492 u16 virt_port;
493
494 };
495
496 /* HW context creation */
497
498 #define QLCNIC_OS_CRB_RETRY_COUNT 4000
499 #define QLCNIC_CDRP_SIGNATURE_MAKE(pcifn, version) \
500 (((pcifn) & 0xff) | (((version) & 0xff) << 8) | (0xcafe << 16))
501
502 #define QLCNIC_CDRP_CMD_BIT 0x80000000
503
504 /*
505 * All responses must have the QLCNIC_CDRP_CMD_BIT cleared
506 * in the crb QLCNIC_CDRP_CRB_OFFSET.
507 */
508 #define QLCNIC_CDRP_FORM_RSP(rsp) (rsp)
509 #define QLCNIC_CDRP_IS_RSP(rsp) (((rsp) & QLCNIC_CDRP_CMD_BIT) == 0)
510
511 #define QLCNIC_CDRP_RSP_OK 0x00000001
512 #define QLCNIC_CDRP_RSP_FAIL 0x00000002
513 #define QLCNIC_CDRP_RSP_TIMEOUT 0x00000003
514
515 /*
516 * All commands must have the QLCNIC_CDRP_CMD_BIT set in
517 * the crb QLCNIC_CDRP_CRB_OFFSET.
518 */
519 #define QLCNIC_CDRP_FORM_CMD(cmd) (QLCNIC_CDRP_CMD_BIT | (cmd))
520 #define QLCNIC_CDRP_IS_CMD(cmd) (((cmd) & QLCNIC_CDRP_CMD_BIT) != 0)
521
522 #define QLCNIC_CDRP_CMD_SUBMIT_CAPABILITIES 0x00000001
523 #define QLCNIC_CDRP_CMD_READ_MAX_RDS_PER_CTX 0x00000002
524 #define QLCNIC_CDRP_CMD_READ_MAX_SDS_PER_CTX 0x00000003
525 #define QLCNIC_CDRP_CMD_READ_MAX_RULES_PER_CTX 0x00000004
526 #define QLCNIC_CDRP_CMD_READ_MAX_RX_CTX 0x00000005
527 #define QLCNIC_CDRP_CMD_READ_MAX_TX_CTX 0x00000006
528 #define QLCNIC_CDRP_CMD_CREATE_RX_CTX 0x00000007
529 #define QLCNIC_CDRP_CMD_DESTROY_RX_CTX 0x00000008
530 #define QLCNIC_CDRP_CMD_CREATE_TX_CTX 0x00000009
531 #define QLCNIC_CDRP_CMD_DESTROY_TX_CTX 0x0000000a
532 #define QLCNIC_CDRP_CMD_SET_MTU 0x00000012
533 #define QLCNIC_CDRP_CMD_READ_PHY 0x00000013
534 #define QLCNIC_CDRP_CMD_WRITE_PHY 0x00000014
535 #define QLCNIC_CDRP_CMD_READ_HW_REG 0x00000015
536 #define QLCNIC_CDRP_CMD_GET_FLOW_CTL 0x00000016
537 #define QLCNIC_CDRP_CMD_SET_FLOW_CTL 0x00000017
538 #define QLCNIC_CDRP_CMD_READ_MAX_MTU 0x00000018
539 #define QLCNIC_CDRP_CMD_READ_MAX_LRO 0x00000019
540 #define QLCNIC_CDRP_CMD_MAC_ADDRESS 0x0000001f
541
542 #define QLCNIC_CDRP_CMD_GET_PCI_INFO 0x00000020
543 #define QLCNIC_CDRP_CMD_GET_NIC_INFO 0x00000021
544 #define QLCNIC_CDRP_CMD_SET_NIC_INFO 0x00000022
545 #define QLCNIC_CDRP_CMD_GET_ESWITCH_CAPABILITY 0x00000024
546 #define QLCNIC_CDRP_CMD_TOGGLE_ESWITCH 0x00000025
547 #define QLCNIC_CDRP_CMD_GET_ESWITCH_STATUS 0x00000026
548 #define QLCNIC_CDRP_CMD_SET_PORTMIRRORING 0x00000027
549 #define QLCNIC_CDRP_CMD_CONFIGURE_ESWITCH 0x00000028
550 #define QLCNIC_CDRP_CMD_GET_ESWITCH_PORT_CONFIG 0x00000029
551 #define QLCNIC_CDRP_CMD_GET_ESWITCH_STATS 0x0000002a
552
553 #define QLCNIC_RCODE_SUCCESS 0
554 #define QLCNIC_RCODE_TIMEOUT 17
555 #define QLCNIC_DESTROY_CTX_RESET 0
556
557 /*
558 * Capabilities Announced
559 */
560 #define QLCNIC_CAP0_LEGACY_CONTEXT (1)
561 #define QLCNIC_CAP0_LEGACY_MN (1 << 2)
562 #define QLCNIC_CAP0_LSO (1 << 6)
563 #define QLCNIC_CAP0_JUMBO_CONTIGUOUS (1 << 7)
564 #define QLCNIC_CAP0_LRO_CONTIGUOUS (1 << 8)
565 #define QLCNIC_CAP0_VALIDOFF (1 << 11)
566
567 /*
568 * Context state
569 */
570 #define QLCNIC_HOST_CTX_STATE_FREED 0
571 #define QLCNIC_HOST_CTX_STATE_ACTIVE 2
572
573 /*
574 * Rx context
575 */
576
577 struct qlcnic_hostrq_sds_ring {
578 __le64 host_phys_addr; /* Ring base addr */
579 __le32 ring_size; /* Ring entries */
580 __le16 msi_index;
581 __le16 rsvd; /* Padding */
582 } __packed;
583
584 struct qlcnic_hostrq_rds_ring {
585 __le64 host_phys_addr; /* Ring base addr */
586 __le64 buff_size; /* Packet buffer size */
587 __le32 ring_size; /* Ring entries */
588 __le32 ring_kind; /* Class of ring */
589 } __packed;
590
591 struct qlcnic_hostrq_rx_ctx {
592 __le64 host_rsp_dma_addr; /* Response dma'd here */
593 __le32 capabilities[4]; /* Flag bit vector */
594 __le32 host_int_crb_mode; /* Interrupt crb usage */
595 __le32 host_rds_crb_mode; /* RDS crb usage */
596 /* These ring offsets are relative to data[0] below */
597 __le32 rds_ring_offset; /* Offset to RDS config */
598 __le32 sds_ring_offset; /* Offset to SDS config */
599 __le16 num_rds_rings; /* Count of RDS rings */
600 __le16 num_sds_rings; /* Count of SDS rings */
601 __le16 valid_field_offset;
602 u8 txrx_sds_binding;
603 u8 msix_handler;
604 u8 reserved[128]; /* reserve space for future expansion*/
605 /* MUST BE 64-bit aligned.
606 The following is packed:
607 - N hostrq_rds_rings
608 - N hostrq_sds_rings */
609 char data[0];
610 } __packed;
611
612 struct qlcnic_cardrsp_rds_ring{
613 __le32 host_producer_crb; /* Crb to use */
614 __le32 rsvd1; /* Padding */
615 } __packed;
616
617 struct qlcnic_cardrsp_sds_ring {
618 __le32 host_consumer_crb; /* Crb to use */
619 __le32 interrupt_crb; /* Crb to use */
620 } __packed;
621
622 struct qlcnic_cardrsp_rx_ctx {
623 /* These ring offsets are relative to data[0] below */
624 __le32 rds_ring_offset; /* Offset to RDS config */
625 __le32 sds_ring_offset; /* Offset to SDS config */
626 __le32 host_ctx_state; /* Starting State */
627 __le32 num_fn_per_port; /* How many PCI fn share the port */
628 __le16 num_rds_rings; /* Count of RDS rings */
629 __le16 num_sds_rings; /* Count of SDS rings */
630 __le16 context_id; /* Handle for context */
631 u8 phys_port; /* Physical id of port */
632 u8 virt_port; /* Virtual/Logical id of port */
633 u8 reserved[128]; /* save space for future expansion */
634 /* MUST BE 64-bit aligned.
635 The following is packed:
636 - N cardrsp_rds_rings
637 - N cardrs_sds_rings */
638 char data[0];
639 } __packed;
640
641 #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \
642 (sizeof(HOSTRQ_RX) + \
643 (rds_rings)*(sizeof(struct qlcnic_hostrq_rds_ring)) + \
644 (sds_rings)*(sizeof(struct qlcnic_hostrq_sds_ring)))
645
646 #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \
647 (sizeof(CARDRSP_RX) + \
648 (rds_rings)*(sizeof(struct qlcnic_cardrsp_rds_ring)) + \
649 (sds_rings)*(sizeof(struct qlcnic_cardrsp_sds_ring)))
650
651 /*
652 * Tx context
653 */
654
655 struct qlcnic_hostrq_cds_ring {
656 __le64 host_phys_addr; /* Ring base addr */
657 __le32 ring_size; /* Ring entries */
658 __le32 rsvd; /* Padding */
659 } __packed;
660
661 struct qlcnic_hostrq_tx_ctx {
662 __le64 host_rsp_dma_addr; /* Response dma'd here */
663 __le64 cmd_cons_dma_addr; /* */
664 __le64 dummy_dma_addr; /* */
665 __le32 capabilities[4]; /* Flag bit vector */
666 __le32 host_int_crb_mode; /* Interrupt crb usage */
667 __le32 rsvd1; /* Padding */
668 __le16 rsvd2; /* Padding */
669 __le16 interrupt_ctl;
670 __le16 msi_index;
671 __le16 rsvd3; /* Padding */
672 struct qlcnic_hostrq_cds_ring cds_ring; /* Desc of cds ring */
673 u8 reserved[128]; /* future expansion */
674 } __packed;
675
676 struct qlcnic_cardrsp_cds_ring {
677 __le32 host_producer_crb; /* Crb to use */
678 __le32 interrupt_crb; /* Crb to use */
679 } __packed;
680
681 struct qlcnic_cardrsp_tx_ctx {
682 __le32 host_ctx_state; /* Starting state */
683 __le16 context_id; /* Handle for context */
684 u8 phys_port; /* Physical id of port */
685 u8 virt_port; /* Virtual/Logical id of port */
686 struct qlcnic_cardrsp_cds_ring cds_ring; /* Card cds settings */
687 u8 reserved[128]; /* future expansion */
688 } __packed;
689
690 #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX))
691 #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX))
692
693 /* CRB */
694
695 #define QLCNIC_HOST_RDS_CRB_MODE_UNIQUE 0
696 #define QLCNIC_HOST_RDS_CRB_MODE_SHARED 1
697 #define QLCNIC_HOST_RDS_CRB_MODE_CUSTOM 2
698 #define QLCNIC_HOST_RDS_CRB_MODE_MAX 3
699
700 #define QLCNIC_HOST_INT_CRB_MODE_UNIQUE 0
701 #define QLCNIC_HOST_INT_CRB_MODE_SHARED 1
702 #define QLCNIC_HOST_INT_CRB_MODE_NORX 2
703 #define QLCNIC_HOST_INT_CRB_MODE_NOTX 3
704 #define QLCNIC_HOST_INT_CRB_MODE_NORXTX 4
705
706
707 /* MAC */
708
709 #define MC_COUNT_P3P 38
710
711 #define QLCNIC_MAC_NOOP 0
712 #define QLCNIC_MAC_ADD 1
713 #define QLCNIC_MAC_DEL 2
714 #define QLCNIC_MAC_VLAN_ADD 3
715 #define QLCNIC_MAC_VLAN_DEL 4
716
717 struct qlcnic_mac_list_s {
718 struct list_head list;
719 uint8_t mac_addr[ETH_ALEN+2];
720 };
721
722 /*
723 * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is
724 * adjusted based on configured MTU.
725 */
726 #define QLCNIC_DEFAULT_INTR_COALESCE_RX_TIME_US 3
727 #define QLCNIC_DEFAULT_INTR_COALESCE_RX_PACKETS 256
728 #define QLCNIC_DEFAULT_INTR_COALESCE_TX_PACKETS 64
729 #define QLCNIC_DEFAULT_INTR_COALESCE_TX_TIME_US 4
730
731 #define QLCNIC_INTR_DEFAULT 0x04
732
733 union qlcnic_nic_intr_coalesce_data {
734 struct {
735 u16 rx_packets;
736 u16 rx_time_us;
737 u16 tx_packets;
738 u16 tx_time_us;
739 } data;
740 u64 word;
741 };
742
743 struct qlcnic_nic_intr_coalesce {
744 u16 stats_time_us;
745 u16 rate_sample_time;
746 u16 flags;
747 u16 rsvd_1;
748 u32 low_threshold;
749 u32 high_threshold;
750 union qlcnic_nic_intr_coalesce_data normal;
751 union qlcnic_nic_intr_coalesce_data low;
752 union qlcnic_nic_intr_coalesce_data high;
753 union qlcnic_nic_intr_coalesce_data irq;
754 };
755
756 #define QLCNIC_HOST_REQUEST 0x13
757 #define QLCNIC_REQUEST 0x14
758
759 #define QLCNIC_MAC_EVENT 0x1
760
761 #define QLCNIC_IP_UP 2
762 #define QLCNIC_IP_DOWN 3
763
764 /*
765 * Driver --> Firmware
766 */
767 #define QLCNIC_H2C_OPCODE_CONFIG_RSS 0x1
768 #define QLCNIC_H2C_OPCODE_CONFIG_INTR_COALESCE 0x3
769 #define QLCNIC_H2C_OPCODE_CONFIG_LED 0x4
770 #define QLCNIC_H2C_OPCODE_LRO_REQUEST 0x7
771 #define QLCNIC_H2C_OPCODE_SET_MAC_RECEIVE_MODE 0xc
772 #define QLCNIC_H2C_OPCODE_CONFIG_IPADDR 0x12
773 #define QLCNIC_H2C_OPCODE_GET_LINKEVENT 0x15
774 #define QLCNIC_H2C_OPCODE_CONFIG_BRIDGING 0x17
775 #define QLCNIC_H2C_OPCODE_CONFIG_HW_LRO 0x18
776 /*
777 * Firmware --> Driver
778 */
779
780 #define QLCNIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 141
781
782 #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */
783 #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */
784 #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */
785
786 #define QLCNIC_LRO_REQUEST_CLEANUP 4
787
788 /* Capabilites received */
789 #define QLCNIC_FW_CAPABILITY_TSO BIT_1
790 #define QLCNIC_FW_CAPABILITY_BDG BIT_8
791 #define QLCNIC_FW_CAPABILITY_FVLANTX BIT_9
792 #define QLCNIC_FW_CAPABILITY_HW_LRO BIT_10
793
794 /* module types */
795 #define LINKEVENT_MODULE_NOT_PRESENT 1
796 #define LINKEVENT_MODULE_OPTICAL_UNKNOWN 2
797 #define LINKEVENT_MODULE_OPTICAL_SRLR 3
798 #define LINKEVENT_MODULE_OPTICAL_LRM 4
799 #define LINKEVENT_MODULE_OPTICAL_SFP_1G 5
800 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE 6
801 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN 7
802 #define LINKEVENT_MODULE_TWINAX 8
803
804 #define LINKSPEED_10GBPS 10000
805 #define LINKSPEED_1GBPS 1000
806 #define LINKSPEED_100MBPS 100
807 #define LINKSPEED_10MBPS 10
808
809 #define LINKSPEED_ENCODED_10MBPS 0
810 #define LINKSPEED_ENCODED_100MBPS 1
811 #define LINKSPEED_ENCODED_1GBPS 2
812
813 #define LINKEVENT_AUTONEG_DISABLED 0
814 #define LINKEVENT_AUTONEG_ENABLED 1
815
816 #define LINKEVENT_HALF_DUPLEX 0
817 #define LINKEVENT_FULL_DUPLEX 1
818
819 #define LINKEVENT_LINKSPEED_MBPS 0
820 #define LINKEVENT_LINKSPEED_ENCODED 1
821
822 /* firmware response header:
823 * 63:58 - message type
824 * 57:56 - owner
825 * 55:53 - desc count
826 * 52:48 - reserved
827 * 47:40 - completion id
828 * 39:32 - opcode
829 * 31:16 - error code
830 * 15:00 - reserved
831 */
832 #define qlcnic_get_nic_msg_opcode(msg_hdr) \
833 ((msg_hdr >> 32) & 0xFF)
834
835 struct qlcnic_fw_msg {
836 union {
837 struct {
838 u64 hdr;
839 u64 body[7];
840 };
841 u64 words[8];
842 };
843 };
844
845 struct qlcnic_nic_req {
846 __le64 qhdr;
847 __le64 req_hdr;
848 __le64 words[6];
849 } __packed;
850
851 struct qlcnic_mac_req {
852 u8 op;
853 u8 tag;
854 u8 mac_addr[6];
855 };
856
857 struct qlcnic_vlan_req {
858 __le16 vlan_id;
859 __le16 rsvd[3];
860 } __packed;
861
862 struct qlcnic_ipaddr {
863 __be32 ipv4;
864 __be32 ipv6[4];
865 };
866
867 #define QLCNIC_MSI_ENABLED 0x02
868 #define QLCNIC_MSIX_ENABLED 0x04
869 #define QLCNIC_LRO_ENABLED 0x08
870 #define QLCNIC_LRO_DISABLED 0x00
871 #define QLCNIC_BRIDGE_ENABLED 0X10
872 #define QLCNIC_DIAG_ENABLED 0x20
873 #define QLCNIC_ESWITCH_ENABLED 0x40
874 #define QLCNIC_ADAPTER_INITIALIZED 0x80
875 #define QLCNIC_TAGGING_ENABLED 0x100
876 #define QLCNIC_MACSPOOF 0x200
877 #define QLCNIC_MAC_OVERRIDE_DISABLED 0x400
878 #define QLCNIC_PROMISC_DISABLED 0x800
879 #define QLCNIC_NEED_FLR 0x1000
880 #define QLCNIC_IS_MSI_FAMILY(adapter) \
881 ((adapter)->flags & (QLCNIC_MSI_ENABLED | QLCNIC_MSIX_ENABLED))
882
883 #define MSIX_ENTRIES_PER_ADAPTER NUM_STS_DESC_RINGS
884 #define QLCNIC_MSIX_TBL_SPACE 8192
885 #define QLCNIC_PCI_REG_MSIX_TBL 0x44
886 #define QLCNIC_MSIX_TBL_PGSIZE 4096
887
888 #define QLCNIC_NETDEV_WEIGHT 128
889 #define QLCNIC_ADAPTER_UP_MAGIC 777
890
891 #define __QLCNIC_FW_ATTACHED 0
892 #define __QLCNIC_DEV_UP 1
893 #define __QLCNIC_RESETTING 2
894 #define __QLCNIC_START_FW 4
895 #define __QLCNIC_AER 5
896
897 #define QLCNIC_INTERRUPT_TEST 1
898 #define QLCNIC_LOOPBACK_TEST 2
899 #define QLCNIC_LED_TEST 3
900
901 #define QLCNIC_FILTER_AGE 80
902 #define QLCNIC_READD_AGE 20
903 #define QLCNIC_LB_MAX_FILTERS 64
904
905 struct qlcnic_filter {
906 struct hlist_node fnode;
907 u8 faddr[ETH_ALEN];
908 __le16 vlan_id;
909 unsigned long ftime;
910 };
911
912 struct qlcnic_filter_hash {
913 struct hlist_head *fhead;
914 u8 fnum;
915 u8 fmax;
916 };
917
918 struct qlcnic_adapter {
919 struct qlcnic_hardware_context *ahw;
920 struct qlcnic_recv_context *recv_ctx;
921 struct qlcnic_host_tx_ring *tx_ring;
922 struct net_device *netdev;
923 struct pci_dev *pdev;
924
925 unsigned long state;
926 u32 flags;
927
928 u16 num_txd;
929 u16 num_rxd;
930 u16 num_jumbo_rxd;
931 u16 max_rxd;
932 u16 max_jumbo_rxd;
933
934 u8 max_rds_rings;
935 u8 max_sds_rings;
936 u8 msix_supported;
937 u8 rx_csum;
938 u8 portnum;
939 u8 physical_port;
940 u8 reset_context;
941
942 u8 mc_enabled;
943 u8 max_mc_count;
944 u8 fw_wait_cnt;
945 u8 fw_fail_cnt;
946 u8 tx_timeo_cnt;
947 u8 need_fw_reset;
948
949 u8 has_link_events;
950 u8 fw_type;
951 u16 tx_context_id;
952 u16 is_up;
953
954 u16 link_speed;
955 u16 link_duplex;
956 u16 link_autoneg;
957 u16 module_type;
958
959 u16 op_mode;
960 u16 switch_mode;
961 u16 max_tx_ques;
962 u16 max_rx_ques;
963 u16 max_mtu;
964 u16 pvid;
965
966 u32 fw_hal_version;
967 u32 capabilities;
968 u32 irq;
969 u32 temp;
970
971 u32 int_vec_bit;
972 u32 heartbeat;
973
974 u8 max_mac_filters;
975 u8 dev_state;
976 u8 diag_test;
977 u8 diag_cnt;
978 u8 reset_ack_timeo;
979 u8 dev_init_timeo;
980 u16 msg_enable;
981
982 u8 mac_addr[ETH_ALEN];
983
984 u64 dev_rst_time;
985
986 struct vlan_group *vlgrp;
987 struct qlcnic_npar_info *npars;
988 struct qlcnic_eswitch *eswitch;
989 struct qlcnic_nic_template *nic_ops;
990
991 struct qlcnic_adapter_stats stats;
992 struct list_head mac_list;
993
994 void __iomem *tgt_mask_reg;
995 void __iomem *tgt_status_reg;
996 void __iomem *crb_int_state_reg;
997 void __iomem *isr_int_vec;
998
999 struct msix_entry msix_entries[MSIX_ENTRIES_PER_ADAPTER];
1000
1001 struct delayed_work fw_work;
1002
1003 struct qlcnic_nic_intr_coalesce coal;
1004
1005 struct qlcnic_filter_hash fhash;
1006
1007 spinlock_t tx_clean_lock;
1008 spinlock_t mac_learn_lock;
1009 __le32 file_prd_off; /*File fw product offset*/
1010 u32 fw_version;
1011 const struct firmware *fw;
1012 };
1013
1014 struct qlcnic_info {
1015 __le16 pci_func;
1016 __le16 op_mode; /* 1 = Priv, 2 = NP, 3 = NP passthru */
1017 __le16 phys_port;
1018 __le16 switch_mode; /* 0 = disabled, 1 = int, 2 = ext */
1019
1020 __le32 capabilities;
1021 u8 max_mac_filters;
1022 u8 reserved1;
1023 __le16 max_mtu;
1024
1025 __le16 max_tx_ques;
1026 __le16 max_rx_ques;
1027 __le16 min_tx_bw;
1028 __le16 max_tx_bw;
1029 u8 reserved2[104];
1030 } __packed;
1031
1032 struct qlcnic_pci_info {
1033 __le16 id; /* pci function id */
1034 __le16 active; /* 1 = Enabled */
1035 __le16 type; /* 1 = NIC, 2 = FCoE, 3 = iSCSI */
1036 __le16 default_port; /* default port number */
1037
1038 __le16 tx_min_bw; /* Multiple of 100mbpc */
1039 __le16 tx_max_bw;
1040 __le16 reserved1[2];
1041
1042 u8 mac[ETH_ALEN];
1043 u8 reserved2[106];
1044 } __packed;
1045
1046 struct qlcnic_npar_info {
1047 u16 pvid;
1048 u16 min_bw;
1049 u16 max_bw;
1050 u8 phy_port;
1051 u8 type;
1052 u8 active;
1053 u8 enable_pm;
1054 u8 dest_npar;
1055 u8 discard_tagged;
1056 u8 mac_override;
1057 u8 mac_anti_spoof;
1058 u8 promisc_mode;
1059 u8 offload_flags;
1060 };
1061
1062 struct qlcnic_eswitch {
1063 u8 port;
1064 u8 active_vports;
1065 u8 active_vlans;
1066 u8 active_ucast_filters;
1067 u8 max_ucast_filters;
1068 u8 max_active_vlans;
1069
1070 u32 flags;
1071 #define QLCNIC_SWITCH_ENABLE BIT_1
1072 #define QLCNIC_SWITCH_VLAN_FILTERING BIT_2
1073 #define QLCNIC_SWITCH_PROMISC_MODE BIT_3
1074 #define QLCNIC_SWITCH_PORT_MIRRORING BIT_4
1075 };
1076
1077
1078 /* Return codes for Error handling */
1079 #define QL_STATUS_INVALID_PARAM -1
1080
1081 #define MAX_BW 100 /* % of link speed */
1082 #define MAX_VLAN_ID 4095
1083 #define MIN_VLAN_ID 2
1084 #define DEFAULT_MAC_LEARN 1
1085
1086 #define IS_VALID_VLAN(vlan) (vlan >= MIN_VLAN_ID && vlan < MAX_VLAN_ID)
1087 #define IS_VALID_BW(bw) (bw <= MAX_BW)
1088
1089 struct qlcnic_pci_func_cfg {
1090 u16 func_type;
1091 u16 min_bw;
1092 u16 max_bw;
1093 u16 port_num;
1094 u8 pci_func;
1095 u8 func_state;
1096 u8 def_mac_addr[6];
1097 };
1098
1099 struct qlcnic_npar_func_cfg {
1100 u32 fw_capab;
1101 u16 port_num;
1102 u16 min_bw;
1103 u16 max_bw;
1104 u16 max_tx_queues;
1105 u16 max_rx_queues;
1106 u8 pci_func;
1107 u8 op_mode;
1108 };
1109
1110 struct qlcnic_pm_func_cfg {
1111 u8 pci_func;
1112 u8 action;
1113 u8 dest_npar;
1114 u8 reserved[5];
1115 };
1116
1117 struct qlcnic_esw_func_cfg {
1118 u16 vlan_id;
1119 u8 op_mode;
1120 u8 op_type;
1121 u8 pci_func;
1122 u8 host_vlan_tag;
1123 u8 promisc_mode;
1124 u8 discard_tagged;
1125 u8 mac_override;
1126 u8 mac_anti_spoof;
1127 u8 offload_flags;
1128 u8 reserved[5];
1129 };
1130
1131 #define QLCNIC_STATS_VERSION 1
1132 #define QLCNIC_STATS_PORT 1
1133 #define QLCNIC_STATS_ESWITCH 2
1134 #define QLCNIC_QUERY_RX_COUNTER 0
1135 #define QLCNIC_QUERY_TX_COUNTER 1
1136 #define QLCNIC_ESW_STATS_NOT_AVAIL 0xffffffffffffffffULL
1137
1138 #define QLCNIC_ADD_ESW_STATS(VAL1, VAL2)\
1139 do { \
1140 if (((VAL1) == QLCNIC_ESW_STATS_NOT_AVAIL) && \
1141 ((VAL2) != QLCNIC_ESW_STATS_NOT_AVAIL)) \
1142 (VAL1) = (VAL2); \
1143 else if (((VAL1) != QLCNIC_ESW_STATS_NOT_AVAIL) && \
1144 ((VAL2) != QLCNIC_ESW_STATS_NOT_AVAIL)) \
1145 (VAL1) += (VAL2); \
1146 } while (0)
1147
1148 struct __qlcnic_esw_statistics {
1149 __le16 context_id;
1150 __le16 version;
1151 __le16 size;
1152 __le16 unused;
1153 __le64 unicast_frames;
1154 __le64 multicast_frames;
1155 __le64 broadcast_frames;
1156 __le64 dropped_frames;
1157 __le64 errors;
1158 __le64 local_frames;
1159 __le64 numbytes;
1160 __le64 rsvd[3];
1161 } __packed;
1162
1163 struct qlcnic_esw_statistics {
1164 struct __qlcnic_esw_statistics rx;
1165 struct __qlcnic_esw_statistics tx;
1166 };
1167
1168 int qlcnic_fw_cmd_query_phy(struct qlcnic_adapter *adapter, u32 reg, u32 *val);
1169 int qlcnic_fw_cmd_set_phy(struct qlcnic_adapter *adapter, u32 reg, u32 val);
1170
1171 u32 qlcnic_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off);
1172 int qlcnic_hw_write_wx_2M(struct qlcnic_adapter *, ulong off, u32 data);
1173 int qlcnic_pci_mem_write_2M(struct qlcnic_adapter *, u64 off, u64 data);
1174 int qlcnic_pci_mem_read_2M(struct qlcnic_adapter *, u64 off, u64 *data);
1175 void qlcnic_pci_camqm_read_2M(struct qlcnic_adapter *, u64, u64 *);
1176 void qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *, u64, u64);
1177
1178 #define ADDR_IN_RANGE(addr, low, high) \
1179 (((addr) < (high)) && ((addr) >= (low)))
1180
1181 #define QLCRD32(adapter, off) \
1182 (qlcnic_hw_read_wx_2M(adapter, off))
1183 #define QLCWR32(adapter, off, val) \
1184 (qlcnic_hw_write_wx_2M(adapter, off, val))
1185
1186 int qlcnic_pcie_sem_lock(struct qlcnic_adapter *, int, u32);
1187 void qlcnic_pcie_sem_unlock(struct qlcnic_adapter *, int);
1188
1189 #define qlcnic_rom_lock(a) \
1190 qlcnic_pcie_sem_lock((a), 2, QLCNIC_ROM_LOCK_ID)
1191 #define qlcnic_rom_unlock(a) \
1192 qlcnic_pcie_sem_unlock((a), 2)
1193 #define qlcnic_phy_lock(a) \
1194 qlcnic_pcie_sem_lock((a), 3, QLCNIC_PHY_LOCK_ID)
1195 #define qlcnic_phy_unlock(a) \
1196 qlcnic_pcie_sem_unlock((a), 3)
1197 #define qlcnic_api_lock(a) \
1198 qlcnic_pcie_sem_lock((a), 5, 0)
1199 #define qlcnic_api_unlock(a) \
1200 qlcnic_pcie_sem_unlock((a), 5)
1201 #define qlcnic_sw_lock(a) \
1202 qlcnic_pcie_sem_lock((a), 6, 0)
1203 #define qlcnic_sw_unlock(a) \
1204 qlcnic_pcie_sem_unlock((a), 6)
1205 #define crb_win_lock(a) \
1206 qlcnic_pcie_sem_lock((a), 7, QLCNIC_CRB_WIN_LOCK_ID)
1207 #define crb_win_unlock(a) \
1208 qlcnic_pcie_sem_unlock((a), 7)
1209
1210 int qlcnic_get_board_info(struct qlcnic_adapter *adapter);
1211 int qlcnic_wol_supported(struct qlcnic_adapter *adapter);
1212 int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate);
1213 void qlcnic_prune_lb_filters(struct qlcnic_adapter *adapter);
1214 void qlcnic_delete_lb_filters(struct qlcnic_adapter *adapter);
1215
1216 /* Functions from qlcnic_init.c */
1217 int qlcnic_load_firmware(struct qlcnic_adapter *adapter);
1218 int qlcnic_need_fw_reset(struct qlcnic_adapter *adapter);
1219 void qlcnic_request_firmware(struct qlcnic_adapter *adapter);
1220 void qlcnic_release_firmware(struct qlcnic_adapter *adapter);
1221 int qlcnic_pinit_from_rom(struct qlcnic_adapter *adapter);
1222 int qlcnic_setup_idc_param(struct qlcnic_adapter *adapter);
1223 int qlcnic_check_flash_fw_ver(struct qlcnic_adapter *adapter);
1224
1225 int qlcnic_rom_fast_read(struct qlcnic_adapter *adapter, int addr, int *valp);
1226 int qlcnic_rom_fast_read_words(struct qlcnic_adapter *adapter, int addr,
1227 u8 *bytes, size_t size);
1228 int qlcnic_alloc_sw_resources(struct qlcnic_adapter *adapter);
1229 void qlcnic_free_sw_resources(struct qlcnic_adapter *adapter);
1230
1231 void __iomem *qlcnic_get_ioaddr(struct qlcnic_adapter *, u32);
1232
1233 int qlcnic_alloc_hw_resources(struct qlcnic_adapter *adapter);
1234 void qlcnic_free_hw_resources(struct qlcnic_adapter *adapter);
1235
1236 int qlcnic_fw_create_ctx(struct qlcnic_adapter *adapter);
1237 void qlcnic_fw_destroy_ctx(struct qlcnic_adapter *adapter);
1238
1239 void qlcnic_reset_rx_buffers_list(struct qlcnic_adapter *adapter);
1240 void qlcnic_release_rx_buffers(struct qlcnic_adapter *adapter);
1241 void qlcnic_release_tx_buffers(struct qlcnic_adapter *adapter);
1242
1243 int qlcnic_check_fw_status(struct qlcnic_adapter *adapter);
1244 void qlcnic_watchdog_task(struct work_struct *work);
1245 void qlcnic_post_rx_buffers(struct qlcnic_adapter *adapter,
1246 struct qlcnic_host_rds_ring *rds_ring);
1247 int qlcnic_process_rcv_ring(struct qlcnic_host_sds_ring *sds_ring, int max);
1248 void qlcnic_set_multi(struct net_device *netdev);
1249 void qlcnic_free_mac_list(struct qlcnic_adapter *adapter);
1250 int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter, u32);
1251 int qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter);
1252 int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable);
1253 int qlcnic_config_ipaddr(struct qlcnic_adapter *adapter, __be32 ip, int cmd);
1254 int qlcnic_linkevent_request(struct qlcnic_adapter *adapter, int enable);
1255 void qlcnic_advert_link_change(struct qlcnic_adapter *adapter, int linkup);
1256
1257 int qlcnic_fw_cmd_set_mtu(struct qlcnic_adapter *adapter, int mtu);
1258 int qlcnic_change_mtu(struct net_device *netdev, int new_mtu);
1259 int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter, int enable);
1260 int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, u32 enable);
1261 int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter);
1262 void qlcnic_update_cmd_producer(struct qlcnic_adapter *adapter,
1263 struct qlcnic_host_tx_ring *tx_ring);
1264 void qlcnic_fetch_mac(struct qlcnic_adapter *, u32, u32, u8, u8 *);
1265
1266 /* Functions from qlcnic_main.c */
1267 int qlcnic_reset_context(struct qlcnic_adapter *);
1268 u32 qlcnic_issue_cmd(struct qlcnic_adapter *adapter,
1269 u32 pci_fn, u32 version, u32 arg1, u32 arg2, u32 arg3, u32 cmd);
1270 void qlcnic_diag_free_res(struct net_device *netdev, int max_sds_rings);
1271 int qlcnic_diag_alloc_res(struct net_device *netdev, int test);
1272 netdev_tx_t qlcnic_xmit_frame(struct sk_buff *skb, struct net_device *netdev);
1273
1274 /* Management functions */
1275 int qlcnic_get_mac_address(struct qlcnic_adapter *, u8*);
1276 int qlcnic_get_nic_info(struct qlcnic_adapter *, struct qlcnic_info *, u8);
1277 int qlcnic_set_nic_info(struct qlcnic_adapter *, struct qlcnic_info *);
1278 int qlcnic_get_pci_info(struct qlcnic_adapter *, struct qlcnic_pci_info*);
1279
1280 /* eSwitch management functions */
1281 int qlcnic_config_switch_port(struct qlcnic_adapter *,
1282 struct qlcnic_esw_func_cfg *);
1283 int qlcnic_get_eswitch_port_config(struct qlcnic_adapter *,
1284 struct qlcnic_esw_func_cfg *);
1285 int qlcnic_config_port_mirroring(struct qlcnic_adapter *, u8, u8, u8);
1286 int qlcnic_get_port_stats(struct qlcnic_adapter *, const u8, const u8,
1287 struct __qlcnic_esw_statistics *);
1288 int qlcnic_get_eswitch_stats(struct qlcnic_adapter *, const u8, u8,
1289 struct __qlcnic_esw_statistics *);
1290 int qlcnic_clear_esw_stats(struct qlcnic_adapter *adapter, u8, u8, u8);
1291 extern int qlcnic_config_tso;
1292
1293 /*
1294 * QLOGIC Board information
1295 */
1296
1297 #define QLCNIC_MAX_BOARD_NAME_LEN 100
1298 struct qlcnic_brdinfo {
1299 unsigned short vendor;
1300 unsigned short device;
1301 unsigned short sub_vendor;
1302 unsigned short sub_device;
1303 char short_name[QLCNIC_MAX_BOARD_NAME_LEN];
1304 };
1305
1306 static const struct qlcnic_brdinfo qlcnic_boards[] = {
1307 {0x1077, 0x8020, 0x1077, 0x203,
1308 "8200 Series Single Port 10GbE Converged Network Adapter "
1309 "(TCP/IP Networking)"},
1310 {0x1077, 0x8020, 0x1077, 0x207,
1311 "8200 Series Dual Port 10GbE Converged Network Adapter "
1312 "(TCP/IP Networking)"},
1313 {0x1077, 0x8020, 0x1077, 0x20b,
1314 "3200 Series Dual Port 10Gb Intelligent Ethernet Adapter"},
1315 {0x1077, 0x8020, 0x1077, 0x20c,
1316 "3200 Series Quad Port 1Gb Intelligent Ethernet Adapter"},
1317 {0x1077, 0x8020, 0x1077, 0x20f,
1318 "3200 Series Single Port 10Gb Intelligent Ethernet Adapter"},
1319 {0x1077, 0x8020, 0x103c, 0x3733,
1320 "NC523SFP 10Gb 2-port Server Adapter"},
1321 {0x1077, 0x8020, 0x103c, 0x3346,
1322 "CN1000Q Dual Port Converged Network Adapter"},
1323 {0x1077, 0x8020, 0x0, 0x0, "cLOM8214 1/10GbE Controller"},
1324 };
1325
1326 #define NUM_SUPPORTED_BOARDS ARRAY_SIZE(qlcnic_boards)
1327
1328 static inline u32 qlcnic_tx_avail(struct qlcnic_host_tx_ring *tx_ring)
1329 {
1330 if (likely(tx_ring->producer < tx_ring->sw_consumer))
1331 return tx_ring->sw_consumer - tx_ring->producer;
1332 else
1333 return tx_ring->sw_consumer + tx_ring->num_desc -
1334 tx_ring->producer;
1335 }
1336
1337 extern const struct ethtool_ops qlcnic_ethtool_ops;
1338
1339 struct qlcnic_nic_template {
1340 int (*config_bridged_mode) (struct qlcnic_adapter *, u32);
1341 int (*config_led) (struct qlcnic_adapter *, u32, u32);
1342 int (*start_firmware) (struct qlcnic_adapter *);
1343 };
1344
1345 #define QLCDB(adapter, lvl, _fmt, _args...) do { \
1346 if (NETIF_MSG_##lvl & adapter->msg_enable) \
1347 printk(KERN_INFO "%s: %s: " _fmt, \
1348 dev_name(&adapter->pdev->dev), \
1349 __func__, ##_args); \
1350 } while (0)
1351
1352 #endif /* __QLCNIC_H_ */
Linux 2.6 libata-dev (mirror)