drivers/mtd/nand/s3c2410.c

   1 /* linux/drivers/mtd/nand/s3c2410.c
   2  *
   3  * Copyright (c) 2004,2005 Simtec Electronics
   4  *      http://www.simtec.co.uk/products/SWLINUX/
   5  *      Ben Dooks <ben@simtec.co.uk>
   6  *
   7  * Samsung S3C2410/S3C240 NAND driver
   8  *
   9  * Changelog:
  10  *      21-Sep-2004  BJD  Initial version
  11  *      23-Sep-2004  BJD  Mulitple device support
  12  *      28-Sep-2004  BJD  Fixed ECC placement for Hardware mode
  13  *      12-Oct-2004  BJD  Fixed errors in use of platform data
  14  *      18-Feb-2005  BJD  Fix sparse errors
  15  *      14-Mar-2005  BJD  Applied tglx's code reduction patch
  16  *      02-May-2005  BJD  Fixed s3c2440 support
  17  *      02-May-2005  BJD  Reduced hwcontrol decode
  18  *      20-Jun-2005  BJD  Updated s3c2440 support, fixed timing bug
  19  *      08-Jul-2005  BJD  Fix OOPS when no platform data supplied
  20  *      20-Oct-2005  BJD  Fix timing calculation bug
  21  *      14-Jan-2006  BJD  Allow clock to be stopped when idle
  22  *
  23  * $Id: s3c2410.c,v 1.23 2006/04/01 18:06:29 bjd Exp $
  24  *
  25  * This program is free software; you can redistribute it and/or modify
  26  * it under the terms of the GNU General Public License as published by
  27  * the Free Software Foundation; either version 2 of the License, or
  28  * (at your option) any later version.
  29  *
  30  * This program is distributed in the hope that it will be useful,
  31  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  32  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  33  * GNU General Public License for more details.
  34  *
  35  * You should have received a copy of the GNU General Public License
  36  * along with this program; if not, write to the Free Software
  37  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  38 */
  39
  40 #ifdef CONFIG_MTD_NAND_S3C2410_DEBUG
  41 #define DEBUG
  42 #endif
  43
  44 #include <linux/module.h>
  45 #include <linux/types.h>
  46 #include <linux/init.h>
  47 #include <linux/kernel.h>
  48 #include <linux/string.h>
  49 #include <linux/ioport.h>
  50 #include <linux/platform_device.h>
  51 #include <linux/delay.h>
  52 #include <linux/err.h>
  53 #include <linux/slab.h>
  54 #include <linux/clk.h>
  55
  56 #include <linux/mtd/mtd.h>
  57 #include <linux/mtd/nand.h>
  58 #include <linux/mtd/nand_ecc.h>
  59 #include <linux/mtd/partitions.h>
  60
  61 #include <asm/io.h>
  62
  63 #include <asm/plat-s3c/regs-nand.h>
  64 #include <asm/plat-s3c/nand.h>
  65
  66 #ifdef CONFIG_MTD_NAND_S3C2410_HWECC
  67 static int hardware_ecc = 1;
  68 #else
  69 static int hardware_ecc = 0;
  70 #endif
  71
  72 #ifdef CONFIG_MTD_NAND_S3C2410_CLKSTOP
  73 static int clock_stop = 1;
  74 #else
  75 static const int clock_stop = 0;
  76 #endif
  77
  78
  79 /* new oob placement block for use with hardware ecc generation
  80  */
  81
  82 static struct nand_ecclayout nand_hw_eccoob = {
  83         .eccbytes = 3,
  84         .eccpos = {0, 1, 2},
  85         .oobfree = {{8, 8}}
  86 };
  87
  88 /* controller and mtd information */
  89
  90 struct s3c2410_nand_info;
  91
  92 struct s3c2410_nand_mtd {
  93         struct mtd_info                 mtd;
  94         struct nand_chip                chip;
  95         struct s3c2410_nand_set         *set;
  96         struct s3c2410_nand_info        *info;
  97         int                             scan_res;
  98 };
  99
 100 enum s3c_cpu_type {
 101         TYPE_S3C2410,
 102         TYPE_S3C2412,
 103         TYPE_S3C2440,
 104 };
 105
 106 /* overview of the s3c2410 nand state */
 107
 108 struct s3c2410_nand_info {
 109         /* mtd info */
 110         struct nand_hw_control          controller;
 111         struct s3c2410_nand_mtd         *mtds;
 112         struct s3c2410_platform_nand    *platform;
 113
 114         /* device info */
 115         struct device                   *device;
 116         struct resource                 *area;
 117         struct clk                      *clk;
 118         void __iomem                    *regs;
 119         void __iomem                    *sel_reg;
 120         int                             sel_bit;
 121         int                             mtd_count;
 122
 123         unsigned long                   save_nfconf;
 124
 125         enum s3c_cpu_type               cpu_type;
 126 };
 127
 128 /* conversion functions */
 129
 130 static struct s3c2410_nand_mtd *s3c2410_nand_mtd_toours(struct mtd_info *mtd)
 131 {
 132         return container_of(mtd, struct s3c2410_nand_mtd, mtd);
 133 }
 134
 135 static struct s3c2410_nand_info *s3c2410_nand_mtd_toinfo(struct mtd_info *mtd)
 136 {
 137         return s3c2410_nand_mtd_toours(mtd)->info;
 138 }
 139
 140 static struct s3c2410_nand_info *to_nand_info(struct platform_device *dev)
 141 {
 142         return platform_get_drvdata(dev);
 143 }
 144
 145 static struct s3c2410_platform_nand *to_nand_plat(struct platform_device *dev)
 146 {
 147         return dev->dev.platform_data;
 148 }
 149
 150 static inline int allow_clk_stop(struct s3c2410_nand_info *info)
 151 {
 152         return clock_stop;
 153 }
 154
 155 /* timing calculations */
 156
 157 #define NS_IN_KHZ 1000000
 158
 159 static int s3c_nand_calc_rate(int wanted, unsigned long clk, int max)
 160 {
 161         int result;
 162
 163         result = (wanted * clk) / NS_IN_KHZ;
 164         result++;
 165
 166         pr_debug("result %d from %ld, %d\n", result, clk, wanted);
 167
 168         if (result > max) {
 169                 printk("%d ns is too big for current clock rate %ld\n", wanted, clk);
 170                 return -1;
 171         }
 172
 173         if (result < 1)
 174                 result = 1;
 175
 176         return result;
 177 }
 178
 179 #define to_ns(ticks,clk) (((ticks) * NS_IN_KHZ) / (unsigned int)(clk))
 180
 181 /* controller setup */
 182
 183 static int s3c2410_nand_inithw(struct s3c2410_nand_info *info,
 184                                struct platform_device *pdev)
 185 {
 186         struct s3c2410_platform_nand *plat = to_nand_plat(pdev);
 187         unsigned long clkrate = clk_get_rate(info->clk);
 188         int tacls_max = (info->cpu_type == TYPE_S3C2412) ? 8 : 4;
 189         int tacls, twrph0, twrph1;
 190         unsigned long cfg = 0;
 191
 192         /* calculate the timing information for the controller */
 193
 194         clkrate /= 1000;        /* turn clock into kHz for ease of use */
 195
 196         if (plat != NULL) {
 197                 tacls = s3c_nand_calc_rate(plat->tacls, clkrate, tacls_max);
 198                 twrph0 = s3c_nand_calc_rate(plat->twrph0, clkrate, 8);
 199                 twrph1 = s3c_nand_calc_rate(plat->twrph1, clkrate, 8);
 200         } else {
 201                 /* default timings */
 202                 tacls = tacls_max;
 203                 twrph0 = 8;
 204                 twrph1 = 8;
 205         }
 206
 207         if (tacls < 0 || twrph0 < 0 || twrph1 < 0) {
 208                 dev_err(info->device, "cannot get suitable timings\n");
 209                 return -EINVAL;
 210         }
 211
 212         dev_info(info->device, "Tacls=%d, %dns Twrph0=%d %dns, Twrph1=%d %dns\n",
 213                tacls, to_ns(tacls, clkrate), twrph0, to_ns(twrph0, clkrate), twrph1, to_ns(twrph1, clkrate));
 214
 215         switch (info->cpu_type) {
 216         case TYPE_S3C2410:
 217                 cfg = S3C2410_NFCONF_EN;
 218                 cfg |= S3C2410_NFCONF_TACLS(tacls - 1);
 219                 cfg |= S3C2410_NFCONF_TWRPH0(twrph0 - 1);
 220                 cfg |= S3C2410_NFCONF_TWRPH1(twrph1 - 1);
 221                 break;
 222
 223         case TYPE_S3C2440:
 224         case TYPE_S3C2412:
 225                 cfg = S3C2440_NFCONF_TACLS(tacls - 1);
 226                 cfg |= S3C2440_NFCONF_TWRPH0(twrph0 - 1);
 227                 cfg |= S3C2440_NFCONF_TWRPH1(twrph1 - 1);
 228
 229                 /* enable the controller and de-assert nFCE */
 230
 231                 writel(S3C2440_NFCONT_ENABLE, info->regs + S3C2440_NFCONT);
 232         }
 233
 234         dev_dbg(info->device, "NF_CONF is 0x%lx\n", cfg);
 235
 236         writel(cfg, info->regs + S3C2410_NFCONF);
 237         return 0;
 238 }
 239
 240 /* select chip */
 241
 242 static void s3c2410_nand_select_chip(struct mtd_info *mtd, int chip)
 243 {
 244         struct s3c2410_nand_info *info;
 245         struct s3c2410_nand_mtd *nmtd;
 246         struct nand_chip *this = mtd->priv;
 247         unsigned long cur;
 248
 249         nmtd = this->priv;
 250         info = nmtd->info;
 251
 252         if (chip != -1 && allow_clk_stop(info))
 253                 clk_enable(info->clk);
 254
 255         cur = readl(info->sel_reg);
 256
 257         if (chip == -1) {
 258                 cur |= info->sel_bit;
 259         } else {
 260                 if (nmtd->set != NULL && chip > nmtd->set->nr_chips) {
 261                         dev_err(info->device, "invalid chip %d\n", chip);
 262                         return;
 263                 }
 264
 265                 if (info->platform != NULL) {
 266                         if (info->platform->select_chip != NULL)
 267                                 (info->platform->select_chip) (nmtd->set, chip);
 268                 }
 269
 270                 cur &= ~info->sel_bit;
 271         }
 272
 273         writel(cur, info->sel_reg);
 274
 275         if (chip == -1 && allow_clk_stop(info))
 276                 clk_disable(info->clk);
 277 }
 278
 279 /* s3c2410_nand_hwcontrol
 280  *
 281  * Issue command and address cycles to the chip
 282 */
 283
 284 static void s3c2410_nand_hwcontrol(struct mtd_info *mtd, int cmd,
 285                                    unsigned int ctrl)
 286 {
 287         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 288
 289         if (cmd == NAND_CMD_NONE)
 290                 return;
 291
 292         if (ctrl & NAND_CLE)
 293                 writeb(cmd, info->regs + S3C2410_NFCMD);
 294         else
 295                 writeb(cmd, info->regs + S3C2410_NFADDR);
 296 }
 297
 298 /* command and control functions */
 299
 300 static void s3c2440_nand_hwcontrol(struct mtd_info *mtd, int cmd,
 301                                    unsigned int ctrl)
 302 {
 303         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 304
 305         if (cmd == NAND_CMD_NONE)
 306                 return;
 307
 308         if (ctrl & NAND_CLE)
 309                 writeb(cmd, info->regs + S3C2440_NFCMD);
 310         else
 311                 writeb(cmd, info->regs + S3C2440_NFADDR);
 312 }
 313
 314 /* s3c2410_nand_devready()
 315  *
 316  * returns 0 if the nand is busy, 1 if it is ready
 317 */
 318
 319 static int s3c2410_nand_devready(struct mtd_info *mtd)
 320 {
 321         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 322         return readb(info->regs + S3C2410_NFSTAT) & S3C2410_NFSTAT_BUSY;
 323 }
 324
 325 static int s3c2440_nand_devready(struct mtd_info *mtd)
 326 {
 327         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 328         return readb(info->regs + S3C2440_NFSTAT) & S3C2440_NFSTAT_READY;
 329 }
 330
 331 static int s3c2412_nand_devready(struct mtd_info *mtd)
 332 {
 333         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 334         return readb(info->regs + S3C2412_NFSTAT) & S3C2412_NFSTAT_READY;
 335 }
 336
 337 /* ECC handling functions */
 338
 339 static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat,
 340                                      u_char *read_ecc, u_char *calc_ecc)
 341 {
 342         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 343         unsigned int diff0, diff1, diff2;
 344         unsigned int bit, byte;
 345
 346         pr_debug("%s(%p,%p,%p,%p)\n", __func__, mtd, dat, read_ecc, calc_ecc);
 347
 348         diff0 = read_ecc[0] ^ calc_ecc[0];
 349         diff1 = read_ecc[1] ^ calc_ecc[1];
 350         diff2 = read_ecc[2] ^ calc_ecc[2];
 351
 352         pr_debug("%s: rd %02x%02x%02x calc %02x%02x%02x diff %02x%02x%02x\n",
 353                  __func__,
 354                  read_ecc[0], read_ecc[1], read_ecc[2],
 355                  calc_ecc[0], calc_ecc[1], calc_ecc[2],
 356                  diff0, diff1, diff2);
 357
 358         if (diff0 == 0 && diff1 == 0 && diff2 == 0)
 359                 return 0;               /* ECC is ok */
 360
 361         /* Can we correct this ECC (ie, one row and column change).
 362          * Note, this is similar to the 256 error code on smartmedia */
 363
 364         if (((diff0 ^ (diff0 >> 1)) & 0x55) == 0x55 &&
 365             ((diff1 ^ (diff1 >> 1)) & 0x55) == 0x55 &&
 366             ((diff2 ^ (diff2 >> 1)) & 0x55) == 0x55) {
 367                 /* calculate the bit position of the error */
 368
 369                 bit  = (diff2 >> 2) & 1;
 370                 bit |= (diff2 >> 3) & 2;
 371                 bit |= (diff2 >> 4) & 4;
 372
 373                 /* calculate the byte position of the error */
 374
 375                 byte  = (diff1 << 1) & 0x80;
 376                 byte |= (diff1 << 2) & 0x40;
 377                 byte |= (diff1 << 3) & 0x20;
 378                 byte |= (diff1 << 4) & 0x10;
 379
 380                 byte |= (diff0 >> 3) & 0x08;
 381                 byte |= (diff0 >> 2) & 0x04;
 382                 byte |= (diff0 >> 1) & 0x02;
 383                 byte |= (diff0 >> 0) & 0x01;
 384
 385                 byte |= (diff2 << 8) & 0x100;
 386
 387                 dev_dbg(info->device, "correcting error bit %d, byte %d\n",
 388                         bit, byte);
 389
 390                 dat[byte] ^= (1 << bit);
 391                 return 1;
 392         }
 393
 394         /* if there is only one bit difference in the ECC, then
 395          * one of only a row or column parity has changed, which
 396          * means the error is most probably in the ECC itself */
 397
 398         diff0 |= (diff1 << 8);
 399         diff0 |= (diff2 << 16);
 400
 401         if ((diff0 & ~(1<<fls(diff0))) == 0)
 402                 return 1;
 403
 404         return 0;
 405 }
 406
 407 /* ECC functions
 408  *
 409  * These allow the s3c2410 and s3c2440 to use the controller's ECC
 410  * generator block to ECC the data as it passes through]
 411 */
 412
 413 static void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode)
 414 {
 415         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 416         unsigned long ctrl;
 417
 418         ctrl = readl(info->regs + S3C2410_NFCONF);
 419         ctrl |= S3C2410_NFCONF_INITECC;
 420         writel(ctrl, info->regs + S3C2410_NFCONF);
 421 }
 422
 423 static void s3c2412_nand_enable_hwecc(struct mtd_info *mtd, int mode)
 424 {
 425         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 426         unsigned long ctrl;
 427
 428         ctrl = readl(info->regs + S3C2440_NFCONT);
 429         writel(ctrl | S3C2412_NFCONT_INIT_MAIN_ECC, info->regs + S3C2440_NFCONT);
 430 }
 431
 432 static void s3c2440_nand_enable_hwecc(struct mtd_info *mtd, int mode)
 433 {
 434         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 435         unsigned long ctrl;
 436
 437         ctrl = readl(info->regs + S3C2440_NFCONT);
 438         writel(ctrl | S3C2440_NFCONT_INITECC, info->regs + S3C2440_NFCONT);
 439 }
 440
 441 static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
 442 {
 443         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 444
 445         ecc_code[0] = readb(info->regs + S3C2410_NFECC + 0);
 446         ecc_code[1] = readb(info->regs + S3C2410_NFECC + 1);
 447         ecc_code[2] = readb(info->regs + S3C2410_NFECC + 2);
 448
 449         pr_debug("%s: returning ecc %02x%02x%02x\n", __func__,
 450                  ecc_code[0], ecc_code[1], ecc_code[2]);
 451
 452         return 0;
 453 }
 454
 455 static int s3c2412_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
 456 {
 457         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 458         unsigned long ecc = readl(info->regs + S3C2412_NFMECC0);
 459
 460         ecc_code[0] = ecc;
 461         ecc_code[1] = ecc >> 8;
 462         ecc_code[2] = ecc >> 16;
 463
 464         pr_debug("calculate_ecc: returning ecc %02x,%02x,%02x\n", ecc_code[0], ecc_code[1], ecc_code[2]);
 465
 466         return 0;
 467 }
 468
 469 static int s3c2440_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
 470 {
 471         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 472         unsigned long ecc = readl(info->regs + S3C2440_NFMECC0);
 473
 474         ecc_code[0] = ecc;
 475         ecc_code[1] = ecc >> 8;
 476         ecc_code[2] = ecc >> 16;
 477
 478         pr_debug("%s: returning ecc %06lx\n", __func__, ecc);
 479
 480         return 0;
 481 }
 482
 483 /* over-ride the standard functions for a little more speed. We can
 484  * use read/write block to move the data buffers to/from the controller
 485 */
 486
 487 static void s3c2410_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
 488 {
 489         struct nand_chip *this = mtd->priv;
 490         readsb(this->IO_ADDR_R, buf, len);
 491 }
 492
 493 static void s3c2440_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
 494 {
 495         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 496         readsl(info->regs + S3C2440_NFDATA, buf, len / 4);
 497 }
 498
 499 static void s3c2410_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
 500 {
 501         struct nand_chip *this = mtd->priv;
 502         writesb(this->IO_ADDR_W, buf, len);
 503 }
 504
 505 static void s3c2440_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
 506 {
 507         struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
 508         writesl(info->regs + S3C2440_NFDATA, buf, len / 4);
 509 }
 510
 511 /* device management functions */
 512
 513 static int s3c2410_nand_remove(struct platform_device *pdev)
 514 {
 515         struct s3c2410_nand_info *info = to_nand_info(pdev);
 516
 517         platform_set_drvdata(pdev, NULL);
 518
 519         if (info == NULL)
 520                 return 0;
 521
 522         /* first thing we need to do is release all our mtds
 523          * and their partitions, then go through freeing the
 524          * resources used
 525          */
 526
 527         if (info->mtds != NULL) {
 528                 struct s3c2410_nand_mtd *ptr = info->mtds;
 529                 int mtdno;
 530
 531                 for (mtdno = 0; mtdno < info->mtd_count; mtdno++, ptr++) {
 532                         pr_debug("releasing mtd %d (%p)\n", mtdno, ptr);
 533                         nand_release(&ptr->mtd);
 534                 }
 535
 536                 kfree(info->mtds);
 537         }
 538
 539         /* free the common resources */
 540
 541         if (info->clk != NULL && !IS_ERR(info->clk)) {
 542                 if (!allow_clk_stop(info))
 543                         clk_disable(info->clk);
 544                 clk_put(info->clk);
 545         }
 546
 547         if (info->regs != NULL) {
 548                 iounmap(info->regs);
 549                 info->regs = NULL;
 550         }
 551
 552         if (info->area != NULL) {
 553                 release_resource(info->area);
 554                 kfree(info->area);
 555                 info->area = NULL;
 556         }
 557
 558         kfree(info);
 559
 560         return 0;
 561 }
 562
 563 #ifdef CONFIG_MTD_PARTITIONS
 564 static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info,
 565                                       struct s3c2410_nand_mtd *mtd,
 566                                       struct s3c2410_nand_set *set)
 567 {
 568         if (set == NULL)
 569                 return add_mtd_device(&mtd->mtd);
 570
 571         if (set->nr_partitions > 0 && set->partitions != NULL) {
 572                 return add_mtd_partitions(&mtd->mtd, set->partitions, set->nr_partitions);
 573         }
 574
 575         return add_mtd_device(&mtd->mtd);
 576 }
 577 #else
 578 static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info,
 579                                       struct s3c2410_nand_mtd *mtd,
 580                                       struct s3c2410_nand_set *set)
 581 {
 582         return add_mtd_device(&mtd->mtd);
 583 }
 584 #endif
 585
 586 /* s3c2410_nand_init_chip
 587  *
 588  * init a single instance of an chip
 589 */
 590
 591 static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info,
 592                                    struct s3c2410_nand_mtd *nmtd,
 593                                    struct s3c2410_nand_set *set)
 594 {
 595         struct nand_chip *chip = &nmtd->chip;
 596         void __iomem *regs = info->regs;
 597
 598         chip->write_buf    = s3c2410_nand_write_buf;
 599         chip->read_buf     = s3c2410_nand_read_buf;
 600         chip->select_chip  = s3c2410_nand_select_chip;
 601         chip->chip_delay   = 50;
 602         chip->priv         = nmtd;
 603         chip->options      = 0;
 604         chip->controller   = &info->controller;
 605
 606         switch (info->cpu_type) {
 607         case TYPE_S3C2410:
 608                 chip->IO_ADDR_W = regs + S3C2410_NFDATA;
 609                 info->sel_reg   = regs + S3C2410_NFCONF;
 610                 info->sel_bit   = S3C2410_NFCONF_nFCE;
 611                 chip->cmd_ctrl  = s3c2410_nand_hwcontrol;
 612                 chip->dev_ready = s3c2410_nand_devready;
 613                 break;
 614
 615         case TYPE_S3C2440:
 616                 chip->IO_ADDR_W = regs + S3C2440_NFDATA;
 617                 info->sel_reg   = regs + S3C2440_NFCONT;
 618                 info->sel_bit   = S3C2440_NFCONT_nFCE;
 619                 chip->cmd_ctrl  = s3c2440_nand_hwcontrol;
 620                 chip->dev_ready = s3c2440_nand_devready;
 621                 chip->read_buf  = s3c2440_nand_read_buf;
 622                 chip->write_buf = s3c2440_nand_write_buf;
 623                 break;
 624
 625         case TYPE_S3C2412:
 626                 chip->IO_ADDR_W = regs + S3C2440_NFDATA;
 627                 info->sel_reg   = regs + S3C2440_NFCONT;
 628                 info->sel_bit   = S3C2412_NFCONT_nFCE0;
 629                 chip->cmd_ctrl  = s3c2440_nand_hwcontrol;
 630                 chip->dev_ready = s3c2412_nand_devready;
 631
 632                 if (readl(regs + S3C2410_NFCONF) & S3C2412_NFCONF_NANDBOOT)
 633                         dev_info(info->device, "System booted from NAND\n");
 634
 635                 break;
 636         }
 637
 638         chip->IO_ADDR_R = chip->IO_ADDR_W;
 639
 640         nmtd->info         = info;
 641         nmtd->mtd.priv     = chip;
 642         nmtd->mtd.owner    = THIS_MODULE;
 643         nmtd->set          = set;
 644
 645         if (hardware_ecc) {
 646                 chip->ecc.calculate = s3c2410_nand_calculate_ecc;
 647                 chip->ecc.correct   = s3c2410_nand_correct_data;
 648                 chip->ecc.mode      = NAND_ECC_HW;
 649                 chip->ecc.size      = 512;
 650                 chip->ecc.bytes     = 3;
 651                 chip->ecc.layout    = &nand_hw_eccoob;
 652
 653                 switch (info->cpu_type) {
 654                 case TYPE_S3C2410:
 655                         chip->ecc.hwctl     = s3c2410_nand_enable_hwecc;
 656                         chip->ecc.calculate = s3c2410_nand_calculate_ecc;
 657                         break;
 658
 659                 case TYPE_S3C2412:
 660                         chip->ecc.hwctl     = s3c2412_nand_enable_hwecc;
 661                         chip->ecc.calculate = s3c2412_nand_calculate_ecc;
 662                         break;
 663
 664                 case TYPE_S3C2440:
 665                         chip->ecc.hwctl     = s3c2440_nand_enable_hwecc;
 666                         chip->ecc.calculate = s3c2440_nand_calculate_ecc;
 667                         break;
 668
 669                 }
 670         } else {
 671                 chip->ecc.mode      = NAND_ECC_SOFT;
 672         }
 673 }
 674
 675 /* s3c2410_nand_probe
 676  *
 677  * called by device layer when it finds a device matching
 678  * one our driver can handled. This code checks to see if
 679  * it can allocate all necessary resources then calls the
 680  * nand layer to look for devices
 681 */
 682
 683 static int s3c24xx_nand_probe(struct platform_device *pdev,
 684                               enum s3c_cpu_type cpu_type)
 685 {
 686         struct s3c2410_platform_nand *plat = to_nand_plat(pdev);
 687         struct s3c2410_nand_info *info;
 688         struct s3c2410_nand_mtd *nmtd;
 689         struct s3c2410_nand_set *sets;
 690         struct resource *res;
 691         int err = 0;
 692         int size;
 693         int nr_sets;
 694         int setno;
 695
 696         pr_debug("s3c2410_nand_probe(%p)\n", pdev);
 697
 698         info = kmalloc(sizeof(*info), GFP_KERNEL);
 699         if (info == NULL) {
 700                 dev_err(&pdev->dev, "no memory for flash info\n");
 701                 err = -ENOMEM;
 702                 goto exit_error;
 703         }
 704
 705         memzero(info, sizeof(*info));
 706         platform_set_drvdata(pdev, info);
 707
 708         spin_lock_init(&info->controller.lock);
 709         init_waitqueue_head(&info->controller.wq);
 710
 711         /* get the clock source and enable it */
 712
 713         info->clk = clk_get(&pdev->dev, "nand");
 714         if (IS_ERR(info->clk)) {
 715                 dev_err(&pdev->dev, "failed to get clock\n");
 716                 err = -ENOENT;
 717                 goto exit_error;
 718         }
 719
 720         clk_enable(info->clk);
 721
 722         /* allocate and map the resource */
 723
 724         /* currently we assume we have the one resource */
 725         res  = pdev->resource;
 726         size = res->end - res->start + 1;
 727
 728         info->area = request_mem_region(res->start, size, pdev->name);
 729
 730         if (info->area == NULL) {
 731                 dev_err(&pdev->dev, "cannot reserve register region\n");
 732                 err = -ENOENT;
 733                 goto exit_error;
 734         }
 735
 736         info->device     = &pdev->dev;
 737         info->platform   = plat;
 738         info->regs       = ioremap(res->start, size);
 739         info->cpu_type   = cpu_type;
 740
 741         if (info->regs == NULL) {
 742                 dev_err(&pdev->dev, "cannot reserve register region\n");
 743                 err = -EIO;
 744                 goto exit_error;
 745         }
 746
 747         dev_dbg(&pdev->dev, "mapped registers at %p\n", info->regs);
 748
 749         /* initialise the hardware */
 750
 751         err = s3c2410_nand_inithw(info, pdev);
 752         if (err != 0)
 753                 goto exit_error;
 754
 755         sets = (plat != NULL) ? plat->sets : NULL;
 756         nr_sets = (plat != NULL) ? plat->nr_sets : 1;
 757
 758         info->mtd_count = nr_sets;
 759
 760         /* allocate our information */
 761
 762         size = nr_sets * sizeof(*info->mtds);
 763         info->mtds = kmalloc(size, GFP_KERNEL);
 764         if (info->mtds == NULL) {
 765                 dev_err(&pdev->dev, "failed to allocate mtd storage\n");
 766                 err = -ENOMEM;
 767                 goto exit_error;
 768         }
 769
 770         memzero(info->mtds, size);
 771
 772         /* initialise all possible chips */
 773
 774         nmtd = info->mtds;
 775
 776         for (setno = 0; setno < nr_sets; setno++, nmtd++) {
 777                 pr_debug("initialising set %d (%p, info %p)\n", setno, nmtd, info);
 778
 779                 s3c2410_nand_init_chip(info, nmtd, sets);
 780
 781                 nmtd->scan_res = nand_scan(&nmtd->mtd, (sets) ? sets->nr_chips : 1);
 782
 783                 if (nmtd->scan_res == 0) {
 784                         s3c2410_nand_add_partition(info, nmtd, sets);
 785                 }
 786
 787                 if (sets != NULL)
 788                         sets++;
 789         }
 790
 791         if (allow_clk_stop(info)) {
 792                 dev_info(&pdev->dev, "clock idle support enabled\n");
 793                 clk_disable(info->clk);
 794         }
 795
 796         pr_debug("initialised ok\n");
 797         return 0;
 798
 799  exit_error:
 800         s3c2410_nand_remove(pdev);
 801
 802         if (err == 0)
 803                 err = -EINVAL;
 804         return err;
 805 }
 806
 807 /* PM Support */
 808 #ifdef CONFIG_PM
 809
 810 static int s3c24xx_nand_suspend(struct platform_device *dev, pm_message_t pm)
 811 {
 812         struct s3c2410_nand_info *info = platform_get_drvdata(dev);
 813
 814         if (info) {
 815                 info->save_nfconf = readl(info->regs + S3C2410_NFCONF);
 816
 817                 /* For the moment, we must ensure nFCE is high during
 818                  * the time we are suspended. This really should be
 819                  * handled by suspending the MTDs we are using, but
 820                  * that is currently not the case. */
 821
 822                 writel(info->save_nfconf | info->sel_bit,
 823                        info->regs + S3C2410_NFCONF);
 824
 825                 if (!allow_clk_stop(info))
 826                         clk_disable(info->clk);
 827         }
 828
 829         return 0;
 830 }
 831
 832 static int s3c24xx_nand_resume(struct platform_device *dev)
 833 {
 834         struct s3c2410_nand_info *info = platform_get_drvdata(dev);
 835         unsigned long nfconf;
 836
 837         if (info) {
 838                 clk_enable(info->clk);
 839                 s3c2410_nand_inithw(info, dev);
 840
 841                 /* Restore the state of the nFCE line. */
 842
 843                 nfconf = readl(info->regs + S3C2410_NFCONF);
 844                 nfconf &= ~info->sel_bit;
 845                 nfconf |= info->save_nfconf & info->sel_bit;
 846                 writel(nfconf, info->regs + S3C2410_NFCONF);
 847
 848                 if (allow_clk_stop(info))
 849                         clk_disable(info->clk);
 850         }
 851
 852         return 0;
 853 }
 854
 855 #else
 856 #define s3c24xx_nand_suspend NULL
 857 #define s3c24xx_nand_resume NULL
 858 #endif
 859
 860 /* driver device registration */
 861
 862 static int s3c2410_nand_probe(struct platform_device *dev)
 863 {
 864         return s3c24xx_nand_probe(dev, TYPE_S3C2410);
 865 }
 866
 867 static int s3c2440_nand_probe(struct platform_device *dev)
 868 {
 869         return s3c24xx_nand_probe(dev, TYPE_S3C2440);
 870 }
 871
 872 static int s3c2412_nand_probe(struct platform_device *dev)
 873 {
 874         return s3c24xx_nand_probe(dev, TYPE_S3C2412);
 875 }
 876
 877 static struct platform_driver s3c2410_nand_driver = {
 878         .probe          = s3c2410_nand_probe,
 879         .remove         = s3c2410_nand_remove,
 880         .suspend        = s3c24xx_nand_suspend,
 881         .resume         = s3c24xx_nand_resume,
 882         .driver         = {
 883                 .name   = "s3c2410-nand",
 884                 .owner  = THIS_MODULE,
 885         },
 886 };
 887
 888 static struct platform_driver s3c2440_nand_driver = {
 889         .probe          = s3c2440_nand_probe,
 890         .remove         = s3c2410_nand_remove,
 891         .suspend        = s3c24xx_nand_suspend,
 892         .resume         = s3c24xx_nand_resume,
 893         .driver         = {
 894                 .name   = "s3c2440-nand",
 895                 .owner  = THIS_MODULE,
 896         },
 897 };
 898
 899 static struct platform_driver s3c2412_nand_driver = {
 900         .probe          = s3c2412_nand_probe,
 901         .remove         = s3c2410_nand_remove,
 902         .suspend        = s3c24xx_nand_suspend,
 903         .resume         = s3c24xx_nand_resume,
 904         .driver         = {
 905                 .name   = "s3c2412-nand",
 906                 .owner  = THIS_MODULE,
 907         },
 908 };
 909
 910 static int __init s3c2410_nand_init(void)
 911 {
 912         printk("S3C24XX NAND Driver, (c) 2004 Simtec Electronics\n");
 913
 914         platform_driver_register(&s3c2412_nand_driver);
 915         platform_driver_register(&s3c2440_nand_driver);
 916         return platform_driver_register(&s3c2410_nand_driver);
 917 }
 918
 919 static void __exit s3c2410_nand_exit(void)
 920 {
 921         platform_driver_unregister(&s3c2412_nand_driver);
 922         platform_driver_unregister(&s3c2440_nand_driver);
 923         platform_driver_unregister(&s3c2410_nand_driver);
 924 }
 925
 926 module_init(s3c2410_nand_init);
 927 module_exit(s3c2410_nand_exit);
 928
 929 MODULE_LICENSE("GPL");
 930 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
 931 MODULE_DESCRIPTION("S3C24XX MTD NAND driver");