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ath9k_hw: fall back to OTP ROM when platform data has no valid eeprom data
[linux-2.6/libata-dev.git] / drivers / net / wireless / ath / ath9k / ar9003_eeprom.c
blob3cddd78e88ac4268bde513c66319b085b3499ea5
1 /*
2 * Copyright (c) 2010-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <asm/unaligned.h>
18 #include "hw.h"
19 #include "ar9003_phy.h"
20 #include "ar9003_eeprom.h"
21
22 #define COMP_HDR_LEN 4
23 #define COMP_CKSUM_LEN 2
24
25 #define LE16(x) __constant_cpu_to_le16(x)
26 #define LE32(x) __constant_cpu_to_le32(x)
27
28 /* Local defines to distinguish between extension and control CTL's */
29 #define EXT_ADDITIVE (0x8000)
30 #define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE)
31 #define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
32 #define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
33
34 #define SUB_NUM_CTL_MODES_AT_5G_40 2 /* excluding HT40, EXT-OFDM */
35 #define SUB_NUM_CTL_MODES_AT_2G_40 3 /* excluding HT40, EXT-OFDM, EXT-CCK */
36
37 #define CTL(_tpower, _flag) ((_tpower) | ((_flag) << 6))
38
39 #define EEPROM_DATA_LEN_9485 1088
40
41 static int ar9003_hw_power_interpolate(int32_t x,
42 int32_t *px, int32_t *py, u_int16_t np);
43
44
45 static const struct ar9300_eeprom ar9300_default = {
46 .eepromVersion = 2,
47 .templateVersion = 2,
48 .macAddr = {0, 2, 3, 4, 5, 6},
49 .custData = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
50 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
51 .baseEepHeader = {
52 .regDmn = { LE16(0), LE16(0x1f) },
53 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
54 .opCapFlags = {
55 .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
56 .eepMisc = 0,
57 },
58 .rfSilent = 0,
59 .blueToothOptions = 0,
60 .deviceCap = 0,
61 .deviceType = 5, /* takes lower byte in eeprom location */
62 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
63 .params_for_tuning_caps = {0, 0},
64 .featureEnable = 0x0c,
65 /*
66 * bit0 - enable tx temp comp - disabled
67 * bit1 - enable tx volt comp - disabled
68 * bit2 - enable fastClock - enabled
69 * bit3 - enable doubling - enabled
70 * bit4 - enable internal regulator - disabled
71 * bit5 - enable pa predistortion - disabled
72 */
73 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
74 .eepromWriteEnableGpio = 3,
75 .wlanDisableGpio = 0,
76 .wlanLedGpio = 8,
77 .rxBandSelectGpio = 0xff,
78 .txrxgain = 0,
79 .swreg = 0,
80 },
81 .modalHeader2G = {
82 /* ar9300_modal_eep_header 2g */
83 /* 4 idle,t1,t2,b(4 bits per setting) */
84 .antCtrlCommon = LE32(0x110),
85 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
86 .antCtrlCommon2 = LE32(0x22222),
87
88 /*
89 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
90 * rx1, rx12, b (2 bits each)
91 */
92 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
93
94 /*
95 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
96 * for ar9280 (0xa20c/b20c 5:0)
97 */
98 .xatten1DB = {0, 0, 0},
99
100 /*
101 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
102 * for ar9280 (0xa20c/b20c 16:12
103 */
104 .xatten1Margin = {0, 0, 0},
105 .tempSlope = 36,
106 .voltSlope = 0,
107
108 /*
109 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
110 * channels in usual fbin coding format
111 */
112 .spurChans = {0, 0, 0, 0, 0},
113
114 /*
115 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
116 * if the register is per chain
117 */
118 .noiseFloorThreshCh = {-1, 0, 0},
119 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
120 .quick_drop = 0,
121 .xpaBiasLvl = 0,
122 .txFrameToDataStart = 0x0e,
123 .txFrameToPaOn = 0x0e,
124 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
125 .antennaGain = 0,
126 .switchSettling = 0x2c,
127 .adcDesiredSize = -30,
128 .txEndToXpaOff = 0,
129 .txEndToRxOn = 0x2,
130 .txFrameToXpaOn = 0xe,
131 .thresh62 = 28,
132 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
133 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
134 .futureModal = {
135 0, 0, 0, 0, 0, 0, 0, 0,
136 },
137 },
138 .base_ext1 = {
139 .ant_div_control = 0,
140 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
141 },
142 .calFreqPier2G = {
143 FREQ2FBIN(2412, 1),
144 FREQ2FBIN(2437, 1),
145 FREQ2FBIN(2472, 1),
146 },
147 /* ar9300_cal_data_per_freq_op_loop 2g */
148 .calPierData2G = {
149 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
150 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
151 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
152 },
153 .calTarget_freqbin_Cck = {
154 FREQ2FBIN(2412, 1),
155 FREQ2FBIN(2484, 1),
156 },
157 .calTarget_freqbin_2G = {
158 FREQ2FBIN(2412, 1),
159 FREQ2FBIN(2437, 1),
160 FREQ2FBIN(2472, 1)
161 },
162 .calTarget_freqbin_2GHT20 = {
163 FREQ2FBIN(2412, 1),
164 FREQ2FBIN(2437, 1),
165 FREQ2FBIN(2472, 1)
166 },
167 .calTarget_freqbin_2GHT40 = {
168 FREQ2FBIN(2412, 1),
169 FREQ2FBIN(2437, 1),
170 FREQ2FBIN(2472, 1)
171 },
172 .calTargetPowerCck = {
173 /* 1L-5L,5S,11L,11S */
174 { {36, 36, 36, 36} },
175 { {36, 36, 36, 36} },
176 },
177 .calTargetPower2G = {
178 /* 6-24,36,48,54 */
179 { {32, 32, 28, 24} },
180 { {32, 32, 28, 24} },
181 { {32, 32, 28, 24} },
182 },
183 .calTargetPower2GHT20 = {
184 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
185 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
186 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
187 },
188 .calTargetPower2GHT40 = {
189 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
190 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
191 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
192 },
193 .ctlIndex_2G = {
194 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
195 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
196 },
197 .ctl_freqbin_2G = {
198 {
199 FREQ2FBIN(2412, 1),
200 FREQ2FBIN(2417, 1),
201 FREQ2FBIN(2457, 1),
202 FREQ2FBIN(2462, 1)
203 },
204 {
205 FREQ2FBIN(2412, 1),
206 FREQ2FBIN(2417, 1),
207 FREQ2FBIN(2462, 1),
208 0xFF,
209 },
210
211 {
212 FREQ2FBIN(2412, 1),
213 FREQ2FBIN(2417, 1),
214 FREQ2FBIN(2462, 1),
215 0xFF,
216 },
217 {
218 FREQ2FBIN(2422, 1),
219 FREQ2FBIN(2427, 1),
220 FREQ2FBIN(2447, 1),
221 FREQ2FBIN(2452, 1)
222 },
223
224 {
225 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
226 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
227 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
228 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
229 },
230
231 {
232 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
233 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
234 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
235 0,
236 },
237
238 {
239 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
240 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
241 FREQ2FBIN(2472, 1),
242 0,
243 },
244
245 {
246 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
247 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
248 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
249 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
250 },
251
252 {
253 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
254 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
255 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
256 },
257
258 {
259 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
260 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
261 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
262 0
263 },
264
265 {
266 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
267 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
268 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
269 0
270 },
271
272 {
273 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
274 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
275 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
276 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
277 }
278 },
279 .ctlPowerData_2G = {
280 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
281 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
282 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
283
284 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
285 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
286 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
287
288 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
289 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
290 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
291
292 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
293 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
294 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
295 },
296 .modalHeader5G = {
297 /* 4 idle,t1,t2,b (4 bits per setting) */
298 .antCtrlCommon = LE32(0x110),
299 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
300 .antCtrlCommon2 = LE32(0x22222),
301 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
302 .antCtrlChain = {
303 LE16(0x000), LE16(0x000), LE16(0x000),
304 },
305 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
306 .xatten1DB = {0, 0, 0},
307
308 /*
309 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
310 * for merlin (0xa20c/b20c 16:12
311 */
312 .xatten1Margin = {0, 0, 0},
313 .tempSlope = 68,
314 .voltSlope = 0,
315 /* spurChans spur channels in usual fbin coding format */
316 .spurChans = {0, 0, 0, 0, 0},
317 /* noiseFloorThreshCh Check if the register is per chain */
318 .noiseFloorThreshCh = {-1, 0, 0},
319 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
320 .quick_drop = 0,
321 .xpaBiasLvl = 0,
322 .txFrameToDataStart = 0x0e,
323 .txFrameToPaOn = 0x0e,
324 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
325 .antennaGain = 0,
326 .switchSettling = 0x2d,
327 .adcDesiredSize = -30,
328 .txEndToXpaOff = 0,
329 .txEndToRxOn = 0x2,
330 .txFrameToXpaOn = 0xe,
331 .thresh62 = 28,
332 .papdRateMaskHt20 = LE32(0x0c80c080),
333 .papdRateMaskHt40 = LE32(0x0080c080),
334 .futureModal = {
335 0, 0, 0, 0, 0, 0, 0, 0,
336 },
337 },
338 .base_ext2 = {
339 .tempSlopeLow = 0,
340 .tempSlopeHigh = 0,
341 .xatten1DBLow = {0, 0, 0},
342 .xatten1MarginLow = {0, 0, 0},
343 .xatten1DBHigh = {0, 0, 0},
344 .xatten1MarginHigh = {0, 0, 0}
345 },
346 .calFreqPier5G = {
347 FREQ2FBIN(5180, 0),
348 FREQ2FBIN(5220, 0),
349 FREQ2FBIN(5320, 0),
350 FREQ2FBIN(5400, 0),
351 FREQ2FBIN(5500, 0),
352 FREQ2FBIN(5600, 0),
353 FREQ2FBIN(5725, 0),
354 FREQ2FBIN(5825, 0)
355 },
356 .calPierData5G = {
357 {
358 {0, 0, 0, 0, 0},
359 {0, 0, 0, 0, 0},
360 {0, 0, 0, 0, 0},
361 {0, 0, 0, 0, 0},
362 {0, 0, 0, 0, 0},
363 {0, 0, 0, 0, 0},
364 {0, 0, 0, 0, 0},
365 {0, 0, 0, 0, 0},
366 },
367 {
368 {0, 0, 0, 0, 0},
369 {0, 0, 0, 0, 0},
370 {0, 0, 0, 0, 0},
371 {0, 0, 0, 0, 0},
372 {0, 0, 0, 0, 0},
373 {0, 0, 0, 0, 0},
374 {0, 0, 0, 0, 0},
375 {0, 0, 0, 0, 0},
376 },
377 {
378 {0, 0, 0, 0, 0},
379 {0, 0, 0, 0, 0},
380 {0, 0, 0, 0, 0},
381 {0, 0, 0, 0, 0},
382 {0, 0, 0, 0, 0},
383 {0, 0, 0, 0, 0},
384 {0, 0, 0, 0, 0},
385 {0, 0, 0, 0, 0},
386 },
387
388 },
389 .calTarget_freqbin_5G = {
390 FREQ2FBIN(5180, 0),
391 FREQ2FBIN(5220, 0),
392 FREQ2FBIN(5320, 0),
393 FREQ2FBIN(5400, 0),
394 FREQ2FBIN(5500, 0),
395 FREQ2FBIN(5600, 0),
396 FREQ2FBIN(5725, 0),
397 FREQ2FBIN(5825, 0)
398 },
399 .calTarget_freqbin_5GHT20 = {
400 FREQ2FBIN(5180, 0),
401 FREQ2FBIN(5240, 0),
402 FREQ2FBIN(5320, 0),
403 FREQ2FBIN(5500, 0),
404 FREQ2FBIN(5700, 0),
405 FREQ2FBIN(5745, 0),
406 FREQ2FBIN(5725, 0),
407 FREQ2FBIN(5825, 0)
408 },
409 .calTarget_freqbin_5GHT40 = {
410 FREQ2FBIN(5180, 0),
411 FREQ2FBIN(5240, 0),
412 FREQ2FBIN(5320, 0),
413 FREQ2FBIN(5500, 0),
414 FREQ2FBIN(5700, 0),
415 FREQ2FBIN(5745, 0),
416 FREQ2FBIN(5725, 0),
417 FREQ2FBIN(5825, 0)
418 },
419 .calTargetPower5G = {
420 /* 6-24,36,48,54 */
421 { {20, 20, 20, 10} },
422 { {20, 20, 20, 10} },
423 { {20, 20, 20, 10} },
424 { {20, 20, 20, 10} },
425 { {20, 20, 20, 10} },
426 { {20, 20, 20, 10} },
427 { {20, 20, 20, 10} },
428 { {20, 20, 20, 10} },
429 },
430 .calTargetPower5GHT20 = {
431 /*
432 * 0_8_16,1-3_9-11_17-19,
433 * 4,5,6,7,12,13,14,15,20,21,22,23
434 */
435 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
436 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
437 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
438 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
439 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
440 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
441 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
442 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
443 },
444 .calTargetPower5GHT40 = {
445 /*
446 * 0_8_16,1-3_9-11_17-19,
447 * 4,5,6,7,12,13,14,15,20,21,22,23
448 */
449 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
450 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
451 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
452 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
453 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
454 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
455 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
456 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
457 },
458 .ctlIndex_5G = {
459 0x10, 0x16, 0x18, 0x40, 0x46,
460 0x48, 0x30, 0x36, 0x38
461 },
462 .ctl_freqbin_5G = {
463 {
464 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
465 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
466 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
467 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
468 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
469 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
470 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
471 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
472 },
473 {
474 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
475 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
476 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
477 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
478 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
479 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
480 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
481 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
482 },
483
484 {
485 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
486 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
487 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
488 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
489 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
490 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
491 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
492 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
493 },
494
495 {
496 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
497 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
498 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
499 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
500 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
501 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
502 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
503 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
504 },
505
506 {
507 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
508 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
509 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
510 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
511 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
512 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
513 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
514 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
515 },
516
517 {
518 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
519 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
520 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
521 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
522 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
523 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
524 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
525 /* Data[5].ctlEdges[7].bChannel */ 0xFF
526 },
527
528 {
529 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
530 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
531 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
532 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
533 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
534 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
535 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
536 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
537 },
538
539 {
540 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
541 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
542 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
543 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
544 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
545 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
546 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
547 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
548 },
549
550 {
551 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
552 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
553 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
554 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
555 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
556 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
557 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
558 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
559 }
560 },
561 .ctlPowerData_5G = {
562 {
563 {
564 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
565 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
566 }
567 },
568 {
569 {
570 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
571 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
572 }
573 },
574 {
575 {
576 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
577 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
578 }
579 },
580 {
581 {
582 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
583 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
584 }
585 },
586 {
587 {
588 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
589 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
590 }
591 },
592 {
593 {
594 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
595 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
596 }
597 },
598 {
599 {
600 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
601 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
602 }
603 },
604 {
605 {
606 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
607 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
608 }
609 },
610 {
611 {
612 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
613 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
614 }
615 },
616 }
617 };
618
619 static const struct ar9300_eeprom ar9300_x113 = {
620 .eepromVersion = 2,
621 .templateVersion = 6,
622 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
623 .custData = {"x113-023-f0000"},
624 .baseEepHeader = {
625 .regDmn = { LE16(0), LE16(0x1f) },
626 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
627 .opCapFlags = {
628 .opFlags = AR5416_OPFLAGS_11A,
629 .eepMisc = 0,
630 },
631 .rfSilent = 0,
632 .blueToothOptions = 0,
633 .deviceCap = 0,
634 .deviceType = 5, /* takes lower byte in eeprom location */
635 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
636 .params_for_tuning_caps = {0, 0},
637 .featureEnable = 0x0d,
638 /*
639 * bit0 - enable tx temp comp - disabled
640 * bit1 - enable tx volt comp - disabled
641 * bit2 - enable fastClock - enabled
642 * bit3 - enable doubling - enabled
643 * bit4 - enable internal regulator - disabled
644 * bit5 - enable pa predistortion - disabled
645 */
646 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
647 .eepromWriteEnableGpio = 6,
648 .wlanDisableGpio = 0,
649 .wlanLedGpio = 8,
650 .rxBandSelectGpio = 0xff,
651 .txrxgain = 0x21,
652 .swreg = 0,
653 },
654 .modalHeader2G = {
655 /* ar9300_modal_eep_header 2g */
656 /* 4 idle,t1,t2,b(4 bits per setting) */
657 .antCtrlCommon = LE32(0x110),
658 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
659 .antCtrlCommon2 = LE32(0x44444),
660
661 /*
662 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
663 * rx1, rx12, b (2 bits each)
664 */
665 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
666
667 /*
668 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
669 * for ar9280 (0xa20c/b20c 5:0)
670 */
671 .xatten1DB = {0, 0, 0},
672
673 /*
674 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
675 * for ar9280 (0xa20c/b20c 16:12
676 */
677 .xatten1Margin = {0, 0, 0},
678 .tempSlope = 25,
679 .voltSlope = 0,
680
681 /*
682 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
683 * channels in usual fbin coding format
684 */
685 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
686
687 /*
688 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
689 * if the register is per chain
690 */
691 .noiseFloorThreshCh = {-1, 0, 0},
692 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
693 .quick_drop = 0,
694 .xpaBiasLvl = 0,
695 .txFrameToDataStart = 0x0e,
696 .txFrameToPaOn = 0x0e,
697 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
698 .antennaGain = 0,
699 .switchSettling = 0x2c,
700 .adcDesiredSize = -30,
701 .txEndToXpaOff = 0,
702 .txEndToRxOn = 0x2,
703 .txFrameToXpaOn = 0xe,
704 .thresh62 = 28,
705 .papdRateMaskHt20 = LE32(0x0c80c080),
706 .papdRateMaskHt40 = LE32(0x0080c080),
707 .futureModal = {
708 0, 0, 0, 0, 0, 0, 0, 0,
709 },
710 },
711 .base_ext1 = {
712 .ant_div_control = 0,
713 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
714 },
715 .calFreqPier2G = {
716 FREQ2FBIN(2412, 1),
717 FREQ2FBIN(2437, 1),
718 FREQ2FBIN(2472, 1),
719 },
720 /* ar9300_cal_data_per_freq_op_loop 2g */
721 .calPierData2G = {
722 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
723 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
724 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
725 },
726 .calTarget_freqbin_Cck = {
727 FREQ2FBIN(2412, 1),
728 FREQ2FBIN(2472, 1),
729 },
730 .calTarget_freqbin_2G = {
731 FREQ2FBIN(2412, 1),
732 FREQ2FBIN(2437, 1),
733 FREQ2FBIN(2472, 1)
734 },
735 .calTarget_freqbin_2GHT20 = {
736 FREQ2FBIN(2412, 1),
737 FREQ2FBIN(2437, 1),
738 FREQ2FBIN(2472, 1)
739 },
740 .calTarget_freqbin_2GHT40 = {
741 FREQ2FBIN(2412, 1),
742 FREQ2FBIN(2437, 1),
743 FREQ2FBIN(2472, 1)
744 },
745 .calTargetPowerCck = {
746 /* 1L-5L,5S,11L,11S */
747 { {34, 34, 34, 34} },
748 { {34, 34, 34, 34} },
749 },
750 .calTargetPower2G = {
751 /* 6-24,36,48,54 */
752 { {34, 34, 32, 32} },
753 { {34, 34, 32, 32} },
754 { {34, 34, 32, 32} },
755 },
756 .calTargetPower2GHT20 = {
757 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
758 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
759 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
760 },
761 .calTargetPower2GHT40 = {
762 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
763 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
764 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
765 },
766 .ctlIndex_2G = {
767 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
768 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
769 },
770 .ctl_freqbin_2G = {
771 {
772 FREQ2FBIN(2412, 1),
773 FREQ2FBIN(2417, 1),
774 FREQ2FBIN(2457, 1),
775 FREQ2FBIN(2462, 1)
776 },
777 {
778 FREQ2FBIN(2412, 1),
779 FREQ2FBIN(2417, 1),
780 FREQ2FBIN(2462, 1),
781 0xFF,
782 },
783
784 {
785 FREQ2FBIN(2412, 1),
786 FREQ2FBIN(2417, 1),
787 FREQ2FBIN(2462, 1),
788 0xFF,
789 },
790 {
791 FREQ2FBIN(2422, 1),
792 FREQ2FBIN(2427, 1),
793 FREQ2FBIN(2447, 1),
794 FREQ2FBIN(2452, 1)
795 },
796
797 {
798 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
799 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
800 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
801 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
802 },
803
804 {
805 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
806 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
807 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
808 0,
809 },
810
811 {
812 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
813 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
814 FREQ2FBIN(2472, 1),
815 0,
816 },
817
818 {
819 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
820 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
821 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
822 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
823 },
824
825 {
826 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
827 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
828 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
829 },
830
831 {
832 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
833 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
834 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
835 0
836 },
837
838 {
839 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
840 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
841 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
842 0
843 },
844
845 {
846 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
847 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
848 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
849 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
850 }
851 },
852 .ctlPowerData_2G = {
853 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
854 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
855 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
856
857 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
858 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
859 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
860
861 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
862 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
863 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
864
865 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
866 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
867 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
868 },
869 .modalHeader5G = {
870 /* 4 idle,t1,t2,b (4 bits per setting) */
871 .antCtrlCommon = LE32(0x220),
872 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
873 .antCtrlCommon2 = LE32(0x11111),
874 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
875 .antCtrlChain = {
876 LE16(0x150), LE16(0x150), LE16(0x150),
877 },
878 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
879 .xatten1DB = {0, 0, 0},
880
881 /*
882 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
883 * for merlin (0xa20c/b20c 16:12
884 */
885 .xatten1Margin = {0, 0, 0},
886 .tempSlope = 68,
887 .voltSlope = 0,
888 /* spurChans spur channels in usual fbin coding format */
889 .spurChans = {FREQ2FBIN(5500, 0), 0, 0, 0, 0},
890 /* noiseFloorThreshCh Check if the register is per chain */
891 .noiseFloorThreshCh = {-1, 0, 0},
892 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
893 .quick_drop = 0,
894 .xpaBiasLvl = 0xf,
895 .txFrameToDataStart = 0x0e,
896 .txFrameToPaOn = 0x0e,
897 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
898 .antennaGain = 0,
899 .switchSettling = 0x2d,
900 .adcDesiredSize = -30,
901 .txEndToXpaOff = 0,
902 .txEndToRxOn = 0x2,
903 .txFrameToXpaOn = 0xe,
904 .thresh62 = 28,
905 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
906 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
907 .futureModal = {
908 0, 0, 0, 0, 0, 0, 0, 0,
909 },
910 },
911 .base_ext2 = {
912 .tempSlopeLow = 72,
913 .tempSlopeHigh = 105,
914 .xatten1DBLow = {0, 0, 0},
915 .xatten1MarginLow = {0, 0, 0},
916 .xatten1DBHigh = {0, 0, 0},
917 .xatten1MarginHigh = {0, 0, 0}
918 },
919 .calFreqPier5G = {
920 FREQ2FBIN(5180, 0),
921 FREQ2FBIN(5240, 0),
922 FREQ2FBIN(5320, 0),
923 FREQ2FBIN(5400, 0),
924 FREQ2FBIN(5500, 0),
925 FREQ2FBIN(5600, 0),
926 FREQ2FBIN(5745, 0),
927 FREQ2FBIN(5785, 0)
928 },
929 .calPierData5G = {
930 {
931 {0, 0, 0, 0, 0},
932 {0, 0, 0, 0, 0},
933 {0, 0, 0, 0, 0},
934 {0, 0, 0, 0, 0},
935 {0, 0, 0, 0, 0},
936 {0, 0, 0, 0, 0},
937 {0, 0, 0, 0, 0},
938 {0, 0, 0, 0, 0},
939 },
940 {
941 {0, 0, 0, 0, 0},
942 {0, 0, 0, 0, 0},
943 {0, 0, 0, 0, 0},
944 {0, 0, 0, 0, 0},
945 {0, 0, 0, 0, 0},
946 {0, 0, 0, 0, 0},
947 {0, 0, 0, 0, 0},
948 {0, 0, 0, 0, 0},
949 },
950 {
951 {0, 0, 0, 0, 0},
952 {0, 0, 0, 0, 0},
953 {0, 0, 0, 0, 0},
954 {0, 0, 0, 0, 0},
955 {0, 0, 0, 0, 0},
956 {0, 0, 0, 0, 0},
957 {0, 0, 0, 0, 0},
958 {0, 0, 0, 0, 0},
959 },
960
961 },
962 .calTarget_freqbin_5G = {
963 FREQ2FBIN(5180, 0),
964 FREQ2FBIN(5220, 0),
965 FREQ2FBIN(5320, 0),
966 FREQ2FBIN(5400, 0),
967 FREQ2FBIN(5500, 0),
968 FREQ2FBIN(5600, 0),
969 FREQ2FBIN(5745, 0),
970 FREQ2FBIN(5785, 0)
971 },
972 .calTarget_freqbin_5GHT20 = {
973 FREQ2FBIN(5180, 0),
974 FREQ2FBIN(5240, 0),
975 FREQ2FBIN(5320, 0),
976 FREQ2FBIN(5400, 0),
977 FREQ2FBIN(5500, 0),
978 FREQ2FBIN(5700, 0),
979 FREQ2FBIN(5745, 0),
980 FREQ2FBIN(5825, 0)
981 },
982 .calTarget_freqbin_5GHT40 = {
983 FREQ2FBIN(5190, 0),
984 FREQ2FBIN(5230, 0),
985 FREQ2FBIN(5320, 0),
986 FREQ2FBIN(5410, 0),
987 FREQ2FBIN(5510, 0),
988 FREQ2FBIN(5670, 0),
989 FREQ2FBIN(5755, 0),
990 FREQ2FBIN(5825, 0)
991 },
992 .calTargetPower5G = {
993 /* 6-24,36,48,54 */
994 { {42, 40, 40, 34} },
995 { {42, 40, 40, 34} },
996 { {42, 40, 40, 34} },
997 { {42, 40, 40, 34} },
998 { {42, 40, 40, 34} },
999 { {42, 40, 40, 34} },
1000 { {42, 40, 40, 34} },
1001 { {42, 40, 40, 34} },
1002 },
1003 .calTargetPower5GHT20 = {
1004 /*
1005 * 0_8_16,1-3_9-11_17-19,
1006 * 4,5,6,7,12,13,14,15,20,21,22,23
1007 */
1008 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1009 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1010 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1011 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1012 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1013 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1014 { {38, 38, 38, 38, 32, 28, 38, 38, 32, 28, 38, 38, 32, 26} },
1015 { {36, 36, 36, 36, 32, 28, 36, 36, 32, 28, 36, 36, 32, 26} },
1016 },
1017 .calTargetPower5GHT40 = {
1018 /*
1019 * 0_8_16,1-3_9-11_17-19,
1020 * 4,5,6,7,12,13,14,15,20,21,22,23
1021 */
1022 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1023 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1024 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1025 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1026 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1027 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1028 { {36, 36, 36, 36, 30, 26, 36, 36, 30, 26, 36, 36, 30, 24} },
1029 { {34, 34, 34, 34, 30, 26, 34, 34, 30, 26, 34, 34, 30, 24} },
1030 },
1031 .ctlIndex_5G = {
1032 0x10, 0x16, 0x18, 0x40, 0x46,
1033 0x48, 0x30, 0x36, 0x38
1034 },
1035 .ctl_freqbin_5G = {
1036 {
1037 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1038 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1039 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1040 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1041 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
1042 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1043 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1044 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1045 },
1046 {
1047 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1048 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1049 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1050 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1051 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
1052 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1053 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1054 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1055 },
1056
1057 {
1058 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1059 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1060 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1061 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
1062 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
1063 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
1064 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
1065 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
1066 },
1067
1068 {
1069 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1070 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1071 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
1072 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
1073 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1074 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1075 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
1076 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
1077 },
1078
1079 {
1080 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1081 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1082 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
1083 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
1084 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
1085 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
1086 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
1087 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
1088 },
1089
1090 {
1091 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1092 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
1093 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
1094 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1095 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
1096 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1097 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
1098 /* Data[5].ctlEdges[7].bChannel */ 0xFF
1099 },
1100
1101 {
1102 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1103 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1104 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
1105 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
1106 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1107 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
1108 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
1109 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
1110 },
1111
1112 {
1113 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1114 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1115 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
1116 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1117 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
1118 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1119 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1120 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1121 },
1122
1123 {
1124 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1125 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1126 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1127 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1128 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
1129 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1130 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
1131 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
1132 }
1133 },
1134 .ctlPowerData_5G = {
1135 {
1136 {
1137 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1138 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1139 }
1140 },
1141 {
1142 {
1143 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1144 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1145 }
1146 },
1147 {
1148 {
1149 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1150 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1151 }
1152 },
1153 {
1154 {
1155 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1156 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1157 }
1158 },
1159 {
1160 {
1161 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1162 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1163 }
1164 },
1165 {
1166 {
1167 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1168 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1169 }
1170 },
1171 {
1172 {
1173 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1174 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1175 }
1176 },
1177 {
1178 {
1179 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1180 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1181 }
1182 },
1183 {
1184 {
1185 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
1186 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1187 }
1188 },
1189 }
1190 };
1191
1192
1193 static const struct ar9300_eeprom ar9300_h112 = {
1194 .eepromVersion = 2,
1195 .templateVersion = 3,
1196 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
1197 .custData = {"h112-241-f0000"},
1198 .baseEepHeader = {
1199 .regDmn = { LE16(0), LE16(0x1f) },
1200 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
1201 .opCapFlags = {
1202 .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
1203 .eepMisc = 0,
1204 },
1205 .rfSilent = 0,
1206 .blueToothOptions = 0,
1207 .deviceCap = 0,
1208 .deviceType = 5, /* takes lower byte in eeprom location */
1209 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
1210 .params_for_tuning_caps = {0, 0},
1211 .featureEnable = 0x0d,
1212 /*
1213 * bit0 - enable tx temp comp - disabled
1214 * bit1 - enable tx volt comp - disabled
1215 * bit2 - enable fastClock - enabled
1216 * bit3 - enable doubling - enabled
1217 * bit4 - enable internal regulator - disabled
1218 * bit5 - enable pa predistortion - disabled
1219 */
1220 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
1221 .eepromWriteEnableGpio = 6,
1222 .wlanDisableGpio = 0,
1223 .wlanLedGpio = 8,
1224 .rxBandSelectGpio = 0xff,
1225 .txrxgain = 0x10,
1226 .swreg = 0,
1227 },
1228 .modalHeader2G = {
1229 /* ar9300_modal_eep_header 2g */
1230 /* 4 idle,t1,t2,b(4 bits per setting) */
1231 .antCtrlCommon = LE32(0x110),
1232 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
1233 .antCtrlCommon2 = LE32(0x44444),
1234
1235 /*
1236 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
1237 * rx1, rx12, b (2 bits each)
1238 */
1239 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
1240
1241 /*
1242 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
1243 * for ar9280 (0xa20c/b20c 5:0)
1244 */
1245 .xatten1DB = {0, 0, 0},
1246
1247 /*
1248 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
1249 * for ar9280 (0xa20c/b20c 16:12
1250 */
1251 .xatten1Margin = {0, 0, 0},
1252 .tempSlope = 25,
1253 .voltSlope = 0,
1254
1255 /*
1256 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
1257 * channels in usual fbin coding format
1258 */
1259 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
1260
1261 /*
1262 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
1263 * if the register is per chain
1264 */
1265 .noiseFloorThreshCh = {-1, 0, 0},
1266 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
1267 .quick_drop = 0,
1268 .xpaBiasLvl = 0,
1269 .txFrameToDataStart = 0x0e,
1270 .txFrameToPaOn = 0x0e,
1271 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1272 .antennaGain = 0,
1273 .switchSettling = 0x2c,
1274 .adcDesiredSize = -30,
1275 .txEndToXpaOff = 0,
1276 .txEndToRxOn = 0x2,
1277 .txFrameToXpaOn = 0xe,
1278 .thresh62 = 28,
1279 .papdRateMaskHt20 = LE32(0x0c80c080),
1280 .papdRateMaskHt40 = LE32(0x0080c080),
1281 .futureModal = {
1282 0, 0, 0, 0, 0, 0, 0, 0,
1283 },
1284 },
1285 .base_ext1 = {
1286 .ant_div_control = 0,
1287 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
1288 },
1289 .calFreqPier2G = {
1290 FREQ2FBIN(2412, 1),
1291 FREQ2FBIN(2437, 1),
1292 FREQ2FBIN(2462, 1),
1293 },
1294 /* ar9300_cal_data_per_freq_op_loop 2g */
1295 .calPierData2G = {
1296 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1297 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1298 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1299 },
1300 .calTarget_freqbin_Cck = {
1301 FREQ2FBIN(2412, 1),
1302 FREQ2FBIN(2472, 1),
1303 },
1304 .calTarget_freqbin_2G = {
1305 FREQ2FBIN(2412, 1),
1306 FREQ2FBIN(2437, 1),
1307 FREQ2FBIN(2472, 1)
1308 },
1309 .calTarget_freqbin_2GHT20 = {
1310 FREQ2FBIN(2412, 1),
1311 FREQ2FBIN(2437, 1),
1312 FREQ2FBIN(2472, 1)
1313 },
1314 .calTarget_freqbin_2GHT40 = {
1315 FREQ2FBIN(2412, 1),
1316 FREQ2FBIN(2437, 1),
1317 FREQ2FBIN(2472, 1)
1318 },
1319 .calTargetPowerCck = {
1320 /* 1L-5L,5S,11L,11S */
1321 { {34, 34, 34, 34} },
1322 { {34, 34, 34, 34} },
1323 },
1324 .calTargetPower2G = {
1325 /* 6-24,36,48,54 */
1326 { {34, 34, 32, 32} },
1327 { {34, 34, 32, 32} },
1328 { {34, 34, 32, 32} },
1329 },
1330 .calTargetPower2GHT20 = {
1331 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1332 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1333 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1334 },
1335 .calTargetPower2GHT40 = {
1336 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1337 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1338 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1339 },
1340 .ctlIndex_2G = {
1341 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
1342 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
1343 },
1344 .ctl_freqbin_2G = {
1345 {
1346 FREQ2FBIN(2412, 1),
1347 FREQ2FBIN(2417, 1),
1348 FREQ2FBIN(2457, 1),
1349 FREQ2FBIN(2462, 1)
1350 },
1351 {
1352 FREQ2FBIN(2412, 1),
1353 FREQ2FBIN(2417, 1),
1354 FREQ2FBIN(2462, 1),
1355 0xFF,
1356 },
1357
1358 {
1359 FREQ2FBIN(2412, 1),
1360 FREQ2FBIN(2417, 1),
1361 FREQ2FBIN(2462, 1),
1362 0xFF,
1363 },
1364 {
1365 FREQ2FBIN(2422, 1),
1366 FREQ2FBIN(2427, 1),
1367 FREQ2FBIN(2447, 1),
1368 FREQ2FBIN(2452, 1)
1369 },
1370
1371 {
1372 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1373 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1374 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1375 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
1376 },
1377
1378 {
1379 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1380 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1381 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1382 0,
1383 },
1384
1385 {
1386 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1387 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1388 FREQ2FBIN(2472, 1),
1389 0,
1390 },
1391
1392 {
1393 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
1394 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
1395 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
1396 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
1397 },
1398
1399 {
1400 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1401 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1402 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1403 },
1404
1405 {
1406 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1407 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1408 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1409 0
1410 },
1411
1412 {
1413 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1414 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1415 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1416 0
1417 },
1418
1419 {
1420 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
1421 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
1422 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
1423 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
1424 }
1425 },
1426 .ctlPowerData_2G = {
1427 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1428 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1429 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
1430
1431 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
1432 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1433 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1434
1435 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
1436 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1437 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1438
1439 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1440 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
1441 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
1442 },
1443 .modalHeader5G = {
1444 /* 4 idle,t1,t2,b (4 bits per setting) */
1445 .antCtrlCommon = LE32(0x220),
1446 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
1447 .antCtrlCommon2 = LE32(0x44444),
1448 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
1449 .antCtrlChain = {
1450 LE16(0x150), LE16(0x150), LE16(0x150),
1451 },
1452 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
1453 .xatten1DB = {0, 0, 0},
1454
1455 /*
1456 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
1457 * for merlin (0xa20c/b20c 16:12
1458 */
1459 .xatten1Margin = {0, 0, 0},
1460 .tempSlope = 45,
1461 .voltSlope = 0,
1462 /* spurChans spur channels in usual fbin coding format */
1463 .spurChans = {0, 0, 0, 0, 0},
1464 /* noiseFloorThreshCh Check if the register is per chain */
1465 .noiseFloorThreshCh = {-1, 0, 0},
1466 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
1467 .quick_drop = 0,
1468 .xpaBiasLvl = 0,
1469 .txFrameToDataStart = 0x0e,
1470 .txFrameToPaOn = 0x0e,
1471 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1472 .antennaGain = 0,
1473 .switchSettling = 0x2d,
1474 .adcDesiredSize = -30,
1475 .txEndToXpaOff = 0,
1476 .txEndToRxOn = 0x2,
1477 .txFrameToXpaOn = 0xe,
1478 .thresh62 = 28,
1479 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
1480 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
1481 .futureModal = {
1482 0, 0, 0, 0, 0, 0, 0, 0,
1483 },
1484 },
1485 .base_ext2 = {
1486 .tempSlopeLow = 40,
1487 .tempSlopeHigh = 50,
1488 .xatten1DBLow = {0, 0, 0},
1489 .xatten1MarginLow = {0, 0, 0},
1490 .xatten1DBHigh = {0, 0, 0},
1491 .xatten1MarginHigh = {0, 0, 0}
1492 },
1493 .calFreqPier5G = {
1494 FREQ2FBIN(5180, 0),
1495 FREQ2FBIN(5220, 0),
1496 FREQ2FBIN(5320, 0),
1497 FREQ2FBIN(5400, 0),
1498 FREQ2FBIN(5500, 0),
1499 FREQ2FBIN(5600, 0),
1500 FREQ2FBIN(5700, 0),
1501 FREQ2FBIN(5785, 0)
1502 },
1503 .calPierData5G = {
1504 {
1505 {0, 0, 0, 0, 0},
1506 {0, 0, 0, 0, 0},
1507 {0, 0, 0, 0, 0},
1508 {0, 0, 0, 0, 0},
1509 {0, 0, 0, 0, 0},
1510 {0, 0, 0, 0, 0},
1511 {0, 0, 0, 0, 0},
1512 {0, 0, 0, 0, 0},
1513 },
1514 {
1515 {0, 0, 0, 0, 0},
1516 {0, 0, 0, 0, 0},
1517 {0, 0, 0, 0, 0},
1518 {0, 0, 0, 0, 0},
1519 {0, 0, 0, 0, 0},
1520 {0, 0, 0, 0, 0},
1521 {0, 0, 0, 0, 0},
1522 {0, 0, 0, 0, 0},
1523 },
1524 {
1525 {0, 0, 0, 0, 0},
1526 {0, 0, 0, 0, 0},
1527 {0, 0, 0, 0, 0},
1528 {0, 0, 0, 0, 0},
1529 {0, 0, 0, 0, 0},
1530 {0, 0, 0, 0, 0},
1531 {0, 0, 0, 0, 0},
1532 {0, 0, 0, 0, 0},
1533 },
1534
1535 },
1536 .calTarget_freqbin_5G = {
1537 FREQ2FBIN(5180, 0),
1538 FREQ2FBIN(5240, 0),
1539 FREQ2FBIN(5320, 0),
1540 FREQ2FBIN(5400, 0),
1541 FREQ2FBIN(5500, 0),
1542 FREQ2FBIN(5600, 0),
1543 FREQ2FBIN(5700, 0),
1544 FREQ2FBIN(5825, 0)
1545 },
1546 .calTarget_freqbin_5GHT20 = {
1547 FREQ2FBIN(5180, 0),
1548 FREQ2FBIN(5240, 0),
1549 FREQ2FBIN(5320, 0),
1550 FREQ2FBIN(5400, 0),
1551 FREQ2FBIN(5500, 0),
1552 FREQ2FBIN(5700, 0),
1553 FREQ2FBIN(5745, 0),
1554 FREQ2FBIN(5825, 0)
1555 },
1556 .calTarget_freqbin_5GHT40 = {
1557 FREQ2FBIN(5180, 0),
1558 FREQ2FBIN(5240, 0),
1559 FREQ2FBIN(5320, 0),
1560 FREQ2FBIN(5400, 0),
1561 FREQ2FBIN(5500, 0),
1562 FREQ2FBIN(5700, 0),
1563 FREQ2FBIN(5745, 0),
1564 FREQ2FBIN(5825, 0)
1565 },
1566 .calTargetPower5G = {
1567 /* 6-24,36,48,54 */
1568 { {30, 30, 28, 24} },
1569 { {30, 30, 28, 24} },
1570 { {30, 30, 28, 24} },
1571 { {30, 30, 28, 24} },
1572 { {30, 30, 28, 24} },
1573 { {30, 30, 28, 24} },
1574 { {30, 30, 28, 24} },
1575 { {30, 30, 28, 24} },
1576 },
1577 .calTargetPower5GHT20 = {
1578 /*
1579 * 0_8_16,1-3_9-11_17-19,
1580 * 4,5,6,7,12,13,14,15,20,21,22,23
1581 */
1582 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
1583 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
1584 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
1585 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
1586 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
1587 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
1588 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
1589 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
1590 },
1591 .calTargetPower5GHT40 = {
1592 /*
1593 * 0_8_16,1-3_9-11_17-19,
1594 * 4,5,6,7,12,13,14,15,20,21,22,23
1595 */
1596 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
1597 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
1598 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
1599 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
1600 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
1601 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
1602 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
1603 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
1604 },
1605 .ctlIndex_5G = {
1606 0x10, 0x16, 0x18, 0x40, 0x46,
1607 0x48, 0x30, 0x36, 0x38
1608 },
1609 .ctl_freqbin_5G = {
1610 {
1611 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1612 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1613 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1614 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1615 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
1616 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1617 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1618 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1619 },
1620 {
1621 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1622 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1623 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1624 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1625 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
1626 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1627 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1628 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1629 },
1630
1631 {
1632 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1633 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1634 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1635 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
1636 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
1637 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
1638 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
1639 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
1640 },
1641
1642 {
1643 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1644 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1645 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
1646 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
1647 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1648 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1649 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
1650 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
1651 },
1652
1653 {
1654 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1655 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1656 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
1657 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
1658 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
1659 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
1660 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
1661 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
1662 },
1663
1664 {
1665 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1666 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
1667 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
1668 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1669 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
1670 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1671 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
1672 /* Data[5].ctlEdges[7].bChannel */ 0xFF
1673 },
1674
1675 {
1676 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1677 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1678 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
1679 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
1680 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1681 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
1682 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
1683 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
1684 },
1685
1686 {
1687 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1688 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1689 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
1690 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1691 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
1692 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1693 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1694 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1695 },
1696
1697 {
1698 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1699 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1700 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1701 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1702 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
1703 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1704 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
1705 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
1706 }
1707 },
1708 .ctlPowerData_5G = {
1709 {
1710 {
1711 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1712 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1713 }
1714 },
1715 {
1716 {
1717 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1718 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1719 }
1720 },
1721 {
1722 {
1723 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1724 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1725 }
1726 },
1727 {
1728 {
1729 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1730 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1731 }
1732 },
1733 {
1734 {
1735 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1736 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1737 }
1738 },
1739 {
1740 {
1741 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1742 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1743 }
1744 },
1745 {
1746 {
1747 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1748 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1749 }
1750 },
1751 {
1752 {
1753 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1754 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1755 }
1756 },
1757 {
1758 {
1759 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
1760 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1761 }
1762 },
1763 }
1764 };
1765
1766
1767 static const struct ar9300_eeprom ar9300_x112 = {
1768 .eepromVersion = 2,
1769 .templateVersion = 5,
1770 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
1771 .custData = {"x112-041-f0000"},
1772 .baseEepHeader = {
1773 .regDmn = { LE16(0), LE16(0x1f) },
1774 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
1775 .opCapFlags = {
1776 .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
1777 .eepMisc = 0,
1778 },
1779 .rfSilent = 0,
1780 .blueToothOptions = 0,
1781 .deviceCap = 0,
1782 .deviceType = 5, /* takes lower byte in eeprom location */
1783 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
1784 .params_for_tuning_caps = {0, 0},
1785 .featureEnable = 0x0d,
1786 /*
1787 * bit0 - enable tx temp comp - disabled
1788 * bit1 - enable tx volt comp - disabled
1789 * bit2 - enable fastclock - enabled
1790 * bit3 - enable doubling - enabled
1791 * bit4 - enable internal regulator - disabled
1792 * bit5 - enable pa predistortion - disabled
1793 */
1794 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
1795 .eepromWriteEnableGpio = 6,
1796 .wlanDisableGpio = 0,
1797 .wlanLedGpio = 8,
1798 .rxBandSelectGpio = 0xff,
1799 .txrxgain = 0x0,
1800 .swreg = 0,
1801 },
1802 .modalHeader2G = {
1803 /* ar9300_modal_eep_header 2g */
1804 /* 4 idle,t1,t2,b(4 bits per setting) */
1805 .antCtrlCommon = LE32(0x110),
1806 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
1807 .antCtrlCommon2 = LE32(0x22222),
1808
1809 /*
1810 * antCtrlChain[ar9300_max_chains]; 6 idle, t, r,
1811 * rx1, rx12, b (2 bits each)
1812 */
1813 .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
1814
1815 /*
1816 * xatten1DB[AR9300_max_chains]; 3 xatten1_db
1817 * for ar9280 (0xa20c/b20c 5:0)
1818 */
1819 .xatten1DB = {0x1b, 0x1b, 0x1b},
1820
1821 /*
1822 * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
1823 * for ar9280 (0xa20c/b20c 16:12
1824 */
1825 .xatten1Margin = {0x15, 0x15, 0x15},
1826 .tempSlope = 50,
1827 .voltSlope = 0,
1828
1829 /*
1830 * spurChans[OSPrey_eeprom_modal_sPURS]; spur
1831 * channels in usual fbin coding format
1832 */
1833 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
1834
1835 /*
1836 * noiseFloorThreshch[ar9300_max_cHAINS]; 3 Check
1837 * if the register is per chain
1838 */
1839 .noiseFloorThreshCh = {-1, 0, 0},
1840 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
1841 .quick_drop = 0,
1842 .xpaBiasLvl = 0,
1843 .txFrameToDataStart = 0x0e,
1844 .txFrameToPaOn = 0x0e,
1845 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1846 .antennaGain = 0,
1847 .switchSettling = 0x2c,
1848 .adcDesiredSize = -30,
1849 .txEndToXpaOff = 0,
1850 .txEndToRxOn = 0x2,
1851 .txFrameToXpaOn = 0xe,
1852 .thresh62 = 28,
1853 .papdRateMaskHt20 = LE32(0x0c80c080),
1854 .papdRateMaskHt40 = LE32(0x0080c080),
1855 .futureModal = {
1856 0, 0, 0, 0, 0, 0, 0, 0,
1857 },
1858 },
1859 .base_ext1 = {
1860 .ant_div_control = 0,
1861 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
1862 },
1863 .calFreqPier2G = {
1864 FREQ2FBIN(2412, 1),
1865 FREQ2FBIN(2437, 1),
1866 FREQ2FBIN(2472, 1),
1867 },
1868 /* ar9300_cal_data_per_freq_op_loop 2g */
1869 .calPierData2G = {
1870 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1871 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1872 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1873 },
1874 .calTarget_freqbin_Cck = {
1875 FREQ2FBIN(2412, 1),
1876 FREQ2FBIN(2472, 1),
1877 },
1878 .calTarget_freqbin_2G = {
1879 FREQ2FBIN(2412, 1),
1880 FREQ2FBIN(2437, 1),
1881 FREQ2FBIN(2472, 1)
1882 },
1883 .calTarget_freqbin_2GHT20 = {
1884 FREQ2FBIN(2412, 1),
1885 FREQ2FBIN(2437, 1),
1886 FREQ2FBIN(2472, 1)
1887 },
1888 .calTarget_freqbin_2GHT40 = {
1889 FREQ2FBIN(2412, 1),
1890 FREQ2FBIN(2437, 1),
1891 FREQ2FBIN(2472, 1)
1892 },
1893 .calTargetPowerCck = {
1894 /* 1L-5L,5S,11L,11s */
1895 { {38, 38, 38, 38} },
1896 { {38, 38, 38, 38} },
1897 },
1898 .calTargetPower2G = {
1899 /* 6-24,36,48,54 */
1900 { {38, 38, 36, 34} },
1901 { {38, 38, 36, 34} },
1902 { {38, 38, 34, 32} },
1903 },
1904 .calTargetPower2GHT20 = {
1905 { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
1906 { {36, 36, 36, 36, 36, 34, 36, 34, 32, 30, 30, 30, 28, 26} },
1907 { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
1908 },
1909 .calTargetPower2GHT40 = {
1910 { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
1911 { {36, 36, 36, 36, 34, 32, 34, 32, 30, 28, 28, 28, 28, 24} },
1912 { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
1913 },
1914 .ctlIndex_2G = {
1915 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
1916 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
1917 },
1918 .ctl_freqbin_2G = {
1919 {
1920 FREQ2FBIN(2412, 1),
1921 FREQ2FBIN(2417, 1),
1922 FREQ2FBIN(2457, 1),
1923 FREQ2FBIN(2462, 1)
1924 },
1925 {
1926 FREQ2FBIN(2412, 1),
1927 FREQ2FBIN(2417, 1),
1928 FREQ2FBIN(2462, 1),
1929 0xFF,
1930 },
1931
1932 {
1933 FREQ2FBIN(2412, 1),
1934 FREQ2FBIN(2417, 1),
1935 FREQ2FBIN(2462, 1),
1936 0xFF,
1937 },
1938 {
1939 FREQ2FBIN(2422, 1),
1940 FREQ2FBIN(2427, 1),
1941 FREQ2FBIN(2447, 1),
1942 FREQ2FBIN(2452, 1)
1943 },
1944
1945 {
1946 /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1947 /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1948 /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1949 /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(2484, 1),
1950 },
1951
1952 {
1953 /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1954 /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1955 /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1956 0,
1957 },
1958
1959 {
1960 /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1961 /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1962 FREQ2FBIN(2472, 1),
1963 0,
1964 },
1965
1966 {
1967 /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
1968 /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
1969 /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
1970 /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
1971 },
1972
1973 {
1974 /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1975 /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1976 /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1977 },
1978
1979 {
1980 /* Data[9].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1981 /* Data[9].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1982 /* Data[9].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1983 0
1984 },
1985
1986 {
1987 /* Data[10].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1988 /* Data[10].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1989 /* Data[10].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1990 0
1991 },
1992
1993 {
1994 /* Data[11].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
1995 /* Data[11].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
1996 /* Data[11].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
1997 /* Data[11].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
1998 }
1999 },
2000 .ctlPowerData_2G = {
2001 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2002 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2003 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
2004
2005 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
2006 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2007 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2008
2009 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
2010 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2011 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2012
2013 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2014 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2015 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2016 },
2017 .modalHeader5G = {
2018 /* 4 idle,t1,t2,b (4 bits per setting) */
2019 .antCtrlCommon = LE32(0x110),
2020 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
2021 .antCtrlCommon2 = LE32(0x22222),
2022 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
2023 .antCtrlChain = {
2024 LE16(0x0), LE16(0x0), LE16(0x0),
2025 },
2026 /* xatten1DB 3 xatten1_db for ar9280 (0xa20c/b20c 5:0) */
2027 .xatten1DB = {0x13, 0x19, 0x17},
2028
2029 /*
2030 * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
2031 * for merlin (0xa20c/b20c 16:12
2032 */
2033 .xatten1Margin = {0x19, 0x19, 0x19},
2034 .tempSlope = 70,
2035 .voltSlope = 15,
2036 /* spurChans spur channels in usual fbin coding format */
2037 .spurChans = {0, 0, 0, 0, 0},
2038 /* noiseFloorThreshch check if the register is per chain */
2039 .noiseFloorThreshCh = {-1, 0, 0},
2040 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
2041 .quick_drop = 0,
2042 .xpaBiasLvl = 0,
2043 .txFrameToDataStart = 0x0e,
2044 .txFrameToPaOn = 0x0e,
2045 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2046 .antennaGain = 0,
2047 .switchSettling = 0x2d,
2048 .adcDesiredSize = -30,
2049 .txEndToXpaOff = 0,
2050 .txEndToRxOn = 0x2,
2051 .txFrameToXpaOn = 0xe,
2052 .thresh62 = 28,
2053 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
2054 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
2055 .futureModal = {
2056 0, 0, 0, 0, 0, 0, 0, 0,
2057 },
2058 },
2059 .base_ext2 = {
2060 .tempSlopeLow = 72,
2061 .tempSlopeHigh = 105,
2062 .xatten1DBLow = {0x10, 0x14, 0x10},
2063 .xatten1MarginLow = {0x19, 0x19 , 0x19},
2064 .xatten1DBHigh = {0x1d, 0x20, 0x24},
2065 .xatten1MarginHigh = {0x10, 0x10, 0x10}
2066 },
2067 .calFreqPier5G = {
2068 FREQ2FBIN(5180, 0),
2069 FREQ2FBIN(5220, 0),
2070 FREQ2FBIN(5320, 0),
2071 FREQ2FBIN(5400, 0),
2072 FREQ2FBIN(5500, 0),
2073 FREQ2FBIN(5600, 0),
2074 FREQ2FBIN(5700, 0),
2075 FREQ2FBIN(5785, 0)
2076 },
2077 .calPierData5G = {
2078 {
2079 {0, 0, 0, 0, 0},
2080 {0, 0, 0, 0, 0},
2081 {0, 0, 0, 0, 0},
2082 {0, 0, 0, 0, 0},
2083 {0, 0, 0, 0, 0},
2084 {0, 0, 0, 0, 0},
2085 {0, 0, 0, 0, 0},
2086 {0, 0, 0, 0, 0},
2087 },
2088 {
2089 {0, 0, 0, 0, 0},
2090 {0, 0, 0, 0, 0},
2091 {0, 0, 0, 0, 0},
2092 {0, 0, 0, 0, 0},
2093 {0, 0, 0, 0, 0},
2094 {0, 0, 0, 0, 0},
2095 {0, 0, 0, 0, 0},
2096 {0, 0, 0, 0, 0},
2097 },
2098 {
2099 {0, 0, 0, 0, 0},
2100 {0, 0, 0, 0, 0},
2101 {0, 0, 0, 0, 0},
2102 {0, 0, 0, 0, 0},
2103 {0, 0, 0, 0, 0},
2104 {0, 0, 0, 0, 0},
2105 {0, 0, 0, 0, 0},
2106 {0, 0, 0, 0, 0},
2107 },
2108
2109 },
2110 .calTarget_freqbin_5G = {
2111 FREQ2FBIN(5180, 0),
2112 FREQ2FBIN(5220, 0),
2113 FREQ2FBIN(5320, 0),
2114 FREQ2FBIN(5400, 0),
2115 FREQ2FBIN(5500, 0),
2116 FREQ2FBIN(5600, 0),
2117 FREQ2FBIN(5725, 0),
2118 FREQ2FBIN(5825, 0)
2119 },
2120 .calTarget_freqbin_5GHT20 = {
2121 FREQ2FBIN(5180, 0),
2122 FREQ2FBIN(5220, 0),
2123 FREQ2FBIN(5320, 0),
2124 FREQ2FBIN(5400, 0),
2125 FREQ2FBIN(5500, 0),
2126 FREQ2FBIN(5600, 0),
2127 FREQ2FBIN(5725, 0),
2128 FREQ2FBIN(5825, 0)
2129 },
2130 .calTarget_freqbin_5GHT40 = {
2131 FREQ2FBIN(5180, 0),
2132 FREQ2FBIN(5220, 0),
2133 FREQ2FBIN(5320, 0),
2134 FREQ2FBIN(5400, 0),
2135 FREQ2FBIN(5500, 0),
2136 FREQ2FBIN(5600, 0),
2137 FREQ2FBIN(5725, 0),
2138 FREQ2FBIN(5825, 0)
2139 },
2140 .calTargetPower5G = {
2141 /* 6-24,36,48,54 */
2142 { {32, 32, 28, 26} },
2143 { {32, 32, 28, 26} },
2144 { {32, 32, 28, 26} },
2145 { {32, 32, 26, 24} },
2146 { {32, 32, 26, 24} },
2147 { {32, 32, 24, 22} },
2148 { {30, 30, 24, 22} },
2149 { {30, 30, 24, 22} },
2150 },
2151 .calTargetPower5GHT20 = {
2152 /*
2153 * 0_8_16,1-3_9-11_17-19,
2154 * 4,5,6,7,12,13,14,15,20,21,22,23
2155 */
2156 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2157 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2158 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2159 { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 22, 22, 20, 20} },
2160 { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 20, 18, 16, 16} },
2161 { {32, 32, 32, 32, 28, 26, 32, 24, 20, 16, 18, 16, 14, 14} },
2162 { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
2163 { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
2164 },
2165 .calTargetPower5GHT40 = {
2166 /*
2167 * 0_8_16,1-3_9-11_17-19,
2168 * 4,5,6,7,12,13,14,15,20,21,22,23
2169 */
2170 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2171 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2172 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2173 { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 22, 22, 20, 20} },
2174 { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 20, 18, 16, 16} },
2175 { {32, 32, 32, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2176 { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2177 { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2178 },
2179 .ctlIndex_5G = {
2180 0x10, 0x16, 0x18, 0x40, 0x46,
2181 0x48, 0x30, 0x36, 0x38
2182 },
2183 .ctl_freqbin_5G = {
2184 {
2185 /* Data[0].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2186 /* Data[0].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2187 /* Data[0].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
2188 /* Data[0].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2189 /* Data[0].ctledges[4].bchannel */ FREQ2FBIN(5600, 0),
2190 /* Data[0].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2191 /* Data[0].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2192 /* Data[0].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2193 },
2194 {
2195 /* Data[1].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2196 /* Data[1].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2197 /* Data[1].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
2198 /* Data[1].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2199 /* Data[1].ctledges[4].bchannel */ FREQ2FBIN(5520, 0),
2200 /* Data[1].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2201 /* Data[1].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2202 /* Data[1].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2203 },
2204
2205 {
2206 /* Data[2].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2207 /* Data[2].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
2208 /* Data[2].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
2209 /* Data[2].ctledges[3].bchannel */ FREQ2FBIN(5310, 0),
2210 /* Data[2].ctledges[4].bchannel */ FREQ2FBIN(5510, 0),
2211 /* Data[2].ctledges[5].bchannel */ FREQ2FBIN(5550, 0),
2212 /* Data[2].ctledges[6].bchannel */ FREQ2FBIN(5670, 0),
2213 /* Data[2].ctledges[7].bchannel */ FREQ2FBIN(5755, 0)
2214 },
2215
2216 {
2217 /* Data[3].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2218 /* Data[3].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
2219 /* Data[3].ctledges[2].bchannel */ FREQ2FBIN(5260, 0),
2220 /* Data[3].ctledges[3].bchannel */ FREQ2FBIN(5320, 0),
2221 /* Data[3].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
2222 /* Data[3].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2223 /* Data[3].ctledges[6].bchannel */ 0xFF,
2224 /* Data[3].ctledges[7].bchannel */ 0xFF,
2225 },
2226
2227 {
2228 /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2229 /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2230 /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(5500, 0),
2231 /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(5700, 0),
2232 /* Data[4].ctledges[4].bchannel */ 0xFF,
2233 /* Data[4].ctledges[5].bchannel */ 0xFF,
2234 /* Data[4].ctledges[6].bchannel */ 0xFF,
2235 /* Data[4].ctledges[7].bchannel */ 0xFF,
2236 },
2237
2238 {
2239 /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2240 /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(5270, 0),
2241 /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(5310, 0),
2242 /* Data[5].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
2243 /* Data[5].ctledges[4].bchannel */ FREQ2FBIN(5590, 0),
2244 /* Data[5].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
2245 /* Data[5].ctledges[6].bchannel */ 0xFF,
2246 /* Data[5].ctledges[7].bchannel */ 0xFF
2247 },
2248
2249 {
2250 /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2251 /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
2252 /* Data[6].ctledges[2].bchannel */ FREQ2FBIN(5220, 0),
2253 /* Data[6].ctledges[3].bchannel */ FREQ2FBIN(5260, 0),
2254 /* Data[6].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
2255 /* Data[6].ctledges[5].bchannel */ FREQ2FBIN(5600, 0),
2256 /* Data[6].ctledges[6].bchannel */ FREQ2FBIN(5700, 0),
2257 /* Data[6].ctledges[7].bchannel */ FREQ2FBIN(5745, 0)
2258 },
2259
2260 {
2261 /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2262 /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2263 /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(5320, 0),
2264 /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2265 /* Data[7].ctledges[4].bchannel */ FREQ2FBIN(5560, 0),
2266 /* Data[7].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2267 /* Data[7].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2268 /* Data[7].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2269 },
2270
2271 {
2272 /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2273 /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
2274 /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
2275 /* Data[8].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
2276 /* Data[8].ctledges[4].bchannel */ FREQ2FBIN(5550, 0),
2277 /* Data[8].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
2278 /* Data[8].ctledges[6].bchannel */ FREQ2FBIN(5755, 0),
2279 /* Data[8].ctledges[7].bchannel */ FREQ2FBIN(5795, 0)
2280 }
2281 },
2282 .ctlPowerData_5G = {
2283 {
2284 {
2285 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2286 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2287 }
2288 },
2289 {
2290 {
2291 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2292 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2293 }
2294 },
2295 {
2296 {
2297 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2298 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2299 }
2300 },
2301 {
2302 {
2303 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2304 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2305 }
2306 },
2307 {
2308 {
2309 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2310 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2311 }
2312 },
2313 {
2314 {
2315 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2316 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2317 }
2318 },
2319 {
2320 {
2321 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2322 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2323 }
2324 },
2325 {
2326 {
2327 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2328 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2329 }
2330 },
2331 {
2332 {
2333 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
2334 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2335 }
2336 },
2337 }
2338 };
2339
2340 static const struct ar9300_eeprom ar9300_h116 = {
2341 .eepromVersion = 2,
2342 .templateVersion = 4,
2343 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
2344 .custData = {"h116-041-f0000"},
2345 .baseEepHeader = {
2346 .regDmn = { LE16(0), LE16(0x1f) },
2347 .txrxMask = 0x33, /* 4 bits tx and 4 bits rx */
2348 .opCapFlags = {
2349 .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
2350 .eepMisc = 0,
2351 },
2352 .rfSilent = 0,
2353 .blueToothOptions = 0,
2354 .deviceCap = 0,
2355 .deviceType = 5, /* takes lower byte in eeprom location */
2356 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
2357 .params_for_tuning_caps = {0, 0},
2358 .featureEnable = 0x0d,
2359 /*
2360 * bit0 - enable tx temp comp - disabled
2361 * bit1 - enable tx volt comp - disabled
2362 * bit2 - enable fastClock - enabled
2363 * bit3 - enable doubling - enabled
2364 * bit4 - enable internal regulator - disabled
2365 * bit5 - enable pa predistortion - disabled
2366 */
2367 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
2368 .eepromWriteEnableGpio = 6,
2369 .wlanDisableGpio = 0,
2370 .wlanLedGpio = 8,
2371 .rxBandSelectGpio = 0xff,
2372 .txrxgain = 0x10,
2373 .swreg = 0,
2374 },
2375 .modalHeader2G = {
2376 /* ar9300_modal_eep_header 2g */
2377 /* 4 idle,t1,t2,b(4 bits per setting) */
2378 .antCtrlCommon = LE32(0x110),
2379 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
2380 .antCtrlCommon2 = LE32(0x44444),
2381
2382 /*
2383 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
2384 * rx1, rx12, b (2 bits each)
2385 */
2386 .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
2387
2388 /*
2389 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
2390 * for ar9280 (0xa20c/b20c 5:0)
2391 */
2392 .xatten1DB = {0x1f, 0x1f, 0x1f},
2393
2394 /*
2395 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
2396 * for ar9280 (0xa20c/b20c 16:12
2397 */
2398 .xatten1Margin = {0x12, 0x12, 0x12},
2399 .tempSlope = 25,
2400 .voltSlope = 0,
2401
2402 /*
2403 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
2404 * channels in usual fbin coding format
2405 */
2406 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
2407
2408 /*
2409 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
2410 * if the register is per chain
2411 */
2412 .noiseFloorThreshCh = {-1, 0, 0},
2413 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
2414 .quick_drop = 0,
2415 .xpaBiasLvl = 0,
2416 .txFrameToDataStart = 0x0e,
2417 .txFrameToPaOn = 0x0e,
2418 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2419 .antennaGain = 0,
2420 .switchSettling = 0x2c,
2421 .adcDesiredSize = -30,
2422 .txEndToXpaOff = 0,
2423 .txEndToRxOn = 0x2,
2424 .txFrameToXpaOn = 0xe,
2425 .thresh62 = 28,
2426 .papdRateMaskHt20 = LE32(0x0c80C080),
2427 .papdRateMaskHt40 = LE32(0x0080C080),
2428 .futureModal = {
2429 0, 0, 0, 0, 0, 0, 0, 0,
2430 },
2431 },
2432 .base_ext1 = {
2433 .ant_div_control = 0,
2434 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
2435 },
2436 .calFreqPier2G = {
2437 FREQ2FBIN(2412, 1),
2438 FREQ2FBIN(2437, 1),
2439 FREQ2FBIN(2462, 1),
2440 },
2441 /* ar9300_cal_data_per_freq_op_loop 2g */
2442 .calPierData2G = {
2443 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2444 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2445 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2446 },
2447 .calTarget_freqbin_Cck = {
2448 FREQ2FBIN(2412, 1),
2449 FREQ2FBIN(2472, 1),
2450 },
2451 .calTarget_freqbin_2G = {
2452 FREQ2FBIN(2412, 1),
2453 FREQ2FBIN(2437, 1),
2454 FREQ2FBIN(2472, 1)
2455 },
2456 .calTarget_freqbin_2GHT20 = {
2457 FREQ2FBIN(2412, 1),
2458 FREQ2FBIN(2437, 1),
2459 FREQ2FBIN(2472, 1)
2460 },
2461 .calTarget_freqbin_2GHT40 = {
2462 FREQ2FBIN(2412, 1),
2463 FREQ2FBIN(2437, 1),
2464 FREQ2FBIN(2472, 1)
2465 },
2466 .calTargetPowerCck = {
2467 /* 1L-5L,5S,11L,11S */
2468 { {34, 34, 34, 34} },
2469 { {34, 34, 34, 34} },
2470 },
2471 .calTargetPower2G = {
2472 /* 6-24,36,48,54 */
2473 { {34, 34, 32, 32} },
2474 { {34, 34, 32, 32} },
2475 { {34, 34, 32, 32} },
2476 },
2477 .calTargetPower2GHT20 = {
2478 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2479 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2480 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2481 },
2482 .calTargetPower2GHT40 = {
2483 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2484 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2485 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2486 },
2487 .ctlIndex_2G = {
2488 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
2489 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
2490 },
2491 .ctl_freqbin_2G = {
2492 {
2493 FREQ2FBIN(2412, 1),
2494 FREQ2FBIN(2417, 1),
2495 FREQ2FBIN(2457, 1),
2496 FREQ2FBIN(2462, 1)
2497 },
2498 {
2499 FREQ2FBIN(2412, 1),
2500 FREQ2FBIN(2417, 1),
2501 FREQ2FBIN(2462, 1),
2502 0xFF,
2503 },
2504
2505 {
2506 FREQ2FBIN(2412, 1),
2507 FREQ2FBIN(2417, 1),
2508 FREQ2FBIN(2462, 1),
2509 0xFF,
2510 },
2511 {
2512 FREQ2FBIN(2422, 1),
2513 FREQ2FBIN(2427, 1),
2514 FREQ2FBIN(2447, 1),
2515 FREQ2FBIN(2452, 1)
2516 },
2517
2518 {
2519 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2520 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2521 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2522 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
2523 },
2524
2525 {
2526 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2527 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2528 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2529 0,
2530 },
2531
2532 {
2533 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2534 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2535 FREQ2FBIN(2472, 1),
2536 0,
2537 },
2538
2539 {
2540 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
2541 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
2542 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
2543 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
2544 },
2545
2546 {
2547 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2548 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2549 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2550 },
2551
2552 {
2553 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2554 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2555 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2556 0
2557 },
2558
2559 {
2560 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2561 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2562 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2563 0
2564 },
2565
2566 {
2567 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
2568 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
2569 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
2570 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
2571 }
2572 },
2573 .ctlPowerData_2G = {
2574 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2575 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2576 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
2577
2578 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
2579 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2580 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2581
2582 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
2583 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2584 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2585
2586 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2587 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2588 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2589 },
2590 .modalHeader5G = {
2591 /* 4 idle,t1,t2,b (4 bits per setting) */
2592 .antCtrlCommon = LE32(0x220),
2593 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
2594 .antCtrlCommon2 = LE32(0x44444),
2595 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
2596 .antCtrlChain = {
2597 LE16(0x150), LE16(0x150), LE16(0x150),
2598 },
2599 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
2600 .xatten1DB = {0x19, 0x19, 0x19},
2601
2602 /*
2603 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
2604 * for merlin (0xa20c/b20c 16:12
2605 */
2606 .xatten1Margin = {0x14, 0x14, 0x14},
2607 .tempSlope = 70,
2608 .voltSlope = 0,
2609 /* spurChans spur channels in usual fbin coding format */
2610 .spurChans = {0, 0, 0, 0, 0},
2611 /* noiseFloorThreshCh Check if the register is per chain */
2612 .noiseFloorThreshCh = {-1, 0, 0},
2613 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
2614 .quick_drop = 0,
2615 .xpaBiasLvl = 0,
2616 .txFrameToDataStart = 0x0e,
2617 .txFrameToPaOn = 0x0e,
2618 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2619 .antennaGain = 0,
2620 .switchSettling = 0x2d,
2621 .adcDesiredSize = -30,
2622 .txEndToXpaOff = 0,
2623 .txEndToRxOn = 0x2,
2624 .txFrameToXpaOn = 0xe,
2625 .thresh62 = 28,
2626 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
2627 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
2628 .futureModal = {
2629 0, 0, 0, 0, 0, 0, 0, 0,
2630 },
2631 },
2632 .base_ext2 = {
2633 .tempSlopeLow = 35,
2634 .tempSlopeHigh = 50,
2635 .xatten1DBLow = {0, 0, 0},
2636 .xatten1MarginLow = {0, 0, 0},
2637 .xatten1DBHigh = {0, 0, 0},
2638 .xatten1MarginHigh = {0, 0, 0}
2639 },
2640 .calFreqPier5G = {
2641 FREQ2FBIN(5160, 0),
2642 FREQ2FBIN(5220, 0),
2643 FREQ2FBIN(5320, 0),
2644 FREQ2FBIN(5400, 0),
2645 FREQ2FBIN(5500, 0),
2646 FREQ2FBIN(5600, 0),
2647 FREQ2FBIN(5700, 0),
2648 FREQ2FBIN(5785, 0)
2649 },
2650 .calPierData5G = {
2651 {
2652 {0, 0, 0, 0, 0},
2653 {0, 0, 0, 0, 0},
2654 {0, 0, 0, 0, 0},
2655 {0, 0, 0, 0, 0},
2656 {0, 0, 0, 0, 0},
2657 {0, 0, 0, 0, 0},
2658 {0, 0, 0, 0, 0},
2659 {0, 0, 0, 0, 0},
2660 },
2661 {
2662 {0, 0, 0, 0, 0},
2663 {0, 0, 0, 0, 0},
2664 {0, 0, 0, 0, 0},
2665 {0, 0, 0, 0, 0},
2666 {0, 0, 0, 0, 0},
2667 {0, 0, 0, 0, 0},
2668 {0, 0, 0, 0, 0},
2669 {0, 0, 0, 0, 0},
2670 },
2671 {
2672 {0, 0, 0, 0, 0},
2673 {0, 0, 0, 0, 0},
2674 {0, 0, 0, 0, 0},
2675 {0, 0, 0, 0, 0},
2676 {0, 0, 0, 0, 0},
2677 {0, 0, 0, 0, 0},
2678 {0, 0, 0, 0, 0},
2679 {0, 0, 0, 0, 0},
2680 },
2681
2682 },
2683 .calTarget_freqbin_5G = {
2684 FREQ2FBIN(5180, 0),
2685 FREQ2FBIN(5240, 0),
2686 FREQ2FBIN(5320, 0),
2687 FREQ2FBIN(5400, 0),
2688 FREQ2FBIN(5500, 0),
2689 FREQ2FBIN(5600, 0),
2690 FREQ2FBIN(5700, 0),
2691 FREQ2FBIN(5825, 0)
2692 },
2693 .calTarget_freqbin_5GHT20 = {
2694 FREQ2FBIN(5180, 0),
2695 FREQ2FBIN(5240, 0),
2696 FREQ2FBIN(5320, 0),
2697 FREQ2FBIN(5400, 0),
2698 FREQ2FBIN(5500, 0),
2699 FREQ2FBIN(5700, 0),
2700 FREQ2FBIN(5745, 0),
2701 FREQ2FBIN(5825, 0)
2702 },
2703 .calTarget_freqbin_5GHT40 = {
2704 FREQ2FBIN(5180, 0),
2705 FREQ2FBIN(5240, 0),
2706 FREQ2FBIN(5320, 0),
2707 FREQ2FBIN(5400, 0),
2708 FREQ2FBIN(5500, 0),
2709 FREQ2FBIN(5700, 0),
2710 FREQ2FBIN(5745, 0),
2711 FREQ2FBIN(5825, 0)
2712 },
2713 .calTargetPower5G = {
2714 /* 6-24,36,48,54 */
2715 { {30, 30, 28, 24} },
2716 { {30, 30, 28, 24} },
2717 { {30, 30, 28, 24} },
2718 { {30, 30, 28, 24} },
2719 { {30, 30, 28, 24} },
2720 { {30, 30, 28, 24} },
2721 { {30, 30, 28, 24} },
2722 { {30, 30, 28, 24} },
2723 },
2724 .calTargetPower5GHT20 = {
2725 /*
2726 * 0_8_16,1-3_9-11_17-19,
2727 * 4,5,6,7,12,13,14,15,20,21,22,23
2728 */
2729 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
2730 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
2731 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
2732 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
2733 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
2734 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
2735 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
2736 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
2737 },
2738 .calTargetPower5GHT40 = {
2739 /*
2740 * 0_8_16,1-3_9-11_17-19,
2741 * 4,5,6,7,12,13,14,15,20,21,22,23
2742 */
2743 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
2744 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
2745 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
2746 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
2747 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
2748 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
2749 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
2750 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
2751 },
2752 .ctlIndex_5G = {
2753 0x10, 0x16, 0x18, 0x40, 0x46,
2754 0x48, 0x30, 0x36, 0x38
2755 },
2756 .ctl_freqbin_5G = {
2757 {
2758 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2759 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2760 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
2761 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2762 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
2763 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2764 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2765 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2766 },
2767 {
2768 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2769 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2770 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
2771 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2772 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
2773 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2774 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2775 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2776 },
2777
2778 {
2779 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2780 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
2781 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
2782 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
2783 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
2784 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
2785 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
2786 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
2787 },
2788
2789 {
2790 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2791 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
2792 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
2793 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
2794 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
2795 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2796 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
2797 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
2798 },
2799
2800 {
2801 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2802 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2803 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
2804 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
2805 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
2806 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
2807 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
2808 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
2809 },
2810
2811 {
2812 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2813 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
2814 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
2815 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
2816 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
2817 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
2818 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
2819 /* Data[5].ctlEdges[7].bChannel */ 0xFF
2820 },
2821
2822 {
2823 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2824 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
2825 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
2826 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
2827 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
2828 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
2829 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
2830 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
2831 },
2832
2833 {
2834 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2835 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2836 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
2837 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2838 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
2839 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2840 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2841 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2842 },
2843
2844 {
2845 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2846 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
2847 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
2848 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
2849 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
2850 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
2851 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
2852 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
2853 }
2854 },
2855 .ctlPowerData_5G = {
2856 {
2857 {
2858 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2859 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2860 }
2861 },
2862 {
2863 {
2864 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2865 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2866 }
2867 },
2868 {
2869 {
2870 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2871 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2872 }
2873 },
2874 {
2875 {
2876 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2877 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2878 }
2879 },
2880 {
2881 {
2882 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2883 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2884 }
2885 },
2886 {
2887 {
2888 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2889 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2890 }
2891 },
2892 {
2893 {
2894 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2895 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2896 }
2897 },
2898 {
2899 {
2900 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2901 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2902 }
2903 },
2904 {
2905 {
2906 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
2907 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2908 }
2909 },
2910 }
2911 };
2912
2913
2914 static const struct ar9300_eeprom *ar9300_eep_templates[] = {
2915 &ar9300_default,
2916 &ar9300_x112,
2917 &ar9300_h116,
2918 &ar9300_h112,
2919 &ar9300_x113,
2920 };
2921
2922 static const struct ar9300_eeprom *ar9003_eeprom_struct_find_by_id(int id)
2923 {
2924 #define N_LOOP (sizeof(ar9300_eep_templates) / sizeof(ar9300_eep_templates[0]))
2925 int it;
2926
2927 for (it = 0; it < N_LOOP; it++)
2928 if (ar9300_eep_templates[it]->templateVersion == id)
2929 return ar9300_eep_templates[it];
2930 return NULL;
2931 #undef N_LOOP
2932 }
2933
2934 static int ath9k_hw_ar9300_check_eeprom(struct ath_hw *ah)
2935 {
2936 return 0;
2937 }
2938
2939 static int interpolate(int x, int xa, int xb, int ya, int yb)
2940 {
2941 int bf, factor, plus;
2942
2943 bf = 2 * (yb - ya) * (x - xa) / (xb - xa);
2944 factor = bf / 2;
2945 plus = bf % 2;
2946 return ya + factor + plus;
2947 }
2948
2949 static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah,
2950 enum eeprom_param param)
2951 {
2952 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
2953 struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
2954
2955 switch (param) {
2956 case EEP_MAC_LSW:
2957 return get_unaligned_be16(eep->macAddr);
2958 case EEP_MAC_MID:
2959 return get_unaligned_be16(eep->macAddr + 2);
2960 case EEP_MAC_MSW:
2961 return get_unaligned_be16(eep->macAddr + 4);
2962 case EEP_REG_0:
2963 return le16_to_cpu(pBase->regDmn[0]);
2964 case EEP_OP_CAP:
2965 return pBase->deviceCap;
2966 case EEP_OP_MODE:
2967 return pBase->opCapFlags.opFlags;
2968 case EEP_RF_SILENT:
2969 return pBase->rfSilent;
2970 case EEP_TX_MASK:
2971 return (pBase->txrxMask >> 4) & 0xf;
2972 case EEP_RX_MASK:
2973 return pBase->txrxMask & 0xf;
2974 case EEP_DRIVE_STRENGTH:
2975 #define AR9300_EEP_BASE_DRIV_STRENGTH 0x1
2976 return pBase->miscConfiguration & AR9300_EEP_BASE_DRIV_STRENGTH;
2977 case EEP_INTERNAL_REGULATOR:
2978 /* Bit 4 is internal regulator flag */
2979 return (pBase->featureEnable & 0x10) >> 4;
2980 case EEP_SWREG:
2981 return le32_to_cpu(pBase->swreg);
2982 case EEP_PAPRD:
2983 return !!(pBase->featureEnable & BIT(5));
2984 case EEP_CHAIN_MASK_REDUCE:
2985 return (pBase->miscConfiguration >> 0x3) & 0x1;
2986 case EEP_ANT_DIV_CTL1:
2987 return eep->base_ext1.ant_div_control;
2988 case EEP_ANTENNA_GAIN_5G:
2989 return eep->modalHeader5G.antennaGain;
2990 case EEP_ANTENNA_GAIN_2G:
2991 return eep->modalHeader2G.antennaGain;
2992 case EEP_QUICK_DROP:
2993 return pBase->miscConfiguration & BIT(1);
2994 default:
2995 return 0;
2996 }
2997 }
2998
2999 static bool ar9300_eeprom_read_byte(struct ath_common *common, int address,
3000 u8 *buffer)
3001 {
3002 u16 val;
3003
3004 if (unlikely(!ath9k_hw_nvram_read(common, address / 2, &val)))
3005 return false;
3006
3007 *buffer = (val >> (8 * (address % 2))) & 0xff;
3008 return true;
3009 }
3010
3011 static bool ar9300_eeprom_read_word(struct ath_common *common, int address,
3012 u8 *buffer)
3013 {
3014 u16 val;
3015
3016 if (unlikely(!ath9k_hw_nvram_read(common, address / 2, &val)))
3017 return false;
3018
3019 buffer[0] = val >> 8;
3020 buffer[1] = val & 0xff;
3021
3022 return true;
3023 }
3024
3025 static bool ar9300_read_eeprom(struct ath_hw *ah, int address, u8 *buffer,
3026 int count)
3027 {
3028 struct ath_common *common = ath9k_hw_common(ah);
3029 int i;
3030
3031 if ((address < 0) || ((address + count) / 2 > AR9300_EEPROM_SIZE - 1)) {
3032 ath_dbg(common, EEPROM, "eeprom address not in range\n");
3033 return false;
3034 }
3035
3036 /*
3037 * Since we're reading the bytes in reverse order from a little-endian
3038 * word stream, an even address means we only use the lower half of
3039 * the 16-bit word at that address
3040 */
3041 if (address % 2 == 0) {
3042 if (!ar9300_eeprom_read_byte(common, address--, buffer++))
3043 goto error;
3044
3045 count--;
3046 }
3047
3048 for (i = 0; i < count / 2; i++) {
3049 if (!ar9300_eeprom_read_word(common, address, buffer))
3050 goto error;
3051
3052 address -= 2;
3053 buffer += 2;
3054 }
3055
3056 if (count % 2)
3057 if (!ar9300_eeprom_read_byte(common, address, buffer))
3058 goto error;
3059
3060 return true;
3061
3062 error:
3063 ath_dbg(common, EEPROM, "unable to read eeprom region at offset %d\n",
3064 address);
3065 return false;
3066 }
3067
3068 static bool ar9300_otp_read_word(struct ath_hw *ah, int addr, u32 *data)
3069 {
3070 REG_READ(ah, AR9300_OTP_BASE + (4 * addr));
3071
3072 if (!ath9k_hw_wait(ah, AR9300_OTP_STATUS, AR9300_OTP_STATUS_TYPE,
3073 AR9300_OTP_STATUS_VALID, 1000))
3074 return false;
3075
3076 *data = REG_READ(ah, AR9300_OTP_READ_DATA);
3077 return true;
3078 }
3079
3080 static bool ar9300_read_otp(struct ath_hw *ah, int address, u8 *buffer,
3081 int count)
3082 {
3083 u32 data;
3084 int i;
3085
3086 for (i = 0; i < count; i++) {
3087 int offset = 8 * ((address - i) % 4);
3088 if (!ar9300_otp_read_word(ah, (address - i) / 4, &data))
3089 return false;
3090
3091 buffer[i] = (data >> offset) & 0xff;
3092 }
3093
3094 return true;
3095 }
3096
3097
3098 static void ar9300_comp_hdr_unpack(u8 *best, int *code, int *reference,
3099 int *length, int *major, int *minor)
3100 {
3101 unsigned long value[4];
3102
3103 value[0] = best[0];
3104 value[1] = best[1];
3105 value[2] = best[2];
3106 value[3] = best[3];
3107 *code = ((value[0] >> 5) & 0x0007);
3108 *reference = (value[0] & 0x001f) | ((value[1] >> 2) & 0x0020);
3109 *length = ((value[1] << 4) & 0x07f0) | ((value[2] >> 4) & 0x000f);
3110 *major = (value[2] & 0x000f);
3111 *minor = (value[3] & 0x00ff);
3112 }
3113
3114 static u16 ar9300_comp_cksum(u8 *data, int dsize)
3115 {
3116 int it, checksum = 0;
3117
3118 for (it = 0; it < dsize; it++) {
3119 checksum += data[it];
3120 checksum &= 0xffff;
3121 }
3122
3123 return checksum;
3124 }
3125
3126 static bool ar9300_uncompress_block(struct ath_hw *ah,
3127 u8 *mptr,
3128 int mdataSize,
3129 u8 *block,
3130 int size)
3131 {
3132 int it;
3133 int spot;
3134 int offset;
3135 int length;
3136 struct ath_common *common = ath9k_hw_common(ah);
3137
3138 spot = 0;
3139
3140 for (it = 0; it < size; it += (length+2)) {
3141 offset = block[it];
3142 offset &= 0xff;
3143 spot += offset;
3144 length = block[it+1];
3145 length &= 0xff;
3146
3147 if (length > 0 && spot >= 0 && spot+length <= mdataSize) {
3148 ath_dbg(common, EEPROM,
3149 "Restore at %d: spot=%d offset=%d length=%d\n",
3150 it, spot, offset, length);
3151 memcpy(&mptr[spot], &block[it+2], length);
3152 spot += length;
3153 } else if (length > 0) {
3154 ath_dbg(common, EEPROM,
3155 "Bad restore at %d: spot=%d offset=%d length=%d\n",
3156 it, spot, offset, length);
3157 return false;
3158 }
3159 }
3160 return true;
3161 }
3162
3163 static int ar9300_compress_decision(struct ath_hw *ah,
3164 int it,
3165 int code,
3166 int reference,
3167 u8 *mptr,
3168 u8 *word, int length, int mdata_size)
3169 {
3170 struct ath_common *common = ath9k_hw_common(ah);
3171 const struct ar9300_eeprom *eep = NULL;
3172
3173 switch (code) {
3174 case _CompressNone:
3175 if (length != mdata_size) {
3176 ath_dbg(common, EEPROM,
3177 "EEPROM structure size mismatch memory=%d eeprom=%d\n",
3178 mdata_size, length);
3179 return -1;
3180 }
3181 memcpy(mptr, (u8 *) (word + COMP_HDR_LEN), length);
3182 ath_dbg(common, EEPROM,
3183 "restored eeprom %d: uncompressed, length %d\n",
3184 it, length);
3185 break;
3186 case _CompressBlock:
3187 if (reference == 0) {
3188 } else {
3189 eep = ar9003_eeprom_struct_find_by_id(reference);
3190 if (eep == NULL) {
3191 ath_dbg(common, EEPROM,
3192 "can't find reference eeprom struct %d\n",
3193 reference);
3194 return -1;
3195 }
3196 memcpy(mptr, eep, mdata_size);
3197 }
3198 ath_dbg(common, EEPROM,
3199 "restore eeprom %d: block, reference %d, length %d\n",
3200 it, reference, length);
3201 ar9300_uncompress_block(ah, mptr, mdata_size,
3202 (u8 *) (word + COMP_HDR_LEN), length);
3203 break;
3204 default:
3205 ath_dbg(common, EEPROM, "unknown compression code %d\n", code);
3206 return -1;
3207 }
3208 return 0;
3209 }
3210
3211 typedef bool (*eeprom_read_op)(struct ath_hw *ah, int address, u8 *buffer,
3212 int count);
3213
3214 static bool ar9300_check_header(void *data)
3215 {
3216 u32 *word = data;
3217 return !(*word == 0 || *word == ~0);
3218 }
3219
3220 static bool ar9300_check_eeprom_header(struct ath_hw *ah, eeprom_read_op read,
3221 int base_addr)
3222 {
3223 u8 header[4];
3224
3225 if (!read(ah, base_addr, header, 4))
3226 return false;
3227
3228 return ar9300_check_header(header);
3229 }
3230
3231 static int ar9300_eeprom_restore_flash(struct ath_hw *ah, u8 *mptr,
3232 int mdata_size)
3233 {
3234 struct ath_common *common = ath9k_hw_common(ah);
3235 u16 *data = (u16 *) mptr;
3236 int i;
3237
3238 for (i = 0; i < mdata_size / 2; i++, data++)
3239 ath9k_hw_nvram_read(common, i, data);
3240
3241 return 0;
3242 }
3243 /*
3244 * Read the configuration data from the eeprom.
3245 * The data can be put in any specified memory buffer.
3246 *
3247 * Returns -1 on error.
3248 * Returns address of next memory location on success.
3249 */
3250 static int ar9300_eeprom_restore_internal(struct ath_hw *ah,
3251 u8 *mptr, int mdata_size)
3252 {
3253 #define MDEFAULT 15
3254 #define MSTATE 100
3255 int cptr;
3256 u8 *word;
3257 int code;
3258 int reference, length, major, minor;
3259 int osize;
3260 int it;
3261 u16 checksum, mchecksum;
3262 struct ath_common *common = ath9k_hw_common(ah);
3263 struct ar9300_eeprom *eep;
3264 eeprom_read_op read;
3265
3266 if (ath9k_hw_use_flash(ah)) {
3267 u8 txrx;
3268
3269 ar9300_eeprom_restore_flash(ah, mptr, mdata_size);
3270
3271 /* check if eeprom contains valid data */
3272 eep = (struct ar9300_eeprom *) mptr;
3273 txrx = eep->baseEepHeader.txrxMask;
3274 if (txrx != 0 && txrx != 0xff)
3275 return 0;
3276 }
3277
3278 word = kzalloc(2048, GFP_KERNEL);
3279 if (!word)
3280 return -ENOMEM;
3281
3282 memcpy(mptr, &ar9300_default, mdata_size);
3283
3284 read = ar9300_read_eeprom;
3285 if (AR_SREV_9485(ah))
3286 cptr = AR9300_BASE_ADDR_4K;
3287 else if (AR_SREV_9330(ah))
3288 cptr = AR9300_BASE_ADDR_512;
3289 else
3290 cptr = AR9300_BASE_ADDR;
3291 ath_dbg(common, EEPROM, "Trying EEPROM access at Address 0x%04x\n",
3292 cptr);
3293 if (ar9300_check_eeprom_header(ah, read, cptr))
3294 goto found;
3295
3296 cptr = AR9300_BASE_ADDR_512;
3297 ath_dbg(common, EEPROM, "Trying EEPROM access at Address 0x%04x\n",
3298 cptr);
3299 if (ar9300_check_eeprom_header(ah, read, cptr))
3300 goto found;
3301
3302 read = ar9300_read_otp;
3303 cptr = AR9300_BASE_ADDR;
3304 ath_dbg(common, EEPROM, "Trying OTP access at Address 0x%04x\n", cptr);
3305 if (ar9300_check_eeprom_header(ah, read, cptr))
3306 goto found;
3307
3308 cptr = AR9300_BASE_ADDR_512;
3309 ath_dbg(common, EEPROM, "Trying OTP access at Address 0x%04x\n", cptr);
3310 if (ar9300_check_eeprom_header(ah, read, cptr))
3311 goto found;
3312
3313 goto fail;
3314
3315 found:
3316 ath_dbg(common, EEPROM, "Found valid EEPROM data\n");
3317
3318 for (it = 0; it < MSTATE; it++) {
3319 if (!read(ah, cptr, word, COMP_HDR_LEN))
3320 goto fail;
3321
3322 if (!ar9300_check_header(word))
3323 break;
3324
3325 ar9300_comp_hdr_unpack(word, &code, &reference,
3326 &length, &major, &minor);
3327 ath_dbg(common, EEPROM,
3328 "Found block at %x: code=%d ref=%d length=%d major=%d minor=%d\n",
3329 cptr, code, reference, length, major, minor);
3330 if ((!AR_SREV_9485(ah) && length >= 1024) ||
3331 (AR_SREV_9485(ah) && length > EEPROM_DATA_LEN_9485)) {
3332 ath_dbg(common, EEPROM, "Skipping bad header\n");
3333 cptr -= COMP_HDR_LEN;
3334 continue;
3335 }
3336
3337 osize = length;
3338 read(ah, cptr, word, COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
3339 checksum = ar9300_comp_cksum(&word[COMP_HDR_LEN], length);
3340 mchecksum = get_unaligned_le16(&word[COMP_HDR_LEN + osize]);
3341 ath_dbg(common, EEPROM, "checksum %x %x\n",
3342 checksum, mchecksum);
3343 if (checksum == mchecksum) {
3344 ar9300_compress_decision(ah, it, code, reference, mptr,
3345 word, length, mdata_size);
3346 } else {
3347 ath_dbg(common, EEPROM,
3348 "skipping block with bad checksum\n");
3349 }
3350 cptr -= (COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
3351 }
3352
3353 kfree(word);
3354 return cptr;
3355
3356 fail:
3357 kfree(word);
3358 return -1;
3359 }
3360
3361 /*
3362 * Restore the configuration structure by reading the eeprom.
3363 * This function destroys any existing in-memory structure
3364 * content.
3365 */
3366 static bool ath9k_hw_ar9300_fill_eeprom(struct ath_hw *ah)
3367 {
3368 u8 *mptr = (u8 *) &ah->eeprom.ar9300_eep;
3369
3370 if (ar9300_eeprom_restore_internal(ah, mptr,
3371 sizeof(struct ar9300_eeprom)) < 0)
3372 return false;
3373
3374 return true;
3375 }
3376
3377 #if defined(CONFIG_ATH9K_DEBUGFS) || defined(CONFIG_ATH9K_HTC_DEBUGFS)
3378 static u32 ar9003_dump_modal_eeprom(char *buf, u32 len, u32 size,
3379 struct ar9300_modal_eep_header *modal_hdr)
3380 {
3381 PR_EEP("Chain0 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[0]));
3382 PR_EEP("Chain1 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[1]));
3383 PR_EEP("Chain2 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[2]));
3384 PR_EEP("Ant. Common Control", le32_to_cpu(modal_hdr->antCtrlCommon));
3385 PR_EEP("Ant. Common Control2", le32_to_cpu(modal_hdr->antCtrlCommon2));
3386 PR_EEP("Ant. Gain", modal_hdr->antennaGain);
3387 PR_EEP("Switch Settle", modal_hdr->switchSettling);
3388 PR_EEP("Chain0 xatten1DB", modal_hdr->xatten1DB[0]);
3389 PR_EEP("Chain1 xatten1DB", modal_hdr->xatten1DB[1]);
3390 PR_EEP("Chain2 xatten1DB", modal_hdr->xatten1DB[2]);
3391 PR_EEP("Chain0 xatten1Margin", modal_hdr->xatten1Margin[0]);
3392 PR_EEP("Chain1 xatten1Margin", modal_hdr->xatten1Margin[1]);
3393 PR_EEP("Chain2 xatten1Margin", modal_hdr->xatten1Margin[2]);
3394 PR_EEP("Temp Slope", modal_hdr->tempSlope);
3395 PR_EEP("Volt Slope", modal_hdr->voltSlope);
3396 PR_EEP("spur Channels0", modal_hdr->spurChans[0]);
3397 PR_EEP("spur Channels1", modal_hdr->spurChans[1]);
3398 PR_EEP("spur Channels2", modal_hdr->spurChans[2]);
3399 PR_EEP("spur Channels3", modal_hdr->spurChans[3]);
3400 PR_EEP("spur Channels4", modal_hdr->spurChans[4]);
3401 PR_EEP("Chain0 NF Threshold", modal_hdr->noiseFloorThreshCh[0]);
3402 PR_EEP("Chain1 NF Threshold", modal_hdr->noiseFloorThreshCh[1]);
3403 PR_EEP("Chain2 NF Threshold", modal_hdr->noiseFloorThreshCh[2]);
3404 PR_EEP("Quick Drop", modal_hdr->quick_drop);
3405 PR_EEP("txEndToXpaOff", modal_hdr->txEndToXpaOff);
3406 PR_EEP("xPA Bias Level", modal_hdr->xpaBiasLvl);
3407 PR_EEP("txFrameToDataStart", modal_hdr->txFrameToDataStart);
3408 PR_EEP("txFrameToPaOn", modal_hdr->txFrameToPaOn);
3409 PR_EEP("txFrameToXpaOn", modal_hdr->txFrameToXpaOn);
3410 PR_EEP("txClip", modal_hdr->txClip);
3411 PR_EEP("ADC Desired size", modal_hdr->adcDesiredSize);
3412
3413 return len;
3414 }
3415
3416 static u32 ath9k_hw_ar9003_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
3417 u8 *buf, u32 len, u32 size)
3418 {
3419 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3420 struct ar9300_base_eep_hdr *pBase;
3421
3422 if (!dump_base_hdr) {
3423 len += snprintf(buf + len, size - len,
3424 "%20s :\n", "2GHz modal Header");
3425 len = ar9003_dump_modal_eeprom(buf, len, size,
3426 &eep->modalHeader2G);
3427 len += snprintf(buf + len, size - len,
3428 "%20s :\n", "5GHz modal Header");
3429 len = ar9003_dump_modal_eeprom(buf, len, size,
3430 &eep->modalHeader5G);
3431 goto out;
3432 }
3433
3434 pBase = &eep->baseEepHeader;
3435
3436 PR_EEP("EEPROM Version", ah->eeprom.ar9300_eep.eepromVersion);
3437 PR_EEP("RegDomain1", le16_to_cpu(pBase->regDmn[0]));
3438 PR_EEP("RegDomain2", le16_to_cpu(pBase->regDmn[1]));
3439 PR_EEP("TX Mask", (pBase->txrxMask >> 4));
3440 PR_EEP("RX Mask", (pBase->txrxMask & 0x0f));
3441 PR_EEP("Allow 5GHz", !!(pBase->opCapFlags.opFlags &
3442 AR5416_OPFLAGS_11A));
3443 PR_EEP("Allow 2GHz", !!(pBase->opCapFlags.opFlags &
3444 AR5416_OPFLAGS_11G));
3445 PR_EEP("Disable 2GHz HT20", !!(pBase->opCapFlags.opFlags &
3446 AR5416_OPFLAGS_N_2G_HT20));
3447 PR_EEP("Disable 2GHz HT40", !!(pBase->opCapFlags.opFlags &
3448 AR5416_OPFLAGS_N_2G_HT40));
3449 PR_EEP("Disable 5Ghz HT20", !!(pBase->opCapFlags.opFlags &
3450 AR5416_OPFLAGS_N_5G_HT20));
3451 PR_EEP("Disable 5Ghz HT40", !!(pBase->opCapFlags.opFlags &
3452 AR5416_OPFLAGS_N_5G_HT40));
3453 PR_EEP("Big Endian", !!(pBase->opCapFlags.eepMisc & 0x01));
3454 PR_EEP("RF Silent", pBase->rfSilent);
3455 PR_EEP("BT option", pBase->blueToothOptions);
3456 PR_EEP("Device Cap", pBase->deviceCap);
3457 PR_EEP("Device Type", pBase->deviceType);
3458 PR_EEP("Power Table Offset", pBase->pwrTableOffset);
3459 PR_EEP("Tuning Caps1", pBase->params_for_tuning_caps[0]);
3460 PR_EEP("Tuning Caps2", pBase->params_for_tuning_caps[1]);
3461 PR_EEP("Enable Tx Temp Comp", !!(pBase->featureEnable & BIT(0)));
3462 PR_EEP("Enable Tx Volt Comp", !!(pBase->featureEnable & BIT(1)));
3463 PR_EEP("Enable fast clock", !!(pBase->featureEnable & BIT(2)));
3464 PR_EEP("Enable doubling", !!(pBase->featureEnable & BIT(3)));
3465 PR_EEP("Internal regulator", !!(pBase->featureEnable & BIT(4)));
3466 PR_EEP("Enable Paprd", !!(pBase->featureEnable & BIT(5)));
3467 PR_EEP("Driver Strength", !!(pBase->miscConfiguration & BIT(0)));
3468 PR_EEP("Quick Drop", !!(pBase->miscConfiguration & BIT(1)));
3469 PR_EEP("Chain mask Reduce", (pBase->miscConfiguration >> 0x3) & 0x1);
3470 PR_EEP("Write enable Gpio", pBase->eepromWriteEnableGpio);
3471 PR_EEP("WLAN Disable Gpio", pBase->wlanDisableGpio);
3472 PR_EEP("WLAN LED Gpio", pBase->wlanLedGpio);
3473 PR_EEP("Rx Band Select Gpio", pBase->rxBandSelectGpio);
3474 PR_EEP("Tx Gain", pBase->txrxgain >> 4);
3475 PR_EEP("Rx Gain", pBase->txrxgain & 0xf);
3476 PR_EEP("SW Reg", le32_to_cpu(pBase->swreg));
3477
3478 len += snprintf(buf + len, size - len, "%20s : %pM\n", "MacAddress",
3479 ah->eeprom.ar9300_eep.macAddr);
3480 out:
3481 if (len > size)
3482 len = size;
3483
3484 return len;
3485 }
3486 #else
3487 static u32 ath9k_hw_ar9003_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
3488 u8 *buf, u32 len, u32 size)
3489 {
3490 return 0;
3491 }
3492 #endif
3493
3494 /* XXX: review hardware docs */
3495 static int ath9k_hw_ar9300_get_eeprom_ver(struct ath_hw *ah)
3496 {
3497 return ah->eeprom.ar9300_eep.eepromVersion;
3498 }
3499
3500 /* XXX: could be read from the eepromVersion, not sure yet */
3501 static int ath9k_hw_ar9300_get_eeprom_rev(struct ath_hw *ah)
3502 {
3503 return 0;
3504 }
3505
3506 static s32 ar9003_hw_xpa_bias_level_get(struct ath_hw *ah, bool is2ghz)
3507 {
3508 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3509
3510 if (is2ghz)
3511 return eep->modalHeader2G.xpaBiasLvl;
3512 else
3513 return eep->modalHeader5G.xpaBiasLvl;
3514 }
3515
3516 static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz)
3517 {
3518 int bias = ar9003_hw_xpa_bias_level_get(ah, is2ghz);
3519
3520 if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))
3521 REG_RMW_FIELD(ah, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, bias);
3522 else if (AR_SREV_9462(ah) || AR_SREV_9550(ah))
3523 REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
3524 else {
3525 REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
3526 REG_RMW_FIELD(ah, AR_CH0_THERM,
3527 AR_CH0_THERM_XPABIASLVL_MSB,
3528 bias >> 2);
3529 REG_RMW_FIELD(ah, AR_CH0_THERM,
3530 AR_CH0_THERM_XPASHORT2GND, 1);
3531 }
3532 }
3533
3534 static u16 ar9003_switch_com_spdt_get(struct ath_hw *ah, bool is_2ghz)
3535 {
3536 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3537 __le16 val;
3538
3539 if (is_2ghz)
3540 val = eep->modalHeader2G.switchcomspdt;
3541 else
3542 val = eep->modalHeader5G.switchcomspdt;
3543 return le16_to_cpu(val);
3544 }
3545
3546
3547 static u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz)
3548 {
3549 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3550 __le32 val;
3551
3552 if (is2ghz)
3553 val = eep->modalHeader2G.antCtrlCommon;
3554 else
3555 val = eep->modalHeader5G.antCtrlCommon;
3556 return le32_to_cpu(val);
3557 }
3558
3559 static u32 ar9003_hw_ant_ctrl_common_2_get(struct ath_hw *ah, bool is2ghz)
3560 {
3561 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3562 __le32 val;
3563
3564 if (is2ghz)
3565 val = eep->modalHeader2G.antCtrlCommon2;
3566 else
3567 val = eep->modalHeader5G.antCtrlCommon2;
3568 return le32_to_cpu(val);
3569 }
3570
3571 static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah,
3572 int chain,
3573 bool is2ghz)
3574 {
3575 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3576 __le16 val = 0;
3577
3578 if (chain >= 0 && chain < AR9300_MAX_CHAINS) {
3579 if (is2ghz)
3580 val = eep->modalHeader2G.antCtrlChain[chain];
3581 else
3582 val = eep->modalHeader5G.antCtrlChain[chain];
3583 }
3584
3585 return le16_to_cpu(val);
3586 }
3587
3588 static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
3589 {
3590 int chain;
3591 u32 regval;
3592 u32 ant_div_ctl1;
3593 static const u32 switch_chain_reg[AR9300_MAX_CHAINS] = {
3594 AR_PHY_SWITCH_CHAIN_0,
3595 AR_PHY_SWITCH_CHAIN_1,
3596 AR_PHY_SWITCH_CHAIN_2,
3597 };
3598
3599 u32 value = ar9003_hw_ant_ctrl_common_get(ah, is2ghz);
3600
3601 if (AR_SREV_9462(ah)) {
3602 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM,
3603 AR_SWITCH_TABLE_COM_AR9462_ALL, value);
3604 } else if (AR_SREV_9550(ah)) {
3605 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM,
3606 AR_SWITCH_TABLE_COM_AR9550_ALL, value);
3607 } else
3608 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM,
3609 AR_SWITCH_TABLE_COM_ALL, value);
3610
3611
3612 /*
3613 * AR9462 defines new switch table for BT/WLAN,
3614 * here's new field name in XXX.ref for both 2G and 5G.
3615 * Register: [GLB_CONTROL] GLB_CONTROL (@0x20044)
3616 * 15:12 R/W SWITCH_TABLE_COM_SPDT_WLAN_RX
3617 * SWITCH_TABLE_COM_SPDT_WLAN_RX
3618 *
3619 * 11:8 R/W SWITCH_TABLE_COM_SPDT_WLAN_TX
3620 * SWITCH_TABLE_COM_SPDT_WLAN_TX
3621 *
3622 * 7:4 R/W SWITCH_TABLE_COM_SPDT_WLAN_IDLE
3623 * SWITCH_TABLE_COM_SPDT_WLAN_IDLE
3624 */
3625 if (AR_SREV_9462_20_OR_LATER(ah)) {
3626 value = ar9003_switch_com_spdt_get(ah, is2ghz);
3627 REG_RMW_FIELD(ah, AR_PHY_GLB_CONTROL,
3628 AR_SWITCH_TABLE_COM_SPDT_ALL, value);
3629 REG_SET_BIT(ah, AR_PHY_GLB_CONTROL, AR_BTCOEX_CTRL_SPDT_ENABLE);
3630 }
3631
3632 value = ar9003_hw_ant_ctrl_common_2_get(ah, is2ghz);
3633 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2, AR_SWITCH_TABLE_COM2_ALL, value);
3634
3635 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
3636 if ((ah->rxchainmask & BIT(chain)) ||
3637 (ah->txchainmask & BIT(chain))) {
3638 value = ar9003_hw_ant_ctrl_chain_get(ah, chain,
3639 is2ghz);
3640 REG_RMW_FIELD(ah, switch_chain_reg[chain],
3641 AR_SWITCH_TABLE_ALL, value);
3642 }
3643 }
3644
3645 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
3646 value = ath9k_hw_ar9300_get_eeprom(ah, EEP_ANT_DIV_CTL1);
3647 /*
3648 * main_lnaconf, alt_lnaconf, main_tb, alt_tb
3649 * are the fields present
3650 */
3651 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
3652 regval &= (~AR_ANT_DIV_CTRL_ALL);
3653 regval |= (value & 0x3f) << AR_ANT_DIV_CTRL_ALL_S;
3654 /* enable_lnadiv */
3655 regval &= (~AR_PHY_9485_ANT_DIV_LNADIV);
3656 regval |= ((value >> 6) & 0x1) <<
3657 AR_PHY_9485_ANT_DIV_LNADIV_S;
3658 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
3659
3660 /*enable fast_div */
3661 regval = REG_READ(ah, AR_PHY_CCK_DETECT);
3662 regval &= (~AR_FAST_DIV_ENABLE);
3663 regval |= ((value >> 7) & 0x1) <<
3664 AR_FAST_DIV_ENABLE_S;
3665 REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
3666 ant_div_ctl1 =
3667 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
3668 /* check whether antenna diversity is enabled */
3669 if ((ant_div_ctl1 >> 0x6) == 0x3) {
3670 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
3671 /*
3672 * clear bits 25-30 main_lnaconf, alt_lnaconf,
3673 * main_tb, alt_tb
3674 */
3675 regval &= (~(AR_PHY_9485_ANT_DIV_MAIN_LNACONF |
3676 AR_PHY_9485_ANT_DIV_ALT_LNACONF |
3677 AR_PHY_9485_ANT_DIV_ALT_GAINTB |
3678 AR_PHY_9485_ANT_DIV_MAIN_GAINTB));
3679 /* by default use LNA1 for the main antenna */
3680 regval |= (AR_PHY_9485_ANT_DIV_LNA1 <<
3681 AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S);
3682 regval |= (AR_PHY_9485_ANT_DIV_LNA2 <<
3683 AR_PHY_9485_ANT_DIV_ALT_LNACONF_S);
3684 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
3685 }
3686
3687
3688 }
3689
3690 }
3691
3692 static void ar9003_hw_drive_strength_apply(struct ath_hw *ah)
3693 {
3694 int drive_strength;
3695 unsigned long reg;
3696
3697 drive_strength = ath9k_hw_ar9300_get_eeprom(ah, EEP_DRIVE_STRENGTH);
3698
3699 if (!drive_strength)
3700 return;
3701
3702 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS1);
3703 reg &= ~0x00ffffc0;
3704 reg |= 0x5 << 21;
3705 reg |= 0x5 << 18;
3706 reg |= 0x5 << 15;
3707 reg |= 0x5 << 12;
3708 reg |= 0x5 << 9;
3709 reg |= 0x5 << 6;
3710 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS1, reg);
3711
3712 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS2);
3713 reg &= ~0xffffffe0;
3714 reg |= 0x5 << 29;
3715 reg |= 0x5 << 26;
3716 reg |= 0x5 << 23;
3717 reg |= 0x5 << 20;
3718 reg |= 0x5 << 17;
3719 reg |= 0x5 << 14;
3720 reg |= 0x5 << 11;
3721 reg |= 0x5 << 8;
3722 reg |= 0x5 << 5;
3723 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS2, reg);
3724
3725 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS4);
3726 reg &= ~0xff800000;
3727 reg |= 0x5 << 29;
3728 reg |= 0x5 << 26;
3729 reg |= 0x5 << 23;
3730 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS4, reg);
3731 }
3732
3733 static u16 ar9003_hw_atten_chain_get(struct ath_hw *ah, int chain,
3734 struct ath9k_channel *chan)
3735 {
3736 int f[3], t[3];
3737 u16 value;
3738 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3739
3740 if (chain >= 0 && chain < 3) {
3741 if (IS_CHAN_2GHZ(chan))
3742 return eep->modalHeader2G.xatten1DB[chain];
3743 else if (eep->base_ext2.xatten1DBLow[chain] != 0) {
3744 t[0] = eep->base_ext2.xatten1DBLow[chain];
3745 f[0] = 5180;
3746 t[1] = eep->modalHeader5G.xatten1DB[chain];
3747 f[1] = 5500;
3748 t[2] = eep->base_ext2.xatten1DBHigh[chain];
3749 f[2] = 5785;
3750 value = ar9003_hw_power_interpolate((s32) chan->channel,
3751 f, t, 3);
3752 return value;
3753 } else
3754 return eep->modalHeader5G.xatten1DB[chain];
3755 }
3756
3757 return 0;
3758 }
3759
3760
3761 static u16 ar9003_hw_atten_chain_get_margin(struct ath_hw *ah, int chain,
3762 struct ath9k_channel *chan)
3763 {
3764 int f[3], t[3];
3765 u16 value;
3766 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3767
3768 if (chain >= 0 && chain < 3) {
3769 if (IS_CHAN_2GHZ(chan))
3770 return eep->modalHeader2G.xatten1Margin[chain];
3771 else if (eep->base_ext2.xatten1MarginLow[chain] != 0) {
3772 t[0] = eep->base_ext2.xatten1MarginLow[chain];
3773 f[0] = 5180;
3774 t[1] = eep->modalHeader5G.xatten1Margin[chain];
3775 f[1] = 5500;
3776 t[2] = eep->base_ext2.xatten1MarginHigh[chain];
3777 f[2] = 5785;
3778 value = ar9003_hw_power_interpolate((s32) chan->channel,
3779 f, t, 3);
3780 return value;
3781 } else
3782 return eep->modalHeader5G.xatten1Margin[chain];
3783 }
3784
3785 return 0;
3786 }
3787
3788 static void ar9003_hw_atten_apply(struct ath_hw *ah, struct ath9k_channel *chan)
3789 {
3790 int i;
3791 u16 value;
3792 unsigned long ext_atten_reg[3] = {AR_PHY_EXT_ATTEN_CTL_0,
3793 AR_PHY_EXT_ATTEN_CTL_1,
3794 AR_PHY_EXT_ATTEN_CTL_2,
3795 };
3796
3797 /* Test value. if 0 then attenuation is unused. Don't load anything. */
3798 for (i = 0; i < 3; i++) {
3799 if (ah->txchainmask & BIT(i)) {
3800 value = ar9003_hw_atten_chain_get(ah, i, chan);
3801 REG_RMW_FIELD(ah, ext_atten_reg[i],
3802 AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB, value);
3803
3804 value = ar9003_hw_atten_chain_get_margin(ah, i, chan);
3805 REG_RMW_FIELD(ah, ext_atten_reg[i],
3806 AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN,
3807 value);
3808 }
3809 }
3810 }
3811
3812 static bool is_pmu_set(struct ath_hw *ah, u32 pmu_reg, int pmu_set)
3813 {
3814 int timeout = 100;
3815
3816 while (pmu_set != REG_READ(ah, pmu_reg)) {
3817 if (timeout-- == 0)
3818 return false;
3819 REG_WRITE(ah, pmu_reg, pmu_set);
3820 udelay(10);
3821 }
3822
3823 return true;
3824 }
3825
3826 void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
3827 {
3828 int internal_regulator =
3829 ath9k_hw_ar9300_get_eeprom(ah, EEP_INTERNAL_REGULATOR);
3830 u32 reg_val;
3831
3832 if (internal_regulator) {
3833 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
3834 int reg_pmu_set;
3835
3836 reg_pmu_set = REG_READ(ah, AR_PHY_PMU2) & ~AR_PHY_PMU2_PGM;
3837 REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3838 if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3839 return;
3840
3841 if (AR_SREV_9330(ah)) {
3842 if (ah->is_clk_25mhz) {
3843 reg_pmu_set = (3 << 1) | (8 << 4) |
3844 (3 << 8) | (1 << 14) |
3845 (6 << 17) | (1 << 20) |
3846 (3 << 24);
3847 } else {
3848 reg_pmu_set = (4 << 1) | (7 << 4) |
3849 (3 << 8) | (1 << 14) |
3850 (6 << 17) | (1 << 20) |
3851 (3 << 24);
3852 }
3853 } else {
3854 reg_pmu_set = (5 << 1) | (7 << 4) |
3855 (2 << 8) | (2 << 14) |
3856 (6 << 17) | (1 << 20) |
3857 (3 << 24) | (1 << 28);
3858 }
3859
3860 REG_WRITE(ah, AR_PHY_PMU1, reg_pmu_set);
3861 if (!is_pmu_set(ah, AR_PHY_PMU1, reg_pmu_set))
3862 return;
3863
3864 reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0xFFC00000)
3865 | (4 << 26);
3866 REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3867 if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3868 return;
3869
3870 reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0x00200000)
3871 | (1 << 21);
3872 REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3873 if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3874 return;
3875 } else if (AR_SREV_9462(ah)) {
3876 reg_val = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG);
3877 REG_WRITE(ah, AR_PHY_PMU1, reg_val);
3878 } else {
3879 /* Internal regulator is ON. Write swreg register. */
3880 reg_val = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG);
3881 REG_WRITE(ah, AR_RTC_REG_CONTROL1,
3882 REG_READ(ah, AR_RTC_REG_CONTROL1) &
3883 (~AR_RTC_REG_CONTROL1_SWREG_PROGRAM));
3884 REG_WRITE(ah, AR_RTC_REG_CONTROL0, reg_val);
3885 /* Set REG_CONTROL1.SWREG_PROGRAM */
3886 REG_WRITE(ah, AR_RTC_REG_CONTROL1,
3887 REG_READ(ah,
3888 AR_RTC_REG_CONTROL1) |
3889 AR_RTC_REG_CONTROL1_SWREG_PROGRAM);
3890 }
3891 } else {
3892 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
3893 REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0);
3894 while (REG_READ_FIELD(ah, AR_PHY_PMU2,
3895 AR_PHY_PMU2_PGM))
3896 udelay(10);
3897
3898 REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1);
3899 while (!REG_READ_FIELD(ah, AR_PHY_PMU1,
3900 AR_PHY_PMU1_PWD))
3901 udelay(10);
3902 REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0x1);
3903 while (!REG_READ_FIELD(ah, AR_PHY_PMU2,
3904 AR_PHY_PMU2_PGM))
3905 udelay(10);
3906 } else if (AR_SREV_9462(ah))
3907 REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1);
3908 else {
3909 reg_val = REG_READ(ah, AR_RTC_SLEEP_CLK) |
3910 AR_RTC_FORCE_SWREG_PRD;
3911 REG_WRITE(ah, AR_RTC_SLEEP_CLK, reg_val);
3912 }
3913 }
3914
3915 }
3916
3917 static void ar9003_hw_apply_tuning_caps(struct ath_hw *ah)
3918 {
3919 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3920 u8 tuning_caps_param = eep->baseEepHeader.params_for_tuning_caps[0];
3921
3922 if (eep->baseEepHeader.featureEnable & 0x40) {
3923 tuning_caps_param &= 0x7f;
3924 REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPINDAC,
3925 tuning_caps_param);
3926 REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPOUTDAC,
3927 tuning_caps_param);
3928 }
3929 }
3930
3931 static void ar9003_hw_quick_drop_apply(struct ath_hw *ah, u16 freq)
3932 {
3933 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3934 int quick_drop = ath9k_hw_ar9300_get_eeprom(ah, EEP_QUICK_DROP);
3935 s32 t[3], f[3] = {5180, 5500, 5785};
3936
3937 if (!quick_drop)
3938 return;
3939
3940 if (freq < 4000)
3941 quick_drop = eep->modalHeader2G.quick_drop;
3942 else {
3943 t[0] = eep->base_ext1.quick_drop_low;
3944 t[1] = eep->modalHeader5G.quick_drop;
3945 t[2] = eep->base_ext1.quick_drop_high;
3946 quick_drop = ar9003_hw_power_interpolate(freq, f, t, 3);
3947 }
3948 REG_RMW_FIELD(ah, AR_PHY_AGC, AR_PHY_AGC_QUICK_DROP, quick_drop);
3949 }
3950
3951 static void ar9003_hw_txend_to_xpa_off_apply(struct ath_hw *ah, u16 freq)
3952 {
3953 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3954 u32 value;
3955
3956 value = (freq < 4000) ? eep->modalHeader2G.txEndToXpaOff :
3957 eep->modalHeader5G.txEndToXpaOff;
3958
3959 REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL,
3960 AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF, value);
3961 REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL,
3962 AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF, value);
3963 }
3964
3965 static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah,
3966 struct ath9k_channel *chan)
3967 {
3968 ar9003_hw_xpa_bias_level_apply(ah, IS_CHAN_2GHZ(chan));
3969 ar9003_hw_ant_ctrl_apply(ah, IS_CHAN_2GHZ(chan));
3970 ar9003_hw_drive_strength_apply(ah);
3971 ar9003_hw_atten_apply(ah, chan);
3972 ar9003_hw_quick_drop_apply(ah, chan->channel);
3973 if (!AR_SREV_9330(ah) && !AR_SREV_9340(ah) && !AR_SREV_9550(ah))
3974 ar9003_hw_internal_regulator_apply(ah);
3975 if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))
3976 ar9003_hw_apply_tuning_caps(ah);
3977 ar9003_hw_txend_to_xpa_off_apply(ah, chan->channel);
3978 }
3979
3980 static void ath9k_hw_ar9300_set_addac(struct ath_hw *ah,
3981 struct ath9k_channel *chan)
3982 {
3983 }
3984
3985 /*
3986 * Returns the interpolated y value corresponding to the specified x value
3987 * from the np ordered pairs of data (px,py).
3988 * The pairs do not have to be in any order.
3989 * If the specified x value is less than any of the px,
3990 * the returned y value is equal to the py for the lowest px.
3991 * If the specified x value is greater than any of the px,
3992 * the returned y value is equal to the py for the highest px.
3993 */
3994 static int ar9003_hw_power_interpolate(int32_t x,
3995 int32_t *px, int32_t *py, u_int16_t np)
3996 {
3997 int ip = 0;
3998 int lx = 0, ly = 0, lhave = 0;
3999 int hx = 0, hy = 0, hhave = 0;
4000 int dx = 0;
4001 int y = 0;
4002
4003 lhave = 0;
4004 hhave = 0;
4005
4006 /* identify best lower and higher x calibration measurement */
4007 for (ip = 0; ip < np; ip++) {
4008 dx = x - px[ip];
4009
4010 /* this measurement is higher than our desired x */
4011 if (dx <= 0) {
4012 if (!hhave || dx > (x - hx)) {
4013 /* new best higher x measurement */
4014 hx = px[ip];
4015 hy = py[ip];
4016 hhave = 1;
4017 }
4018 }
4019 /* this measurement is lower than our desired x */
4020 if (dx >= 0) {
4021 if (!lhave || dx < (x - lx)) {
4022 /* new best lower x measurement */
4023 lx = px[ip];
4024 ly = py[ip];
4025 lhave = 1;
4026 }
4027 }
4028 }
4029
4030 /* the low x is good */
4031 if (lhave) {
4032 /* so is the high x */
4033 if (hhave) {
4034 /* they're the same, so just pick one */
4035 if (hx == lx)
4036 y = ly;
4037 else /* interpolate */
4038 y = interpolate(x, lx, hx, ly, hy);
4039 } else /* only low is good, use it */
4040 y = ly;
4041 } else if (hhave) /* only high is good, use it */
4042 y = hy;
4043 else /* nothing is good,this should never happen unless np=0, ???? */
4044 y = -(1 << 30);
4045 return y;
4046 }
4047
4048 static u8 ar9003_hw_eeprom_get_tgt_pwr(struct ath_hw *ah,
4049 u16 rateIndex, u16 freq, bool is2GHz)
4050 {
4051 u16 numPiers, i;
4052 s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
4053 s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
4054 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4055 struct cal_tgt_pow_legacy *pEepromTargetPwr;
4056 u8 *pFreqBin;
4057
4058 if (is2GHz) {
4059 numPiers = AR9300_NUM_2G_20_TARGET_POWERS;
4060 pEepromTargetPwr = eep->calTargetPower2G;
4061 pFreqBin = eep->calTarget_freqbin_2G;
4062 } else {
4063 numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
4064 pEepromTargetPwr = eep->calTargetPower5G;
4065 pFreqBin = eep->calTarget_freqbin_5G;
4066 }
4067
4068 /*
4069 * create array of channels and targetpower from
4070 * targetpower piers stored on eeprom
4071 */
4072 for (i = 0; i < numPiers; i++) {
4073 freqArray[i] = ath9k_hw_fbin2freq(pFreqBin[i], is2GHz);
4074 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
4075 }
4076
4077 /* interpolate to get target power for given frequency */
4078 return (u8) ar9003_hw_power_interpolate((s32) freq,
4079 freqArray,
4080 targetPowerArray, numPiers);
4081 }
4082
4083 static u8 ar9003_hw_eeprom_get_ht20_tgt_pwr(struct ath_hw *ah,
4084 u16 rateIndex,
4085 u16 freq, bool is2GHz)
4086 {
4087 u16 numPiers, i;
4088 s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
4089 s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
4090 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4091 struct cal_tgt_pow_ht *pEepromTargetPwr;
4092 u8 *pFreqBin;
4093
4094 if (is2GHz) {
4095 numPiers = AR9300_NUM_2G_20_TARGET_POWERS;
4096 pEepromTargetPwr = eep->calTargetPower2GHT20;
4097 pFreqBin = eep->calTarget_freqbin_2GHT20;
4098 } else {
4099 numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
4100 pEepromTargetPwr = eep->calTargetPower5GHT20;
4101 pFreqBin = eep->calTarget_freqbin_5GHT20;
4102 }
4103
4104 /*
4105 * create array of channels and targetpower
4106 * from targetpower piers stored on eeprom
4107 */
4108 for (i = 0; i < numPiers; i++) {
4109 freqArray[i] = ath9k_hw_fbin2freq(pFreqBin[i], is2GHz);
4110 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
4111 }
4112
4113 /* interpolate to get target power for given frequency */
4114 return (u8) ar9003_hw_power_interpolate((s32) freq,
4115 freqArray,
4116 targetPowerArray, numPiers);
4117 }
4118
4119 static u8 ar9003_hw_eeprom_get_ht40_tgt_pwr(struct ath_hw *ah,
4120 u16 rateIndex,
4121 u16 freq, bool is2GHz)
4122 {
4123 u16 numPiers, i;
4124 s32 targetPowerArray[AR9300_NUM_5G_40_TARGET_POWERS];
4125 s32 freqArray[AR9300_NUM_5G_40_TARGET_POWERS];
4126 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4127 struct cal_tgt_pow_ht *pEepromTargetPwr;
4128 u8 *pFreqBin;
4129
4130 if (is2GHz) {
4131 numPiers = AR9300_NUM_2G_40_TARGET_POWERS;
4132 pEepromTargetPwr = eep->calTargetPower2GHT40;
4133 pFreqBin = eep->calTarget_freqbin_2GHT40;
4134 } else {
4135 numPiers = AR9300_NUM_5G_40_TARGET_POWERS;
4136 pEepromTargetPwr = eep->calTargetPower5GHT40;
4137 pFreqBin = eep->calTarget_freqbin_5GHT40;
4138 }
4139
4140 /*
4141 * create array of channels and targetpower from
4142 * targetpower piers stored on eeprom
4143 */
4144 for (i = 0; i < numPiers; i++) {
4145 freqArray[i] = ath9k_hw_fbin2freq(pFreqBin[i], is2GHz);
4146 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
4147 }
4148
4149 /* interpolate to get target power for given frequency */
4150 return (u8) ar9003_hw_power_interpolate((s32) freq,
4151 freqArray,
4152 targetPowerArray, numPiers);
4153 }
4154
4155 static u8 ar9003_hw_eeprom_get_cck_tgt_pwr(struct ath_hw *ah,
4156 u16 rateIndex, u16 freq)
4157 {
4158 u16 numPiers = AR9300_NUM_2G_CCK_TARGET_POWERS, i;
4159 s32 targetPowerArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
4160 s32 freqArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
4161 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4162 struct cal_tgt_pow_legacy *pEepromTargetPwr = eep->calTargetPowerCck;
4163 u8 *pFreqBin = eep->calTarget_freqbin_Cck;
4164
4165 /*
4166 * create array of channels and targetpower from
4167 * targetpower piers stored on eeprom
4168 */
4169 for (i = 0; i < numPiers; i++) {
4170 freqArray[i] = ath9k_hw_fbin2freq(pFreqBin[i], 1);
4171 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
4172 }
4173
4174 /* interpolate to get target power for given frequency */
4175 return (u8) ar9003_hw_power_interpolate((s32) freq,
4176 freqArray,
4177 targetPowerArray, numPiers);
4178 }
4179
4180 /* Set tx power registers to array of values passed in */
4181 static int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray)
4182 {
4183 #define POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
4184 /* make sure forced gain is not set */
4185 REG_WRITE(ah, AR_PHY_TX_FORCED_GAIN, 0);
4186
4187 /* Write the OFDM power per rate set */
4188
4189 /* 6 (LSB), 9, 12, 18 (MSB) */
4190 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(0),
4191 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) |
4192 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 16) |
4193 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 8) |
4194 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
4195
4196 /* 24 (LSB), 36, 48, 54 (MSB) */
4197 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(1),
4198 POW_SM(pPwrArray[ALL_TARGET_LEGACY_54], 24) |
4199 POW_SM(pPwrArray[ALL_TARGET_LEGACY_48], 16) |
4200 POW_SM(pPwrArray[ALL_TARGET_LEGACY_36], 8) |
4201 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
4202
4203 /* Write the CCK power per rate set */
4204
4205 /* 1L (LSB), reserved, 2L, 2S (MSB) */
4206 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(2),
4207 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 24) |
4208 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) |
4209 /* POW_SM(txPowerTimes2, 8) | this is reserved for AR9003 */
4210 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0));
4211
4212 /* 5.5L (LSB), 5.5S, 11L, 11S (MSB) */
4213 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(3),
4214 POW_SM(pPwrArray[ALL_TARGET_LEGACY_11S], 24) |
4215 POW_SM(pPwrArray[ALL_TARGET_LEGACY_11L], 16) |
4216 POW_SM(pPwrArray[ALL_TARGET_LEGACY_5S], 8) |
4217 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0)
4218 );
4219
4220 /* Write the power for duplicated frames - HT40 */
4221
4222 /* dup40_cck (LSB), dup40_ofdm, ext20_cck, ext20_ofdm (MSB) */
4223 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(8),
4224 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) |
4225 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) |
4226 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 8) |
4227 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0)
4228 );
4229
4230 /* Write the HT20 power per rate set */
4231
4232 /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */
4233 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(4),
4234 POW_SM(pPwrArray[ALL_TARGET_HT20_5], 24) |
4235 POW_SM(pPwrArray[ALL_TARGET_HT20_4], 16) |
4236 POW_SM(pPwrArray[ALL_TARGET_HT20_1_3_9_11_17_19], 8) |
4237 POW_SM(pPwrArray[ALL_TARGET_HT20_0_8_16], 0)
4238 );
4239
4240 /* 6 (LSB), 7, 12, 13 (MSB) */
4241 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(5),
4242 POW_SM(pPwrArray[ALL_TARGET_HT20_13], 24) |
4243 POW_SM(pPwrArray[ALL_TARGET_HT20_12], 16) |
4244 POW_SM(pPwrArray[ALL_TARGET_HT20_7], 8) |
4245 POW_SM(pPwrArray[ALL_TARGET_HT20_6], 0)
4246 );
4247
4248 /* 14 (LSB), 15, 20, 21 */
4249 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(9),
4250 POW_SM(pPwrArray[ALL_TARGET_HT20_21], 24) |
4251 POW_SM(pPwrArray[ALL_TARGET_HT20_20], 16) |
4252 POW_SM(pPwrArray[ALL_TARGET_HT20_15], 8) |
4253 POW_SM(pPwrArray[ALL_TARGET_HT20_14], 0)
4254 );
4255
4256 /* Mixed HT20 and HT40 rates */
4257
4258 /* HT20 22 (LSB), HT20 23, HT40 22, HT40 23 (MSB) */
4259 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(10),
4260 POW_SM(pPwrArray[ALL_TARGET_HT40_23], 24) |
4261 POW_SM(pPwrArray[ALL_TARGET_HT40_22], 16) |
4262 POW_SM(pPwrArray[ALL_TARGET_HT20_23], 8) |
4263 POW_SM(pPwrArray[ALL_TARGET_HT20_22], 0)
4264 );
4265
4266 /*
4267 * Write the HT40 power per rate set
4268 * correct PAR difference between HT40 and HT20/LEGACY
4269 * 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB)
4270 */
4271 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(6),
4272 POW_SM(pPwrArray[ALL_TARGET_HT40_5], 24) |
4273 POW_SM(pPwrArray[ALL_TARGET_HT40_4], 16) |
4274 POW_SM(pPwrArray[ALL_TARGET_HT40_1_3_9_11_17_19], 8) |
4275 POW_SM(pPwrArray[ALL_TARGET_HT40_0_8_16], 0)
4276 );
4277
4278 /* 6 (LSB), 7, 12, 13 (MSB) */
4279 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(7),
4280 POW_SM(pPwrArray[ALL_TARGET_HT40_13], 24) |
4281 POW_SM(pPwrArray[ALL_TARGET_HT40_12], 16) |
4282 POW_SM(pPwrArray[ALL_TARGET_HT40_7], 8) |
4283 POW_SM(pPwrArray[ALL_TARGET_HT40_6], 0)
4284 );
4285
4286 /* 14 (LSB), 15, 20, 21 */
4287 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(11),
4288 POW_SM(pPwrArray[ALL_TARGET_HT40_21], 24) |
4289 POW_SM(pPwrArray[ALL_TARGET_HT40_20], 16) |
4290 POW_SM(pPwrArray[ALL_TARGET_HT40_15], 8) |
4291 POW_SM(pPwrArray[ALL_TARGET_HT40_14], 0)
4292 );
4293
4294 return 0;
4295 #undef POW_SM
4296 }
4297
4298 static void ar9003_hw_get_legacy_target_powers(struct ath_hw *ah, u16 freq,
4299 u8 *targetPowerValT2,
4300 bool is2GHz)
4301 {
4302 targetPowerValT2[ALL_TARGET_LEGACY_6_24] =
4303 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_6_24, freq,
4304 is2GHz);
4305 targetPowerValT2[ALL_TARGET_LEGACY_36] =
4306 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_36, freq,
4307 is2GHz);
4308 targetPowerValT2[ALL_TARGET_LEGACY_48] =
4309 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_48, freq,
4310 is2GHz);
4311 targetPowerValT2[ALL_TARGET_LEGACY_54] =
4312 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_54, freq,
4313 is2GHz);
4314 }
4315
4316 static void ar9003_hw_get_cck_target_powers(struct ath_hw *ah, u16 freq,
4317 u8 *targetPowerValT2)
4318 {
4319 targetPowerValT2[ALL_TARGET_LEGACY_1L_5L] =
4320 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_1L_5L,
4321 freq);
4322 targetPowerValT2[ALL_TARGET_LEGACY_5S] =
4323 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_5S, freq);
4324 targetPowerValT2[ALL_TARGET_LEGACY_11L] =
4325 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11L, freq);
4326 targetPowerValT2[ALL_TARGET_LEGACY_11S] =
4327 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11S, freq);
4328 }
4329
4330 static void ar9003_hw_get_ht20_target_powers(struct ath_hw *ah, u16 freq,
4331 u8 *targetPowerValT2, bool is2GHz)
4332 {
4333 targetPowerValT2[ALL_TARGET_HT20_0_8_16] =
4334 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
4335 is2GHz);
4336 targetPowerValT2[ALL_TARGET_HT20_1_3_9_11_17_19] =
4337 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
4338 freq, is2GHz);
4339 targetPowerValT2[ALL_TARGET_HT20_4] =
4340 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
4341 is2GHz);
4342 targetPowerValT2[ALL_TARGET_HT20_5] =
4343 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
4344 is2GHz);
4345 targetPowerValT2[ALL_TARGET_HT20_6] =
4346 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
4347 is2GHz);
4348 targetPowerValT2[ALL_TARGET_HT20_7] =
4349 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
4350 is2GHz);
4351 targetPowerValT2[ALL_TARGET_HT20_12] =
4352 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
4353 is2GHz);
4354 targetPowerValT2[ALL_TARGET_HT20_13] =
4355 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
4356 is2GHz);
4357 targetPowerValT2[ALL_TARGET_HT20_14] =
4358 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
4359 is2GHz);
4360 targetPowerValT2[ALL_TARGET_HT20_15] =
4361 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
4362 is2GHz);
4363 targetPowerValT2[ALL_TARGET_HT20_20] =
4364 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
4365 is2GHz);
4366 targetPowerValT2[ALL_TARGET_HT20_21] =
4367 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
4368 is2GHz);
4369 targetPowerValT2[ALL_TARGET_HT20_22] =
4370 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
4371 is2GHz);
4372 targetPowerValT2[ALL_TARGET_HT20_23] =
4373 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
4374 is2GHz);
4375 }
4376
4377 static void ar9003_hw_get_ht40_target_powers(struct ath_hw *ah,
4378 u16 freq,
4379 u8 *targetPowerValT2,
4380 bool is2GHz)
4381 {
4382 /* XXX: hard code for now, need to get from eeprom struct */
4383 u8 ht40PowerIncForPdadc = 0;
4384
4385 targetPowerValT2[ALL_TARGET_HT40_0_8_16] =
4386 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
4387 is2GHz) + ht40PowerIncForPdadc;
4388 targetPowerValT2[ALL_TARGET_HT40_1_3_9_11_17_19] =
4389 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
4390 freq,
4391 is2GHz) + ht40PowerIncForPdadc;
4392 targetPowerValT2[ALL_TARGET_HT40_4] =
4393 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
4394 is2GHz) + ht40PowerIncForPdadc;
4395 targetPowerValT2[ALL_TARGET_HT40_5] =
4396 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
4397 is2GHz) + ht40PowerIncForPdadc;
4398 targetPowerValT2[ALL_TARGET_HT40_6] =
4399 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
4400 is2GHz) + ht40PowerIncForPdadc;
4401 targetPowerValT2[ALL_TARGET_HT40_7] =
4402 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
4403 is2GHz) + ht40PowerIncForPdadc;
4404 targetPowerValT2[ALL_TARGET_HT40_12] =
4405 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
4406 is2GHz) + ht40PowerIncForPdadc;
4407 targetPowerValT2[ALL_TARGET_HT40_13] =
4408 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
4409 is2GHz) + ht40PowerIncForPdadc;
4410 targetPowerValT2[ALL_TARGET_HT40_14] =
4411 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
4412 is2GHz) + ht40PowerIncForPdadc;
4413 targetPowerValT2[ALL_TARGET_HT40_15] =
4414 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
4415 is2GHz) + ht40PowerIncForPdadc;
4416 targetPowerValT2[ALL_TARGET_HT40_20] =
4417 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
4418 is2GHz) + ht40PowerIncForPdadc;
4419 targetPowerValT2[ALL_TARGET_HT40_21] =
4420 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
4421 is2GHz) + ht40PowerIncForPdadc;
4422 targetPowerValT2[ALL_TARGET_HT40_22] =
4423 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
4424 is2GHz) + ht40PowerIncForPdadc;
4425 targetPowerValT2[ALL_TARGET_HT40_23] =
4426 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
4427 is2GHz) + ht40PowerIncForPdadc;
4428 }
4429
4430 static void ar9003_hw_get_target_power_eeprom(struct ath_hw *ah,
4431 struct ath9k_channel *chan,
4432 u8 *targetPowerValT2)
4433 {
4434 bool is2GHz = IS_CHAN_2GHZ(chan);
4435 unsigned int i = 0;
4436 struct ath_common *common = ath9k_hw_common(ah);
4437 u16 freq = chan->channel;
4438
4439 if (is2GHz)
4440 ar9003_hw_get_cck_target_powers(ah, freq, targetPowerValT2);
4441
4442 ar9003_hw_get_legacy_target_powers(ah, freq, targetPowerValT2, is2GHz);
4443 ar9003_hw_get_ht20_target_powers(ah, freq, targetPowerValT2, is2GHz);
4444
4445 if (IS_CHAN_HT40(chan))
4446 ar9003_hw_get_ht40_target_powers(ah, freq, targetPowerValT2,
4447 is2GHz);
4448
4449 for (i = 0; i < ar9300RateSize; i++) {
4450 ath_dbg(common, EEPROM, "TPC[%02d] 0x%08x\n",
4451 i, targetPowerValT2[i]);
4452 }
4453 }
4454
4455 static int ar9003_hw_cal_pier_get(struct ath_hw *ah,
4456 int mode,
4457 int ipier,
4458 int ichain,
4459 int *pfrequency,
4460 int *pcorrection,
4461 int *ptemperature, int *pvoltage)
4462 {
4463 u8 *pCalPier;
4464 struct ar9300_cal_data_per_freq_op_loop *pCalPierStruct;
4465 int is2GHz;
4466 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4467 struct ath_common *common = ath9k_hw_common(ah);
4468
4469 if (ichain >= AR9300_MAX_CHAINS) {
4470 ath_dbg(common, EEPROM,
4471 "Invalid chain index, must be less than %d\n",
4472 AR9300_MAX_CHAINS);
4473 return -1;
4474 }
4475
4476 if (mode) { /* 5GHz */
4477 if (ipier >= AR9300_NUM_5G_CAL_PIERS) {
4478 ath_dbg(common, EEPROM,
4479 "Invalid 5GHz cal pier index, must be less than %d\n",
4480 AR9300_NUM_5G_CAL_PIERS);
4481 return -1;
4482 }
4483 pCalPier = &(eep->calFreqPier5G[ipier]);
4484 pCalPierStruct = &(eep->calPierData5G[ichain][ipier]);
4485 is2GHz = 0;
4486 } else {
4487 if (ipier >= AR9300_NUM_2G_CAL_PIERS) {
4488 ath_dbg(common, EEPROM,
4489 "Invalid 2GHz cal pier index, must be less than %d\n",
4490 AR9300_NUM_2G_CAL_PIERS);
4491 return -1;
4492 }
4493
4494 pCalPier = &(eep->calFreqPier2G[ipier]);
4495 pCalPierStruct = &(eep->calPierData2G[ichain][ipier]);
4496 is2GHz = 1;
4497 }
4498
4499 *pfrequency = ath9k_hw_fbin2freq(*pCalPier, is2GHz);
4500 *pcorrection = pCalPierStruct->refPower;
4501 *ptemperature = pCalPierStruct->tempMeas;
4502 *pvoltage = pCalPierStruct->voltMeas;
4503
4504 return 0;
4505 }
4506
4507 static int ar9003_hw_power_control_override(struct ath_hw *ah,
4508 int frequency,
4509 int *correction,
4510 int *voltage, int *temperature)
4511 {
4512 int tempSlope = 0;
4513 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4514 int f[3], t[3];
4515
4516 REG_RMW(ah, AR_PHY_TPC_11_B0,
4517 (correction[0] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4518 AR_PHY_TPC_OLPC_GAIN_DELTA);
4519 if (ah->caps.tx_chainmask & BIT(1))
4520 REG_RMW(ah, AR_PHY_TPC_11_B1,
4521 (correction[1] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4522 AR_PHY_TPC_OLPC_GAIN_DELTA);
4523 if (ah->caps.tx_chainmask & BIT(2))
4524 REG_RMW(ah, AR_PHY_TPC_11_B2,
4525 (correction[2] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4526 AR_PHY_TPC_OLPC_GAIN_DELTA);
4527
4528 /* enable open loop power control on chip */
4529 REG_RMW(ah, AR_PHY_TPC_6_B0,
4530 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4531 AR_PHY_TPC_6_ERROR_EST_MODE);
4532 if (ah->caps.tx_chainmask & BIT(1))
4533 REG_RMW(ah, AR_PHY_TPC_6_B1,
4534 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4535 AR_PHY_TPC_6_ERROR_EST_MODE);
4536 if (ah->caps.tx_chainmask & BIT(2))
4537 REG_RMW(ah, AR_PHY_TPC_6_B2,
4538 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4539 AR_PHY_TPC_6_ERROR_EST_MODE);
4540
4541 /*
4542 * enable temperature compensation
4543 * Need to use register names
4544 */
4545 if (frequency < 4000)
4546 tempSlope = eep->modalHeader2G.tempSlope;
4547 else if (eep->base_ext2.tempSlopeLow != 0) {
4548 t[0] = eep->base_ext2.tempSlopeLow;
4549 f[0] = 5180;
4550 t[1] = eep->modalHeader5G.tempSlope;
4551 f[1] = 5500;
4552 t[2] = eep->base_ext2.tempSlopeHigh;
4553 f[2] = 5785;
4554 tempSlope = ar9003_hw_power_interpolate((s32) frequency,
4555 f, t, 3);
4556 } else
4557 tempSlope = eep->modalHeader5G.tempSlope;
4558
4559 REG_RMW_FIELD(ah, AR_PHY_TPC_19, AR_PHY_TPC_19_ALPHA_THERM, tempSlope);
4560
4561 if (AR_SREV_9462_20(ah))
4562 REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1,
4563 AR_PHY_TPC_19_B1_ALPHA_THERM, tempSlope);
4564
4565
4566 REG_RMW_FIELD(ah, AR_PHY_TPC_18, AR_PHY_TPC_18_THERM_CAL_VALUE,
4567 temperature[0]);
4568
4569 return 0;
4570 }
4571
4572 /* Apply the recorded correction values. */
4573 static int ar9003_hw_calibration_apply(struct ath_hw *ah, int frequency)
4574 {
4575 int ichain, ipier, npier;
4576 int mode;
4577 int lfrequency[AR9300_MAX_CHAINS],
4578 lcorrection[AR9300_MAX_CHAINS],
4579 ltemperature[AR9300_MAX_CHAINS], lvoltage[AR9300_MAX_CHAINS];
4580 int hfrequency[AR9300_MAX_CHAINS],
4581 hcorrection[AR9300_MAX_CHAINS],
4582 htemperature[AR9300_MAX_CHAINS], hvoltage[AR9300_MAX_CHAINS];
4583 int fdiff;
4584 int correction[AR9300_MAX_CHAINS],
4585 voltage[AR9300_MAX_CHAINS], temperature[AR9300_MAX_CHAINS];
4586 int pfrequency, pcorrection, ptemperature, pvoltage;
4587 struct ath_common *common = ath9k_hw_common(ah);
4588
4589 mode = (frequency >= 4000);
4590 if (mode)
4591 npier = AR9300_NUM_5G_CAL_PIERS;
4592 else
4593 npier = AR9300_NUM_2G_CAL_PIERS;
4594
4595 for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4596 lfrequency[ichain] = 0;
4597 hfrequency[ichain] = 100000;
4598 }
4599 /* identify best lower and higher frequency calibration measurement */
4600 for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4601 for (ipier = 0; ipier < npier; ipier++) {
4602 if (!ar9003_hw_cal_pier_get(ah, mode, ipier, ichain,
4603 &pfrequency, &pcorrection,
4604 &ptemperature, &pvoltage)) {
4605 fdiff = frequency - pfrequency;
4606
4607 /*
4608 * this measurement is higher than
4609 * our desired frequency
4610 */
4611 if (fdiff <= 0) {
4612 if (hfrequency[ichain] <= 0 ||
4613 hfrequency[ichain] >= 100000 ||
4614 fdiff >
4615 (frequency - hfrequency[ichain])) {
4616 /*
4617 * new best higher
4618 * frequency measurement
4619 */
4620 hfrequency[ichain] = pfrequency;
4621 hcorrection[ichain] =
4622 pcorrection;
4623 htemperature[ichain] =
4624 ptemperature;
4625 hvoltage[ichain] = pvoltage;
4626 }
4627 }
4628 if (fdiff >= 0) {
4629 if (lfrequency[ichain] <= 0
4630 || fdiff <
4631 (frequency - lfrequency[ichain])) {
4632 /*
4633 * new best lower
4634 * frequency measurement
4635 */
4636 lfrequency[ichain] = pfrequency;
4637 lcorrection[ichain] =
4638 pcorrection;
4639 ltemperature[ichain] =
4640 ptemperature;
4641 lvoltage[ichain] = pvoltage;
4642 }
4643 }
4644 }
4645 }
4646 }
4647
4648 /* interpolate */
4649 for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4650 ath_dbg(common, EEPROM, "ch=%d f=%d low=%d %d h=%d %d\n",
4651 ichain, frequency, lfrequency[ichain],
4652 lcorrection[ichain], hfrequency[ichain],
4653 hcorrection[ichain]);
4654 /* they're the same, so just pick one */
4655 if (hfrequency[ichain] == lfrequency[ichain]) {
4656 correction[ichain] = lcorrection[ichain];
4657 voltage[ichain] = lvoltage[ichain];
4658 temperature[ichain] = ltemperature[ichain];
4659 }
4660 /* the low frequency is good */
4661 else if (frequency - lfrequency[ichain] < 1000) {
4662 /* so is the high frequency, interpolate */
4663 if (hfrequency[ichain] - frequency < 1000) {
4664
4665 correction[ichain] = interpolate(frequency,
4666 lfrequency[ichain],
4667 hfrequency[ichain],
4668 lcorrection[ichain],
4669 hcorrection[ichain]);
4670
4671 temperature[ichain] = interpolate(frequency,
4672 lfrequency[ichain],
4673 hfrequency[ichain],
4674 ltemperature[ichain],
4675 htemperature[ichain]);
4676
4677 voltage[ichain] = interpolate(frequency,
4678 lfrequency[ichain],
4679 hfrequency[ichain],
4680 lvoltage[ichain],
4681 hvoltage[ichain]);
4682 }
4683 /* only low is good, use it */
4684 else {
4685 correction[ichain] = lcorrection[ichain];
4686 temperature[ichain] = ltemperature[ichain];
4687 voltage[ichain] = lvoltage[ichain];
4688 }
4689 }
4690 /* only high is good, use it */
4691 else if (hfrequency[ichain] - frequency < 1000) {
4692 correction[ichain] = hcorrection[ichain];
4693 temperature[ichain] = htemperature[ichain];
4694 voltage[ichain] = hvoltage[ichain];
4695 } else { /* nothing is good, presume 0???? */
4696 correction[ichain] = 0;
4697 temperature[ichain] = 0;
4698 voltage[ichain] = 0;
4699 }
4700 }
4701
4702 ar9003_hw_power_control_override(ah, frequency, correction, voltage,
4703 temperature);
4704
4705 ath_dbg(common, EEPROM,
4706 "for frequency=%d, calibration correction = %d %d %d\n",
4707 frequency, correction[0], correction[1], correction[2]);
4708
4709 return 0;
4710 }
4711
4712 static u16 ar9003_hw_get_direct_edge_power(struct ar9300_eeprom *eep,
4713 int idx,
4714 int edge,
4715 bool is2GHz)
4716 {
4717 struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G;
4718 struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;
4719
4720 if (is2GHz)
4721 return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge]);
4722 else
4723 return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge]);
4724 }
4725
4726 static u16 ar9003_hw_get_indirect_edge_power(struct ar9300_eeprom *eep,
4727 int idx,
4728 unsigned int edge,
4729 u16 freq,
4730 bool is2GHz)
4731 {
4732 struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G;
4733 struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;
4734
4735 u8 *ctl_freqbin = is2GHz ?
4736 &eep->ctl_freqbin_2G[idx][0] :
4737 &eep->ctl_freqbin_5G[idx][0];
4738
4739 if (is2GHz) {
4740 if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 1) < freq &&
4741 CTL_EDGE_FLAGS(ctl_2g[idx].ctlEdges[edge - 1]))
4742 return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge - 1]);
4743 } else {
4744 if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 0) < freq &&
4745 CTL_EDGE_FLAGS(ctl_5g[idx].ctlEdges[edge - 1]))
4746 return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge - 1]);
4747 }
4748
4749 return MAX_RATE_POWER;
4750 }
4751
4752 /*
4753 * Find the maximum conformance test limit for the given channel and CTL info
4754 */
4755 static u16 ar9003_hw_get_max_edge_power(struct ar9300_eeprom *eep,
4756 u16 freq, int idx, bool is2GHz)
4757 {
4758 u16 twiceMaxEdgePower = MAX_RATE_POWER;
4759 u8 *ctl_freqbin = is2GHz ?
4760 &eep->ctl_freqbin_2G[idx][0] :
4761 &eep->ctl_freqbin_5G[idx][0];
4762 u16 num_edges = is2GHz ?
4763 AR9300_NUM_BAND_EDGES_2G : AR9300_NUM_BAND_EDGES_5G;
4764 unsigned int edge;
4765
4766 /* Get the edge power */
4767 for (edge = 0;
4768 (edge < num_edges) && (ctl_freqbin[edge] != AR5416_BCHAN_UNUSED);
4769 edge++) {
4770 /*
4771 * If there's an exact channel match or an inband flag set
4772 * on the lower channel use the given rdEdgePower
4773 */
4774 if (freq == ath9k_hw_fbin2freq(ctl_freqbin[edge], is2GHz)) {
4775 twiceMaxEdgePower =
4776 ar9003_hw_get_direct_edge_power(eep, idx,
4777 edge, is2GHz);
4778 break;
4779 } else if ((edge > 0) &&
4780 (freq < ath9k_hw_fbin2freq(ctl_freqbin[edge],
4781 is2GHz))) {
4782 twiceMaxEdgePower =
4783 ar9003_hw_get_indirect_edge_power(eep, idx,
4784 edge, freq,
4785 is2GHz);
4786 /*
4787 * Leave loop - no more affecting edges possible in
4788 * this monotonic increasing list
4789 */
4790 break;
4791 }
4792 }
4793 return twiceMaxEdgePower;
4794 }
4795
4796 static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah,
4797 struct ath9k_channel *chan,
4798 u8 *pPwrArray, u16 cfgCtl,
4799 u8 antenna_reduction,
4800 u16 powerLimit)
4801 {
4802 struct ath_common *common = ath9k_hw_common(ah);
4803 struct ar9300_eeprom *pEepData = &ah->eeprom.ar9300_eep;
4804 u16 twiceMaxEdgePower;
4805 int i;
4806 u16 scaledPower = 0, minCtlPower;
4807 static const u16 ctlModesFor11a[] = {
4808 CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40
4809 };
4810 static const u16 ctlModesFor11g[] = {
4811 CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT,
4812 CTL_11G_EXT, CTL_2GHT40
4813 };
4814 u16 numCtlModes;
4815 const u16 *pCtlMode;
4816 u16 ctlMode, freq;
4817 struct chan_centers centers;
4818 u8 *ctlIndex;
4819 u8 ctlNum;
4820 u16 twiceMinEdgePower;
4821 bool is2ghz = IS_CHAN_2GHZ(chan);
4822
4823 ath9k_hw_get_channel_centers(ah, chan, &centers);
4824 scaledPower = ath9k_hw_get_scaled_power(ah, powerLimit,
4825 antenna_reduction);
4826
4827 if (is2ghz) {
4828 /* Setup for CTL modes */
4829 /* CTL_11B, CTL_11G, CTL_2GHT20 */
4830 numCtlModes =
4831 ARRAY_SIZE(ctlModesFor11g) -
4832 SUB_NUM_CTL_MODES_AT_2G_40;
4833 pCtlMode = ctlModesFor11g;
4834 if (IS_CHAN_HT40(chan))
4835 /* All 2G CTL's */
4836 numCtlModes = ARRAY_SIZE(ctlModesFor11g);
4837 } else {
4838 /* Setup for CTL modes */
4839 /* CTL_11A, CTL_5GHT20 */
4840 numCtlModes = ARRAY_SIZE(ctlModesFor11a) -
4841 SUB_NUM_CTL_MODES_AT_5G_40;
4842 pCtlMode = ctlModesFor11a;
4843 if (IS_CHAN_HT40(chan))
4844 /* All 5G CTL's */
4845 numCtlModes = ARRAY_SIZE(ctlModesFor11a);
4846 }
4847
4848 /*
4849 * For MIMO, need to apply regulatory caps individually across
4850 * dynamically running modes: CCK, OFDM, HT20, HT40
4851 *
4852 * The outer loop walks through each possible applicable runtime mode.
4853 * The inner loop walks through each ctlIndex entry in EEPROM.
4854 * The ctl value is encoded as [7:4] == test group, [3:0] == test mode.
4855 */
4856 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
4857 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
4858 (pCtlMode[ctlMode] == CTL_2GHT40);
4859 if (isHt40CtlMode)
4860 freq = centers.synth_center;
4861 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
4862 freq = centers.ext_center;
4863 else
4864 freq = centers.ctl_center;
4865
4866 ath_dbg(common, REGULATORY,
4867 "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, EXT_ADDITIVE %d\n",
4868 ctlMode, numCtlModes, isHt40CtlMode,
4869 (pCtlMode[ctlMode] & EXT_ADDITIVE));
4870
4871 /* walk through each CTL index stored in EEPROM */
4872 if (is2ghz) {
4873 ctlIndex = pEepData->ctlIndex_2G;
4874 ctlNum = AR9300_NUM_CTLS_2G;
4875 } else {
4876 ctlIndex = pEepData->ctlIndex_5G;
4877 ctlNum = AR9300_NUM_CTLS_5G;
4878 }
4879
4880 twiceMaxEdgePower = MAX_RATE_POWER;
4881 for (i = 0; (i < ctlNum) && ctlIndex[i]; i++) {
4882 ath_dbg(common, REGULATORY,
4883 "LOOP-Ctlidx %d: cfgCtl 0x%2.2x pCtlMode 0x%2.2x ctlIndex 0x%2.2x chan %d\n",
4884 i, cfgCtl, pCtlMode[ctlMode], ctlIndex[i],
4885 chan->channel);
4886
4887 /*
4888 * compare test group from regulatory
4889 * channel list with test mode from pCtlMode
4890 * list
4891 */
4892 if ((((cfgCtl & ~CTL_MODE_M) |
4893 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4894 ctlIndex[i]) ||
4895 (((cfgCtl & ~CTL_MODE_M) |
4896 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4897 ((ctlIndex[i] & CTL_MODE_M) |
4898 SD_NO_CTL))) {
4899 twiceMinEdgePower =
4900 ar9003_hw_get_max_edge_power(pEepData,
4901 freq, i,
4902 is2ghz);
4903
4904 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL)
4905 /*
4906 * Find the minimum of all CTL
4907 * edge powers that apply to
4908 * this channel
4909 */
4910 twiceMaxEdgePower =
4911 min(twiceMaxEdgePower,
4912 twiceMinEdgePower);
4913 else {
4914 /* specific */
4915 twiceMaxEdgePower =
4916 twiceMinEdgePower;
4917 break;
4918 }
4919 }
4920 }
4921
4922 minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
4923
4924 ath_dbg(common, REGULATORY,
4925 "SEL-Min ctlMode %d pCtlMode %d 2xMaxEdge %d sP %d minCtlPwr %d\n",
4926 ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
4927 scaledPower, minCtlPower);
4928
4929 /* Apply ctl mode to correct target power set */
4930 switch (pCtlMode[ctlMode]) {
4931 case CTL_11B:
4932 for (i = ALL_TARGET_LEGACY_1L_5L;
4933 i <= ALL_TARGET_LEGACY_11S; i++)
4934 pPwrArray[i] =
4935 (u8)min((u16)pPwrArray[i],
4936 minCtlPower);
4937 break;
4938 case CTL_11A:
4939 case CTL_11G:
4940 for (i = ALL_TARGET_LEGACY_6_24;
4941 i <= ALL_TARGET_LEGACY_54; i++)
4942 pPwrArray[i] =
4943 (u8)min((u16)pPwrArray[i],
4944 minCtlPower);
4945 break;
4946 case CTL_5GHT20:
4947 case CTL_2GHT20:
4948 for (i = ALL_TARGET_HT20_0_8_16;
4949 i <= ALL_TARGET_HT20_21; i++)
4950 pPwrArray[i] =
4951 (u8)min((u16)pPwrArray[i],
4952 minCtlPower);
4953 pPwrArray[ALL_TARGET_HT20_22] =
4954 (u8)min((u16)pPwrArray[ALL_TARGET_HT20_22],
4955 minCtlPower);
4956 pPwrArray[ALL_TARGET_HT20_23] =
4957 (u8)min((u16)pPwrArray[ALL_TARGET_HT20_23],
4958 minCtlPower);
4959 break;
4960 case CTL_5GHT40:
4961 case CTL_2GHT40:
4962 for (i = ALL_TARGET_HT40_0_8_16;
4963 i <= ALL_TARGET_HT40_23; i++)
4964 pPwrArray[i] =
4965 (u8)min((u16)pPwrArray[i],
4966 minCtlPower);
4967 break;
4968 default:
4969 break;
4970 }
4971 } /* end ctl mode checking */
4972 }
4973
4974 static inline u8 mcsidx_to_tgtpwridx(unsigned int mcs_idx, u8 base_pwridx)
4975 {
4976 u8 mod_idx = mcs_idx % 8;
4977
4978 if (mod_idx <= 3)
4979 return mod_idx ? (base_pwridx + 1) : base_pwridx;
4980 else
4981 return base_pwridx + 4 * (mcs_idx / 8) + mod_idx - 2;
4982 }
4983
4984 static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah,
4985 struct ath9k_channel *chan, u16 cfgCtl,
4986 u8 twiceAntennaReduction,
4987 u8 powerLimit, bool test)
4988 {
4989 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
4990 struct ath_common *common = ath9k_hw_common(ah);
4991 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4992 struct ar9300_modal_eep_header *modal_hdr;
4993 u8 targetPowerValT2[ar9300RateSize];
4994 u8 target_power_val_t2_eep[ar9300RateSize];
4995 unsigned int i = 0, paprd_scale_factor = 0;
4996 u8 pwr_idx, min_pwridx = 0;
4997
4998 memset(targetPowerValT2, 0 , sizeof(targetPowerValT2));
4999
5000 /*
5001 * Get target powers from EEPROM - our baseline for TX Power
5002 */
5003 ar9003_hw_get_target_power_eeprom(ah, chan, targetPowerValT2);
5004
5005 if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) {
5006 if (IS_CHAN_2GHZ(chan))
5007 modal_hdr = &eep->modalHeader2G;
5008 else
5009 modal_hdr = &eep->modalHeader5G;
5010
5011 ah->paprd_ratemask =
5012 le32_to_cpu(modal_hdr->papdRateMaskHt20) &
5013 AR9300_PAPRD_RATE_MASK;
5014
5015 ah->paprd_ratemask_ht40 =
5016 le32_to_cpu(modal_hdr->papdRateMaskHt40) &
5017 AR9300_PAPRD_RATE_MASK;
5018
5019 paprd_scale_factor = ar9003_get_paprd_scale_factor(ah, chan);
5020 min_pwridx = IS_CHAN_HT40(chan) ? ALL_TARGET_HT40_0_8_16 :
5021 ALL_TARGET_HT20_0_8_16;
5022
5023 if (!ah->paprd_table_write_done) {
5024 memcpy(target_power_val_t2_eep, targetPowerValT2,
5025 sizeof(targetPowerValT2));
5026 for (i = 0; i < 24; i++) {
5027 pwr_idx = mcsidx_to_tgtpwridx(i, min_pwridx);
5028 if (ah->paprd_ratemask & (1 << i)) {
5029 if (targetPowerValT2[pwr_idx] &&
5030 targetPowerValT2[pwr_idx] ==
5031 target_power_val_t2_eep[pwr_idx])
5032 targetPowerValT2[pwr_idx] -=
5033 paprd_scale_factor;
5034 }
5035 }
5036 }
5037 memcpy(target_power_val_t2_eep, targetPowerValT2,
5038 sizeof(targetPowerValT2));
5039 }
5040
5041 ar9003_hw_set_power_per_rate_table(ah, chan,
5042 targetPowerValT2, cfgCtl,
5043 twiceAntennaReduction,
5044 powerLimit);
5045
5046 if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) {
5047 for (i = 0; i < ar9300RateSize; i++) {
5048 if ((ah->paprd_ratemask & (1 << i)) &&
5049 (abs(targetPowerValT2[i] -
5050 target_power_val_t2_eep[i]) >
5051 paprd_scale_factor)) {
5052 ah->paprd_ratemask &= ~(1 << i);
5053 ath_dbg(common, EEPROM,
5054 "paprd disabled for mcs %d\n", i);
5055 }
5056 }
5057 }
5058
5059 regulatory->max_power_level = 0;
5060 for (i = 0; i < ar9300RateSize; i++) {
5061 if (targetPowerValT2[i] > regulatory->max_power_level)
5062 regulatory->max_power_level = targetPowerValT2[i];
5063 }
5064
5065 ath9k_hw_update_regulatory_maxpower(ah);
5066
5067 if (test)
5068 return;
5069
5070 for (i = 0; i < ar9300RateSize; i++) {
5071 ath_dbg(common, EEPROM, "TPC[%02d] 0x%08x\n",
5072 i, targetPowerValT2[i]);
5073 }
5074
5075 /* Write target power array to registers */
5076 ar9003_hw_tx_power_regwrite(ah, targetPowerValT2);
5077 ar9003_hw_calibration_apply(ah, chan->channel);
5078
5079 if (IS_CHAN_2GHZ(chan)) {
5080 if (IS_CHAN_HT40(chan))
5081 i = ALL_TARGET_HT40_0_8_16;
5082 else
5083 i = ALL_TARGET_HT20_0_8_16;
5084 } else {
5085 if (IS_CHAN_HT40(chan))
5086 i = ALL_TARGET_HT40_7;
5087 else
5088 i = ALL_TARGET_HT20_7;
5089 }
5090 ah->paprd_target_power = targetPowerValT2[i];
5091 }
5092
5093 static u16 ath9k_hw_ar9300_get_spur_channel(struct ath_hw *ah,
5094 u16 i, bool is2GHz)
5095 {
5096 return AR_NO_SPUR;
5097 }
5098
5099 s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah)
5100 {
5101 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
5102
5103 return (eep->baseEepHeader.txrxgain >> 4) & 0xf; /* bits 7:4 */
5104 }
5105
5106 s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah)
5107 {
5108 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
5109
5110 return (eep->baseEepHeader.txrxgain) & 0xf; /* bits 3:0 */
5111 }
5112
5113 u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is_2ghz)
5114 {
5115 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
5116
5117 if (is_2ghz)
5118 return eep->modalHeader2G.spurChans;
5119 else
5120 return eep->modalHeader5G.spurChans;
5121 }
5122
5123 unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah,
5124 struct ath9k_channel *chan)
5125 {
5126 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
5127
5128 if (IS_CHAN_2GHZ(chan))
5129 return MS(le32_to_cpu(eep->modalHeader2G.papdRateMaskHt20),
5130 AR9300_PAPRD_SCALE_1);
5131 else {
5132 if (chan->channel >= 5700)
5133 return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt20),
5134 AR9300_PAPRD_SCALE_1);
5135 else if (chan->channel >= 5400)
5136 return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt40),
5137 AR9300_PAPRD_SCALE_2);
5138 else
5139 return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt40),
5140 AR9300_PAPRD_SCALE_1);
5141 }
5142 }
5143
5144 const struct eeprom_ops eep_ar9300_ops = {
5145 .check_eeprom = ath9k_hw_ar9300_check_eeprom,
5146 .get_eeprom = ath9k_hw_ar9300_get_eeprom,
5147 .fill_eeprom = ath9k_hw_ar9300_fill_eeprom,
5148 .dump_eeprom = ath9k_hw_ar9003_dump_eeprom,
5149 .get_eeprom_ver = ath9k_hw_ar9300_get_eeprom_ver,
5150 .get_eeprom_rev = ath9k_hw_ar9300_get_eeprom_rev,
5151 .set_board_values = ath9k_hw_ar9300_set_board_values,
5152 .set_addac = ath9k_hw_ar9300_set_addac,
5153 .set_txpower = ath9k_hw_ar9300_set_txpower,
5154 .get_spur_channel = ath9k_hw_ar9300_get_spur_channel
5155 };
Linux 2.6 libata-dev (mirror)