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iwl3945 : Fix a-band association for passive channels
[linux-2.6/libata-dev.git] / drivers / net / wireless / iwlwifi / iwl-tx.c
blob18d6cf67d9b786e639ce39ca783d77eab7976e12
1 /******************************************************************************
2 *
3 * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
30 #include <linux/etherdevice.h>
31 #include <net/mac80211.h>
32 #include "iwl-eeprom.h"
33 #include "iwl-dev.h"
34 #include "iwl-core.h"
35 #include "iwl-sta.h"
36 #include "iwl-io.h"
37 #include "iwl-helpers.h"
38
39 static const u16 default_tid_to_tx_fifo[] = {
40 IWL_TX_FIFO_AC1,
41 IWL_TX_FIFO_AC0,
42 IWL_TX_FIFO_AC0,
43 IWL_TX_FIFO_AC1,
44 IWL_TX_FIFO_AC2,
45 IWL_TX_FIFO_AC2,
46 IWL_TX_FIFO_AC3,
47 IWL_TX_FIFO_AC3,
48 IWL_TX_FIFO_NONE,
49 IWL_TX_FIFO_NONE,
50 IWL_TX_FIFO_NONE,
51 IWL_TX_FIFO_NONE,
52 IWL_TX_FIFO_NONE,
53 IWL_TX_FIFO_NONE,
54 IWL_TX_FIFO_NONE,
55 IWL_TX_FIFO_NONE,
56 IWL_TX_FIFO_AC3
57 };
58
59 static inline int iwl_alloc_dma_ptr(struct iwl_priv *priv,
60 struct iwl_dma_ptr *ptr, size_t size)
61 {
62 ptr->addr = pci_alloc_consistent(priv->pci_dev, size, &ptr->dma);
63 if (!ptr->addr)
64 return -ENOMEM;
65 ptr->size = size;
66 return 0;
67 }
68
69 static inline void iwl_free_dma_ptr(struct iwl_priv *priv,
70 struct iwl_dma_ptr *ptr)
71 {
72 if (unlikely(!ptr->addr))
73 return;
74
75 pci_free_consistent(priv->pci_dev, ptr->size, ptr->addr, ptr->dma);
76 memset(ptr, 0, sizeof(*ptr));
77 }
78
79 static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
80 {
81 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
82
83 dma_addr_t addr = get_unaligned_le32(&tb->lo);
84 if (sizeof(dma_addr_t) > sizeof(u32))
85 addr |=
86 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
87
88 return addr;
89 }
90
91 static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
92 {
93 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
94
95 return le16_to_cpu(tb->hi_n_len) >> 4;
96 }
97
98 static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
99 dma_addr_t addr, u16 len)
100 {
101 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
102 u16 hi_n_len = len << 4;
103
104 put_unaligned_le32(addr, &tb->lo);
105 if (sizeof(dma_addr_t) > sizeof(u32))
106 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
107
108 tb->hi_n_len = cpu_to_le16(hi_n_len);
109
110 tfd->num_tbs = idx + 1;
111 }
112
113 static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
114 {
115 return tfd->num_tbs & 0x1f;
116 }
117
118 /**
119 * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
120 * @priv - driver private data
121 * @txq - tx queue
122 *
123 * Does NOT advance any TFD circular buffer read/write indexes
124 * Does NOT free the TFD itself (which is within circular buffer)
125 */
126 static void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
127 {
128 struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)&txq->tfds[0];
129 struct iwl_tfd *tfd;
130 struct pci_dev *dev = priv->pci_dev;
131 int index = txq->q.read_ptr;
132 int i;
133 int num_tbs;
134
135 tfd = &tfd_tmp[index];
136
137 /* Sanity check on number of chunks */
138 num_tbs = iwl_tfd_get_num_tbs(tfd);
139
140 if (num_tbs >= IWL_NUM_OF_TBS) {
141 IWL_ERROR("Too many chunks: %i\n", num_tbs);
142 /* @todo issue fatal error, it is quite serious situation */
143 return;
144 }
145
146 /* Unmap tx_cmd */
147 if (num_tbs)
148 pci_unmap_single(dev,
149 pci_unmap_addr(&txq->cmd[index]->meta, mapping),
150 pci_unmap_len(&txq->cmd[index]->meta, len),
151 PCI_DMA_TODEVICE);
152
153 /* Unmap chunks, if any. */
154 for (i = 1; i < num_tbs; i++) {
155 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
156 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
157
158 if (txq->txb) {
159 dev_kfree_skb(txq->txb[txq->q.read_ptr].skb[i - 1]);
160 txq->txb[txq->q.read_ptr].skb[i - 1] = NULL;
161 }
162 }
163 }
164
165 static int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
166 struct iwl_tfd *tfd,
167 dma_addr_t addr, u16 len)
168 {
169
170 u32 num_tbs = iwl_tfd_get_num_tbs(tfd);
171
172 /* Each TFD can point to a maximum 20 Tx buffers */
173 if (num_tbs >= IWL_NUM_OF_TBS) {
174 IWL_ERROR("Error can not send more than %d chunks\n",
175 IWL_NUM_OF_TBS);
176 return -EINVAL;
177 }
178
179 BUG_ON(addr & ~DMA_BIT_MASK(36));
180 if (unlikely(addr & ~IWL_TX_DMA_MASK))
181 IWL_ERROR("Unaligned address = %llx\n",
182 (unsigned long long)addr);
183
184 iwl_tfd_set_tb(tfd, num_tbs, addr, len);
185
186 return 0;
187 }
188
189 /**
190 * iwl_txq_update_write_ptr - Send new write index to hardware
191 */
192 int iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq)
193 {
194 u32 reg = 0;
195 int ret = 0;
196 int txq_id = txq->q.id;
197
198 if (txq->need_update == 0)
199 return ret;
200
201 /* if we're trying to save power */
202 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
203 /* wake up nic if it's powered down ...
204 * uCode will wake up, and interrupt us again, so next
205 * time we'll skip this part. */
206 reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
207
208 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
209 IWL_DEBUG_INFO("Requesting wakeup, GP1 = 0x%x\n", reg);
210 iwl_set_bit(priv, CSR_GP_CNTRL,
211 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
212 return ret;
213 }
214
215 /* restore this queue's parameters in nic hardware. */
216 ret = iwl_grab_nic_access(priv);
217 if (ret)
218 return ret;
219 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
220 txq->q.write_ptr | (txq_id << 8));
221 iwl_release_nic_access(priv);
222
223 /* else not in power-save mode, uCode will never sleep when we're
224 * trying to tx (during RFKILL, we're not trying to tx). */
225 } else
226 iwl_write32(priv, HBUS_TARG_WRPTR,
227 txq->q.write_ptr | (txq_id << 8));
228
229 txq->need_update = 0;
230
231 return ret;
232 }
233 EXPORT_SYMBOL(iwl_txq_update_write_ptr);
234
235
236 /**
237 * iwl_tx_queue_free - Deallocate DMA queue.
238 * @txq: Transmit queue to deallocate.
239 *
240 * Empty queue by removing and destroying all BD's.
241 * Free all buffers.
242 * 0-fill, but do not free "txq" descriptor structure.
243 */
244 static void iwl_tx_queue_free(struct iwl_priv *priv, int txq_id)
245 {
246 struct iwl_tx_queue *txq = &priv->txq[txq_id];
247 struct iwl_queue *q = &txq->q;
248 struct pci_dev *dev = priv->pci_dev;
249 int i, len;
250
251 if (q->n_bd == 0)
252 return;
253
254 /* first, empty all BD's */
255 for (; q->write_ptr != q->read_ptr;
256 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd))
257 iwl_hw_txq_free_tfd(priv, txq);
258
259 len = sizeof(struct iwl_cmd) * q->n_window;
260
261 /* De-alloc array of command/tx buffers */
262 for (i = 0; i < TFD_TX_CMD_SLOTS; i++)
263 kfree(txq->cmd[i]);
264
265 /* De-alloc circular buffer of TFDs */
266 if (txq->q.n_bd)
267 pci_free_consistent(dev, sizeof(struct iwl_tfd) *
268 txq->q.n_bd, txq->tfds, txq->q.dma_addr);
269
270 /* De-alloc array of per-TFD driver data */
271 kfree(txq->txb);
272 txq->txb = NULL;
273
274 /* 0-fill queue descriptor structure */
275 memset(txq, 0, sizeof(*txq));
276 }
277
278
279 /**
280 * iwl_cmd_queue_free - Deallocate DMA queue.
281 * @txq: Transmit queue to deallocate.
282 *
283 * Empty queue by removing and destroying all BD's.
284 * Free all buffers.
285 * 0-fill, but do not free "txq" descriptor structure.
286 */
287 static void iwl_cmd_queue_free(struct iwl_priv *priv)
288 {
289 struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
290 struct iwl_queue *q = &txq->q;
291 struct pci_dev *dev = priv->pci_dev;
292 int i, len;
293
294 if (q->n_bd == 0)
295 return;
296
297 len = sizeof(struct iwl_cmd) * q->n_window;
298 len += IWL_MAX_SCAN_SIZE;
299
300 /* De-alloc array of command/tx buffers */
301 for (i = 0; i <= TFD_CMD_SLOTS; i++)
302 kfree(txq->cmd[i]);
303
304 /* De-alloc circular buffer of TFDs */
305 if (txq->q.n_bd)
306 pci_free_consistent(dev, sizeof(struct iwl_tfd) *
307 txq->q.n_bd, txq->tfds, txq->q.dma_addr);
308
309 /* 0-fill queue descriptor structure */
310 memset(txq, 0, sizeof(*txq));
311 }
312 /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
313 * DMA services
314 *
315 * Theory of operation
316 *
317 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
318 * of buffer descriptors, each of which points to one or more data buffers for
319 * the device to read from or fill. Driver and device exchange status of each
320 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
321 * entries in each circular buffer, to protect against confusing empty and full
322 * queue states.
323 *
324 * The device reads or writes the data in the queues via the device's several
325 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
326 *
327 * For Tx queue, there are low mark and high mark limits. If, after queuing
328 * the packet for Tx, free space become < low mark, Tx queue stopped. When
329 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
330 * Tx queue resumed.
331 *
332 * See more detailed info in iwl-4965-hw.h.
333 ***************************************************/
334
335 int iwl_queue_space(const struct iwl_queue *q)
336 {
337 int s = q->read_ptr - q->write_ptr;
338
339 if (q->read_ptr > q->write_ptr)
340 s -= q->n_bd;
341
342 if (s <= 0)
343 s += q->n_window;
344 /* keep some reserve to not confuse empty and full situations */
345 s -= 2;
346 if (s < 0)
347 s = 0;
348 return s;
349 }
350 EXPORT_SYMBOL(iwl_queue_space);
351
352
353 /**
354 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
355 */
356 static int iwl_queue_init(struct iwl_priv *priv, struct iwl_queue *q,
357 int count, int slots_num, u32 id)
358 {
359 q->n_bd = count;
360 q->n_window = slots_num;
361 q->id = id;
362
363 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
364 * and iwl_queue_dec_wrap are broken. */
365 BUG_ON(!is_power_of_2(count));
366
367 /* slots_num must be power-of-two size, otherwise
368 * get_cmd_index is broken. */
369 BUG_ON(!is_power_of_2(slots_num));
370
371 q->low_mark = q->n_window / 4;
372 if (q->low_mark < 4)
373 q->low_mark = 4;
374
375 q->high_mark = q->n_window / 8;
376 if (q->high_mark < 2)
377 q->high_mark = 2;
378
379 q->write_ptr = q->read_ptr = 0;
380
381 return 0;
382 }
383
384 /**
385 * iwl_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
386 */
387 static int iwl_tx_queue_alloc(struct iwl_priv *priv,
388 struct iwl_tx_queue *txq, u32 id)
389 {
390 struct pci_dev *dev = priv->pci_dev;
391
392 /* Driver private data, only for Tx (not command) queues,
393 * not shared with device. */
394 if (id != IWL_CMD_QUEUE_NUM) {
395 txq->txb = kmalloc(sizeof(txq->txb[0]) *
396 TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
397 if (!txq->txb) {
398 IWL_ERROR("kmalloc for auxiliary BD "
399 "structures failed\n");
400 goto error;
401 }
402 } else
403 txq->txb = NULL;
404
405 /* Circular buffer of transmit frame descriptors (TFDs),
406 * shared with device */
407 txq->tfds = pci_alloc_consistent(dev,
408 sizeof(txq->tfds[0]) * TFD_QUEUE_SIZE_MAX,
409 &txq->q.dma_addr);
410
411 if (!txq->tfds) {
412 IWL_ERROR("pci_alloc_consistent(%zd) failed\n",
413 sizeof(txq->tfds[0]) * TFD_QUEUE_SIZE_MAX);
414 goto error;
415 }
416 txq->q.id = id;
417
418 return 0;
419
420 error:
421 kfree(txq->txb);
422 txq->txb = NULL;
423
424 return -ENOMEM;
425 }
426
427 /*
428 * Tell nic where to find circular buffer of Tx Frame Descriptors for
429 * given Tx queue, and enable the DMA channel used for that queue.
430 *
431 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
432 * channels supported in hardware.
433 */
434 static int iwl_hw_tx_queue_init(struct iwl_priv *priv,
435 struct iwl_tx_queue *txq)
436 {
437 int ret;
438 unsigned long flags;
439 int txq_id = txq->q.id;
440
441 spin_lock_irqsave(&priv->lock, flags);
442 ret = iwl_grab_nic_access(priv);
443 if (ret) {
444 spin_unlock_irqrestore(&priv->lock, flags);
445 return ret;
446 }
447
448 /* Circular buffer (TFD queue in DRAM) physical base address */
449 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
450 txq->q.dma_addr >> 8);
451
452 iwl_release_nic_access(priv);
453 spin_unlock_irqrestore(&priv->lock, flags);
454
455 return 0;
456 }
457
458 /**
459 * iwl_tx_queue_init - Allocate and initialize one tx/cmd queue
460 */
461 static int iwl_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq,
462 int slots_num, u32 txq_id)
463 {
464 int i, len;
465 int ret;
466
467 /*
468 * Alloc buffer array for commands (Tx or other types of commands).
469 * For the command queue (#4), allocate command space + one big
470 * command for scan, since scan command is very huge; the system will
471 * not have two scans at the same time, so only one is needed.
472 * For normal Tx queues (all other queues), no super-size command
473 * space is needed.
474 */
475 len = sizeof(struct iwl_cmd);
476 for (i = 0; i <= slots_num; i++) {
477 if (i == slots_num) {
478 if (txq_id == IWL_CMD_QUEUE_NUM)
479 len += IWL_MAX_SCAN_SIZE;
480 else
481 continue;
482 }
483
484 txq->cmd[i] = kmalloc(len, GFP_KERNEL);
485 if (!txq->cmd[i])
486 goto err;
487 }
488
489 /* Alloc driver data array and TFD circular buffer */
490 ret = iwl_tx_queue_alloc(priv, txq, txq_id);
491 if (ret)
492 goto err;
493
494 txq->need_update = 0;
495
496 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
497 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
498 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
499
500 /* Initialize queue's high/low-water marks, and head/tail indexes */
501 iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
502
503 /* Tell device where to find queue */
504 iwl_hw_tx_queue_init(priv, txq);
505
506 return 0;
507 err:
508 for (i = 0; i < slots_num; i++) {
509 kfree(txq->cmd[i]);
510 txq->cmd[i] = NULL;
511 }
512
513 if (txq_id == IWL_CMD_QUEUE_NUM) {
514 kfree(txq->cmd[slots_num]);
515 txq->cmd[slots_num] = NULL;
516 }
517 return -ENOMEM;
518 }
519 /**
520 * iwl_hw_txq_ctx_free - Free TXQ Context
521 *
522 * Destroy all TX DMA queues and structures
523 */
524 void iwl_hw_txq_ctx_free(struct iwl_priv *priv)
525 {
526 int txq_id;
527
528 /* Tx queues */
529 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
530 if (txq_id == IWL_CMD_QUEUE_NUM)
531 iwl_cmd_queue_free(priv);
532 else
533 iwl_tx_queue_free(priv, txq_id);
534
535 iwl_free_dma_ptr(priv, &priv->kw);
536
537 iwl_free_dma_ptr(priv, &priv->scd_bc_tbls);
538 }
539 EXPORT_SYMBOL(iwl_hw_txq_ctx_free);
540
541 /**
542 * iwl_txq_ctx_reset - Reset TX queue context
543 * Destroys all DMA structures and initialize them again
544 *
545 * @param priv
546 * @return error code
547 */
548 int iwl_txq_ctx_reset(struct iwl_priv *priv)
549 {
550 int ret = 0;
551 int txq_id, slots_num;
552 unsigned long flags;
553
554 /* Free all tx/cmd queues and keep-warm buffer */
555 iwl_hw_txq_ctx_free(priv);
556
557 ret = iwl_alloc_dma_ptr(priv, &priv->scd_bc_tbls,
558 priv->hw_params.scd_bc_tbls_size);
559 if (ret) {
560 IWL_ERROR("Scheduler BC Table allocation failed\n");
561 goto error_bc_tbls;
562 }
563 /* Alloc keep-warm buffer */
564 ret = iwl_alloc_dma_ptr(priv, &priv->kw, IWL_KW_SIZE);
565 if (ret) {
566 IWL_ERROR("Keep Warm allocation failed\n");
567 goto error_kw;
568 }
569 spin_lock_irqsave(&priv->lock, flags);
570 ret = iwl_grab_nic_access(priv);
571 if (unlikely(ret)) {
572 spin_unlock_irqrestore(&priv->lock, flags);
573 goto error_reset;
574 }
575
576 /* Turn off all Tx DMA fifos */
577 priv->cfg->ops->lib->txq_set_sched(priv, 0);
578
579 /* Tell NIC where to find the "keep warm" buffer */
580 iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG, priv->kw.dma >> 4);
581
582 iwl_release_nic_access(priv);
583 spin_unlock_irqrestore(&priv->lock, flags);
584
585 /* Alloc and init all Tx queues, including the command queue (#4) */
586 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
587 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
588 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
589 ret = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
590 txq_id);
591 if (ret) {
592 IWL_ERROR("Tx %d queue init failed\n", txq_id);
593 goto error;
594 }
595 }
596
597 return ret;
598
599 error:
600 iwl_hw_txq_ctx_free(priv);
601 error_reset:
602 iwl_free_dma_ptr(priv, &priv->kw);
603 error_kw:
604 iwl_free_dma_ptr(priv, &priv->scd_bc_tbls);
605 error_bc_tbls:
606 return ret;
607 }
608
609 /**
610 * iwl_txq_ctx_stop - Stop all Tx DMA channels, free Tx queue memory
611 */
612 void iwl_txq_ctx_stop(struct iwl_priv *priv)
613 {
614 int ch;
615 unsigned long flags;
616
617 /* Turn off all Tx DMA fifos */
618 spin_lock_irqsave(&priv->lock, flags);
619 if (iwl_grab_nic_access(priv)) {
620 spin_unlock_irqrestore(&priv->lock, flags);
621 return;
622 }
623
624 priv->cfg->ops->lib->txq_set_sched(priv, 0);
625
626 /* Stop each Tx DMA channel, and wait for it to be idle */
627 for (ch = 0; ch < priv->hw_params.dma_chnl_num; ch++) {
628 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
629 iwl_poll_direct_bit(priv, FH_TSSR_TX_STATUS_REG,
630 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
631 200);
632 }
633 iwl_release_nic_access(priv);
634 spin_unlock_irqrestore(&priv->lock, flags);
635
636 /* Deallocate memory for all Tx queues */
637 iwl_hw_txq_ctx_free(priv);
638 }
639 EXPORT_SYMBOL(iwl_txq_ctx_stop);
640
641 /*
642 * handle build REPLY_TX command notification.
643 */
644 static void iwl_tx_cmd_build_basic(struct iwl_priv *priv,
645 struct iwl_tx_cmd *tx_cmd,
646 struct ieee80211_tx_info *info,
647 struct ieee80211_hdr *hdr,
648 int is_unicast, u8 std_id)
649 {
650 __le16 fc = hdr->frame_control;
651 __le32 tx_flags = tx_cmd->tx_flags;
652
653 tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
654 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
655 tx_flags |= TX_CMD_FLG_ACK_MSK;
656 if (ieee80211_is_mgmt(fc))
657 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
658 if (ieee80211_is_probe_resp(fc) &&
659 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
660 tx_flags |= TX_CMD_FLG_TSF_MSK;
661 } else {
662 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
663 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
664 }
665
666 if (ieee80211_is_back_req(fc))
667 tx_flags |= TX_CMD_FLG_ACK_MSK | TX_CMD_FLG_IMM_BA_RSP_MASK;
668
669
670 tx_cmd->sta_id = std_id;
671 if (ieee80211_has_morefrags(fc))
672 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
673
674 if (ieee80211_is_data_qos(fc)) {
675 u8 *qc = ieee80211_get_qos_ctl(hdr);
676 tx_cmd->tid_tspec = qc[0] & 0xf;
677 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
678 } else {
679 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
680 }
681
682 priv->cfg->ops->utils->rts_tx_cmd_flag(info, &tx_flags);
683
684 if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
685 tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
686
687 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
688 if (ieee80211_is_mgmt(fc)) {
689 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
690 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3);
691 else
692 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2);
693 } else {
694 tx_cmd->timeout.pm_frame_timeout = 0;
695 }
696
697 tx_cmd->driver_txop = 0;
698 tx_cmd->tx_flags = tx_flags;
699 tx_cmd->next_frame_len = 0;
700 }
701
702 #define RTS_HCCA_RETRY_LIMIT 3
703 #define RTS_DFAULT_RETRY_LIMIT 60
704
705 static void iwl_tx_cmd_build_rate(struct iwl_priv *priv,
706 struct iwl_tx_cmd *tx_cmd,
707 struct ieee80211_tx_info *info,
708 __le16 fc, int sta_id,
709 int is_hcca)
710 {
711 u32 rate_flags = 0;
712 int rate_idx;
713 u8 rts_retry_limit = 0;
714 u8 data_retry_limit = 0;
715 u8 rate_plcp;
716
717 rate_idx = min(ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xffff,
718 IWL_RATE_COUNT - 1);
719
720 rate_plcp = iwl_rates[rate_idx].plcp;
721
722 rts_retry_limit = (is_hcca) ?
723 RTS_HCCA_RETRY_LIMIT : RTS_DFAULT_RETRY_LIMIT;
724
725 if ((rate_idx >= IWL_FIRST_CCK_RATE) && (rate_idx <= IWL_LAST_CCK_RATE))
726 rate_flags |= RATE_MCS_CCK_MSK;
727
728
729 if (ieee80211_is_probe_resp(fc)) {
730 data_retry_limit = 3;
731 if (data_retry_limit < rts_retry_limit)
732 rts_retry_limit = data_retry_limit;
733 } else
734 data_retry_limit = IWL_DEFAULT_TX_RETRY;
735
736 if (priv->data_retry_limit != -1)
737 data_retry_limit = priv->data_retry_limit;
738
739
740 if (ieee80211_is_data(fc)) {
741 tx_cmd->initial_rate_index = 0;
742 tx_cmd->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
743 } else {
744 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
745 case cpu_to_le16(IEEE80211_STYPE_AUTH):
746 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
747 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
748 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
749 if (tx_cmd->tx_flags & TX_CMD_FLG_RTS_MSK) {
750 tx_cmd->tx_flags &= ~TX_CMD_FLG_RTS_MSK;
751 tx_cmd->tx_flags |= TX_CMD_FLG_CTS_MSK;
752 }
753 break;
754 default:
755 break;
756 }
757
758 priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant);
759 rate_flags |= iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
760 }
761
762 tx_cmd->rts_retry_limit = rts_retry_limit;
763 tx_cmd->data_retry_limit = data_retry_limit;
764 tx_cmd->rate_n_flags = iwl_hw_set_rate_n_flags(rate_plcp, rate_flags);
765 }
766
767 static void iwl_tx_cmd_build_hwcrypto(struct iwl_priv *priv,
768 struct ieee80211_tx_info *info,
769 struct iwl_tx_cmd *tx_cmd,
770 struct sk_buff *skb_frag,
771 int sta_id)
772 {
773 struct ieee80211_key_conf *keyconf = info->control.hw_key;
774
775 switch (keyconf->alg) {
776 case ALG_CCMP:
777 tx_cmd->sec_ctl = TX_CMD_SEC_CCM;
778 memcpy(tx_cmd->key, keyconf->key, keyconf->keylen);
779 if (info->flags & IEEE80211_TX_CTL_AMPDU)
780 tx_cmd->tx_flags |= TX_CMD_FLG_AGG_CCMP_MSK;
781 IWL_DEBUG_TX("tx_cmd with AES hwcrypto\n");
782 break;
783
784 case ALG_TKIP:
785 tx_cmd->sec_ctl = TX_CMD_SEC_TKIP;
786 ieee80211_get_tkip_key(keyconf, skb_frag,
787 IEEE80211_TKIP_P2_KEY, tx_cmd->key);
788 IWL_DEBUG_TX("tx_cmd with tkip hwcrypto\n");
789 break;
790
791 case ALG_WEP:
792 tx_cmd->sec_ctl |= (TX_CMD_SEC_WEP |
793 (keyconf->keyidx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT);
794
795 if (keyconf->keylen == WEP_KEY_LEN_128)
796 tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128;
797
798 memcpy(&tx_cmd->key[3], keyconf->key, keyconf->keylen);
799
800 IWL_DEBUG_TX("Configuring packet for WEP encryption "
801 "with key %d\n", keyconf->keyidx);
802 break;
803
804 default:
805 printk(KERN_ERR "Unknown encode alg %d\n", keyconf->alg);
806 break;
807 }
808 }
809
810 static void iwl_update_tx_stats(struct iwl_priv *priv, u16 fc, u16 len)
811 {
812 /* 0 - mgmt, 1 - cnt, 2 - data */
813 int idx = (fc & IEEE80211_FCTL_FTYPE) >> 2;
814 priv->tx_stats[idx].cnt++;
815 priv->tx_stats[idx].bytes += len;
816 }
817
818 /*
819 * start REPLY_TX command process
820 */
821 int iwl_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
822 {
823 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
824 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
825 struct iwl_tfd *tfd;
826 struct iwl_tx_queue *txq;
827 struct iwl_queue *q;
828 struct iwl_cmd *out_cmd;
829 struct iwl_tx_cmd *tx_cmd;
830 int swq_id, txq_id;
831 dma_addr_t phys_addr;
832 dma_addr_t txcmd_phys;
833 dma_addr_t scratch_phys;
834 u16 len, len_org;
835 u16 seq_number = 0;
836 __le16 fc;
837 u8 hdr_len, unicast;
838 u8 sta_id;
839 u8 wait_write_ptr = 0;
840 u8 tid = 0;
841 u8 *qc = NULL;
842 unsigned long flags;
843 int ret;
844
845 spin_lock_irqsave(&priv->lock, flags);
846 if (iwl_is_rfkill(priv)) {
847 IWL_DEBUG_DROP("Dropping - RF KILL\n");
848 goto drop_unlock;
849 }
850
851 if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) ==
852 IWL_INVALID_RATE) {
853 IWL_ERROR("ERROR: No TX rate available.\n");
854 goto drop_unlock;
855 }
856
857 unicast = !is_multicast_ether_addr(hdr->addr1);
858
859 fc = hdr->frame_control;
860
861 #ifdef CONFIG_IWLWIFI_DEBUG
862 if (ieee80211_is_auth(fc))
863 IWL_DEBUG_TX("Sending AUTH frame\n");
864 else if (ieee80211_is_assoc_req(fc))
865 IWL_DEBUG_TX("Sending ASSOC frame\n");
866 else if (ieee80211_is_reassoc_req(fc))
867 IWL_DEBUG_TX("Sending REASSOC frame\n");
868 #endif
869
870 /* drop all data frame if we are not associated */
871 if (ieee80211_is_data(fc) &&
872 (priv->iw_mode != NL80211_IFTYPE_MONITOR ||
873 !(info->flags & IEEE80211_TX_CTL_INJECTED)) && /* packet injection */
874 (!iwl_is_associated(priv) ||
875 ((priv->iw_mode == NL80211_IFTYPE_STATION) && !priv->assoc_id) ||
876 !priv->assoc_station_added)) {
877 IWL_DEBUG_DROP("Dropping - !iwl_is_associated\n");
878 goto drop_unlock;
879 }
880
881 spin_unlock_irqrestore(&priv->lock, flags);
882
883 hdr_len = ieee80211_hdrlen(fc);
884
885 /* Find (or create) index into station table for destination station */
886 sta_id = iwl_get_sta_id(priv, hdr);
887 if (sta_id == IWL_INVALID_STATION) {
888 IWL_DEBUG_DROP("Dropping - INVALID STATION: %pM\n",
889 hdr->addr1);
890 goto drop;
891 }
892
893 IWL_DEBUG_TX("station Id %d\n", sta_id);
894
895 swq_id = skb_get_queue_mapping(skb);
896 txq_id = swq_id;
897 if (ieee80211_is_data_qos(fc)) {
898 qc = ieee80211_get_qos_ctl(hdr);
899 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
900 seq_number = priv->stations[sta_id].tid[tid].seq_number;
901 seq_number &= IEEE80211_SCTL_SEQ;
902 hdr->seq_ctrl = hdr->seq_ctrl &
903 __constant_cpu_to_le16(IEEE80211_SCTL_FRAG);
904 hdr->seq_ctrl |= cpu_to_le16(seq_number);
905 seq_number += 0x10;
906 /* aggregation is on for this <sta,tid> */
907 if (info->flags & IEEE80211_TX_CTL_AMPDU)
908 txq_id = priv->stations[sta_id].tid[tid].agg.txq_id;
909 priv->stations[sta_id].tid[tid].tfds_in_queue++;
910 }
911
912 txq = &priv->txq[txq_id];
913 q = &txq->q;
914 txq->swq_id = swq_id;
915
916 spin_lock_irqsave(&priv->lock, flags);
917
918 /* Set up first empty TFD within this queue's circular TFD buffer */
919 tfd = &txq->tfds[q->write_ptr];
920 memset(tfd, 0, sizeof(*tfd));
921
922 /* Set up driver data for this TFD */
923 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info));
924 txq->txb[q->write_ptr].skb[0] = skb;
925
926 /* Set up first empty entry in queue's array of Tx/cmd buffers */
927 out_cmd = txq->cmd[q->write_ptr];
928 tx_cmd = &out_cmd->cmd.tx;
929 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
930 memset(tx_cmd, 0, sizeof(struct iwl_tx_cmd));
931
932 /*
933 * Set up the Tx-command (not MAC!) header.
934 * Store the chosen Tx queue and TFD index within the sequence field;
935 * after Tx, uCode's Tx response will return this value so driver can
936 * locate the frame within the tx queue and do post-tx processing.
937 */
938 out_cmd->hdr.cmd = REPLY_TX;
939 out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
940 INDEX_TO_SEQ(q->write_ptr)));
941
942 /* Copy MAC header from skb into command buffer */
943 memcpy(tx_cmd->hdr, hdr, hdr_len);
944
945 /*
946 * Use the first empty entry in this queue's command buffer array
947 * to contain the Tx command and MAC header concatenated together
948 * (payload data will be in another buffer).
949 * Size of this varies, due to varying MAC header length.
950 * If end is not dword aligned, we'll have 2 extra bytes at the end
951 * of the MAC header (device reads on dword boundaries).
952 * We'll tell device about this padding later.
953 */
954 len = sizeof(struct iwl_tx_cmd) +
955 sizeof(struct iwl_cmd_header) + hdr_len;
956
957 len_org = len;
958 len = (len + 3) & ~3;
959
960 if (len_org != len)
961 len_org = 1;
962 else
963 len_org = 0;
964
965 /* Physical address of this Tx command's header (not MAC header!),
966 * within command buffer array. */
967 txcmd_phys = pci_map_single(priv->pci_dev,
968 out_cmd, sizeof(struct iwl_cmd),
969 PCI_DMA_TODEVICE);
970 pci_unmap_addr_set(&out_cmd->meta, mapping, txcmd_phys);
971 pci_unmap_len_set(&out_cmd->meta, len, sizeof(struct iwl_cmd));
972 /* Add buffer containing Tx command and MAC(!) header to TFD's
973 * first entry */
974 txcmd_phys += offsetof(struct iwl_cmd, hdr);
975 iwl_hw_txq_attach_buf_to_tfd(priv, tfd, txcmd_phys, len);
976
977 if (info->control.hw_key)
978 iwl_tx_cmd_build_hwcrypto(priv, info, tx_cmd, skb, sta_id);
979
980 /* Set up TFD's 2nd entry to point directly to remainder of skb,
981 * if any (802.11 null frames have no payload). */
982 len = skb->len - hdr_len;
983 if (len) {
984 phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
985 len, PCI_DMA_TODEVICE);
986 iwl_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, len);
987 }
988
989 /* Tell NIC about any 2-byte padding after MAC header */
990 if (len_org)
991 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
992
993 /* Total # bytes to be transmitted */
994 len = (u16)skb->len;
995 tx_cmd->len = cpu_to_le16(len);
996 /* TODO need this for burst mode later on */
997 iwl_tx_cmd_build_basic(priv, tx_cmd, info, hdr, unicast, sta_id);
998
999 /* set is_hcca to 0; it probably will never be implemented */
1000 iwl_tx_cmd_build_rate(priv, tx_cmd, info, fc, sta_id, 0);
1001
1002 iwl_update_tx_stats(priv, le16_to_cpu(fc), len);
1003
1004 scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
1005 offsetof(struct iwl_tx_cmd, scratch);
1006 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1007 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
1008
1009 if (!ieee80211_has_morefrags(hdr->frame_control)) {
1010 txq->need_update = 1;
1011 if (qc)
1012 priv->stations[sta_id].tid[tid].seq_number = seq_number;
1013 } else {
1014 wait_write_ptr = 1;
1015 txq->need_update = 0;
1016 }
1017
1018 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd));
1019
1020 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len);
1021
1022 /* Set up entry for this TFD in Tx byte-count array */
1023 priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, len);
1024
1025 /* Tell device the write index *just past* this latest filled TFD */
1026 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1027 ret = iwl_txq_update_write_ptr(priv, txq);
1028 spin_unlock_irqrestore(&priv->lock, flags);
1029
1030 if (ret)
1031 return ret;
1032
1033 if ((iwl_queue_space(q) < q->high_mark) && priv->mac80211_registered) {
1034 if (wait_write_ptr) {
1035 spin_lock_irqsave(&priv->lock, flags);
1036 txq->need_update = 1;
1037 iwl_txq_update_write_ptr(priv, txq);
1038 spin_unlock_irqrestore(&priv->lock, flags);
1039 } else {
1040 ieee80211_stop_queue(priv->hw, txq->swq_id);
1041 }
1042 }
1043
1044 return 0;
1045
1046 drop_unlock:
1047 spin_unlock_irqrestore(&priv->lock, flags);
1048 drop:
1049 return -1;
1050 }
1051 EXPORT_SYMBOL(iwl_tx_skb);
1052
1053 /*************** HOST COMMAND QUEUE FUNCTIONS *****/
1054
1055 /**
1056 * iwl_enqueue_hcmd - enqueue a uCode command
1057 * @priv: device private data point
1058 * @cmd: a point to the ucode command structure
1059 *
1060 * The function returns < 0 values to indicate the operation is
1061 * failed. On success, it turns the index (> 0) of command in the
1062 * command queue.
1063 */
1064 int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
1065 {
1066 struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
1067 struct iwl_queue *q = &txq->q;
1068 struct iwl_tfd *tfd;
1069 struct iwl_cmd *out_cmd;
1070 dma_addr_t phys_addr;
1071 unsigned long flags;
1072 int len, ret;
1073 u32 idx;
1074 u16 fix_size;
1075
1076 cmd->len = priv->cfg->ops->utils->get_hcmd_size(cmd->id, cmd->len);
1077 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
1078
1079 /* If any of the command structures end up being larger than
1080 * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
1081 * we will need to increase the size of the TFD entries */
1082 BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
1083 !(cmd->meta.flags & CMD_SIZE_HUGE));
1084
1085 if (iwl_is_rfkill(priv)) {
1086 IWL_DEBUG_INFO("Not sending command - RF KILL");
1087 return -EIO;
1088 }
1089
1090 if (iwl_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) {
1091 IWL_ERROR("No space for Tx\n");
1092 return -ENOSPC;
1093 }
1094
1095 spin_lock_irqsave(&priv->hcmd_lock, flags);
1096
1097 tfd = &txq->tfds[q->write_ptr];
1098 memset(tfd, 0, sizeof(*tfd));
1099
1100
1101 idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE);
1102 out_cmd = txq->cmd[idx];
1103
1104 out_cmd->hdr.cmd = cmd->id;
1105 memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta));
1106 memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
1107
1108 /* At this point, the out_cmd now has all of the incoming cmd
1109 * information */
1110
1111 out_cmd->hdr.flags = 0;
1112 out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
1113 INDEX_TO_SEQ(q->write_ptr));
1114 if (out_cmd->meta.flags & CMD_SIZE_HUGE)
1115 out_cmd->hdr.sequence |= SEQ_HUGE_FRAME;
1116 len = (idx == TFD_CMD_SLOTS) ?
1117 IWL_MAX_SCAN_SIZE : sizeof(struct iwl_cmd);
1118
1119 phys_addr = pci_map_single(priv->pci_dev, out_cmd,
1120 len, PCI_DMA_TODEVICE);
1121 pci_unmap_addr_set(&out_cmd->meta, mapping, phys_addr);
1122 pci_unmap_len_set(&out_cmd->meta, len, len);
1123 phys_addr += offsetof(struct iwl_cmd, hdr);
1124
1125 iwl_hw_txq_attach_buf_to_tfd(priv, tfd, phys_addr, fix_size);
1126
1127 #ifdef CONFIG_IWLWIFI_DEBUG
1128 switch (out_cmd->hdr.cmd) {
1129 case REPLY_TX_LINK_QUALITY_CMD:
1130 case SENSITIVITY_CMD:
1131 IWL_DEBUG_HC_DUMP("Sending command %s (#%x), seq: 0x%04X, "
1132 "%d bytes at %d[%d]:%d\n",
1133 get_cmd_string(out_cmd->hdr.cmd),
1134 out_cmd->hdr.cmd,
1135 le16_to_cpu(out_cmd->hdr.sequence), fix_size,
1136 q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
1137 break;
1138 default:
1139 IWL_DEBUG_HC("Sending command %s (#%x), seq: 0x%04X, "
1140 "%d bytes at %d[%d]:%d\n",
1141 get_cmd_string(out_cmd->hdr.cmd),
1142 out_cmd->hdr.cmd,
1143 le16_to_cpu(out_cmd->hdr.sequence), fix_size,
1144 q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
1145 }
1146 #endif
1147 txq->need_update = 1;
1148
1149 /* Set up entry in queue's byte count circular buffer */
1150 priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, 0);
1151
1152 /* Increment and update queue's write index */
1153 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1154 ret = iwl_txq_update_write_ptr(priv, txq);
1155
1156 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
1157 return ret ? ret : idx;
1158 }
1159
1160 int iwl_tx_queue_reclaim(struct iwl_priv *priv, int txq_id, int index)
1161 {
1162 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1163 struct iwl_queue *q = &txq->q;
1164 struct iwl_tx_info *tx_info;
1165 int nfreed = 0;
1166
1167 if ((index >= q->n_bd) || (iwl_queue_used(q, index) == 0)) {
1168 IWL_ERROR("Read index for DMA queue txq id (%d), index %d, "
1169 "is out of range [0-%d] %d %d.\n", txq_id,
1170 index, q->n_bd, q->write_ptr, q->read_ptr);
1171 return 0;
1172 }
1173
1174 for (index = iwl_queue_inc_wrap(index, q->n_bd);
1175 q->read_ptr != index;
1176 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
1177
1178 tx_info = &txq->txb[txq->q.read_ptr];
1179 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
1180 tx_info->skb[0] = NULL;
1181
1182 if (priv->cfg->ops->lib->txq_inval_byte_cnt_tbl)
1183 priv->cfg->ops->lib->txq_inval_byte_cnt_tbl(priv, txq);
1184
1185 iwl_hw_txq_free_tfd(priv, txq);
1186 nfreed++;
1187 }
1188 return nfreed;
1189 }
1190 EXPORT_SYMBOL(iwl_tx_queue_reclaim);
1191
1192
1193 /**
1194 * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
1195 *
1196 * When FW advances 'R' index, all entries between old and new 'R' index
1197 * need to be reclaimed. As result, some free space forms. If there is
1198 * enough free space (> low mark), wake the stack that feeds us.
1199 */
1200 static void iwl_hcmd_queue_reclaim(struct iwl_priv *priv, int txq_id,
1201 int idx, int cmd_idx)
1202 {
1203 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1204 struct iwl_queue *q = &txq->q;
1205 int nfreed = 0;
1206
1207 if ((idx >= q->n_bd) || (iwl_queue_used(q, idx) == 0)) {
1208 IWL_ERROR("Read index for DMA queue txq id (%d), index %d, "
1209 "is out of range [0-%d] %d %d.\n", txq_id,
1210 idx, q->n_bd, q->write_ptr, q->read_ptr);
1211 return;
1212 }
1213
1214 pci_unmap_single(priv->pci_dev,
1215 pci_unmap_addr(&txq->cmd[cmd_idx]->meta, mapping),
1216 pci_unmap_len(&txq->cmd[cmd_idx]->meta, len),
1217 PCI_DMA_TODEVICE);
1218
1219 for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
1220 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
1221
1222 if (nfreed++ > 0) {
1223 IWL_ERROR("HCMD skipped: index (%d) %d %d\n", idx,
1224 q->write_ptr, q->read_ptr);
1225 queue_work(priv->workqueue, &priv->restart);
1226 }
1227
1228 }
1229 }
1230
1231 /**
1232 * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
1233 * @rxb: Rx buffer to reclaim
1234 *
1235 * If an Rx buffer has an async callback associated with it the callback
1236 * will be executed. The attached skb (if present) will only be freed
1237 * if the callback returns 1
1238 */
1239 void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
1240 {
1241 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
1242 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1243 int txq_id = SEQ_TO_QUEUE(sequence);
1244 int index = SEQ_TO_INDEX(sequence);
1245 int cmd_index;
1246 bool huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME);
1247 struct iwl_cmd *cmd;
1248
1249 /* If a Tx command is being handled and it isn't in the actual
1250 * command queue then there a command routing bug has been introduced
1251 * in the queue management code. */
1252 if (WARN(txq_id != IWL_CMD_QUEUE_NUM,
1253 "wrong command queue %d, sequence 0x%X readp=%d writep=%d\n",
1254 txq_id, sequence,
1255 priv->txq[IWL_CMD_QUEUE_NUM].q.read_ptr,
1256 priv->txq[IWL_CMD_QUEUE_NUM].q.write_ptr)) {
1257 iwl_print_hex_dump(priv, IWL_DL_INFO , rxb, 32);
1258 return;
1259 }
1260
1261 cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
1262 cmd = priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
1263
1264 /* Input error checking is done when commands are added to queue. */
1265 if (cmd->meta.flags & CMD_WANT_SKB) {
1266 cmd->meta.source->u.skb = rxb->skb;
1267 rxb->skb = NULL;
1268 } else if (cmd->meta.u.callback &&
1269 !cmd->meta.u.callback(priv, cmd, rxb->skb))
1270 rxb->skb = NULL;
1271
1272 iwl_hcmd_queue_reclaim(priv, txq_id, index, cmd_index);
1273
1274 if (!(cmd->meta.flags & CMD_ASYNC)) {
1275 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1276 wake_up_interruptible(&priv->wait_command_queue);
1277 }
1278 }
1279 EXPORT_SYMBOL(iwl_tx_cmd_complete);
1280
1281 /*
1282 * Find first available (lowest unused) Tx Queue, mark it "active".
1283 * Called only when finding queue for aggregation.
1284 * Should never return anything < 7, because they should already
1285 * be in use as EDCA AC (0-3), Command (4), HCCA (5, 6).
1286 */
1287 static int iwl_txq_ctx_activate_free(struct iwl_priv *priv)
1288 {
1289 int txq_id;
1290
1291 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
1292 if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk))
1293 return txq_id;
1294 return -1;
1295 }
1296
1297 int iwl_tx_agg_start(struct iwl_priv *priv, const u8 *ra, u16 tid, u16 *ssn)
1298 {
1299 int sta_id;
1300 int tx_fifo;
1301 int txq_id;
1302 int ret;
1303 unsigned long flags;
1304 struct iwl_tid_data *tid_data;
1305
1306 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
1307 tx_fifo = default_tid_to_tx_fifo[tid];
1308 else
1309 return -EINVAL;
1310
1311 IWL_WARNING("%s on ra = %pM tid = %d\n",
1312 __func__, ra, tid);
1313
1314 sta_id = iwl_find_station(priv, ra);
1315 if (sta_id == IWL_INVALID_STATION)
1316 return -ENXIO;
1317
1318 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_OFF) {
1319 IWL_ERROR("Start AGG when state is not IWL_AGG_OFF !\n");
1320 return -ENXIO;
1321 }
1322
1323 txq_id = iwl_txq_ctx_activate_free(priv);
1324 if (txq_id == -1)
1325 return -ENXIO;
1326
1327 spin_lock_irqsave(&priv->sta_lock, flags);
1328 tid_data = &priv->stations[sta_id].tid[tid];
1329 *ssn = SEQ_TO_SN(tid_data->seq_number);
1330 tid_data->agg.txq_id = txq_id;
1331 spin_unlock_irqrestore(&priv->sta_lock, flags);
1332
1333 ret = priv->cfg->ops->lib->txq_agg_enable(priv, txq_id, tx_fifo,
1334 sta_id, tid, *ssn);
1335 if (ret)
1336 return ret;
1337
1338 if (tid_data->tfds_in_queue == 0) {
1339 printk(KERN_ERR "HW queue is empty\n");
1340 tid_data->agg.state = IWL_AGG_ON;
1341 ieee80211_start_tx_ba_cb_irqsafe(priv->hw, ra, tid);
1342 } else {
1343 IWL_DEBUG_HT("HW queue is NOT empty: %d packets in HW queue\n",
1344 tid_data->tfds_in_queue);
1345 tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA;
1346 }
1347 return ret;
1348 }
1349 EXPORT_SYMBOL(iwl_tx_agg_start);
1350
1351 int iwl_tx_agg_stop(struct iwl_priv *priv , const u8 *ra, u16 tid)
1352 {
1353 int tx_fifo_id, txq_id, sta_id, ssn = -1;
1354 struct iwl_tid_data *tid_data;
1355 int ret, write_ptr, read_ptr;
1356 unsigned long flags;
1357
1358 if (!ra) {
1359 IWL_ERROR("ra = NULL\n");
1360 return -EINVAL;
1361 }
1362
1363 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
1364 tx_fifo_id = default_tid_to_tx_fifo[tid];
1365 else
1366 return -EINVAL;
1367
1368 sta_id = iwl_find_station(priv, ra);
1369
1370 if (sta_id == IWL_INVALID_STATION)
1371 return -ENXIO;
1372
1373 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_ON)
1374 IWL_WARNING("Stopping AGG while state not IWL_AGG_ON\n");
1375
1376 tid_data = &priv->stations[sta_id].tid[tid];
1377 ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
1378 txq_id = tid_data->agg.txq_id;
1379 write_ptr = priv->txq[txq_id].q.write_ptr;
1380 read_ptr = priv->txq[txq_id].q.read_ptr;
1381
1382 /* The queue is not empty */
1383 if (write_ptr != read_ptr) {
1384 IWL_DEBUG_HT("Stopping a non empty AGG HW QUEUE\n");
1385 priv->stations[sta_id].tid[tid].agg.state =
1386 IWL_EMPTYING_HW_QUEUE_DELBA;
1387 return 0;
1388 }
1389
1390 IWL_DEBUG_HT("HW queue is empty\n");
1391 priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF;
1392
1393 spin_lock_irqsave(&priv->lock, flags);
1394 ret = priv->cfg->ops->lib->txq_agg_disable(priv, txq_id, ssn,
1395 tx_fifo_id);
1396 spin_unlock_irqrestore(&priv->lock, flags);
1397
1398 if (ret)
1399 return ret;
1400
1401 ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, ra, tid);
1402
1403 return 0;
1404 }
1405 EXPORT_SYMBOL(iwl_tx_agg_stop);
1406
1407 int iwl_txq_check_empty(struct iwl_priv *priv, int sta_id, u8 tid, int txq_id)
1408 {
1409 struct iwl_queue *q = &priv->txq[txq_id].q;
1410 u8 *addr = priv->stations[sta_id].sta.sta.addr;
1411 struct iwl_tid_data *tid_data = &priv->stations[sta_id].tid[tid];
1412
1413 switch (priv->stations[sta_id].tid[tid].agg.state) {
1414 case IWL_EMPTYING_HW_QUEUE_DELBA:
1415 /* We are reclaiming the last packet of the */
1416 /* aggregated HW queue */
1417 if ((txq_id == tid_data->agg.txq_id) &&
1418 (q->read_ptr == q->write_ptr)) {
1419 u16 ssn = SEQ_TO_SN(tid_data->seq_number);
1420 int tx_fifo = default_tid_to_tx_fifo[tid];
1421 IWL_DEBUG_HT("HW queue empty: continue DELBA flow\n");
1422 priv->cfg->ops->lib->txq_agg_disable(priv, txq_id,
1423 ssn, tx_fifo);
1424 tid_data->agg.state = IWL_AGG_OFF;
1425 ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, addr, tid);
1426 }
1427 break;
1428 case IWL_EMPTYING_HW_QUEUE_ADDBA:
1429 /* We are reclaiming the last packet of the queue */
1430 if (tid_data->tfds_in_queue == 0) {
1431 IWL_DEBUG_HT("HW queue empty: continue ADDBA flow\n");
1432 tid_data->agg.state = IWL_AGG_ON;
1433 ieee80211_start_tx_ba_cb_irqsafe(priv->hw, addr, tid);
1434 }
1435 break;
1436 }
1437 return 0;
1438 }
1439 EXPORT_SYMBOL(iwl_txq_check_empty);
1440
1441 /**
1442 * iwl_tx_status_reply_compressed_ba - Update tx status from block-ack
1443 *
1444 * Go through block-ack's bitmap of ACK'd frames, update driver's record of
1445 * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
1446 */
1447 static int iwl_tx_status_reply_compressed_ba(struct iwl_priv *priv,
1448 struct iwl_ht_agg *agg,
1449 struct iwl_compressed_ba_resp *ba_resp)
1450
1451 {
1452 int i, sh, ack;
1453 u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
1454 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
1455 u64 bitmap;
1456 int successes = 0;
1457 struct ieee80211_tx_info *info;
1458
1459 if (unlikely(!agg->wait_for_ba)) {
1460 IWL_ERROR("Received BA when not expected\n");
1461 return -EINVAL;
1462 }
1463
1464 /* Mark that the expected block-ack response arrived */
1465 agg->wait_for_ba = 0;
1466 IWL_DEBUG_TX_REPLY("BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
1467
1468 /* Calculate shift to align block-ack bits with our Tx window bits */
1469 sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl >> 4);
1470 if (sh < 0) /* tbw something is wrong with indices */
1471 sh += 0x100;
1472
1473 /* don't use 64-bit values for now */
1474 bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
1475
1476 if (agg->frame_count > (64 - sh)) {
1477 IWL_DEBUG_TX_REPLY("more frames than bitmap size");
1478 return -1;
1479 }
1480
1481 /* check for success or failure according to the
1482 * transmitted bitmap and block-ack bitmap */
1483 bitmap &= agg->bitmap;
1484
1485 /* For each frame attempted in aggregation,
1486 * update driver's record of tx frame's status. */
1487 for (i = 0; i < agg->frame_count ; i++) {
1488 ack = bitmap & (1ULL << i);
1489 successes += !!ack;
1490 IWL_DEBUG_TX_REPLY("%s ON i=%d idx=%d raw=%d\n",
1491 ack ? "ACK" : "NACK", i, (agg->start_idx + i) & 0xff,
1492 agg->start_idx + i);
1493 }
1494
1495 info = IEEE80211_SKB_CB(priv->txq[scd_flow].txb[agg->start_idx].skb[0]);
1496 memset(&info->status, 0, sizeof(info->status));
1497 info->flags = IEEE80211_TX_STAT_ACK;
1498 info->flags |= IEEE80211_TX_STAT_AMPDU;
1499 info->status.ampdu_ack_map = successes;
1500 info->status.ampdu_ack_len = agg->frame_count;
1501 iwl_hwrate_to_tx_control(priv, agg->rate_n_flags, info);
1502
1503 IWL_DEBUG_TX_REPLY("Bitmap %llx\n", (unsigned long long)bitmap);
1504
1505 return 0;
1506 }
1507
1508 /**
1509 * iwl_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
1510 *
1511 * Handles block-acknowledge notification from device, which reports success
1512 * of frames sent via aggregation.
1513 */
1514 void iwl_rx_reply_compressed_ba(struct iwl_priv *priv,
1515 struct iwl_rx_mem_buffer *rxb)
1516 {
1517 struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
1518 struct iwl_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
1519 struct iwl_tx_queue *txq = NULL;
1520 struct iwl_ht_agg *agg;
1521 int index;
1522 int sta_id;
1523 int tid;
1524
1525 /* "flow" corresponds to Tx queue */
1526 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
1527
1528 /* "ssn" is start of block-ack Tx window, corresponds to index
1529 * (in Tx queue's circular buffer) of first TFD/frame in window */
1530 u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
1531
1532 if (scd_flow >= priv->hw_params.max_txq_num) {
1533 IWL_ERROR("BUG_ON scd_flow is bigger than number of queues\n");
1534 return;
1535 }
1536
1537 txq = &priv->txq[scd_flow];
1538 sta_id = ba_resp->sta_id;
1539 tid = ba_resp->tid;
1540 agg = &priv->stations[sta_id].tid[tid].agg;
1541
1542 /* Find index just before block-ack window */
1543 index = iwl_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
1544
1545 /* TODO: Need to get this copy more safely - now good for debug */
1546
1547 IWL_DEBUG_TX_REPLY("REPLY_COMPRESSED_BA [%d] Received from %pM, "
1548 "sta_id = %d\n",
1549 agg->wait_for_ba,
1550 (u8 *) &ba_resp->sta_addr_lo32,
1551 ba_resp->sta_id);
1552 IWL_DEBUG_TX_REPLY("TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = "
1553 "%d, scd_ssn = %d\n",
1554 ba_resp->tid,
1555 ba_resp->seq_ctl,
1556 (unsigned long long)le64_to_cpu(ba_resp->bitmap),
1557 ba_resp->scd_flow,
1558 ba_resp->scd_ssn);
1559 IWL_DEBUG_TX_REPLY("DAT start_idx = %d, bitmap = 0x%llx \n",
1560 agg->start_idx,
1561 (unsigned long long)agg->bitmap);
1562
1563 /* Update driver's record of ACK vs. not for each frame in window */
1564 iwl_tx_status_reply_compressed_ba(priv, agg, ba_resp);
1565
1566 /* Release all TFDs before the SSN, i.e. all TFDs in front of
1567 * block-ack window (we assume that they've been successfully
1568 * transmitted ... if not, it's too late anyway). */
1569 if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
1570 /* calculate mac80211 ampdu sw queue to wake */
1571 int freed = iwl_tx_queue_reclaim(priv, scd_flow, index);
1572 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1573
1574 if ((iwl_queue_space(&txq->q) > txq->q.low_mark) &&
1575 priv->mac80211_registered &&
1576 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA))
1577 ieee80211_wake_queue(priv->hw, txq->swq_id);
1578
1579 iwl_txq_check_empty(priv, sta_id, tid, scd_flow);
1580 }
1581 }
1582 EXPORT_SYMBOL(iwl_rx_reply_compressed_ba);
1583
1584 #ifdef CONFIG_IWLWIFI_DEBUG
1585 #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
1586
1587 const char *iwl_get_tx_fail_reason(u32 status)
1588 {
1589 switch (status & TX_STATUS_MSK) {
1590 case TX_STATUS_SUCCESS:
1591 return "SUCCESS";
1592 TX_STATUS_ENTRY(SHORT_LIMIT);
1593 TX_STATUS_ENTRY(LONG_LIMIT);
1594 TX_STATUS_ENTRY(FIFO_UNDERRUN);
1595 TX_STATUS_ENTRY(MGMNT_ABORT);
1596 TX_STATUS_ENTRY(NEXT_FRAG);
1597 TX_STATUS_ENTRY(LIFE_EXPIRE);
1598 TX_STATUS_ENTRY(DEST_PS);
1599 TX_STATUS_ENTRY(ABORTED);
1600 TX_STATUS_ENTRY(BT_RETRY);
1601 TX_STATUS_ENTRY(STA_INVALID);
1602 TX_STATUS_ENTRY(FRAG_DROPPED);
1603 TX_STATUS_ENTRY(TID_DISABLE);
1604 TX_STATUS_ENTRY(FRAME_FLUSHED);
1605 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
1606 TX_STATUS_ENTRY(TX_LOCKED);
1607 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
1608 }
1609
1610 return "UNKNOWN";
1611 }
1612 EXPORT_SYMBOL(iwl_get_tx_fail_reason);
1613 #endif /* CONFIG_IWLWIFI_DEBUG */
Linux 2.6 libata-dev (mirror)