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iwl3945 : Fix a-band association for passive channels
[linux-2.6/libata-dev.git] / drivers / net / sungem.c
blob6f935cd30176e99969d072d2c8ebcaaf7977a300
1 /* $Id: sungem.c,v 1.44.2.22 2002/03/13 01:18:12 davem Exp $
2 * sungem.c: Sun GEM ethernet driver.
3 *
4 * Copyright (C) 2000, 2001, 2002, 2003 David S. Miller (davem@redhat.com)
5 *
6 * Support for Apple GMAC and assorted PHYs, WOL, Power Management
7 * (C) 2001,2002,2003 Benjamin Herrenscmidt (benh@kernel.crashing.org)
8 * (C) 2004,2005 Benjamin Herrenscmidt, IBM Corp.
9 *
10 * NAPI and NETPOLL support
11 * (C) 2004 by Eric Lemoine (eric.lemoine@gmail.com)
12 *
13 * TODO:
14 * - Now that the driver was significantly simplified, I need to rework
15 * the locking. I'm sure we don't need _2_ spinlocks, and we probably
16 * can avoid taking most of them for so long period of time (and schedule
17 * instead). The main issues at this point are caused by the netdev layer
18 * though:
19 *
20 * gem_change_mtu() and gem_set_multicast() are called with a read_lock()
21 * help by net/core/dev.c, thus they can't schedule. That means they can't
22 * call napi_disable() neither, thus force gem_poll() to keep a spinlock
23 * where it could have been dropped. change_mtu especially would love also to
24 * be able to msleep instead of horrid locked delays when resetting the HW,
25 * but that read_lock() makes it impossible, unless I defer it's action to
26 * the reset task, which means it'll be asynchronous (won't take effect until
27 * the system schedules a bit).
28 *
29 * Also, it would probably be possible to also remove most of the long-life
30 * locking in open/resume code path (gem_reinit_chip) by beeing more careful
31 * about when we can start taking interrupts or get xmit() called...
32 */
33
34 #include <linux/module.h>
35 #include <linux/kernel.h>
36 #include <linux/types.h>
37 #include <linux/fcntl.h>
38 #include <linux/interrupt.h>
39 #include <linux/ioport.h>
40 #include <linux/in.h>
41 #include <linux/slab.h>
42 #include <linux/string.h>
43 #include <linux/delay.h>
44 #include <linux/init.h>
45 #include <linux/errno.h>
46 #include <linux/pci.h>
47 #include <linux/dma-mapping.h>
48 #include <linux/netdevice.h>
49 #include <linux/etherdevice.h>
50 #include <linux/skbuff.h>
51 #include <linux/mii.h>
52 #include <linux/ethtool.h>
53 #include <linux/crc32.h>
54 #include <linux/random.h>
55 #include <linux/workqueue.h>
56 #include <linux/if_vlan.h>
57 #include <linux/bitops.h>
58 #include <linux/mutex.h>
59 #include <linux/mm.h>
60
61 #include <asm/system.h>
62 #include <asm/io.h>
63 #include <asm/byteorder.h>
64 #include <asm/uaccess.h>
65 #include <asm/irq.h>
66
67 #ifdef CONFIG_SPARC
68 #include <asm/idprom.h>
69 #include <asm/prom.h>
70 #endif
71
72 #ifdef CONFIG_PPC_PMAC
73 #include <asm/pci-bridge.h>
74 #include <asm/prom.h>
75 #include <asm/machdep.h>
76 #include <asm/pmac_feature.h>
77 #endif
78
79 #include "sungem_phy.h"
80 #include "sungem.h"
81
82 /* Stripping FCS is causing problems, disabled for now */
83 #undef STRIP_FCS
84
85 #define DEFAULT_MSG (NETIF_MSG_DRV | \
86 NETIF_MSG_PROBE | \
87 NETIF_MSG_LINK)
88
89 #define ADVERTISE_MASK (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | \
90 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | \
91 SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full | \
92 SUPPORTED_Pause | SUPPORTED_Autoneg)
93
94 #define DRV_NAME "sungem"
95 #define DRV_VERSION "0.98"
96 #define DRV_RELDATE "8/24/03"
97 #define DRV_AUTHOR "David S. Miller (davem@redhat.com)"
98
99 static char version[] __devinitdata =
100 DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " " DRV_AUTHOR "\n";
101
102 MODULE_AUTHOR(DRV_AUTHOR);
103 MODULE_DESCRIPTION("Sun GEM Gbit ethernet driver");
104 MODULE_LICENSE("GPL");
105
106 #define GEM_MODULE_NAME "gem"
107 #define PFX GEM_MODULE_NAME ": "
108
109 static struct pci_device_id gem_pci_tbl[] = {
110 { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_GEM,
111 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
112
113 /* These models only differ from the original GEM in
114 * that their tx/rx fifos are of a different size and
115 * they only support 10/100 speeds. -DaveM
116 *
117 * Apple's GMAC does support gigabit on machines with
118 * the BCM54xx PHYs. -BenH
119 */
120 { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_RIO_GEM,
121 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
122 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMAC,
123 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
124 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMACP,
125 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
126 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMAC2,
127 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
128 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_K2_GMAC,
129 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
130 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_SH_SUNGEM,
131 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
132 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_IPID2_GMAC,
133 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
134 {0, }
135 };
136
137 MODULE_DEVICE_TABLE(pci, gem_pci_tbl);
138
139 static u16 __phy_read(struct gem *gp, int phy_addr, int reg)
140 {
141 u32 cmd;
142 int limit = 10000;
143
144 cmd = (1 << 30);
145 cmd |= (2 << 28);
146 cmd |= (phy_addr << 23) & MIF_FRAME_PHYAD;
147 cmd |= (reg << 18) & MIF_FRAME_REGAD;
148 cmd |= (MIF_FRAME_TAMSB);
149 writel(cmd, gp->regs + MIF_FRAME);
150
151 while (limit--) {
152 cmd = readl(gp->regs + MIF_FRAME);
153 if (cmd & MIF_FRAME_TALSB)
154 break;
155
156 udelay(10);
157 }
158
159 if (!limit)
160 cmd = 0xffff;
161
162 return cmd & MIF_FRAME_DATA;
163 }
164
165 static inline int _phy_read(struct net_device *dev, int mii_id, int reg)
166 {
167 struct gem *gp = netdev_priv(dev);
168 return __phy_read(gp, mii_id, reg);
169 }
170
171 static inline u16 phy_read(struct gem *gp, int reg)
172 {
173 return __phy_read(gp, gp->mii_phy_addr, reg);
174 }
175
176 static void __phy_write(struct gem *gp, int phy_addr, int reg, u16 val)
177 {
178 u32 cmd;
179 int limit = 10000;
180
181 cmd = (1 << 30);
182 cmd |= (1 << 28);
183 cmd |= (phy_addr << 23) & MIF_FRAME_PHYAD;
184 cmd |= (reg << 18) & MIF_FRAME_REGAD;
185 cmd |= (MIF_FRAME_TAMSB);
186 cmd |= (val & MIF_FRAME_DATA);
187 writel(cmd, gp->regs + MIF_FRAME);
188
189 while (limit--) {
190 cmd = readl(gp->regs + MIF_FRAME);
191 if (cmd & MIF_FRAME_TALSB)
192 break;
193
194 udelay(10);
195 }
196 }
197
198 static inline void _phy_write(struct net_device *dev, int mii_id, int reg, int val)
199 {
200 struct gem *gp = netdev_priv(dev);
201 __phy_write(gp, mii_id, reg, val & 0xffff);
202 }
203
204 static inline void phy_write(struct gem *gp, int reg, u16 val)
205 {
206 __phy_write(gp, gp->mii_phy_addr, reg, val);
207 }
208
209 static inline void gem_enable_ints(struct gem *gp)
210 {
211 /* Enable all interrupts but TXDONE */
212 writel(GREG_STAT_TXDONE, gp->regs + GREG_IMASK);
213 }
214
215 static inline void gem_disable_ints(struct gem *gp)
216 {
217 /* Disable all interrupts, including TXDONE */
218 writel(GREG_STAT_NAPI | GREG_STAT_TXDONE, gp->regs + GREG_IMASK);
219 }
220
221 static void gem_get_cell(struct gem *gp)
222 {
223 BUG_ON(gp->cell_enabled < 0);
224 gp->cell_enabled++;
225 #ifdef CONFIG_PPC_PMAC
226 if (gp->cell_enabled == 1) {
227 mb();
228 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 1);
229 udelay(10);
230 }
231 #endif /* CONFIG_PPC_PMAC */
232 }
233
234 /* Turn off the chip's clock */
235 static void gem_put_cell(struct gem *gp)
236 {
237 BUG_ON(gp->cell_enabled <= 0);
238 gp->cell_enabled--;
239 #ifdef CONFIG_PPC_PMAC
240 if (gp->cell_enabled == 0) {
241 mb();
242 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 0);
243 udelay(10);
244 }
245 #endif /* CONFIG_PPC_PMAC */
246 }
247
248 static void gem_handle_mif_event(struct gem *gp, u32 reg_val, u32 changed_bits)
249 {
250 if (netif_msg_intr(gp))
251 printk(KERN_DEBUG "%s: mif interrupt\n", gp->dev->name);
252 }
253
254 static int gem_pcs_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
255 {
256 u32 pcs_istat = readl(gp->regs + PCS_ISTAT);
257 u32 pcs_miistat;
258
259 if (netif_msg_intr(gp))
260 printk(KERN_DEBUG "%s: pcs interrupt, pcs_istat: 0x%x\n",
261 gp->dev->name, pcs_istat);
262
263 if (!(pcs_istat & PCS_ISTAT_LSC)) {
264 printk(KERN_ERR "%s: PCS irq but no link status change???\n",
265 dev->name);
266 return 0;
267 }
268
269 /* The link status bit latches on zero, so you must
270 * read it twice in such a case to see a transition
271 * to the link being up.
272 */
273 pcs_miistat = readl(gp->regs + PCS_MIISTAT);
274 if (!(pcs_miistat & PCS_MIISTAT_LS))
275 pcs_miistat |=
276 (readl(gp->regs + PCS_MIISTAT) &
277 PCS_MIISTAT_LS);
278
279 if (pcs_miistat & PCS_MIISTAT_ANC) {
280 /* The remote-fault indication is only valid
281 * when autoneg has completed.
282 */
283 if (pcs_miistat & PCS_MIISTAT_RF)
284 printk(KERN_INFO "%s: PCS AutoNEG complete, "
285 "RemoteFault\n", dev->name);
286 else
287 printk(KERN_INFO "%s: PCS AutoNEG complete.\n",
288 dev->name);
289 }
290
291 if (pcs_miistat & PCS_MIISTAT_LS) {
292 printk(KERN_INFO "%s: PCS link is now up.\n",
293 dev->name);
294 netif_carrier_on(gp->dev);
295 } else {
296 printk(KERN_INFO "%s: PCS link is now down.\n",
297 dev->name);
298 netif_carrier_off(gp->dev);
299 /* If this happens and the link timer is not running,
300 * reset so we re-negotiate.
301 */
302 if (!timer_pending(&gp->link_timer))
303 return 1;
304 }
305
306 return 0;
307 }
308
309 static int gem_txmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
310 {
311 u32 txmac_stat = readl(gp->regs + MAC_TXSTAT);
312
313 if (netif_msg_intr(gp))
314 printk(KERN_DEBUG "%s: txmac interrupt, txmac_stat: 0x%x\n",
315 gp->dev->name, txmac_stat);
316
317 /* Defer timer expiration is quite normal,
318 * don't even log the event.
319 */
320 if ((txmac_stat & MAC_TXSTAT_DTE) &&
321 !(txmac_stat & ~MAC_TXSTAT_DTE))
322 return 0;
323
324 if (txmac_stat & MAC_TXSTAT_URUN) {
325 printk(KERN_ERR "%s: TX MAC xmit underrun.\n",
326 dev->name);
327 gp->net_stats.tx_fifo_errors++;
328 }
329
330 if (txmac_stat & MAC_TXSTAT_MPE) {
331 printk(KERN_ERR "%s: TX MAC max packet size error.\n",
332 dev->name);
333 gp->net_stats.tx_errors++;
334 }
335
336 /* The rest are all cases of one of the 16-bit TX
337 * counters expiring.
338 */
339 if (txmac_stat & MAC_TXSTAT_NCE)
340 gp->net_stats.collisions += 0x10000;
341
342 if (txmac_stat & MAC_TXSTAT_ECE) {
343 gp->net_stats.tx_aborted_errors += 0x10000;
344 gp->net_stats.collisions += 0x10000;
345 }
346
347 if (txmac_stat & MAC_TXSTAT_LCE) {
348 gp->net_stats.tx_aborted_errors += 0x10000;
349 gp->net_stats.collisions += 0x10000;
350 }
351
352 /* We do not keep track of MAC_TXSTAT_FCE and
353 * MAC_TXSTAT_PCE events.
354 */
355 return 0;
356 }
357
358 /* When we get a RX fifo overflow, the RX unit in GEM is probably hung
359 * so we do the following.
360 *
361 * If any part of the reset goes wrong, we return 1 and that causes the
362 * whole chip to be reset.
363 */
364 static int gem_rxmac_reset(struct gem *gp)
365 {
366 struct net_device *dev = gp->dev;
367 int limit, i;
368 u64 desc_dma;
369 u32 val;
370
371 /* First, reset & disable MAC RX. */
372 writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST);
373 for (limit = 0; limit < 5000; limit++) {
374 if (!(readl(gp->regs + MAC_RXRST) & MAC_RXRST_CMD))
375 break;
376 udelay(10);
377 }
378 if (limit == 5000) {
379 printk(KERN_ERR "%s: RX MAC will not reset, resetting whole "
380 "chip.\n", dev->name);
381 return 1;
382 }
383
384 writel(gp->mac_rx_cfg & ~MAC_RXCFG_ENAB,
385 gp->regs + MAC_RXCFG);
386 for (limit = 0; limit < 5000; limit++) {
387 if (!(readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB))
388 break;
389 udelay(10);
390 }
391 if (limit == 5000) {
392 printk(KERN_ERR "%s: RX MAC will not disable, resetting whole "
393 "chip.\n", dev->name);
394 return 1;
395 }
396
397 /* Second, disable RX DMA. */
398 writel(0, gp->regs + RXDMA_CFG);
399 for (limit = 0; limit < 5000; limit++) {
400 if (!(readl(gp->regs + RXDMA_CFG) & RXDMA_CFG_ENABLE))
401 break;
402 udelay(10);
403 }
404 if (limit == 5000) {
405 printk(KERN_ERR "%s: RX DMA will not disable, resetting whole "
406 "chip.\n", dev->name);
407 return 1;
408 }
409
410 udelay(5000);
411
412 /* Execute RX reset command. */
413 writel(gp->swrst_base | GREG_SWRST_RXRST,
414 gp->regs + GREG_SWRST);
415 for (limit = 0; limit < 5000; limit++) {
416 if (!(readl(gp->regs + GREG_SWRST) & GREG_SWRST_RXRST))
417 break;
418 udelay(10);
419 }
420 if (limit == 5000) {
421 printk(KERN_ERR "%s: RX reset command will not execute, resetting "
422 "whole chip.\n", dev->name);
423 return 1;
424 }
425
426 /* Refresh the RX ring. */
427 for (i = 0; i < RX_RING_SIZE; i++) {
428 struct gem_rxd *rxd = &gp->init_block->rxd[i];
429
430 if (gp->rx_skbs[i] == NULL) {
431 printk(KERN_ERR "%s: Parts of RX ring empty, resetting "
432 "whole chip.\n", dev->name);
433 return 1;
434 }
435
436 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
437 }
438 gp->rx_new = gp->rx_old = 0;
439
440 /* Now we must reprogram the rest of RX unit. */
441 desc_dma = (u64) gp->gblock_dvma;
442 desc_dma += (INIT_BLOCK_TX_RING_SIZE * sizeof(struct gem_txd));
443 writel(desc_dma >> 32, gp->regs + RXDMA_DBHI);
444 writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW);
445 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
446 val = (RXDMA_CFG_BASE | (RX_OFFSET << 10) |
447 ((14 / 2) << 13) | RXDMA_CFG_FTHRESH_128);
448 writel(val, gp->regs + RXDMA_CFG);
449 if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN)
450 writel(((5 & RXDMA_BLANK_IPKTS) |
451 ((8 << 12) & RXDMA_BLANK_ITIME)),
452 gp->regs + RXDMA_BLANK);
453 else
454 writel(((5 & RXDMA_BLANK_IPKTS) |
455 ((4 << 12) & RXDMA_BLANK_ITIME)),
456 gp->regs + RXDMA_BLANK);
457 val = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF);
458 val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON);
459 writel(val, gp->regs + RXDMA_PTHRESH);
460 val = readl(gp->regs + RXDMA_CFG);
461 writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
462 writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK);
463 val = readl(gp->regs + MAC_RXCFG);
464 writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
465
466 return 0;
467 }
468
469 static int gem_rxmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
470 {
471 u32 rxmac_stat = readl(gp->regs + MAC_RXSTAT);
472 int ret = 0;
473
474 if (netif_msg_intr(gp))
475 printk(KERN_DEBUG "%s: rxmac interrupt, rxmac_stat: 0x%x\n",
476 gp->dev->name, rxmac_stat);
477
478 if (rxmac_stat & MAC_RXSTAT_OFLW) {
479 u32 smac = readl(gp->regs + MAC_SMACHINE);
480
481 printk(KERN_ERR "%s: RX MAC fifo overflow smac[%08x].\n",
482 dev->name, smac);
483 gp->net_stats.rx_over_errors++;
484 gp->net_stats.rx_fifo_errors++;
485
486 ret = gem_rxmac_reset(gp);
487 }
488
489 if (rxmac_stat & MAC_RXSTAT_ACE)
490 gp->net_stats.rx_frame_errors += 0x10000;
491
492 if (rxmac_stat & MAC_RXSTAT_CCE)
493 gp->net_stats.rx_crc_errors += 0x10000;
494
495 if (rxmac_stat & MAC_RXSTAT_LCE)
496 gp->net_stats.rx_length_errors += 0x10000;
497
498 /* We do not track MAC_RXSTAT_FCE and MAC_RXSTAT_VCE
499 * events.
500 */
501 return ret;
502 }
503
504 static int gem_mac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
505 {
506 u32 mac_cstat = readl(gp->regs + MAC_CSTAT);
507
508 if (netif_msg_intr(gp))
509 printk(KERN_DEBUG "%s: mac interrupt, mac_cstat: 0x%x\n",
510 gp->dev->name, mac_cstat);
511
512 /* This interrupt is just for pause frame and pause
513 * tracking. It is useful for diagnostics and debug
514 * but probably by default we will mask these events.
515 */
516 if (mac_cstat & MAC_CSTAT_PS)
517 gp->pause_entered++;
518
519 if (mac_cstat & MAC_CSTAT_PRCV)
520 gp->pause_last_time_recvd = (mac_cstat >> 16);
521
522 return 0;
523 }
524
525 static int gem_mif_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
526 {
527 u32 mif_status = readl(gp->regs + MIF_STATUS);
528 u32 reg_val, changed_bits;
529
530 reg_val = (mif_status & MIF_STATUS_DATA) >> 16;
531 changed_bits = (mif_status & MIF_STATUS_STAT);
532
533 gem_handle_mif_event(gp, reg_val, changed_bits);
534
535 return 0;
536 }
537
538 static int gem_pci_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
539 {
540 u32 pci_estat = readl(gp->regs + GREG_PCIESTAT);
541
542 if (gp->pdev->vendor == PCI_VENDOR_ID_SUN &&
543 gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) {
544 printk(KERN_ERR "%s: PCI error [%04x] ",
545 dev->name, pci_estat);
546
547 if (pci_estat & GREG_PCIESTAT_BADACK)
548 printk("<No ACK64# during ABS64 cycle> ");
549 if (pci_estat & GREG_PCIESTAT_DTRTO)
550 printk("<Delayed transaction timeout> ");
551 if (pci_estat & GREG_PCIESTAT_OTHER)
552 printk("<other>");
553 printk("\n");
554 } else {
555 pci_estat |= GREG_PCIESTAT_OTHER;
556 printk(KERN_ERR "%s: PCI error\n", dev->name);
557 }
558
559 if (pci_estat & GREG_PCIESTAT_OTHER) {
560 u16 pci_cfg_stat;
561
562 /* Interrogate PCI config space for the
563 * true cause.
564 */
565 pci_read_config_word(gp->pdev, PCI_STATUS,
566 &pci_cfg_stat);
567 printk(KERN_ERR "%s: Read PCI cfg space status [%04x]\n",
568 dev->name, pci_cfg_stat);
569 if (pci_cfg_stat & PCI_STATUS_PARITY)
570 printk(KERN_ERR "%s: PCI parity error detected.\n",
571 dev->name);
572 if (pci_cfg_stat & PCI_STATUS_SIG_TARGET_ABORT)
573 printk(KERN_ERR "%s: PCI target abort.\n",
574 dev->name);
575 if (pci_cfg_stat & PCI_STATUS_REC_TARGET_ABORT)
576 printk(KERN_ERR "%s: PCI master acks target abort.\n",
577 dev->name);
578 if (pci_cfg_stat & PCI_STATUS_REC_MASTER_ABORT)
579 printk(KERN_ERR "%s: PCI master abort.\n",
580 dev->name);
581 if (pci_cfg_stat & PCI_STATUS_SIG_SYSTEM_ERROR)
582 printk(KERN_ERR "%s: PCI system error SERR#.\n",
583 dev->name);
584 if (pci_cfg_stat & PCI_STATUS_DETECTED_PARITY)
585 printk(KERN_ERR "%s: PCI parity error.\n",
586 dev->name);
587
588 /* Write the error bits back to clear them. */
589 pci_cfg_stat &= (PCI_STATUS_PARITY |
590 PCI_STATUS_SIG_TARGET_ABORT |
591 PCI_STATUS_REC_TARGET_ABORT |
592 PCI_STATUS_REC_MASTER_ABORT |
593 PCI_STATUS_SIG_SYSTEM_ERROR |
594 PCI_STATUS_DETECTED_PARITY);
595 pci_write_config_word(gp->pdev,
596 PCI_STATUS, pci_cfg_stat);
597 }
598
599 /* For all PCI errors, we should reset the chip. */
600 return 1;
601 }
602
603 /* All non-normal interrupt conditions get serviced here.
604 * Returns non-zero if we should just exit the interrupt
605 * handler right now (ie. if we reset the card which invalidates
606 * all of the other original irq status bits).
607 */
608 static int gem_abnormal_irq(struct net_device *dev, struct gem *gp, u32 gem_status)
609 {
610 if (gem_status & GREG_STAT_RXNOBUF) {
611 /* Frame arrived, no free RX buffers available. */
612 if (netif_msg_rx_err(gp))
613 printk(KERN_DEBUG "%s: no buffer for rx frame\n",
614 gp->dev->name);
615 gp->net_stats.rx_dropped++;
616 }
617
618 if (gem_status & GREG_STAT_RXTAGERR) {
619 /* corrupt RX tag framing */
620 if (netif_msg_rx_err(gp))
621 printk(KERN_DEBUG "%s: corrupt rx tag framing\n",
622 gp->dev->name);
623 gp->net_stats.rx_errors++;
624
625 goto do_reset;
626 }
627
628 if (gem_status & GREG_STAT_PCS) {
629 if (gem_pcs_interrupt(dev, gp, gem_status))
630 goto do_reset;
631 }
632
633 if (gem_status & GREG_STAT_TXMAC) {
634 if (gem_txmac_interrupt(dev, gp, gem_status))
635 goto do_reset;
636 }
637
638 if (gem_status & GREG_STAT_RXMAC) {
639 if (gem_rxmac_interrupt(dev, gp, gem_status))
640 goto do_reset;
641 }
642
643 if (gem_status & GREG_STAT_MAC) {
644 if (gem_mac_interrupt(dev, gp, gem_status))
645 goto do_reset;
646 }
647
648 if (gem_status & GREG_STAT_MIF) {
649 if (gem_mif_interrupt(dev, gp, gem_status))
650 goto do_reset;
651 }
652
653 if (gem_status & GREG_STAT_PCIERR) {
654 if (gem_pci_interrupt(dev, gp, gem_status))
655 goto do_reset;
656 }
657
658 return 0;
659
660 do_reset:
661 gp->reset_task_pending = 1;
662 schedule_work(&gp->reset_task);
663
664 return 1;
665 }
666
667 static __inline__ void gem_tx(struct net_device *dev, struct gem *gp, u32 gem_status)
668 {
669 int entry, limit;
670
671 if (netif_msg_intr(gp))
672 printk(KERN_DEBUG "%s: tx interrupt, gem_status: 0x%x\n",
673 gp->dev->name, gem_status);
674
675 entry = gp->tx_old;
676 limit = ((gem_status & GREG_STAT_TXNR) >> GREG_STAT_TXNR_SHIFT);
677 while (entry != limit) {
678 struct sk_buff *skb;
679 struct gem_txd *txd;
680 dma_addr_t dma_addr;
681 u32 dma_len;
682 int frag;
683
684 if (netif_msg_tx_done(gp))
685 printk(KERN_DEBUG "%s: tx done, slot %d\n",
686 gp->dev->name, entry);
687 skb = gp->tx_skbs[entry];
688 if (skb_shinfo(skb)->nr_frags) {
689 int last = entry + skb_shinfo(skb)->nr_frags;
690 int walk = entry;
691 int incomplete = 0;
692
693 last &= (TX_RING_SIZE - 1);
694 for (;;) {
695 walk = NEXT_TX(walk);
696 if (walk == limit)
697 incomplete = 1;
698 if (walk == last)
699 break;
700 }
701 if (incomplete)
702 break;
703 }
704 gp->tx_skbs[entry] = NULL;
705 gp->net_stats.tx_bytes += skb->len;
706
707 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
708 txd = &gp->init_block->txd[entry];
709
710 dma_addr = le64_to_cpu(txd->buffer);
711 dma_len = le64_to_cpu(txd->control_word) & TXDCTRL_BUFSZ;
712
713 pci_unmap_page(gp->pdev, dma_addr, dma_len, PCI_DMA_TODEVICE);
714 entry = NEXT_TX(entry);
715 }
716
717 gp->net_stats.tx_packets++;
718 dev_kfree_skb_irq(skb);
719 }
720 gp->tx_old = entry;
721
722 if (netif_queue_stopped(dev) &&
723 TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1))
724 netif_wake_queue(dev);
725 }
726
727 static __inline__ void gem_post_rxds(struct gem *gp, int limit)
728 {
729 int cluster_start, curr, count, kick;
730
731 cluster_start = curr = (gp->rx_new & ~(4 - 1));
732 count = 0;
733 kick = -1;
734 wmb();
735 while (curr != limit) {
736 curr = NEXT_RX(curr);
737 if (++count == 4) {
738 struct gem_rxd *rxd =
739 &gp->init_block->rxd[cluster_start];
740 for (;;) {
741 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
742 rxd++;
743 cluster_start = NEXT_RX(cluster_start);
744 if (cluster_start == curr)
745 break;
746 }
747 kick = curr;
748 count = 0;
749 }
750 }
751 if (kick >= 0) {
752 mb();
753 writel(kick, gp->regs + RXDMA_KICK);
754 }
755 }
756
757 static int gem_rx(struct gem *gp, int work_to_do)
758 {
759 int entry, drops, work_done = 0;
760 u32 done;
761 __sum16 csum;
762
763 if (netif_msg_rx_status(gp))
764 printk(KERN_DEBUG "%s: rx interrupt, done: %d, rx_new: %d\n",
765 gp->dev->name, readl(gp->regs + RXDMA_DONE), gp->rx_new);
766
767 entry = gp->rx_new;
768 drops = 0;
769 done = readl(gp->regs + RXDMA_DONE);
770 for (;;) {
771 struct gem_rxd *rxd = &gp->init_block->rxd[entry];
772 struct sk_buff *skb;
773 u64 status = le64_to_cpu(rxd->status_word);
774 dma_addr_t dma_addr;
775 int len;
776
777 if ((status & RXDCTRL_OWN) != 0)
778 break;
779
780 if (work_done >= RX_RING_SIZE || work_done >= work_to_do)
781 break;
782
783 /* When writing back RX descriptor, GEM writes status
784 * then buffer address, possibly in seperate transactions.
785 * If we don't wait for the chip to write both, we could
786 * post a new buffer to this descriptor then have GEM spam
787 * on the buffer address. We sync on the RX completion
788 * register to prevent this from happening.
789 */
790 if (entry == done) {
791 done = readl(gp->regs + RXDMA_DONE);
792 if (entry == done)
793 break;
794 }
795
796 /* We can now account for the work we're about to do */
797 work_done++;
798
799 skb = gp->rx_skbs[entry];
800
801 len = (status & RXDCTRL_BUFSZ) >> 16;
802 if ((len < ETH_ZLEN) || (status & RXDCTRL_BAD)) {
803 gp->net_stats.rx_errors++;
804 if (len < ETH_ZLEN)
805 gp->net_stats.rx_length_errors++;
806 if (len & RXDCTRL_BAD)
807 gp->net_stats.rx_crc_errors++;
808
809 /* We'll just return it to GEM. */
810 drop_it:
811 gp->net_stats.rx_dropped++;
812 goto next;
813 }
814
815 dma_addr = le64_to_cpu(rxd->buffer);
816 if (len > RX_COPY_THRESHOLD) {
817 struct sk_buff *new_skb;
818
819 new_skb = gem_alloc_skb(RX_BUF_ALLOC_SIZE(gp), GFP_ATOMIC);
820 if (new_skb == NULL) {
821 drops++;
822 goto drop_it;
823 }
824 pci_unmap_page(gp->pdev, dma_addr,
825 RX_BUF_ALLOC_SIZE(gp),
826 PCI_DMA_FROMDEVICE);
827 gp->rx_skbs[entry] = new_skb;
828 new_skb->dev = gp->dev;
829 skb_put(new_skb, (gp->rx_buf_sz + RX_OFFSET));
830 rxd->buffer = cpu_to_le64(pci_map_page(gp->pdev,
831 virt_to_page(new_skb->data),
832 offset_in_page(new_skb->data),
833 RX_BUF_ALLOC_SIZE(gp),
834 PCI_DMA_FROMDEVICE));
835 skb_reserve(new_skb, RX_OFFSET);
836
837 /* Trim the original skb for the netif. */
838 skb_trim(skb, len);
839 } else {
840 struct sk_buff *copy_skb = dev_alloc_skb(len + 2);
841
842 if (copy_skb == NULL) {
843 drops++;
844 goto drop_it;
845 }
846
847 skb_reserve(copy_skb, 2);
848 skb_put(copy_skb, len);
849 pci_dma_sync_single_for_cpu(gp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
850 skb_copy_from_linear_data(skb, copy_skb->data, len);
851 pci_dma_sync_single_for_device(gp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
852
853 /* We'll reuse the original ring buffer. */
854 skb = copy_skb;
855 }
856
857 csum = (__force __sum16)htons((status & RXDCTRL_TCPCSUM) ^ 0xffff);
858 skb->csum = csum_unfold(csum);
859 skb->ip_summed = CHECKSUM_COMPLETE;
860 skb->protocol = eth_type_trans(skb, gp->dev);
861
862 netif_receive_skb(skb);
863
864 gp->net_stats.rx_packets++;
865 gp->net_stats.rx_bytes += len;
866
867 next:
868 entry = NEXT_RX(entry);
869 }
870
871 gem_post_rxds(gp, entry);
872
873 gp->rx_new = entry;
874
875 if (drops)
876 printk(KERN_INFO "%s: Memory squeeze, deferring packet.\n",
877 gp->dev->name);
878
879 return work_done;
880 }
881
882 static int gem_poll(struct napi_struct *napi, int budget)
883 {
884 struct gem *gp = container_of(napi, struct gem, napi);
885 struct net_device *dev = gp->dev;
886 unsigned long flags;
887 int work_done;
888
889 /*
890 * NAPI locking nightmare: See comment at head of driver
891 */
892 spin_lock_irqsave(&gp->lock, flags);
893
894 work_done = 0;
895 do {
896 /* Handle anomalies */
897 if (gp->status & GREG_STAT_ABNORMAL) {
898 if (gem_abnormal_irq(dev, gp, gp->status))
899 break;
900 }
901
902 /* Run TX completion thread */
903 spin_lock(&gp->tx_lock);
904 gem_tx(dev, gp, gp->status);
905 spin_unlock(&gp->tx_lock);
906
907 spin_unlock_irqrestore(&gp->lock, flags);
908
909 /* Run RX thread. We don't use any locking here,
910 * code willing to do bad things - like cleaning the
911 * rx ring - must call napi_disable(), which
912 * schedule_timeout()'s if polling is already disabled.
913 */
914 work_done += gem_rx(gp, budget - work_done);
915
916 if (work_done >= budget)
917 return work_done;
918
919 spin_lock_irqsave(&gp->lock, flags);
920
921 gp->status = readl(gp->regs + GREG_STAT);
922 } while (gp->status & GREG_STAT_NAPI);
923
924 __netif_rx_complete(dev, napi);
925 gem_enable_ints(gp);
926
927 spin_unlock_irqrestore(&gp->lock, flags);
928
929 return work_done;
930 }
931
932 static irqreturn_t gem_interrupt(int irq, void *dev_id)
933 {
934 struct net_device *dev = dev_id;
935 struct gem *gp = netdev_priv(dev);
936 unsigned long flags;
937
938 /* Swallow interrupts when shutting the chip down, though
939 * that shouldn't happen, we should have done free_irq() at
940 * this point...
941 */
942 if (!gp->running)
943 return IRQ_HANDLED;
944
945 spin_lock_irqsave(&gp->lock, flags);
946
947 if (netif_rx_schedule_prep(dev, &gp->napi)) {
948 u32 gem_status = readl(gp->regs + GREG_STAT);
949
950 if (gem_status == 0) {
951 napi_enable(&gp->napi);
952 spin_unlock_irqrestore(&gp->lock, flags);
953 return IRQ_NONE;
954 }
955 gp->status = gem_status;
956 gem_disable_ints(gp);
957 __netif_rx_schedule(dev, &gp->napi);
958 }
959
960 spin_unlock_irqrestore(&gp->lock, flags);
961
962 /* If polling was disabled at the time we received that
963 * interrupt, we may return IRQ_HANDLED here while we
964 * should return IRQ_NONE. No big deal...
965 */
966 return IRQ_HANDLED;
967 }
968
969 #ifdef CONFIG_NET_POLL_CONTROLLER
970 static void gem_poll_controller(struct net_device *dev)
971 {
972 /* gem_interrupt is safe to reentrance so no need
973 * to disable_irq here.
974 */
975 gem_interrupt(dev->irq, dev);
976 }
977 #endif
978
979 static void gem_tx_timeout(struct net_device *dev)
980 {
981 struct gem *gp = netdev_priv(dev);
982
983 printk(KERN_ERR "%s: transmit timed out, resetting\n", dev->name);
984 if (!gp->running) {
985 printk("%s: hrm.. hw not running !\n", dev->name);
986 return;
987 }
988 printk(KERN_ERR "%s: TX_STATE[%08x:%08x:%08x]\n",
989 dev->name,
990 readl(gp->regs + TXDMA_CFG),
991 readl(gp->regs + MAC_TXSTAT),
992 readl(gp->regs + MAC_TXCFG));
993 printk(KERN_ERR "%s: RX_STATE[%08x:%08x:%08x]\n",
994 dev->name,
995 readl(gp->regs + RXDMA_CFG),
996 readl(gp->regs + MAC_RXSTAT),
997 readl(gp->regs + MAC_RXCFG));
998
999 spin_lock_irq(&gp->lock);
1000 spin_lock(&gp->tx_lock);
1001
1002 gp->reset_task_pending = 1;
1003 schedule_work(&gp->reset_task);
1004
1005 spin_unlock(&gp->tx_lock);
1006 spin_unlock_irq(&gp->lock);
1007 }
1008
1009 static __inline__ int gem_intme(int entry)
1010 {
1011 /* Algorithm: IRQ every 1/2 of descriptors. */
1012 if (!(entry & ((TX_RING_SIZE>>1)-1)))
1013 return 1;
1014
1015 return 0;
1016 }
1017
1018 static int gem_start_xmit(struct sk_buff *skb, struct net_device *dev)
1019 {
1020 struct gem *gp = netdev_priv(dev);
1021 int entry;
1022 u64 ctrl;
1023 unsigned long flags;
1024
1025 ctrl = 0;
1026 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1027 const u64 csum_start_off = skb_transport_offset(skb);
1028 const u64 csum_stuff_off = csum_start_off + skb->csum_offset;
1029
1030 ctrl = (TXDCTRL_CENAB |
1031 (csum_start_off << 15) |
1032 (csum_stuff_off << 21));
1033 }
1034
1035 local_irq_save(flags);
1036 if (!spin_trylock(&gp->tx_lock)) {
1037 /* Tell upper layer to requeue */
1038 local_irq_restore(flags);
1039 return NETDEV_TX_LOCKED;
1040 }
1041 /* We raced with gem_do_stop() */
1042 if (!gp->running) {
1043 spin_unlock_irqrestore(&gp->tx_lock, flags);
1044 return NETDEV_TX_BUSY;
1045 }
1046
1047 /* This is a hard error, log it. */
1048 if (TX_BUFFS_AVAIL(gp) <= (skb_shinfo(skb)->nr_frags + 1)) {
1049 netif_stop_queue(dev);
1050 spin_unlock_irqrestore(&gp->tx_lock, flags);
1051 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
1052 dev->name);
1053 return NETDEV_TX_BUSY;
1054 }
1055
1056 entry = gp->tx_new;
1057 gp->tx_skbs[entry] = skb;
1058
1059 if (skb_shinfo(skb)->nr_frags == 0) {
1060 struct gem_txd *txd = &gp->init_block->txd[entry];
1061 dma_addr_t mapping;
1062 u32 len;
1063
1064 len = skb->len;
1065 mapping = pci_map_page(gp->pdev,
1066 virt_to_page(skb->data),
1067 offset_in_page(skb->data),
1068 len, PCI_DMA_TODEVICE);
1069 ctrl |= TXDCTRL_SOF | TXDCTRL_EOF | len;
1070 if (gem_intme(entry))
1071 ctrl |= TXDCTRL_INTME;
1072 txd->buffer = cpu_to_le64(mapping);
1073 wmb();
1074 txd->control_word = cpu_to_le64(ctrl);
1075 entry = NEXT_TX(entry);
1076 } else {
1077 struct gem_txd *txd;
1078 u32 first_len;
1079 u64 intme;
1080 dma_addr_t first_mapping;
1081 int frag, first_entry = entry;
1082
1083 intme = 0;
1084 if (gem_intme(entry))
1085 intme |= TXDCTRL_INTME;
1086
1087 /* We must give this initial chunk to the device last.
1088 * Otherwise we could race with the device.
1089 */
1090 first_len = skb_headlen(skb);
1091 first_mapping = pci_map_page(gp->pdev, virt_to_page(skb->data),
1092 offset_in_page(skb->data),
1093 first_len, PCI_DMA_TODEVICE);
1094 entry = NEXT_TX(entry);
1095
1096 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1097 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
1098 u32 len;
1099 dma_addr_t mapping;
1100 u64 this_ctrl;
1101
1102 len = this_frag->size;
1103 mapping = pci_map_page(gp->pdev,
1104 this_frag->page,
1105 this_frag->page_offset,
1106 len, PCI_DMA_TODEVICE);
1107 this_ctrl = ctrl;
1108 if (frag == skb_shinfo(skb)->nr_frags - 1)
1109 this_ctrl |= TXDCTRL_EOF;
1110
1111 txd = &gp->init_block->txd[entry];
1112 txd->buffer = cpu_to_le64(mapping);
1113 wmb();
1114 txd->control_word = cpu_to_le64(this_ctrl | len);
1115
1116 if (gem_intme(entry))
1117 intme |= TXDCTRL_INTME;
1118
1119 entry = NEXT_TX(entry);
1120 }
1121 txd = &gp->init_block->txd[first_entry];
1122 txd->buffer = cpu_to_le64(first_mapping);
1123 wmb();
1124 txd->control_word =
1125 cpu_to_le64(ctrl | TXDCTRL_SOF | intme | first_len);
1126 }
1127
1128 gp->tx_new = entry;
1129 if (TX_BUFFS_AVAIL(gp) <= (MAX_SKB_FRAGS + 1))
1130 netif_stop_queue(dev);
1131
1132 if (netif_msg_tx_queued(gp))
1133 printk(KERN_DEBUG "%s: tx queued, slot %d, skblen %d\n",
1134 dev->name, entry, skb->len);
1135 mb();
1136 writel(gp->tx_new, gp->regs + TXDMA_KICK);
1137 spin_unlock_irqrestore(&gp->tx_lock, flags);
1138
1139 dev->trans_start = jiffies;
1140
1141 return NETDEV_TX_OK;
1142 }
1143
1144 #define STOP_TRIES 32
1145
1146 /* Must be invoked under gp->lock and gp->tx_lock. */
1147 static void gem_reset(struct gem *gp)
1148 {
1149 int limit;
1150 u32 val;
1151
1152 /* Make sure we won't get any more interrupts */
1153 writel(0xffffffff, gp->regs + GREG_IMASK);
1154
1155 /* Reset the chip */
1156 writel(gp->swrst_base | GREG_SWRST_TXRST | GREG_SWRST_RXRST,
1157 gp->regs + GREG_SWRST);
1158
1159 limit = STOP_TRIES;
1160
1161 do {
1162 udelay(20);
1163 val = readl(gp->regs + GREG_SWRST);
1164 if (limit-- <= 0)
1165 break;
1166 } while (val & (GREG_SWRST_TXRST | GREG_SWRST_RXRST));
1167
1168 if (limit <= 0)
1169 printk(KERN_ERR "%s: SW reset is ghetto.\n", gp->dev->name);
1170 }
1171
1172 /* Must be invoked under gp->lock and gp->tx_lock. */
1173 static void gem_start_dma(struct gem *gp)
1174 {
1175 u32 val;
1176
1177 /* We are ready to rock, turn everything on. */
1178 val = readl(gp->regs + TXDMA_CFG);
1179 writel(val | TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG);
1180 val = readl(gp->regs + RXDMA_CFG);
1181 writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
1182 val = readl(gp->regs + MAC_TXCFG);
1183 writel(val | MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG);
1184 val = readl(gp->regs + MAC_RXCFG);
1185 writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
1186
1187 (void) readl(gp->regs + MAC_RXCFG);
1188 udelay(100);
1189
1190 gem_enable_ints(gp);
1191
1192 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
1193 }
1194
1195 /* Must be invoked under gp->lock and gp->tx_lock. DMA won't be
1196 * actually stopped before about 4ms tho ...
1197 */
1198 static void gem_stop_dma(struct gem *gp)
1199 {
1200 u32 val;
1201
1202 /* We are done rocking, turn everything off. */
1203 val = readl(gp->regs + TXDMA_CFG);
1204 writel(val & ~TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG);
1205 val = readl(gp->regs + RXDMA_CFG);
1206 writel(val & ~RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
1207 val = readl(gp->regs + MAC_TXCFG);
1208 writel(val & ~MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG);
1209 val = readl(gp->regs + MAC_RXCFG);
1210 writel(val & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
1211
1212 (void) readl(gp->regs + MAC_RXCFG);
1213
1214 /* Need to wait a bit ... done by the caller */
1215 }
1216
1217
1218 /* Must be invoked under gp->lock and gp->tx_lock. */
1219 // XXX dbl check what that function should do when called on PCS PHY
1220 static void gem_begin_auto_negotiation(struct gem *gp, struct ethtool_cmd *ep)
1221 {
1222 u32 advertise, features;
1223 int autoneg;
1224 int speed;
1225 int duplex;
1226
1227 if (gp->phy_type != phy_mii_mdio0 &&
1228 gp->phy_type != phy_mii_mdio1)
1229 goto non_mii;
1230
1231 /* Setup advertise */
1232 if (found_mii_phy(gp))
1233 features = gp->phy_mii.def->features;
1234 else
1235 features = 0;
1236
1237 advertise = features & ADVERTISE_MASK;
1238 if (gp->phy_mii.advertising != 0)
1239 advertise &= gp->phy_mii.advertising;
1240
1241 autoneg = gp->want_autoneg;
1242 speed = gp->phy_mii.speed;
1243 duplex = gp->phy_mii.duplex;
1244
1245 /* Setup link parameters */
1246 if (!ep)
1247 goto start_aneg;
1248 if (ep->autoneg == AUTONEG_ENABLE) {
1249 advertise = ep->advertising;
1250 autoneg = 1;
1251 } else {
1252 autoneg = 0;
1253 speed = ep->speed;
1254 duplex = ep->duplex;
1255 }
1256
1257 start_aneg:
1258 /* Sanitize settings based on PHY capabilities */
1259 if ((features & SUPPORTED_Autoneg) == 0)
1260 autoneg = 0;
1261 if (speed == SPEED_1000 &&
1262 !(features & (SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full)))
1263 speed = SPEED_100;
1264 if (speed == SPEED_100 &&
1265 !(features & (SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full)))
1266 speed = SPEED_10;
1267 if (duplex == DUPLEX_FULL &&
1268 !(features & (SUPPORTED_1000baseT_Full |
1269 SUPPORTED_100baseT_Full |
1270 SUPPORTED_10baseT_Full)))
1271 duplex = DUPLEX_HALF;
1272 if (speed == 0)
1273 speed = SPEED_10;
1274
1275 /* If we are asleep, we don't try to actually setup the PHY, we
1276 * just store the settings
1277 */
1278 if (gp->asleep) {
1279 gp->phy_mii.autoneg = gp->want_autoneg = autoneg;
1280 gp->phy_mii.speed = speed;
1281 gp->phy_mii.duplex = duplex;
1282 return;
1283 }
1284
1285 /* Configure PHY & start aneg */
1286 gp->want_autoneg = autoneg;
1287 if (autoneg) {
1288 if (found_mii_phy(gp))
1289 gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, advertise);
1290 gp->lstate = link_aneg;
1291 } else {
1292 if (found_mii_phy(gp))
1293 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, speed, duplex);
1294 gp->lstate = link_force_ok;
1295 }
1296
1297 non_mii:
1298 gp->timer_ticks = 0;
1299 mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));
1300 }
1301
1302 /* A link-up condition has occurred, initialize and enable the
1303 * rest of the chip.
1304 *
1305 * Must be invoked under gp->lock and gp->tx_lock.
1306 */
1307 static int gem_set_link_modes(struct gem *gp)
1308 {
1309 u32 val;
1310 int full_duplex, speed, pause;
1311
1312 full_duplex = 0;
1313 speed = SPEED_10;
1314 pause = 0;
1315
1316 if (found_mii_phy(gp)) {
1317 if (gp->phy_mii.def->ops->read_link(&gp->phy_mii))
1318 return 1;
1319 full_duplex = (gp->phy_mii.duplex == DUPLEX_FULL);
1320 speed = gp->phy_mii.speed;
1321 pause = gp->phy_mii.pause;
1322 } else if (gp->phy_type == phy_serialink ||
1323 gp->phy_type == phy_serdes) {
1324 u32 pcs_lpa = readl(gp->regs + PCS_MIILP);
1325
1326 if (pcs_lpa & PCS_MIIADV_FD)
1327 full_duplex = 1;
1328 speed = SPEED_1000;
1329 }
1330
1331 if (netif_msg_link(gp))
1332 printk(KERN_INFO "%s: Link is up at %d Mbps, %s-duplex.\n",
1333 gp->dev->name, speed, (full_duplex ? "full" : "half"));
1334
1335 if (!gp->running)
1336 return 0;
1337
1338 val = (MAC_TXCFG_EIPG0 | MAC_TXCFG_NGU);
1339 if (full_duplex) {
1340 val |= (MAC_TXCFG_ICS | MAC_TXCFG_ICOLL);
1341 } else {
1342 /* MAC_TXCFG_NBO must be zero. */
1343 }
1344 writel(val, gp->regs + MAC_TXCFG);
1345
1346 val = (MAC_XIFCFG_OE | MAC_XIFCFG_LLED);
1347 if (!full_duplex &&
1348 (gp->phy_type == phy_mii_mdio0 ||
1349 gp->phy_type == phy_mii_mdio1)) {
1350 val |= MAC_XIFCFG_DISE;
1351 } else if (full_duplex) {
1352 val |= MAC_XIFCFG_FLED;
1353 }
1354
1355 if (speed == SPEED_1000)
1356 val |= (MAC_XIFCFG_GMII);
1357
1358 writel(val, gp->regs + MAC_XIFCFG);
1359
1360 /* If gigabit and half-duplex, enable carrier extension
1361 * mode. Else, disable it.
1362 */
1363 if (speed == SPEED_1000 && !full_duplex) {
1364 val = readl(gp->regs + MAC_TXCFG);
1365 writel(val | MAC_TXCFG_TCE, gp->regs + MAC_TXCFG);
1366
1367 val = readl(gp->regs + MAC_RXCFG);
1368 writel(val | MAC_RXCFG_RCE, gp->regs + MAC_RXCFG);
1369 } else {
1370 val = readl(gp->regs + MAC_TXCFG);
1371 writel(val & ~MAC_TXCFG_TCE, gp->regs + MAC_TXCFG);
1372
1373 val = readl(gp->regs + MAC_RXCFG);
1374 writel(val & ~MAC_RXCFG_RCE, gp->regs + MAC_RXCFG);
1375 }
1376
1377 if (gp->phy_type == phy_serialink ||
1378 gp->phy_type == phy_serdes) {
1379 u32 pcs_lpa = readl(gp->regs + PCS_MIILP);
1380
1381 if (pcs_lpa & (PCS_MIIADV_SP | PCS_MIIADV_AP))
1382 pause = 1;
1383 }
1384
1385 if (netif_msg_link(gp)) {
1386 if (pause) {
1387 printk(KERN_INFO "%s: Pause is enabled "
1388 "(rxfifo: %d off: %d on: %d)\n",
1389 gp->dev->name,
1390 gp->rx_fifo_sz,
1391 gp->rx_pause_off,
1392 gp->rx_pause_on);
1393 } else {
1394 printk(KERN_INFO "%s: Pause is disabled\n",
1395 gp->dev->name);
1396 }
1397 }
1398
1399 if (!full_duplex)
1400 writel(512, gp->regs + MAC_STIME);
1401 else
1402 writel(64, gp->regs + MAC_STIME);
1403 val = readl(gp->regs + MAC_MCCFG);
1404 if (pause)
1405 val |= (MAC_MCCFG_SPE | MAC_MCCFG_RPE);
1406 else
1407 val &= ~(MAC_MCCFG_SPE | MAC_MCCFG_RPE);
1408 writel(val, gp->regs + MAC_MCCFG);
1409
1410 gem_start_dma(gp);
1411
1412 return 0;
1413 }
1414
1415 /* Must be invoked under gp->lock and gp->tx_lock. */
1416 static int gem_mdio_link_not_up(struct gem *gp)
1417 {
1418 switch (gp->lstate) {
1419 case link_force_ret:
1420 if (netif_msg_link(gp))
1421 printk(KERN_INFO "%s: Autoneg failed again, keeping"
1422 " forced mode\n", gp->dev->name);
1423 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii,
1424 gp->last_forced_speed, DUPLEX_HALF);
1425 gp->timer_ticks = 5;
1426 gp->lstate = link_force_ok;
1427 return 0;
1428 case link_aneg:
1429 /* We try forced modes after a failed aneg only on PHYs that don't
1430 * have "magic_aneg" bit set, which means they internally do the
1431 * while forced-mode thingy. On these, we just restart aneg
1432 */
1433 if (gp->phy_mii.def->magic_aneg)
1434 return 1;
1435 if (netif_msg_link(gp))
1436 printk(KERN_INFO "%s: switching to forced 100bt\n",
1437 gp->dev->name);
1438 /* Try forced modes. */
1439 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_100,
1440 DUPLEX_HALF);
1441 gp->timer_ticks = 5;
1442 gp->lstate = link_force_try;
1443 return 0;
1444 case link_force_try:
1445 /* Downgrade from 100 to 10 Mbps if necessary.
1446 * If already at 10Mbps, warn user about the
1447 * situation every 10 ticks.
1448 */
1449 if (gp->phy_mii.speed == SPEED_100) {
1450 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_10,
1451 DUPLEX_HALF);
1452 gp->timer_ticks = 5;
1453 if (netif_msg_link(gp))
1454 printk(KERN_INFO "%s: switching to forced 10bt\n",
1455 gp->dev->name);
1456 return 0;
1457 } else
1458 return 1;
1459 default:
1460 return 0;
1461 }
1462 }
1463
1464 static void gem_link_timer(unsigned long data)
1465 {
1466 struct gem *gp = (struct gem *) data;
1467 int restart_aneg = 0;
1468
1469 if (gp->asleep)
1470 return;
1471
1472 spin_lock_irq(&gp->lock);
1473 spin_lock(&gp->tx_lock);
1474 gem_get_cell(gp);
1475
1476 /* If the reset task is still pending, we just
1477 * reschedule the link timer
1478 */
1479 if (gp->reset_task_pending)
1480 goto restart;
1481
1482 if (gp->phy_type == phy_serialink ||
1483 gp->phy_type == phy_serdes) {
1484 u32 val = readl(gp->regs + PCS_MIISTAT);
1485
1486 if (!(val & PCS_MIISTAT_LS))
1487 val = readl(gp->regs + PCS_MIISTAT);
1488
1489 if ((val & PCS_MIISTAT_LS) != 0) {
1490 gp->lstate = link_up;
1491 netif_carrier_on(gp->dev);
1492 (void)gem_set_link_modes(gp);
1493 }
1494 goto restart;
1495 }
1496 if (found_mii_phy(gp) && gp->phy_mii.def->ops->poll_link(&gp->phy_mii)) {
1497 /* Ok, here we got a link. If we had it due to a forced
1498 * fallback, and we were configured for autoneg, we do
1499 * retry a short autoneg pass. If you know your hub is
1500 * broken, use ethtool ;)
1501 */
1502 if (gp->lstate == link_force_try && gp->want_autoneg) {
1503 gp->lstate = link_force_ret;
1504 gp->last_forced_speed = gp->phy_mii.speed;
1505 gp->timer_ticks = 5;
1506 if (netif_msg_link(gp))
1507 printk(KERN_INFO "%s: Got link after fallback, retrying"
1508 " autoneg once...\n", gp->dev->name);
1509 gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, gp->phy_mii.advertising);
1510 } else if (gp->lstate != link_up) {
1511 gp->lstate = link_up;
1512 netif_carrier_on(gp->dev);
1513 if (gem_set_link_modes(gp))
1514 restart_aneg = 1;
1515 }
1516 } else {
1517 /* If the link was previously up, we restart the
1518 * whole process
1519 */
1520 if (gp->lstate == link_up) {
1521 gp->lstate = link_down;
1522 if (netif_msg_link(gp))
1523 printk(KERN_INFO "%s: Link down\n",
1524 gp->dev->name);
1525 netif_carrier_off(gp->dev);
1526 gp->reset_task_pending = 1;
1527 schedule_work(&gp->reset_task);
1528 restart_aneg = 1;
1529 } else if (++gp->timer_ticks > 10) {
1530 if (found_mii_phy(gp))
1531 restart_aneg = gem_mdio_link_not_up(gp);
1532 else
1533 restart_aneg = 1;
1534 }
1535 }
1536 if (restart_aneg) {
1537 gem_begin_auto_negotiation(gp, NULL);
1538 goto out_unlock;
1539 }
1540 restart:
1541 mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));
1542 out_unlock:
1543 gem_put_cell(gp);
1544 spin_unlock(&gp->tx_lock);
1545 spin_unlock_irq(&gp->lock);
1546 }
1547
1548 /* Must be invoked under gp->lock and gp->tx_lock. */
1549 static void gem_clean_rings(struct gem *gp)
1550 {
1551 struct gem_init_block *gb = gp->init_block;
1552 struct sk_buff *skb;
1553 int i;
1554 dma_addr_t dma_addr;
1555
1556 for (i = 0; i < RX_RING_SIZE; i++) {
1557 struct gem_rxd *rxd;
1558
1559 rxd = &gb->rxd[i];
1560 if (gp->rx_skbs[i] != NULL) {
1561 skb = gp->rx_skbs[i];
1562 dma_addr = le64_to_cpu(rxd->buffer);
1563 pci_unmap_page(gp->pdev, dma_addr,
1564 RX_BUF_ALLOC_SIZE(gp),
1565 PCI_DMA_FROMDEVICE);
1566 dev_kfree_skb_any(skb);
1567 gp->rx_skbs[i] = NULL;
1568 }
1569 rxd->status_word = 0;
1570 wmb();
1571 rxd->buffer = 0;
1572 }
1573
1574 for (i = 0; i < TX_RING_SIZE; i++) {
1575 if (gp->tx_skbs[i] != NULL) {
1576 struct gem_txd *txd;
1577 int frag;
1578
1579 skb = gp->tx_skbs[i];
1580 gp->tx_skbs[i] = NULL;
1581
1582 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1583 int ent = i & (TX_RING_SIZE - 1);
1584
1585 txd = &gb->txd[ent];
1586 dma_addr = le64_to_cpu(txd->buffer);
1587 pci_unmap_page(gp->pdev, dma_addr,
1588 le64_to_cpu(txd->control_word) &
1589 TXDCTRL_BUFSZ, PCI_DMA_TODEVICE);
1590
1591 if (frag != skb_shinfo(skb)->nr_frags)
1592 i++;
1593 }
1594 dev_kfree_skb_any(skb);
1595 }
1596 }
1597 }
1598
1599 /* Must be invoked under gp->lock and gp->tx_lock. */
1600 static void gem_init_rings(struct gem *gp)
1601 {
1602 struct gem_init_block *gb = gp->init_block;
1603 struct net_device *dev = gp->dev;
1604 int i;
1605 dma_addr_t dma_addr;
1606
1607 gp->rx_new = gp->rx_old = gp->tx_new = gp->tx_old = 0;
1608
1609 gem_clean_rings(gp);
1610
1611 gp->rx_buf_sz = max(dev->mtu + ETH_HLEN + VLAN_HLEN,
1612 (unsigned)VLAN_ETH_FRAME_LEN);
1613
1614 for (i = 0; i < RX_RING_SIZE; i++) {
1615 struct sk_buff *skb;
1616 struct gem_rxd *rxd = &gb->rxd[i];
1617
1618 skb = gem_alloc_skb(RX_BUF_ALLOC_SIZE(gp), GFP_ATOMIC);
1619 if (!skb) {
1620 rxd->buffer = 0;
1621 rxd->status_word = 0;
1622 continue;
1623 }
1624
1625 gp->rx_skbs[i] = skb;
1626 skb->dev = dev;
1627 skb_put(skb, (gp->rx_buf_sz + RX_OFFSET));
1628 dma_addr = pci_map_page(gp->pdev,
1629 virt_to_page(skb->data),
1630 offset_in_page(skb->data),
1631 RX_BUF_ALLOC_SIZE(gp),
1632 PCI_DMA_FROMDEVICE);
1633 rxd->buffer = cpu_to_le64(dma_addr);
1634 wmb();
1635 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
1636 skb_reserve(skb, RX_OFFSET);
1637 }
1638
1639 for (i = 0; i < TX_RING_SIZE; i++) {
1640 struct gem_txd *txd = &gb->txd[i];
1641
1642 txd->control_word = 0;
1643 wmb();
1644 txd->buffer = 0;
1645 }
1646 wmb();
1647 }
1648
1649 /* Init PHY interface and start link poll state machine */
1650 static void gem_init_phy(struct gem *gp)
1651 {
1652 u32 mifcfg;
1653
1654 /* Revert MIF CFG setting done on stop_phy */
1655 mifcfg = readl(gp->regs + MIF_CFG);
1656 mifcfg &= ~MIF_CFG_BBMODE;
1657 writel(mifcfg, gp->regs + MIF_CFG);
1658
1659 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE) {
1660 int i;
1661
1662 /* Those delay sucks, the HW seem to love them though, I'll
1663 * serisouly consider breaking some locks here to be able
1664 * to schedule instead
1665 */
1666 for (i = 0; i < 3; i++) {
1667 #ifdef CONFIG_PPC_PMAC
1668 pmac_call_feature(PMAC_FTR_GMAC_PHY_RESET, gp->of_node, 0, 0);
1669 msleep(20);
1670 #endif
1671 /* Some PHYs used by apple have problem getting back to us,
1672 * we do an additional reset here
1673 */
1674 phy_write(gp, MII_BMCR, BMCR_RESET);
1675 msleep(20);
1676 if (phy_read(gp, MII_BMCR) != 0xffff)
1677 break;
1678 if (i == 2)
1679 printk(KERN_WARNING "%s: GMAC PHY not responding !\n",
1680 gp->dev->name);
1681 }
1682 }
1683
1684 if (gp->pdev->vendor == PCI_VENDOR_ID_SUN &&
1685 gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) {
1686 u32 val;
1687
1688 /* Init datapath mode register. */
1689 if (gp->phy_type == phy_mii_mdio0 ||
1690 gp->phy_type == phy_mii_mdio1) {
1691 val = PCS_DMODE_MGM;
1692 } else if (gp->phy_type == phy_serialink) {
1693 val = PCS_DMODE_SM | PCS_DMODE_GMOE;
1694 } else {
1695 val = PCS_DMODE_ESM;
1696 }
1697
1698 writel(val, gp->regs + PCS_DMODE);
1699 }
1700
1701 if (gp->phy_type == phy_mii_mdio0 ||
1702 gp->phy_type == phy_mii_mdio1) {
1703 // XXX check for errors
1704 mii_phy_probe(&gp->phy_mii, gp->mii_phy_addr);
1705
1706 /* Init PHY */
1707 if (gp->phy_mii.def && gp->phy_mii.def->ops->init)
1708 gp->phy_mii.def->ops->init(&gp->phy_mii);
1709 } else {
1710 u32 val;
1711 int limit;
1712
1713 /* Reset PCS unit. */
1714 val = readl(gp->regs + PCS_MIICTRL);
1715 val |= PCS_MIICTRL_RST;
1716 writel(val, gp->regs + PCS_MIICTRL);
1717
1718 limit = 32;
1719 while (readl(gp->regs + PCS_MIICTRL) & PCS_MIICTRL_RST) {
1720 udelay(100);
1721 if (limit-- <= 0)
1722 break;
1723 }
1724 if (limit <= 0)
1725 printk(KERN_WARNING "%s: PCS reset bit would not clear.\n",
1726 gp->dev->name);
1727
1728 /* Make sure PCS is disabled while changing advertisement
1729 * configuration.
1730 */
1731 val = readl(gp->regs + PCS_CFG);
1732 val &= ~(PCS_CFG_ENABLE | PCS_CFG_TO);
1733 writel(val, gp->regs + PCS_CFG);
1734
1735 /* Advertise all capabilities except assymetric
1736 * pause.
1737 */
1738 val = readl(gp->regs + PCS_MIIADV);
1739 val |= (PCS_MIIADV_FD | PCS_MIIADV_HD |
1740 PCS_MIIADV_SP | PCS_MIIADV_AP);
1741 writel(val, gp->regs + PCS_MIIADV);
1742
1743 /* Enable and restart auto-negotiation, disable wrapback/loopback,
1744 * and re-enable PCS.
1745 */
1746 val = readl(gp->regs + PCS_MIICTRL);
1747 val |= (PCS_MIICTRL_RAN | PCS_MIICTRL_ANE);
1748 val &= ~PCS_MIICTRL_WB;
1749 writel(val, gp->regs + PCS_MIICTRL);
1750
1751 val = readl(gp->regs + PCS_CFG);
1752 val |= PCS_CFG_ENABLE;
1753 writel(val, gp->regs + PCS_CFG);
1754
1755 /* Make sure serialink loopback is off. The meaning
1756 * of this bit is logically inverted based upon whether
1757 * you are in Serialink or SERDES mode.
1758 */
1759 val = readl(gp->regs + PCS_SCTRL);
1760 if (gp->phy_type == phy_serialink)
1761 val &= ~PCS_SCTRL_LOOP;
1762 else
1763 val |= PCS_SCTRL_LOOP;
1764 writel(val, gp->regs + PCS_SCTRL);
1765 }
1766
1767 /* Default aneg parameters */
1768 gp->timer_ticks = 0;
1769 gp->lstate = link_down;
1770 netif_carrier_off(gp->dev);
1771
1772 /* Can I advertise gigabit here ? I'd need BCM PHY docs... */
1773 spin_lock_irq(&gp->lock);
1774 gem_begin_auto_negotiation(gp, NULL);
1775 spin_unlock_irq(&gp->lock);
1776 }
1777
1778 /* Must be invoked under gp->lock and gp->tx_lock. */
1779 static void gem_init_dma(struct gem *gp)
1780 {
1781 u64 desc_dma = (u64) gp->gblock_dvma;
1782 u32 val;
1783
1784 val = (TXDMA_CFG_BASE | (0x7ff << 10) | TXDMA_CFG_PMODE);
1785 writel(val, gp->regs + TXDMA_CFG);
1786
1787 writel(desc_dma >> 32, gp->regs + TXDMA_DBHI);
1788 writel(desc_dma & 0xffffffff, gp->regs + TXDMA_DBLOW);
1789 desc_dma += (INIT_BLOCK_TX_RING_SIZE * sizeof(struct gem_txd));
1790
1791 writel(0, gp->regs + TXDMA_KICK);
1792
1793 val = (RXDMA_CFG_BASE | (RX_OFFSET << 10) |
1794 ((14 / 2) << 13) | RXDMA_CFG_FTHRESH_128);
1795 writel(val, gp->regs + RXDMA_CFG);
1796
1797 writel(desc_dma >> 32, gp->regs + RXDMA_DBHI);
1798 writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW);
1799
1800 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
1801
1802 val = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF);
1803 val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON);
1804 writel(val, gp->regs + RXDMA_PTHRESH);
1805
1806 if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN)
1807 writel(((5 & RXDMA_BLANK_IPKTS) |
1808 ((8 << 12) & RXDMA_BLANK_ITIME)),
1809 gp->regs + RXDMA_BLANK);
1810 else
1811 writel(((5 & RXDMA_BLANK_IPKTS) |
1812 ((4 << 12) & RXDMA_BLANK_ITIME)),
1813 gp->regs + RXDMA_BLANK);
1814 }
1815
1816 /* Must be invoked under gp->lock and gp->tx_lock. */
1817 static u32 gem_setup_multicast(struct gem *gp)
1818 {
1819 u32 rxcfg = 0;
1820 int i;
1821
1822 if ((gp->dev->flags & IFF_ALLMULTI) ||
1823 (gp->dev->mc_count > 256)) {
1824 for (i=0; i<16; i++)
1825 writel(0xffff, gp->regs + MAC_HASH0 + (i << 2));
1826 rxcfg |= MAC_RXCFG_HFE;
1827 } else if (gp->dev->flags & IFF_PROMISC) {
1828 rxcfg |= MAC_RXCFG_PROM;
1829 } else {
1830 u16 hash_table[16];
1831 u32 crc;
1832 struct dev_mc_list *dmi = gp->dev->mc_list;
1833 int i;
1834
1835 for (i = 0; i < 16; i++)
1836 hash_table[i] = 0;
1837
1838 for (i = 0; i < gp->dev->mc_count; i++) {
1839 char *addrs = dmi->dmi_addr;
1840
1841 dmi = dmi->next;
1842
1843 if (!(*addrs & 1))
1844 continue;
1845
1846 crc = ether_crc_le(6, addrs);
1847 crc >>= 24;
1848 hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
1849 }
1850 for (i=0; i<16; i++)
1851 writel(hash_table[i], gp->regs + MAC_HASH0 + (i << 2));
1852 rxcfg |= MAC_RXCFG_HFE;
1853 }
1854
1855 return rxcfg;
1856 }
1857
1858 /* Must be invoked under gp->lock and gp->tx_lock. */
1859 static void gem_init_mac(struct gem *gp)
1860 {
1861 unsigned char *e = &gp->dev->dev_addr[0];
1862
1863 writel(0x1bf0, gp->regs + MAC_SNDPAUSE);
1864
1865 writel(0x00, gp->regs + MAC_IPG0);
1866 writel(0x08, gp->regs + MAC_IPG1);
1867 writel(0x04, gp->regs + MAC_IPG2);
1868 writel(0x40, gp->regs + MAC_STIME);
1869 writel(0x40, gp->regs + MAC_MINFSZ);
1870
1871 /* Ethernet payload + header + FCS + optional VLAN tag. */
1872 writel(0x20000000 | (gp->rx_buf_sz + 4), gp->regs + MAC_MAXFSZ);
1873
1874 writel(0x07, gp->regs + MAC_PASIZE);
1875 writel(0x04, gp->regs + MAC_JAMSIZE);
1876 writel(0x10, gp->regs + MAC_ATTLIM);
1877 writel(0x8808, gp->regs + MAC_MCTYPE);
1878
1879 writel((e[5] | (e[4] << 8)) & 0x3ff, gp->regs + MAC_RANDSEED);
1880
1881 writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0);
1882 writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1);
1883 writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2);
1884
1885 writel(0, gp->regs + MAC_ADDR3);
1886 writel(0, gp->regs + MAC_ADDR4);
1887 writel(0, gp->regs + MAC_ADDR5);
1888
1889 writel(0x0001, gp->regs + MAC_ADDR6);
1890 writel(0xc200, gp->regs + MAC_ADDR7);
1891 writel(0x0180, gp->regs + MAC_ADDR8);
1892
1893 writel(0, gp->regs + MAC_AFILT0);
1894 writel(0, gp->regs + MAC_AFILT1);
1895 writel(0, gp->regs + MAC_AFILT2);
1896 writel(0, gp->regs + MAC_AF21MSK);
1897 writel(0, gp->regs + MAC_AF0MSK);
1898
1899 gp->mac_rx_cfg = gem_setup_multicast(gp);
1900 #ifdef STRIP_FCS
1901 gp->mac_rx_cfg |= MAC_RXCFG_SFCS;
1902 #endif
1903 writel(0, gp->regs + MAC_NCOLL);
1904 writel(0, gp->regs + MAC_FASUCC);
1905 writel(0, gp->regs + MAC_ECOLL);
1906 writel(0, gp->regs + MAC_LCOLL);
1907 writel(0, gp->regs + MAC_DTIMER);
1908 writel(0, gp->regs + MAC_PATMPS);
1909 writel(0, gp->regs + MAC_RFCTR);
1910 writel(0, gp->regs + MAC_LERR);
1911 writel(0, gp->regs + MAC_AERR);
1912 writel(0, gp->regs + MAC_FCSERR);
1913 writel(0, gp->regs + MAC_RXCVERR);
1914
1915 /* Clear RX/TX/MAC/XIF config, we will set these up and enable
1916 * them once a link is established.
1917 */
1918 writel(0, gp->regs + MAC_TXCFG);
1919 writel(gp->mac_rx_cfg, gp->regs + MAC_RXCFG);
1920 writel(0, gp->regs + MAC_MCCFG);
1921 writel(0, gp->regs + MAC_XIFCFG);
1922
1923 /* Setup MAC interrupts. We want to get all of the interesting
1924 * counter expiration events, but we do not want to hear about
1925 * normal rx/tx as the DMA engine tells us that.
1926 */
1927 writel(MAC_TXSTAT_XMIT, gp->regs + MAC_TXMASK);
1928 writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK);
1929
1930 /* Don't enable even the PAUSE interrupts for now, we
1931 * make no use of those events other than to record them.
1932 */
1933 writel(0xffffffff, gp->regs + MAC_MCMASK);
1934
1935 /* Don't enable GEM's WOL in normal operations
1936 */
1937 if (gp->has_wol)
1938 writel(0, gp->regs + WOL_WAKECSR);
1939 }
1940
1941 /* Must be invoked under gp->lock and gp->tx_lock. */
1942 static void gem_init_pause_thresholds(struct gem *gp)
1943 {
1944 u32 cfg;
1945
1946 /* Calculate pause thresholds. Setting the OFF threshold to the
1947 * full RX fifo size effectively disables PAUSE generation which
1948 * is what we do for 10/100 only GEMs which have FIFOs too small
1949 * to make real gains from PAUSE.
1950 */
1951 if (gp->rx_fifo_sz <= (2 * 1024)) {
1952 gp->rx_pause_off = gp->rx_pause_on = gp->rx_fifo_sz;
1953 } else {
1954 int max_frame = (gp->rx_buf_sz + 4 + 64) & ~63;
1955 int off = (gp->rx_fifo_sz - (max_frame * 2));
1956 int on = off - max_frame;
1957
1958 gp->rx_pause_off = off;
1959 gp->rx_pause_on = on;
1960 }
1961
1962
1963 /* Configure the chip "burst" DMA mode & enable some
1964 * HW bug fixes on Apple version
1965 */
1966 cfg = 0;
1967 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE)
1968 cfg |= GREG_CFG_RONPAULBIT | GREG_CFG_ENBUG2FIX;
1969 #if !defined(CONFIG_SPARC64) && !defined(CONFIG_ALPHA)
1970 cfg |= GREG_CFG_IBURST;
1971 #endif
1972 cfg |= ((31 << 1) & GREG_CFG_TXDMALIM);
1973 cfg |= ((31 << 6) & GREG_CFG_RXDMALIM);
1974 writel(cfg, gp->regs + GREG_CFG);
1975
1976 /* If Infinite Burst didn't stick, then use different
1977 * thresholds (and Apple bug fixes don't exist)
1978 */
1979 if (!(readl(gp->regs + GREG_CFG) & GREG_CFG_IBURST)) {
1980 cfg = ((2 << 1) & GREG_CFG_TXDMALIM);
1981 cfg |= ((8 << 6) & GREG_CFG_RXDMALIM);
1982 writel(cfg, gp->regs + GREG_CFG);
1983 }
1984 }
1985
1986 static int gem_check_invariants(struct gem *gp)
1987 {
1988 struct pci_dev *pdev = gp->pdev;
1989 u32 mif_cfg;
1990
1991 /* On Apple's sungem, we can't rely on registers as the chip
1992 * was been powered down by the firmware. The PHY is looked
1993 * up later on.
1994 */
1995 if (pdev->vendor == PCI_VENDOR_ID_APPLE) {
1996 gp->phy_type = phy_mii_mdio0;
1997 gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64;
1998 gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64;
1999 gp->swrst_base = 0;
2000
2001 mif_cfg = readl(gp->regs + MIF_CFG);
2002 mif_cfg &= ~(MIF_CFG_PSELECT|MIF_CFG_POLL|MIF_CFG_BBMODE|MIF_CFG_MDI1);
2003 mif_cfg |= MIF_CFG_MDI0;
2004 writel(mif_cfg, gp->regs + MIF_CFG);
2005 writel(PCS_DMODE_MGM, gp->regs + PCS_DMODE);
2006 writel(MAC_XIFCFG_OE, gp->regs + MAC_XIFCFG);
2007
2008 /* We hard-code the PHY address so we can properly bring it out of
2009 * reset later on, we can't really probe it at this point, though
2010 * that isn't an issue.
2011 */
2012 if (gp->pdev->device == PCI_DEVICE_ID_APPLE_K2_GMAC)
2013 gp->mii_phy_addr = 1;
2014 else
2015 gp->mii_phy_addr = 0;
2016
2017 return 0;
2018 }
2019
2020 mif_cfg = readl(gp->regs + MIF_CFG);
2021
2022 if (pdev->vendor == PCI_VENDOR_ID_SUN &&
2023 pdev->device == PCI_DEVICE_ID_SUN_RIO_GEM) {
2024 /* One of the MII PHYs _must_ be present
2025 * as this chip has no gigabit PHY.
2026 */
2027 if ((mif_cfg & (MIF_CFG_MDI0 | MIF_CFG_MDI1)) == 0) {
2028 printk(KERN_ERR PFX "RIO GEM lacks MII phy, mif_cfg[%08x]\n",
2029 mif_cfg);
2030 return -1;
2031 }
2032 }
2033
2034 /* Determine initial PHY interface type guess. MDIO1 is the
2035 * external PHY and thus takes precedence over MDIO0.
2036 */
2037
2038 if (mif_cfg & MIF_CFG_MDI1) {
2039 gp->phy_type = phy_mii_mdio1;
2040 mif_cfg |= MIF_CFG_PSELECT;
2041 writel(mif_cfg, gp->regs + MIF_CFG);
2042 } else if (mif_cfg & MIF_CFG_MDI0) {
2043 gp->phy_type = phy_mii_mdio0;
2044 mif_cfg &= ~MIF_CFG_PSELECT;
2045 writel(mif_cfg, gp->regs + MIF_CFG);
2046 } else {
2047 gp->phy_type = phy_serialink;
2048 }
2049 if (gp->phy_type == phy_mii_mdio1 ||
2050 gp->phy_type == phy_mii_mdio0) {
2051 int i;
2052
2053 for (i = 0; i < 32; i++) {
2054 gp->mii_phy_addr = i;
2055 if (phy_read(gp, MII_BMCR) != 0xffff)
2056 break;
2057 }
2058 if (i == 32) {
2059 if (pdev->device != PCI_DEVICE_ID_SUN_GEM) {
2060 printk(KERN_ERR PFX "RIO MII phy will not respond.\n");
2061 return -1;
2062 }
2063 gp->phy_type = phy_serdes;
2064 }
2065 }
2066
2067 /* Fetch the FIFO configurations now too. */
2068 gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64;
2069 gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64;
2070
2071 if (pdev->vendor == PCI_VENDOR_ID_SUN) {
2072 if (pdev->device == PCI_DEVICE_ID_SUN_GEM) {
2073 if (gp->tx_fifo_sz != (9 * 1024) ||
2074 gp->rx_fifo_sz != (20 * 1024)) {
2075 printk(KERN_ERR PFX "GEM has bogus fifo sizes tx(%d) rx(%d)\n",
2076 gp->tx_fifo_sz, gp->rx_fifo_sz);
2077 return -1;
2078 }
2079 gp->swrst_base = 0;
2080 } else {
2081 if (gp->tx_fifo_sz != (2 * 1024) ||
2082 gp->rx_fifo_sz != (2 * 1024)) {
2083 printk(KERN_ERR PFX "RIO GEM has bogus fifo sizes tx(%d) rx(%d)\n",
2084 gp->tx_fifo_sz, gp->rx_fifo_sz);
2085 return -1;
2086 }
2087 gp->swrst_base = (64 / 4) << GREG_SWRST_CACHE_SHIFT;
2088 }
2089 }
2090
2091 return 0;
2092 }
2093
2094 /* Must be invoked under gp->lock and gp->tx_lock. */
2095 static void gem_reinit_chip(struct gem *gp)
2096 {
2097 /* Reset the chip */
2098 gem_reset(gp);
2099
2100 /* Make sure ints are disabled */
2101 gem_disable_ints(gp);
2102
2103 /* Allocate & setup ring buffers */
2104 gem_init_rings(gp);
2105
2106 /* Configure pause thresholds */
2107 gem_init_pause_thresholds(gp);
2108
2109 /* Init DMA & MAC engines */
2110 gem_init_dma(gp);
2111 gem_init_mac(gp);
2112 }
2113
2114
2115 /* Must be invoked with no lock held. */
2116 static void gem_stop_phy(struct gem *gp, int wol)
2117 {
2118 u32 mifcfg;
2119 unsigned long flags;
2120
2121 /* Let the chip settle down a bit, it seems that helps
2122 * for sleep mode on some models
2123 */
2124 msleep(10);
2125
2126 /* Make sure we aren't polling PHY status change. We
2127 * don't currently use that feature though
2128 */
2129 mifcfg = readl(gp->regs + MIF_CFG);
2130 mifcfg &= ~MIF_CFG_POLL;
2131 writel(mifcfg, gp->regs + MIF_CFG);
2132
2133 if (wol && gp->has_wol) {
2134 unsigned char *e = &gp->dev->dev_addr[0];
2135 u32 csr;
2136
2137 /* Setup wake-on-lan for MAGIC packet */
2138 writel(MAC_RXCFG_HFE | MAC_RXCFG_SFCS | MAC_RXCFG_ENAB,
2139 gp->regs + MAC_RXCFG);
2140 writel((e[4] << 8) | e[5], gp->regs + WOL_MATCH0);
2141 writel((e[2] << 8) | e[3], gp->regs + WOL_MATCH1);
2142 writel((e[0] << 8) | e[1], gp->regs + WOL_MATCH2);
2143
2144 writel(WOL_MCOUNT_N | WOL_MCOUNT_M, gp->regs + WOL_MCOUNT);
2145 csr = WOL_WAKECSR_ENABLE;
2146 if ((readl(gp->regs + MAC_XIFCFG) & MAC_XIFCFG_GMII) == 0)
2147 csr |= WOL_WAKECSR_MII;
2148 writel(csr, gp->regs + WOL_WAKECSR);
2149 } else {
2150 writel(0, gp->regs + MAC_RXCFG);
2151 (void)readl(gp->regs + MAC_RXCFG);
2152 /* Machine sleep will die in strange ways if we
2153 * dont wait a bit here, looks like the chip takes
2154 * some time to really shut down
2155 */
2156 msleep(10);
2157 }
2158
2159 writel(0, gp->regs + MAC_TXCFG);
2160 writel(0, gp->regs + MAC_XIFCFG);
2161 writel(0, gp->regs + TXDMA_CFG);
2162 writel(0, gp->regs + RXDMA_CFG);
2163
2164 if (!wol) {
2165 spin_lock_irqsave(&gp->lock, flags);
2166 spin_lock(&gp->tx_lock);
2167 gem_reset(gp);
2168 writel(MAC_TXRST_CMD, gp->regs + MAC_TXRST);
2169 writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST);
2170 spin_unlock(&gp->tx_lock);
2171 spin_unlock_irqrestore(&gp->lock, flags);
2172
2173 /* No need to take the lock here */
2174
2175 if (found_mii_phy(gp) && gp->phy_mii.def->ops->suspend)
2176 gp->phy_mii.def->ops->suspend(&gp->phy_mii);
2177
2178 /* According to Apple, we must set the MDIO pins to this begnign
2179 * state or we may 1) eat more current, 2) damage some PHYs
2180 */
2181 writel(mifcfg | MIF_CFG_BBMODE, gp->regs + MIF_CFG);
2182 writel(0, gp->regs + MIF_BBCLK);
2183 writel(0, gp->regs + MIF_BBDATA);
2184 writel(0, gp->regs + MIF_BBOENAB);
2185 writel(MAC_XIFCFG_GMII | MAC_XIFCFG_LBCK, gp->regs + MAC_XIFCFG);
2186 (void) readl(gp->regs + MAC_XIFCFG);
2187 }
2188 }
2189
2190
2191 static int gem_do_start(struct net_device *dev)
2192 {
2193 struct gem *gp = netdev_priv(dev);
2194 unsigned long flags;
2195
2196 spin_lock_irqsave(&gp->lock, flags);
2197 spin_lock(&gp->tx_lock);
2198
2199 /* Enable the cell */
2200 gem_get_cell(gp);
2201
2202 /* Init & setup chip hardware */
2203 gem_reinit_chip(gp);
2204
2205 gp->running = 1;
2206
2207 if (gp->lstate == link_up) {
2208 netif_carrier_on(gp->dev);
2209 gem_set_link_modes(gp);
2210 }
2211
2212 netif_wake_queue(gp->dev);
2213
2214 spin_unlock(&gp->tx_lock);
2215 spin_unlock_irqrestore(&gp->lock, flags);
2216
2217 if (request_irq(gp->pdev->irq, gem_interrupt,
2218 IRQF_SHARED, dev->name, (void *)dev)) {
2219 printk(KERN_ERR "%s: failed to request irq !\n", gp->dev->name);
2220
2221 spin_lock_irqsave(&gp->lock, flags);
2222 spin_lock(&gp->tx_lock);
2223
2224 gp->running = 0;
2225 gem_reset(gp);
2226 gem_clean_rings(gp);
2227 gem_put_cell(gp);
2228
2229 spin_unlock(&gp->tx_lock);
2230 spin_unlock_irqrestore(&gp->lock, flags);
2231
2232 return -EAGAIN;
2233 }
2234
2235 return 0;
2236 }
2237
2238 static void gem_do_stop(struct net_device *dev, int wol)
2239 {
2240 struct gem *gp = netdev_priv(dev);
2241 unsigned long flags;
2242
2243 spin_lock_irqsave(&gp->lock, flags);
2244 spin_lock(&gp->tx_lock);
2245
2246 gp->running = 0;
2247
2248 /* Stop netif queue */
2249 netif_stop_queue(dev);
2250
2251 /* Make sure ints are disabled */
2252 gem_disable_ints(gp);
2253
2254 /* We can drop the lock now */
2255 spin_unlock(&gp->tx_lock);
2256 spin_unlock_irqrestore(&gp->lock, flags);
2257
2258 /* If we are going to sleep with WOL */
2259 gem_stop_dma(gp);
2260 msleep(10);
2261 if (!wol)
2262 gem_reset(gp);
2263 msleep(10);
2264
2265 /* Get rid of rings */
2266 gem_clean_rings(gp);
2267
2268 /* No irq needed anymore */
2269 free_irq(gp->pdev->irq, (void *) dev);
2270
2271 /* Cell not needed neither if no WOL */
2272 if (!wol) {
2273 spin_lock_irqsave(&gp->lock, flags);
2274 gem_put_cell(gp);
2275 spin_unlock_irqrestore(&gp->lock, flags);
2276 }
2277 }
2278
2279 static void gem_reset_task(struct work_struct *work)
2280 {
2281 struct gem *gp = container_of(work, struct gem, reset_task);
2282
2283 mutex_lock(&gp->pm_mutex);
2284
2285 if (gp->opened)
2286 napi_disable(&gp->napi);
2287
2288 spin_lock_irq(&gp->lock);
2289 spin_lock(&gp->tx_lock);
2290
2291 if (gp->running) {
2292 netif_stop_queue(gp->dev);
2293
2294 /* Reset the chip & rings */
2295 gem_reinit_chip(gp);
2296 if (gp->lstate == link_up)
2297 gem_set_link_modes(gp);
2298 netif_wake_queue(gp->dev);
2299 }
2300
2301 gp->reset_task_pending = 0;
2302
2303 spin_unlock(&gp->tx_lock);
2304 spin_unlock_irq(&gp->lock);
2305
2306 if (gp->opened)
2307 napi_enable(&gp->napi);
2308
2309 mutex_unlock(&gp->pm_mutex);
2310 }
2311
2312
2313 static int gem_open(struct net_device *dev)
2314 {
2315 struct gem *gp = netdev_priv(dev);
2316 int rc = 0;
2317
2318 mutex_lock(&gp->pm_mutex);
2319
2320 /* We need the cell enabled */
2321 if (!gp->asleep)
2322 rc = gem_do_start(dev);
2323 gp->opened = (rc == 0);
2324 if (gp->opened)
2325 napi_enable(&gp->napi);
2326
2327 mutex_unlock(&gp->pm_mutex);
2328
2329 return rc;
2330 }
2331
2332 static int gem_close(struct net_device *dev)
2333 {
2334 struct gem *gp = netdev_priv(dev);
2335
2336 mutex_lock(&gp->pm_mutex);
2337
2338 napi_disable(&gp->napi);
2339
2340 gp->opened = 0;
2341 if (!gp->asleep)
2342 gem_do_stop(dev, 0);
2343
2344 mutex_unlock(&gp->pm_mutex);
2345
2346 return 0;
2347 }
2348
2349 #ifdef CONFIG_PM
2350 static int gem_suspend(struct pci_dev *pdev, pm_message_t state)
2351 {
2352 struct net_device *dev = pci_get_drvdata(pdev);
2353 struct gem *gp = netdev_priv(dev);
2354 unsigned long flags;
2355
2356 mutex_lock(&gp->pm_mutex);
2357
2358 printk(KERN_INFO "%s: suspending, WakeOnLan %s\n",
2359 dev->name,
2360 (gp->wake_on_lan && gp->opened) ? "enabled" : "disabled");
2361
2362 /* Keep the cell enabled during the entire operation */
2363 spin_lock_irqsave(&gp->lock, flags);
2364 spin_lock(&gp->tx_lock);
2365 gem_get_cell(gp);
2366 spin_unlock(&gp->tx_lock);
2367 spin_unlock_irqrestore(&gp->lock, flags);
2368
2369 /* If the driver is opened, we stop the MAC */
2370 if (gp->opened) {
2371 napi_disable(&gp->napi);
2372
2373 /* Stop traffic, mark us closed */
2374 netif_device_detach(dev);
2375
2376 /* Switch off MAC, remember WOL setting */
2377 gp->asleep_wol = gp->wake_on_lan;
2378 gem_do_stop(dev, gp->asleep_wol);
2379 } else
2380 gp->asleep_wol = 0;
2381
2382 /* Mark us asleep */
2383 gp->asleep = 1;
2384 wmb();
2385
2386 /* Stop the link timer */
2387 del_timer_sync(&gp->link_timer);
2388
2389 /* Now we release the mutex to not block the reset task who
2390 * can take it too. We are marked asleep, so there will be no
2391 * conflict here
2392 */
2393 mutex_unlock(&gp->pm_mutex);
2394
2395 /* Wait for a pending reset task to complete */
2396 while (gp->reset_task_pending)
2397 yield();
2398 flush_scheduled_work();
2399
2400 /* Shut the PHY down eventually and setup WOL */
2401 gem_stop_phy(gp, gp->asleep_wol);
2402
2403 /* Make sure bus master is disabled */
2404 pci_disable_device(gp->pdev);
2405
2406 /* Release the cell, no need to take a lock at this point since
2407 * nothing else can happen now
2408 */
2409 gem_put_cell(gp);
2410
2411 return 0;
2412 }
2413
2414 static int gem_resume(struct pci_dev *pdev)
2415 {
2416 struct net_device *dev = pci_get_drvdata(pdev);
2417 struct gem *gp = netdev_priv(dev);
2418 unsigned long flags;
2419
2420 printk(KERN_INFO "%s: resuming\n", dev->name);
2421
2422 mutex_lock(&gp->pm_mutex);
2423
2424 /* Keep the cell enabled during the entire operation, no need to
2425 * take a lock here tho since nothing else can happen while we are
2426 * marked asleep
2427 */
2428 gem_get_cell(gp);
2429
2430 /* Make sure PCI access and bus master are enabled */
2431 if (pci_enable_device(gp->pdev)) {
2432 printk(KERN_ERR "%s: Can't re-enable chip !\n",
2433 dev->name);
2434 /* Put cell and forget it for now, it will be considered as
2435 * still asleep, a new sleep cycle may bring it back
2436 */
2437 gem_put_cell(gp);
2438 mutex_unlock(&gp->pm_mutex);
2439 return 0;
2440 }
2441 pci_set_master(gp->pdev);
2442
2443 /* Reset everything */
2444 gem_reset(gp);
2445
2446 /* Mark us woken up */
2447 gp->asleep = 0;
2448 wmb();
2449
2450 /* Bring the PHY back. Again, lock is useless at this point as
2451 * nothing can be happening until we restart the whole thing
2452 */
2453 gem_init_phy(gp);
2454
2455 /* If we were opened, bring everything back */
2456 if (gp->opened) {
2457 /* Restart MAC */
2458 gem_do_start(dev);
2459
2460 /* Re-attach net device */
2461 netif_device_attach(dev);
2462
2463 napi_enable(&gp->napi);
2464 }
2465
2466 spin_lock_irqsave(&gp->lock, flags);
2467 spin_lock(&gp->tx_lock);
2468
2469 /* If we had WOL enabled, the cell clock was never turned off during
2470 * sleep, so we end up beeing unbalanced. Fix that here
2471 */
2472 if (gp->asleep_wol)
2473 gem_put_cell(gp);
2474
2475 /* This function doesn't need to hold the cell, it will be held if the
2476 * driver is open by gem_do_start().
2477 */
2478 gem_put_cell(gp);
2479
2480 spin_unlock(&gp->tx_lock);
2481 spin_unlock_irqrestore(&gp->lock, flags);
2482
2483 mutex_unlock(&gp->pm_mutex);
2484
2485 return 0;
2486 }
2487 #endif /* CONFIG_PM */
2488
2489 static struct net_device_stats *gem_get_stats(struct net_device *dev)
2490 {
2491 struct gem *gp = netdev_priv(dev);
2492 struct net_device_stats *stats = &gp->net_stats;
2493
2494 spin_lock_irq(&gp->lock);
2495 spin_lock(&gp->tx_lock);
2496
2497 /* I have seen this being called while the PM was in progress,
2498 * so we shield against this
2499 */
2500 if (gp->running) {
2501 stats->rx_crc_errors += readl(gp->regs + MAC_FCSERR);
2502 writel(0, gp->regs + MAC_FCSERR);
2503
2504 stats->rx_frame_errors += readl(gp->regs + MAC_AERR);
2505 writel(0, gp->regs + MAC_AERR);
2506
2507 stats->rx_length_errors += readl(gp->regs + MAC_LERR);
2508 writel(0, gp->regs + MAC_LERR);
2509
2510 stats->tx_aborted_errors += readl(gp->regs + MAC_ECOLL);
2511 stats->collisions +=
2512 (readl(gp->regs + MAC_ECOLL) +
2513 readl(gp->regs + MAC_LCOLL));
2514 writel(0, gp->regs + MAC_ECOLL);
2515 writel(0, gp->regs + MAC_LCOLL);
2516 }
2517
2518 spin_unlock(&gp->tx_lock);
2519 spin_unlock_irq(&gp->lock);
2520
2521 return &gp->net_stats;
2522 }
2523
2524 static int gem_set_mac_address(struct net_device *dev, void *addr)
2525 {
2526 struct sockaddr *macaddr = (struct sockaddr *) addr;
2527 struct gem *gp = netdev_priv(dev);
2528 unsigned char *e = &dev->dev_addr[0];
2529
2530 if (!is_valid_ether_addr(macaddr->sa_data))
2531 return -EADDRNOTAVAIL;
2532
2533 if (!netif_running(dev) || !netif_device_present(dev)) {
2534 /* We'll just catch it later when the
2535 * device is up'd or resumed.
2536 */
2537 memcpy(dev->dev_addr, macaddr->sa_data, dev->addr_len);
2538 return 0;
2539 }
2540
2541 mutex_lock(&gp->pm_mutex);
2542 memcpy(dev->dev_addr, macaddr->sa_data, dev->addr_len);
2543 if (gp->running) {
2544 writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0);
2545 writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1);
2546 writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2);
2547 }
2548 mutex_unlock(&gp->pm_mutex);
2549
2550 return 0;
2551 }
2552
2553 static void gem_set_multicast(struct net_device *dev)
2554 {
2555 struct gem *gp = netdev_priv(dev);
2556 u32 rxcfg, rxcfg_new;
2557 int limit = 10000;
2558
2559
2560 spin_lock_irq(&gp->lock);
2561 spin_lock(&gp->tx_lock);
2562
2563 if (!gp->running)
2564 goto bail;
2565
2566 netif_stop_queue(dev);
2567
2568 rxcfg = readl(gp->regs + MAC_RXCFG);
2569 rxcfg_new = gem_setup_multicast(gp);
2570 #ifdef STRIP_FCS
2571 rxcfg_new |= MAC_RXCFG_SFCS;
2572 #endif
2573 gp->mac_rx_cfg = rxcfg_new;
2574
2575 writel(rxcfg & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
2576 while (readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB) {
2577 if (!limit--)
2578 break;
2579 udelay(10);
2580 }
2581
2582 rxcfg &= ~(MAC_RXCFG_PROM | MAC_RXCFG_HFE);
2583 rxcfg |= rxcfg_new;
2584
2585 writel(rxcfg, gp->regs + MAC_RXCFG);
2586
2587 netif_wake_queue(dev);
2588
2589 bail:
2590 spin_unlock(&gp->tx_lock);
2591 spin_unlock_irq(&gp->lock);
2592 }
2593
2594 /* Jumbo-grams don't seem to work :-( */
2595 #define GEM_MIN_MTU 68
2596 #if 1
2597 #define GEM_MAX_MTU 1500
2598 #else
2599 #define GEM_MAX_MTU 9000
2600 #endif
2601
2602 static int gem_change_mtu(struct net_device *dev, int new_mtu)
2603 {
2604 struct gem *gp = netdev_priv(dev);
2605
2606 if (new_mtu < GEM_MIN_MTU || new_mtu > GEM_MAX_MTU)
2607 return -EINVAL;
2608
2609 if (!netif_running(dev) || !netif_device_present(dev)) {
2610 /* We'll just catch it later when the
2611 * device is up'd or resumed.
2612 */
2613 dev->mtu = new_mtu;
2614 return 0;
2615 }
2616
2617 mutex_lock(&gp->pm_mutex);
2618 spin_lock_irq(&gp->lock);
2619 spin_lock(&gp->tx_lock);
2620 dev->mtu = new_mtu;
2621 if (gp->running) {
2622 gem_reinit_chip(gp);
2623 if (gp->lstate == link_up)
2624 gem_set_link_modes(gp);
2625 }
2626 spin_unlock(&gp->tx_lock);
2627 spin_unlock_irq(&gp->lock);
2628 mutex_unlock(&gp->pm_mutex);
2629
2630 return 0;
2631 }
2632
2633 static void gem_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2634 {
2635 struct gem *gp = netdev_priv(dev);
2636
2637 strcpy(info->driver, DRV_NAME);
2638 strcpy(info->version, DRV_VERSION);
2639 strcpy(info->bus_info, pci_name(gp->pdev));
2640 }
2641
2642 static int gem_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2643 {
2644 struct gem *gp = netdev_priv(dev);
2645
2646 if (gp->phy_type == phy_mii_mdio0 ||
2647 gp->phy_type == phy_mii_mdio1) {
2648 if (gp->phy_mii.def)
2649 cmd->supported = gp->phy_mii.def->features;
2650 else
2651 cmd->supported = (SUPPORTED_10baseT_Half |
2652 SUPPORTED_10baseT_Full);
2653
2654 /* XXX hardcoded stuff for now */
2655 cmd->port = PORT_MII;
2656 cmd->transceiver = XCVR_EXTERNAL;
2657 cmd->phy_address = 0; /* XXX fixed PHYAD */
2658
2659 /* Return current PHY settings */
2660 spin_lock_irq(&gp->lock);
2661 cmd->autoneg = gp->want_autoneg;
2662 cmd->speed = gp->phy_mii.speed;
2663 cmd->duplex = gp->phy_mii.duplex;
2664 cmd->advertising = gp->phy_mii.advertising;
2665
2666 /* If we started with a forced mode, we don't have a default
2667 * advertise set, we need to return something sensible so
2668 * userland can re-enable autoneg properly.
2669 */
2670 if (cmd->advertising == 0)
2671 cmd->advertising = cmd->supported;
2672 spin_unlock_irq(&gp->lock);
2673 } else { // XXX PCS ?
2674 cmd->supported =
2675 (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2676 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2677 SUPPORTED_Autoneg);
2678 cmd->advertising = cmd->supported;
2679 cmd->speed = 0;
2680 cmd->duplex = cmd->port = cmd->phy_address =
2681 cmd->transceiver = cmd->autoneg = 0;
2682 }
2683 cmd->maxtxpkt = cmd->maxrxpkt = 0;
2684
2685 return 0;
2686 }
2687
2688 static int gem_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2689 {
2690 struct gem *gp = netdev_priv(dev);
2691
2692 /* Verify the settings we care about. */
2693 if (cmd->autoneg != AUTONEG_ENABLE &&
2694 cmd->autoneg != AUTONEG_DISABLE)
2695 return -EINVAL;
2696
2697 if (cmd->autoneg == AUTONEG_ENABLE &&
2698 cmd->advertising == 0)
2699 return -EINVAL;
2700
2701 if (cmd->autoneg == AUTONEG_DISABLE &&
2702 ((cmd->speed != SPEED_1000 &&
2703 cmd->speed != SPEED_100 &&
2704 cmd->speed != SPEED_10) ||
2705 (cmd->duplex != DUPLEX_HALF &&
2706 cmd->duplex != DUPLEX_FULL)))
2707 return -EINVAL;
2708
2709 /* Apply settings and restart link process. */
2710 spin_lock_irq(&gp->lock);
2711 gem_get_cell(gp);
2712 gem_begin_auto_negotiation(gp, cmd);
2713 gem_put_cell(gp);
2714 spin_unlock_irq(&gp->lock);
2715
2716 return 0;
2717 }
2718
2719 static int gem_nway_reset(struct net_device *dev)
2720 {
2721 struct gem *gp = netdev_priv(dev);
2722
2723 if (!gp->want_autoneg)
2724 return -EINVAL;
2725
2726 /* Restart link process. */
2727 spin_lock_irq(&gp->lock);
2728 gem_get_cell(gp);
2729 gem_begin_auto_negotiation(gp, NULL);
2730 gem_put_cell(gp);
2731 spin_unlock_irq(&gp->lock);
2732
2733 return 0;
2734 }
2735
2736 static u32 gem_get_msglevel(struct net_device *dev)
2737 {
2738 struct gem *gp = netdev_priv(dev);
2739 return gp->msg_enable;
2740 }
2741
2742 static void gem_set_msglevel(struct net_device *dev, u32 value)
2743 {
2744 struct gem *gp = netdev_priv(dev);
2745 gp->msg_enable = value;
2746 }
2747
2748
2749 /* Add more when I understand how to program the chip */
2750 /* like WAKE_UCAST | WAKE_MCAST | WAKE_BCAST */
2751
2752 #define WOL_SUPPORTED_MASK (WAKE_MAGIC)
2753
2754 static void gem_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2755 {
2756 struct gem *gp = netdev_priv(dev);
2757
2758 /* Add more when I understand how to program the chip */
2759 if (gp->has_wol) {
2760 wol->supported = WOL_SUPPORTED_MASK;
2761 wol->wolopts = gp->wake_on_lan;
2762 } else {
2763 wol->supported = 0;
2764 wol->wolopts = 0;
2765 }
2766 }
2767
2768 static int gem_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2769 {
2770 struct gem *gp = netdev_priv(dev);
2771
2772 if (!gp->has_wol)
2773 return -EOPNOTSUPP;
2774 gp->wake_on_lan = wol->wolopts & WOL_SUPPORTED_MASK;
2775 return 0;
2776 }
2777
2778 static const struct ethtool_ops gem_ethtool_ops = {
2779 .get_drvinfo = gem_get_drvinfo,
2780 .get_link = ethtool_op_get_link,
2781 .get_settings = gem_get_settings,
2782 .set_settings = gem_set_settings,
2783 .nway_reset = gem_nway_reset,
2784 .get_msglevel = gem_get_msglevel,
2785 .set_msglevel = gem_set_msglevel,
2786 .get_wol = gem_get_wol,
2787 .set_wol = gem_set_wol,
2788 };
2789
2790 static int gem_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2791 {
2792 struct gem *gp = netdev_priv(dev);
2793 struct mii_ioctl_data *data = if_mii(ifr);
2794 int rc = -EOPNOTSUPP;
2795 unsigned long flags;
2796
2797 /* Hold the PM mutex while doing ioctl's or we may collide
2798 * with power management.
2799 */
2800 mutex_lock(&gp->pm_mutex);
2801
2802 spin_lock_irqsave(&gp->lock, flags);
2803 gem_get_cell(gp);
2804 spin_unlock_irqrestore(&gp->lock, flags);
2805
2806 switch (cmd) {
2807 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
2808 data->phy_id = gp->mii_phy_addr;
2809 /* Fallthrough... */
2810
2811 case SIOCGMIIREG: /* Read MII PHY register. */
2812 if (!gp->running)
2813 rc = -EAGAIN;
2814 else {
2815 data->val_out = __phy_read(gp, data->phy_id & 0x1f,
2816 data->reg_num & 0x1f);
2817 rc = 0;
2818 }
2819 break;
2820
2821 case SIOCSMIIREG: /* Write MII PHY register. */
2822 if (!capable(CAP_NET_ADMIN))
2823 rc = -EPERM;
2824 else if (!gp->running)
2825 rc = -EAGAIN;
2826 else {
2827 __phy_write(gp, data->phy_id & 0x1f, data->reg_num & 0x1f,
2828 data->val_in);
2829 rc = 0;
2830 }
2831 break;
2832 };
2833
2834 spin_lock_irqsave(&gp->lock, flags);
2835 gem_put_cell(gp);
2836 spin_unlock_irqrestore(&gp->lock, flags);
2837
2838 mutex_unlock(&gp->pm_mutex);
2839
2840 return rc;
2841 }
2842
2843 #if (!defined(CONFIG_SPARC) && !defined(CONFIG_PPC_PMAC))
2844 /* Fetch MAC address from vital product data of PCI ROM. */
2845 static int find_eth_addr_in_vpd(void __iomem *rom_base, int len, unsigned char *dev_addr)
2846 {
2847 int this_offset;
2848
2849 for (this_offset = 0x20; this_offset < len; this_offset++) {
2850 void __iomem *p = rom_base + this_offset;
2851 int i;
2852
2853 if (readb(p + 0) != 0x90 ||
2854 readb(p + 1) != 0x00 ||
2855 readb(p + 2) != 0x09 ||
2856 readb(p + 3) != 0x4e ||
2857 readb(p + 4) != 0x41 ||
2858 readb(p + 5) != 0x06)
2859 continue;
2860
2861 this_offset += 6;
2862 p += 6;
2863
2864 for (i = 0; i < 6; i++)
2865 dev_addr[i] = readb(p + i);
2866 return 1;
2867 }
2868 return 0;
2869 }
2870
2871 static void get_gem_mac_nonobp(struct pci_dev *pdev, unsigned char *dev_addr)
2872 {
2873 size_t size;
2874 void __iomem *p = pci_map_rom(pdev, &size);
2875
2876 if (p) {
2877 int found;
2878
2879 found = readb(p) == 0x55 &&
2880 readb(p + 1) == 0xaa &&
2881 find_eth_addr_in_vpd(p, (64 * 1024), dev_addr);
2882 pci_unmap_rom(pdev, p);
2883 if (found)
2884 return;
2885 }
2886
2887 /* Sun MAC prefix then 3 random bytes. */
2888 dev_addr[0] = 0x08;
2889 dev_addr[1] = 0x00;
2890 dev_addr[2] = 0x20;
2891 get_random_bytes(dev_addr + 3, 3);
2892 return;
2893 }
2894 #endif /* not Sparc and not PPC */
2895
2896 static int __devinit gem_get_device_address(struct gem *gp)
2897 {
2898 #if defined(CONFIG_SPARC) || defined(CONFIG_PPC_PMAC)
2899 struct net_device *dev = gp->dev;
2900 const unsigned char *addr;
2901
2902 addr = of_get_property(gp->of_node, "local-mac-address", NULL);
2903 if (addr == NULL) {
2904 #ifdef CONFIG_SPARC
2905 addr = idprom->id_ethaddr;
2906 #else
2907 printk("\n");
2908 printk(KERN_ERR "%s: can't get mac-address\n", dev->name);
2909 return -1;
2910 #endif
2911 }
2912 memcpy(dev->dev_addr, addr, 6);
2913 #else
2914 get_gem_mac_nonobp(gp->pdev, gp->dev->dev_addr);
2915 #endif
2916 return 0;
2917 }
2918
2919 static void gem_remove_one(struct pci_dev *pdev)
2920 {
2921 struct net_device *dev = pci_get_drvdata(pdev);
2922
2923 if (dev) {
2924 struct gem *gp = netdev_priv(dev);
2925
2926 unregister_netdev(dev);
2927
2928 /* Stop the link timer */
2929 del_timer_sync(&gp->link_timer);
2930
2931 /* We shouldn't need any locking here */
2932 gem_get_cell(gp);
2933
2934 /* Wait for a pending reset task to complete */
2935 while (gp->reset_task_pending)
2936 yield();
2937 flush_scheduled_work();
2938
2939 /* Shut the PHY down */
2940 gem_stop_phy(gp, 0);
2941
2942 gem_put_cell(gp);
2943
2944 /* Make sure bus master is disabled */
2945 pci_disable_device(gp->pdev);
2946
2947 /* Free resources */
2948 pci_free_consistent(pdev,
2949 sizeof(struct gem_init_block),
2950 gp->init_block,
2951 gp->gblock_dvma);
2952 iounmap(gp->regs);
2953 pci_release_regions(pdev);
2954 free_netdev(dev);
2955
2956 pci_set_drvdata(pdev, NULL);
2957 }
2958 }
2959
2960 static int __devinit gem_init_one(struct pci_dev *pdev,
2961 const struct pci_device_id *ent)
2962 {
2963 static int gem_version_printed = 0;
2964 unsigned long gemreg_base, gemreg_len;
2965 struct net_device *dev;
2966 struct gem *gp;
2967 int err, pci_using_dac;
2968
2969 if (gem_version_printed++ == 0)
2970 printk(KERN_INFO "%s", version);
2971
2972 /* Apple gmac note: during probe, the chip is powered up by
2973 * the arch code to allow the code below to work (and to let
2974 * the chip be probed on the config space. It won't stay powered
2975 * up until the interface is brought up however, so we can't rely
2976 * on register configuration done at this point.
2977 */
2978 err = pci_enable_device(pdev);
2979 if (err) {
2980 printk(KERN_ERR PFX "Cannot enable MMIO operation, "
2981 "aborting.\n");
2982 return err;
2983 }
2984 pci_set_master(pdev);
2985
2986 /* Configure DMA attributes. */
2987
2988 /* All of the GEM documentation states that 64-bit DMA addressing
2989 * is fully supported and should work just fine. However the
2990 * front end for RIO based GEMs is different and only supports
2991 * 32-bit addressing.
2992 *
2993 * For now we assume the various PPC GEMs are 32-bit only as well.
2994 */
2995 if (pdev->vendor == PCI_VENDOR_ID_SUN &&
2996 pdev->device == PCI_DEVICE_ID_SUN_GEM &&
2997 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
2998 pci_using_dac = 1;
2999 } else {
3000 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3001 if (err) {
3002 printk(KERN_ERR PFX "No usable DMA configuration, "
3003 "aborting.\n");
3004 goto err_disable_device;
3005 }
3006 pci_using_dac = 0;
3007 }
3008
3009 gemreg_base = pci_resource_start(pdev, 0);
3010 gemreg_len = pci_resource_len(pdev, 0);
3011
3012 if ((pci_resource_flags(pdev, 0) & IORESOURCE_IO) != 0) {
3013 printk(KERN_ERR PFX "Cannot find proper PCI device "
3014 "base address, aborting.\n");
3015 err = -ENODEV;
3016 goto err_disable_device;
3017 }
3018
3019 dev = alloc_etherdev(sizeof(*gp));
3020 if (!dev) {
3021 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
3022 err = -ENOMEM;
3023 goto err_disable_device;
3024 }
3025 SET_NETDEV_DEV(dev, &pdev->dev);
3026
3027 gp = netdev_priv(dev);
3028
3029 err = pci_request_regions(pdev, DRV_NAME);
3030 if (err) {
3031 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
3032 "aborting.\n");
3033 goto err_out_free_netdev;
3034 }
3035
3036 gp->pdev = pdev;
3037 dev->base_addr = (long) pdev;
3038 gp->dev = dev;
3039
3040 gp->msg_enable = DEFAULT_MSG;
3041
3042 spin_lock_init(&gp->lock);
3043 spin_lock_init(&gp->tx_lock);
3044 mutex_init(&gp->pm_mutex);
3045
3046 init_timer(&gp->link_timer);
3047 gp->link_timer.function = gem_link_timer;
3048 gp->link_timer.data = (unsigned long) gp;
3049
3050 INIT_WORK(&gp->reset_task, gem_reset_task);
3051
3052 gp->lstate = link_down;
3053 gp->timer_ticks = 0;
3054 netif_carrier_off(dev);
3055
3056 gp->regs = ioremap(gemreg_base, gemreg_len);
3057 if (!gp->regs) {
3058 printk(KERN_ERR PFX "Cannot map device registers, "
3059 "aborting.\n");
3060 err = -EIO;
3061 goto err_out_free_res;
3062 }
3063
3064 /* On Apple, we want a reference to the Open Firmware device-tree
3065 * node. We use it for clock control.
3066 */
3067 #if defined(CONFIG_PPC_PMAC) || defined(CONFIG_SPARC)
3068 gp->of_node = pci_device_to_OF_node(pdev);
3069 #endif
3070
3071 /* Only Apple version supports WOL afaik */
3072 if (pdev->vendor == PCI_VENDOR_ID_APPLE)
3073 gp->has_wol = 1;
3074
3075 /* Make sure cell is enabled */
3076 gem_get_cell(gp);
3077
3078 /* Make sure everything is stopped and in init state */
3079 gem_reset(gp);
3080
3081 /* Fill up the mii_phy structure (even if we won't use it) */
3082 gp->phy_mii.dev = dev;
3083 gp->phy_mii.mdio_read = _phy_read;
3084 gp->phy_mii.mdio_write = _phy_write;
3085 #ifdef CONFIG_PPC_PMAC
3086 gp->phy_mii.platform_data = gp->of_node;
3087 #endif
3088 /* By default, we start with autoneg */
3089 gp->want_autoneg = 1;
3090
3091 /* Check fifo sizes, PHY type, etc... */
3092 if (gem_check_invariants(gp)) {
3093 err = -ENODEV;
3094 goto err_out_iounmap;
3095 }
3096
3097 /* It is guaranteed that the returned buffer will be at least
3098 * PAGE_SIZE aligned.
3099 */
3100 gp->init_block = (struct gem_init_block *)
3101 pci_alloc_consistent(pdev, sizeof(struct gem_init_block),
3102 &gp->gblock_dvma);
3103 if (!gp->init_block) {
3104 printk(KERN_ERR PFX "Cannot allocate init block, "
3105 "aborting.\n");
3106 err = -ENOMEM;
3107 goto err_out_iounmap;
3108 }
3109
3110 if (gem_get_device_address(gp))
3111 goto err_out_free_consistent;
3112
3113 dev->open = gem_open;
3114 dev->stop = gem_close;
3115 dev->hard_start_xmit = gem_start_xmit;
3116 dev->get_stats = gem_get_stats;
3117 dev->set_multicast_list = gem_set_multicast;
3118 dev->do_ioctl = gem_ioctl;
3119 netif_napi_add(dev, &gp->napi, gem_poll, 64);
3120 dev->ethtool_ops = &gem_ethtool_ops;
3121 dev->tx_timeout = gem_tx_timeout;
3122 dev->watchdog_timeo = 5 * HZ;
3123 dev->change_mtu = gem_change_mtu;
3124 dev->irq = pdev->irq;
3125 dev->dma = 0;
3126 dev->set_mac_address = gem_set_mac_address;
3127 #ifdef CONFIG_NET_POLL_CONTROLLER
3128 dev->poll_controller = gem_poll_controller;
3129 #endif
3130
3131 /* Set that now, in case PM kicks in now */
3132 pci_set_drvdata(pdev, dev);
3133
3134 /* Detect & init PHY, start autoneg, we release the cell now
3135 * too, it will be managed by whoever needs it
3136 */
3137 gem_init_phy(gp);
3138
3139 spin_lock_irq(&gp->lock);
3140 gem_put_cell(gp);
3141 spin_unlock_irq(&gp->lock);
3142
3143 /* Register with kernel */
3144 if (register_netdev(dev)) {
3145 printk(KERN_ERR PFX "Cannot register net device, "
3146 "aborting.\n");
3147 err = -ENOMEM;
3148 goto err_out_free_consistent;
3149 }
3150
3151 printk(KERN_INFO "%s: Sun GEM (PCI) 10/100/1000BaseT Ethernet %pM\n",
3152 dev->name, dev->dev_addr);
3153
3154 if (gp->phy_type == phy_mii_mdio0 ||
3155 gp->phy_type == phy_mii_mdio1)
3156 printk(KERN_INFO "%s: Found %s PHY\n", dev->name,
3157 gp->phy_mii.def ? gp->phy_mii.def->name : "no");
3158
3159 /* GEM can do it all... */
3160 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_LLTX;
3161 if (pci_using_dac)
3162 dev->features |= NETIF_F_HIGHDMA;
3163
3164 return 0;
3165
3166 err_out_free_consistent:
3167 gem_remove_one(pdev);
3168 err_out_iounmap:
3169 gem_put_cell(gp);
3170 iounmap(gp->regs);
3171
3172 err_out_free_res:
3173 pci_release_regions(pdev);
3174
3175 err_out_free_netdev:
3176 free_netdev(dev);
3177 err_disable_device:
3178 pci_disable_device(pdev);
3179 return err;
3180
3181 }
3182
3183
3184 static struct pci_driver gem_driver = {
3185 .name = GEM_MODULE_NAME,
3186 .id_table = gem_pci_tbl,
3187 .probe = gem_init_one,
3188 .remove = gem_remove_one,
3189 #ifdef CONFIG_PM
3190 .suspend = gem_suspend,
3191 .resume = gem_resume,
3192 #endif /* CONFIG_PM */
3193 };
3194
3195 static int __init gem_init(void)
3196 {
3197 return pci_register_driver(&gem_driver);
3198 }
3199
3200 static void __exit gem_cleanup(void)
3201 {
3202 pci_unregister_driver(&gem_driver);
3203 }
3204
3205 module_init(gem_init);
3206 module_exit(gem_cleanup);
Linux 2.6 libata-dev (mirror)