2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
5 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Much of the core SMP work is based on previous work by Thomas Radke, to
8 * whom a great many thanks are extended.
10 * Thanks to Intel for making available several different Pentium,
11 * Pentium Pro and Pentium-II/Xeon MP machines.
12 * Original development of Linux SMP code supported by Caldera.
14 * This code is released under the GNU General Public License version 2 or
18 * Felix Koop : NR_CPUS used properly
19 * Jose Renau : Handle single CPU case.
20 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
21 * Greg Wright : Fix for kernel stacks panic.
22 * Erich Boleyn : MP v1.4 and additional changes.
23 * Matthias Sattler : Changes for 2.1 kernel map.
24 * Michel Lespinasse : Changes for 2.1 kernel map.
25 * Michael Chastain : Change trampoline.S to gnu as.
26 * Alan Cox : Dumb bug: 'B' step PPro's are fine
27 * Ingo Molnar : Added APIC timers, based on code
29 * Ingo Molnar : various cleanups and rewrites
30 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
31 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
32 * Martin J. Bligh : Added support for multi-quad systems
33 * Dave Jones : Report invalid combinations of Athlon CPUs.
34 * Rusty Russell : Hacked into shape for new "hotplug" boot process. */
36 #include <linux/module.h>
37 #include <linux/init.h>
38 #include <linux/kernel.h>
41 #include <linux/sched.h>
42 #include <linux/kernel_stat.h>
43 #include <linux/smp_lock.h>
44 #include <linux/bootmem.h>
45 #include <linux/notifier.h>
46 #include <linux/cpu.h>
47 #include <linux/percpu.h>
48 #include <linux/nmi.h>
50 #include <linux/delay.h>
51 #include <linux/mc146818rtc.h>
52 #include <asm/tlbflush.h>
54 #include <asm/arch_hooks.h>
57 #include <mach_apic.h>
58 #include <mach_wakecpu.h>
59 #include <smpboot_hooks.h>
63 /* Set if we find a B stepping CPU */
64 static int __devinitdata smp_b_stepping
;
66 /* Number of siblings per CPU package */
67 int smp_num_siblings
= 1;
68 EXPORT_SYMBOL(smp_num_siblings
);
70 /* Last level cache ID of each logical CPU */
71 int cpu_llc_id
[NR_CPUS
] __cpuinitdata
= {[0 ... NR_CPUS
-1] = BAD_APICID
};
73 /* representing HT siblings of each logical CPU */
74 cpumask_t cpu_sibling_map
[NR_CPUS
] __read_mostly
;
75 EXPORT_SYMBOL(cpu_sibling_map
);
77 /* representing HT and core siblings of each logical CPU */
78 cpumask_t cpu_core_map
[NR_CPUS
] __read_mostly
;
79 EXPORT_SYMBOL(cpu_core_map
);
81 /* bitmap of online cpus */
82 cpumask_t cpu_online_map __read_mostly
;
83 EXPORT_SYMBOL(cpu_online_map
);
85 cpumask_t cpu_callin_map
;
86 cpumask_t cpu_callout_map
;
87 EXPORT_SYMBOL(cpu_callout_map
);
88 cpumask_t cpu_possible_map
;
89 EXPORT_SYMBOL(cpu_possible_map
);
90 static cpumask_t smp_commenced_mask
;
92 /* Per CPU bogomips and other parameters */
93 struct cpuinfo_x86 cpu_data
[NR_CPUS
] __cacheline_aligned
;
94 EXPORT_SYMBOL(cpu_data
);
96 u8 x86_cpu_to_apicid
[NR_CPUS
] __read_mostly
=
97 { [0 ... NR_CPUS
-1] = 0xff };
98 EXPORT_SYMBOL(x86_cpu_to_apicid
);
100 u8 apicid_2_node
[MAX_APICID
];
102 DEFINE_PER_CPU(unsigned long, this_cpu_off
);
103 EXPORT_PER_CPU_SYMBOL(this_cpu_off
);
106 * Trampoline 80x86 program as an array.
109 extern unsigned char trampoline_data
[];
110 extern unsigned char trampoline_end
[];
111 static unsigned char *trampoline_base
;
112 static int trampoline_exec
;
114 static void map_cpu_to_logical_apicid(void);
116 /* State of each CPU. */
117 DEFINE_PER_CPU(int, cpu_state
) = { 0 };
120 * Currently trivial. Write the real->protected mode
121 * bootstrap into the page concerned. The caller
122 * has made sure it's suitably aligned.
125 static unsigned long __devinit
setup_trampoline(void)
127 memcpy(trampoline_base
, trampoline_data
, trampoline_end
- trampoline_data
);
128 return virt_to_phys(trampoline_base
);
132 * We are called very early to get the low memory for the
133 * SMP bootup trampoline page.
135 void __init
smp_alloc_memory(void)
137 trampoline_base
= (void *) alloc_bootmem_low_pages(PAGE_SIZE
);
139 * Has to be in very low memory so we can execute
142 if (__pa(trampoline_base
) >= 0x9F000)
145 * Make the SMP trampoline executable:
147 trampoline_exec
= set_kernel_exec((unsigned long)trampoline_base
, 1);
151 * The bootstrap kernel entry code has set these up. Save them for
155 static void __cpuinit
smp_store_cpu_info(int id
)
157 struct cpuinfo_x86
*c
= cpu_data
+ id
;
161 identify_secondary_cpu(c
);
163 * Mask B, Pentium, but not Pentium MMX
165 if (c
->x86_vendor
== X86_VENDOR_INTEL
&&
167 c
->x86_mask
>= 1 && c
->x86_mask
<= 4 &&
170 * Remember we have B step Pentia with bugs
175 * Certain Athlons might work (for various values of 'work') in SMP
176 * but they are not certified as MP capable.
178 if ((c
->x86_vendor
== X86_VENDOR_AMD
) && (c
->x86
== 6)) {
180 if (num_possible_cpus() == 1)
183 /* Athlon 660/661 is valid. */
184 if ((c
->x86_model
==6) && ((c
->x86_mask
==0) || (c
->x86_mask
==1)))
187 /* Duron 670 is valid */
188 if ((c
->x86_model
==7) && (c
->x86_mask
==0))
192 * Athlon 662, Duron 671, and Athlon >model 7 have capability bit.
193 * It's worth noting that the A5 stepping (662) of some Athlon XP's
194 * have the MP bit set.
195 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for more.
197 if (((c
->x86_model
==6) && (c
->x86_mask
>=2)) ||
198 ((c
->x86_model
==7) && (c
->x86_mask
>=1)) ||
203 /* If we get here, it's not a certified SMP capable AMD system. */
204 add_taint(TAINT_UNSAFE_SMP
);
211 extern void calibrate_delay(void);
213 static atomic_t init_deasserted
;
215 static void __cpuinit
smp_callin(void)
218 unsigned long timeout
;
221 * If waken up by an INIT in an 82489DX configuration
222 * we may get here before an INIT-deassert IPI reaches
223 * our local APIC. We have to wait for the IPI or we'll
224 * lock up on an APIC access.
226 wait_for_init_deassert(&init_deasserted
);
229 * (This works even if the APIC is not enabled.)
231 phys_id
= GET_APIC_ID(apic_read(APIC_ID
));
232 cpuid
= smp_processor_id();
233 if (cpu_isset(cpuid
, cpu_callin_map
)) {
234 printk("huh, phys CPU#%d, CPU#%d already present??\n",
238 Dprintk("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid
, phys_id
);
241 * STARTUP IPIs are fragile beasts as they might sometimes
242 * trigger some glue motherboard logic. Complete APIC bus
243 * silence for 1 second, this overestimates the time the
244 * boot CPU is spending to send the up to 2 STARTUP IPIs
245 * by a factor of two. This should be enough.
249 * Waiting 2s total for startup (udelay is not yet working)
251 timeout
= jiffies
+ 2*HZ
;
252 while (time_before(jiffies
, timeout
)) {
254 * Has the boot CPU finished it's STARTUP sequence?
256 if (cpu_isset(cpuid
, cpu_callout_map
))
261 if (!time_before(jiffies
, timeout
)) {
262 printk("BUG: CPU%d started up but did not get a callout!\n",
268 * the boot CPU has finished the init stage and is spinning
269 * on callin_map until we finish. We are free to set up this
270 * CPU, first the APIC. (this is probably redundant on most
274 Dprintk("CALLIN, before setup_local_APIC().\n");
275 smp_callin_clear_local_apic();
277 map_cpu_to_logical_apicid();
283 Dprintk("Stack at about %p\n",&cpuid
);
286 * Save our processor parameters
288 smp_store_cpu_info(cpuid
);
291 * Allow the master to continue.
293 cpu_set(cpuid
, cpu_callin_map
);
298 /* maps the cpu to the sched domain representing multi-core */
299 cpumask_t
cpu_coregroup_map(int cpu
)
301 struct cpuinfo_x86
*c
= cpu_data
+ cpu
;
303 * For perf, we return last level cache shared map.
304 * And for power savings, we return cpu_core_map
306 if (sched_mc_power_savings
|| sched_smt_power_savings
)
307 return cpu_core_map
[cpu
];
309 return c
->llc_shared_map
;
312 /* representing cpus for which sibling maps can be computed */
313 static cpumask_t cpu_sibling_setup_map
;
316 set_cpu_sibling_map(int cpu
)
319 struct cpuinfo_x86
*c
= cpu_data
;
321 cpu_set(cpu
, cpu_sibling_setup_map
);
323 if (smp_num_siblings
> 1) {
324 for_each_cpu_mask(i
, cpu_sibling_setup_map
) {
325 if (c
[cpu
].phys_proc_id
== c
[i
].phys_proc_id
&&
326 c
[cpu
].cpu_core_id
== c
[i
].cpu_core_id
) {
327 cpu_set(i
, cpu_sibling_map
[cpu
]);
328 cpu_set(cpu
, cpu_sibling_map
[i
]);
329 cpu_set(i
, cpu_core_map
[cpu
]);
330 cpu_set(cpu
, cpu_core_map
[i
]);
331 cpu_set(i
, c
[cpu
].llc_shared_map
);
332 cpu_set(cpu
, c
[i
].llc_shared_map
);
336 cpu_set(cpu
, cpu_sibling_map
[cpu
]);
339 cpu_set(cpu
, c
[cpu
].llc_shared_map
);
341 if (current_cpu_data
.x86_max_cores
== 1) {
342 cpu_core_map
[cpu
] = cpu_sibling_map
[cpu
];
343 c
[cpu
].booted_cores
= 1;
347 for_each_cpu_mask(i
, cpu_sibling_setup_map
) {
348 if (cpu_llc_id
[cpu
] != BAD_APICID
&&
349 cpu_llc_id
[cpu
] == cpu_llc_id
[i
]) {
350 cpu_set(i
, c
[cpu
].llc_shared_map
);
351 cpu_set(cpu
, c
[i
].llc_shared_map
);
353 if (c
[cpu
].phys_proc_id
== c
[i
].phys_proc_id
) {
354 cpu_set(i
, cpu_core_map
[cpu
]);
355 cpu_set(cpu
, cpu_core_map
[i
]);
357 * Does this new cpu bringup a new core?
359 if (cpus_weight(cpu_sibling_map
[cpu
]) == 1) {
361 * for each core in package, increment
362 * the booted_cores for this new cpu
364 if (first_cpu(cpu_sibling_map
[i
]) == i
)
365 c
[cpu
].booted_cores
++;
367 * increment the core count for all
368 * the other cpus in this package
372 } else if (i
!= cpu
&& !c
[cpu
].booted_cores
)
373 c
[cpu
].booted_cores
= c
[i
].booted_cores
;
379 * Activate a secondary processor.
381 static void __cpuinit
start_secondary(void *unused
)
384 * Don't put *anything* before cpu_init(), SMP booting is too
385 * fragile that we want to limit the things done here to the
386 * most necessary things.
394 while (!cpu_isset(smp_processor_id(), smp_commenced_mask
))
397 * Check TSC synchronization with the BP:
399 check_tsc_sync_target();
401 setup_secondary_clock();
402 if (nmi_watchdog
== NMI_IO_APIC
) {
403 disable_8259A_irq(0);
404 enable_NMI_through_LVT0(NULL
);
408 * low-memory mappings have been cleared, flush them from
409 * the local TLBs too.
413 /* This must be done before setting cpu_online_map */
414 set_cpu_sibling_map(raw_smp_processor_id());
418 * We need to hold call_lock, so there is no inconsistency
419 * between the time smp_call_function() determines number of
420 * IPI receipients, and the time when the determination is made
421 * for which cpus receive the IPI. Holding this
422 * lock helps us to not include this cpu in a currently in progress
423 * smp_call_function().
425 lock_ipi_call_lock();
426 cpu_set(smp_processor_id(), cpu_online_map
);
427 unlock_ipi_call_lock();
428 per_cpu(cpu_state
, smp_processor_id()) = CPU_ONLINE
;
430 /* We can take interrupts now: we're officially "up". */
438 * Everything has been set up for the secondary
439 * CPUs - they just need to reload everything
440 * from the task structure
441 * This function must not return.
443 void __devinit
initialize_secondary(void)
446 * We don't actually need to load the full TSS,
447 * basically just the stack pointer and the eip.
454 :"m" (current
->thread
.esp
),"m" (current
->thread
.eip
));
457 /* Static state in head.S used to set up a CPU */
465 /* which logical CPUs are on which nodes */
466 cpumask_t node_2_cpu_mask
[MAX_NUMNODES
] __read_mostly
=
467 { [0 ... MAX_NUMNODES
-1] = CPU_MASK_NONE
};
468 EXPORT_SYMBOL(node_2_cpu_mask
);
469 /* which node each logical CPU is on */
470 int cpu_2_node
[NR_CPUS
] __read_mostly
= { [0 ... NR_CPUS
-1] = 0 };
471 EXPORT_SYMBOL(cpu_2_node
);
473 /* set up a mapping between cpu and node. */
474 static inline void map_cpu_to_node(int cpu
, int node
)
476 printk("Mapping cpu %d to node %d\n", cpu
, node
);
477 cpu_set(cpu
, node_2_cpu_mask
[node
]);
478 cpu_2_node
[cpu
] = node
;
481 /* undo a mapping between cpu and node. */
482 static inline void unmap_cpu_to_node(int cpu
)
486 printk("Unmapping cpu %d from all nodes\n", cpu
);
487 for (node
= 0; node
< MAX_NUMNODES
; node
++)
488 cpu_clear(cpu
, node_2_cpu_mask
[node
]);
491 #else /* !CONFIG_NUMA */
493 #define map_cpu_to_node(cpu, node) ({})
494 #define unmap_cpu_to_node(cpu) ({})
496 #endif /* CONFIG_NUMA */
498 u8 cpu_2_logical_apicid
[NR_CPUS
] __read_mostly
= { [0 ... NR_CPUS
-1] = BAD_APICID
};
500 static void map_cpu_to_logical_apicid(void)
502 int cpu
= smp_processor_id();
503 int apicid
= logical_smp_processor_id();
504 int node
= apicid_to_node(apicid
);
506 if (!node_online(node
))
507 node
= first_online_node
;
509 cpu_2_logical_apicid
[cpu
] = apicid
;
510 map_cpu_to_node(cpu
, node
);
513 static void unmap_cpu_to_logical_apicid(int cpu
)
515 cpu_2_logical_apicid
[cpu
] = BAD_APICID
;
516 unmap_cpu_to_node(cpu
);
520 static inline void __inquire_remote_apic(int apicid
)
522 int i
, regs
[] = { APIC_ID
>> 4, APIC_LVR
>> 4, APIC_SPIV
>> 4 };
523 char *names
[] = { "ID", "VERSION", "SPIV" };
526 printk("Inquiring remote APIC #%d...\n", apicid
);
528 for (i
= 0; i
< ARRAY_SIZE(regs
); i
++) {
529 printk("... APIC #%d %s: ", apicid
, names
[i
]);
534 apic_wait_icr_idle();
536 apic_write_around(APIC_ICR2
, SET_APIC_DEST_FIELD(apicid
));
537 apic_write_around(APIC_ICR
, APIC_DM_REMRD
| regs
[i
]);
542 status
= apic_read(APIC_ICR
) & APIC_ICR_RR_MASK
;
543 } while (status
== APIC_ICR_RR_INPROG
&& timeout
++ < 1000);
546 case APIC_ICR_RR_VALID
:
547 status
= apic_read(APIC_RRR
);
548 printk("%08x\n", status
);
557 #ifdef WAKE_SECONDARY_VIA_NMI
559 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
560 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
561 * won't ... remember to clear down the APIC, etc later.
564 wakeup_secondary_cpu(int logical_apicid
, unsigned long start_eip
)
566 unsigned long send_status
= 0, accept_status
= 0;
570 apic_write_around(APIC_ICR2
, SET_APIC_DEST_FIELD(logical_apicid
));
572 /* Boot on the stack */
573 /* Kick the second */
574 apic_write_around(APIC_ICR
, APIC_DM_NMI
| APIC_DEST_LOGICAL
);
576 Dprintk("Waiting for send to finish...\n");
581 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
582 } while (send_status
&& (timeout
++ < 1000));
585 * Give the other CPU some time to accept the IPI.
589 * Due to the Pentium erratum 3AP.
591 maxlvt
= lapic_get_maxlvt();
593 apic_read_around(APIC_SPIV
);
594 apic_write(APIC_ESR
, 0);
596 accept_status
= (apic_read(APIC_ESR
) & 0xEF);
597 Dprintk("NMI sent.\n");
600 printk("APIC never delivered???\n");
602 printk("APIC delivery error (%lx).\n", accept_status
);
604 return (send_status
| accept_status
);
606 #endif /* WAKE_SECONDARY_VIA_NMI */
608 #ifdef WAKE_SECONDARY_VIA_INIT
610 wakeup_secondary_cpu(int phys_apicid
, unsigned long start_eip
)
612 unsigned long send_status
= 0, accept_status
= 0;
613 int maxlvt
, timeout
, num_starts
, j
;
616 * Be paranoid about clearing APIC errors.
618 if (APIC_INTEGRATED(apic_version
[phys_apicid
])) {
619 apic_read_around(APIC_SPIV
);
620 apic_write(APIC_ESR
, 0);
624 Dprintk("Asserting INIT.\n");
627 * Turn INIT on target chip
629 apic_write_around(APIC_ICR2
, SET_APIC_DEST_FIELD(phys_apicid
));
634 apic_write_around(APIC_ICR
, APIC_INT_LEVELTRIG
| APIC_INT_ASSERT
637 Dprintk("Waiting for send to finish...\n");
642 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
643 } while (send_status
&& (timeout
++ < 1000));
647 Dprintk("Deasserting INIT.\n");
650 apic_write_around(APIC_ICR2
, SET_APIC_DEST_FIELD(phys_apicid
));
653 apic_write_around(APIC_ICR
, APIC_INT_LEVELTRIG
| APIC_DM_INIT
);
655 Dprintk("Waiting for send to finish...\n");
660 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
661 } while (send_status
&& (timeout
++ < 1000));
663 atomic_set(&init_deasserted
, 1);
666 * Should we send STARTUP IPIs ?
668 * Determine this based on the APIC version.
669 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
671 if (APIC_INTEGRATED(apic_version
[phys_apicid
]))
677 * Paravirt / VMI wants a startup IPI hook here to set up the
678 * target processor state.
680 startup_ipi_hook(phys_apicid
, (unsigned long) start_secondary
,
681 (unsigned long) stack_start
.esp
);
684 * Run STARTUP IPI loop.
686 Dprintk("#startup loops: %d.\n", num_starts
);
688 maxlvt
= lapic_get_maxlvt();
690 for (j
= 1; j
<= num_starts
; j
++) {
691 Dprintk("Sending STARTUP #%d.\n",j
);
692 apic_read_around(APIC_SPIV
);
693 apic_write(APIC_ESR
, 0);
695 Dprintk("After apic_write.\n");
702 apic_write_around(APIC_ICR2
, SET_APIC_DEST_FIELD(phys_apicid
));
704 /* Boot on the stack */
705 /* Kick the second */
706 apic_write_around(APIC_ICR
, APIC_DM_STARTUP
707 | (start_eip
>> 12));
710 * Give the other CPU some time to accept the IPI.
714 Dprintk("Startup point 1.\n");
716 Dprintk("Waiting for send to finish...\n");
721 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
722 } while (send_status
&& (timeout
++ < 1000));
725 * Give the other CPU some time to accept the IPI.
729 * Due to the Pentium erratum 3AP.
732 apic_read_around(APIC_SPIV
);
733 apic_write(APIC_ESR
, 0);
735 accept_status
= (apic_read(APIC_ESR
) & 0xEF);
736 if (send_status
|| accept_status
)
739 Dprintk("After Startup.\n");
742 printk("APIC never delivered???\n");
744 printk("APIC delivery error (%lx).\n", accept_status
);
746 return (send_status
| accept_status
);
748 #endif /* WAKE_SECONDARY_VIA_INIT */
750 extern cpumask_t cpu_initialized
;
751 static inline int alloc_cpu_id(void)
755 cpus_complement(tmp_map
, cpu_present_map
);
756 cpu
= first_cpu(tmp_map
);
762 #ifdef CONFIG_HOTPLUG_CPU
763 static struct task_struct
* __devinitdata cpu_idle_tasks
[NR_CPUS
];
764 static inline struct task_struct
* alloc_idle_task(int cpu
)
766 struct task_struct
*idle
;
768 if ((idle
= cpu_idle_tasks
[cpu
]) != NULL
) {
769 /* initialize thread_struct. we really want to avoid destroy
772 idle
->thread
.esp
= (unsigned long)task_pt_regs(idle
);
773 init_idle(idle
, cpu
);
776 idle
= fork_idle(cpu
);
779 cpu_idle_tasks
[cpu
] = idle
;
783 #define alloc_idle_task(cpu) fork_idle(cpu)
786 /* Initialize the CPU's GDT. This is either the boot CPU doing itself
787 (still using the master per-cpu area), or a CPU doing it for a
788 secondary which will soon come up. */
789 static __cpuinit
void init_gdt(int cpu
)
791 struct desc_struct
*gdt
= get_cpu_gdt_table(cpu
);
793 pack_descriptor((u32
*)&gdt
[GDT_ENTRY_PERCPU
].a
,
794 (u32
*)&gdt
[GDT_ENTRY_PERCPU
].b
,
795 __per_cpu_offset
[cpu
], 0xFFFFF,
796 0x80 | DESCTYPE_S
| 0x2, 0x8);
798 per_cpu(this_cpu_off
, cpu
) = __per_cpu_offset
[cpu
];
799 per_cpu(cpu_number
, cpu
) = cpu
;
802 /* Defined in head.S */
803 extern struct Xgt_desc_struct early_gdt_descr
;
805 static int __cpuinit
do_boot_cpu(int apicid
, int cpu
)
807 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
808 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
809 * Returns zero if CPU booted OK, else error code from wakeup_secondary_cpu.
812 struct task_struct
*idle
;
813 unsigned long boot_error
;
815 unsigned long start_eip
;
816 unsigned short nmi_high
= 0, nmi_low
= 0;
819 * Save current MTRR state in case it was changed since early boot
820 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
825 * We can't use kernel_thread since we must avoid to
826 * reschedule the child.
828 idle
= alloc_idle_task(cpu
);
830 panic("failed fork for CPU %d", cpu
);
833 per_cpu(current_task
, cpu
) = idle
;
834 early_gdt_descr
.address
= (unsigned long)get_cpu_gdt_table(cpu
);
836 idle
->thread
.eip
= (unsigned long) start_secondary
;
837 /* start_eip had better be page-aligned! */
838 start_eip
= setup_trampoline();
841 alternatives_smp_switch(1);
843 /* So we see what's up */
844 printk("Booting processor %d/%d eip %lx\n", cpu
, apicid
, start_eip
);
845 /* Stack for startup_32 can be just as for start_secondary onwards */
846 stack_start
.esp
= (void *) idle
->thread
.esp
;
850 x86_cpu_to_apicid
[cpu
] = apicid
;
852 * This grunge runs the startup process for
853 * the targeted processor.
856 atomic_set(&init_deasserted
, 0);
858 Dprintk("Setting warm reset code and vector.\n");
860 store_NMI_vector(&nmi_high
, &nmi_low
);
862 smpboot_setup_warm_reset_vector(start_eip
);
865 * Starting actual IPI sequence...
867 boot_error
= wakeup_secondary_cpu(apicid
, start_eip
);
871 * allow APs to start initializing.
873 Dprintk("Before Callout %d.\n", cpu
);
874 cpu_set(cpu
, cpu_callout_map
);
875 Dprintk("After Callout %d.\n", cpu
);
878 * Wait 5s total for a response
880 for (timeout
= 0; timeout
< 50000; timeout
++) {
881 if (cpu_isset(cpu
, cpu_callin_map
))
882 break; /* It has booted */
886 if (cpu_isset(cpu
, cpu_callin_map
)) {
887 /* number CPUs logically, starting from 1 (BSP is 0) */
889 printk("CPU%d: ", cpu
);
890 print_cpu_info(&cpu_data
[cpu
]);
891 Dprintk("CPU has booted.\n");
894 if (*((volatile unsigned char *)trampoline_base
)
896 /* trampoline started but...? */
897 printk("Stuck ??\n");
899 /* trampoline code not run */
900 printk("Not responding.\n");
901 inquire_remote_apic(apicid
);
906 /* Try to put things back the way they were before ... */
907 unmap_cpu_to_logical_apicid(cpu
);
908 cpu_clear(cpu
, cpu_callout_map
); /* was set here (do_boot_cpu()) */
909 cpu_clear(cpu
, cpu_initialized
); /* was set by cpu_init() */
912 x86_cpu_to_apicid
[cpu
] = apicid
;
913 cpu_set(cpu
, cpu_present_map
);
916 /* mark "stuck" area as not stuck */
917 *((volatile unsigned long *)trampoline_base
) = 0;
922 #ifdef CONFIG_HOTPLUG_CPU
923 void cpu_exit_clear(void)
925 int cpu
= raw_smp_processor_id();
933 cpu_clear(cpu
, cpu_callout_map
);
934 cpu_clear(cpu
, cpu_callin_map
);
936 cpu_clear(cpu
, smp_commenced_mask
);
937 unmap_cpu_to_logical_apicid(cpu
);
940 struct warm_boot_cpu_info
{
941 struct completion
*complete
;
942 struct work_struct task
;
947 static void __cpuinit
do_warm_boot_cpu(struct work_struct
*work
)
949 struct warm_boot_cpu_info
*info
=
950 container_of(work
, struct warm_boot_cpu_info
, task
);
951 do_boot_cpu(info
->apicid
, info
->cpu
);
952 complete(info
->complete
);
955 static int __cpuinit
__smp_prepare_cpu(int cpu
)
957 DECLARE_COMPLETION_ONSTACK(done
);
958 struct warm_boot_cpu_info info
;
961 apicid
= x86_cpu_to_apicid
[cpu
];
962 if (apicid
== BAD_APICID
) {
967 info
.complete
= &done
;
968 info
.apicid
= apicid
;
970 INIT_WORK(&info
.task
, do_warm_boot_cpu
);
972 /* init low mem mapping */
973 clone_pgd_range(swapper_pg_dir
, swapper_pg_dir
+ USER_PGD_PTRS
,
974 min_t(unsigned long, KERNEL_PGD_PTRS
, USER_PGD_PTRS
));
976 schedule_work(&info
.task
);
977 wait_for_completion(&done
);
986 static void smp_tune_scheduling(void)
988 unsigned long cachesize
; /* kB */
991 cachesize
= boot_cpu_data
.x86_cache_size
;
994 max_cache_size
= cachesize
* 1024;
999 * Cycle through the processors sending APIC IPIs to boot each.
1002 static int boot_cpu_logical_apicid
;
1003 /* Where the IO area was mapped on multiquad, always 0 otherwise */
1005 #ifdef CONFIG_X86_NUMAQ
1006 EXPORT_SYMBOL(xquad_portio
);
1009 static void __init
smp_boot_cpus(unsigned int max_cpus
)
1011 int apicid
, cpu
, bit
, kicked
;
1012 unsigned long bogosum
= 0;
1015 * Setup boot CPU information
1017 smp_store_cpu_info(0); /* Final full version of the data */
1018 printk("CPU%d: ", 0);
1019 print_cpu_info(&cpu_data
[0]);
1021 boot_cpu_physical_apicid
= GET_APIC_ID(apic_read(APIC_ID
));
1022 boot_cpu_logical_apicid
= logical_smp_processor_id();
1023 x86_cpu_to_apicid
[0] = boot_cpu_physical_apicid
;
1025 current_thread_info()->cpu
= 0;
1026 smp_tune_scheduling();
1028 set_cpu_sibling_map(0);
1031 * If we couldn't find an SMP configuration at boot time,
1032 * get out of here now!
1034 if (!smp_found_config
&& !acpi_lapic
) {
1035 printk(KERN_NOTICE
"SMP motherboard not detected.\n");
1036 smpboot_clear_io_apic_irqs();
1037 phys_cpu_present_map
= physid_mask_of_physid(0);
1038 if (APIC_init_uniprocessor())
1039 printk(KERN_NOTICE
"Local APIC not detected."
1040 " Using dummy APIC emulation.\n");
1041 map_cpu_to_logical_apicid();
1042 cpu_set(0, cpu_sibling_map
[0]);
1043 cpu_set(0, cpu_core_map
[0]);
1048 * Should not be necessary because the MP table should list the boot
1049 * CPU too, but we do it for the sake of robustness anyway.
1050 * Makes no sense to do this check in clustered apic mode, so skip it
1052 if (!check_phys_apicid_present(boot_cpu_physical_apicid
)) {
1053 printk("weird, boot CPU (#%d) not listed by the BIOS.\n",
1054 boot_cpu_physical_apicid
);
1055 physid_set(hard_smp_processor_id(), phys_cpu_present_map
);
1059 * If we couldn't find a local APIC, then get out of here now!
1061 if (APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
]) && !cpu_has_apic
) {
1062 printk(KERN_ERR
"BIOS bug, local APIC #%d not detected!...\n",
1063 boot_cpu_physical_apicid
);
1064 printk(KERN_ERR
"... forcing use of dummy APIC emulation. (tell your hw vendor)\n");
1065 smpboot_clear_io_apic_irqs();
1066 phys_cpu_present_map
= physid_mask_of_physid(0);
1067 cpu_set(0, cpu_sibling_map
[0]);
1068 cpu_set(0, cpu_core_map
[0]);
1072 verify_local_APIC();
1075 * If SMP should be disabled, then really disable it!
1078 smp_found_config
= 0;
1079 printk(KERN_INFO
"SMP mode deactivated, forcing use of dummy APIC emulation.\n");
1080 smpboot_clear_io_apic_irqs();
1081 phys_cpu_present_map
= physid_mask_of_physid(0);
1082 cpu_set(0, cpu_sibling_map
[0]);
1083 cpu_set(0, cpu_core_map
[0]);
1089 map_cpu_to_logical_apicid();
1092 setup_portio_remap();
1095 * Scan the CPU present map and fire up the other CPUs via do_boot_cpu
1097 * In clustered apic mode, phys_cpu_present_map is a constructed thus:
1098 * bits 0-3 are quad0, 4-7 are quad1, etc. A perverse twist on the
1099 * clustered apic ID.
1101 Dprintk("CPU present map: %lx\n", physids_coerce(phys_cpu_present_map
));
1104 for (bit
= 0; kicked
< NR_CPUS
&& bit
< MAX_APICS
; bit
++) {
1105 apicid
= cpu_present_to_apicid(bit
);
1107 * Don't even attempt to start the boot CPU!
1109 if ((apicid
== boot_cpu_apicid
) || (apicid
== BAD_APICID
))
1112 if (!check_apicid_present(bit
))
1114 if (max_cpus
<= cpucount
+1)
1117 if (((cpu
= alloc_cpu_id()) <= 0) || do_boot_cpu(apicid
, cpu
))
1118 printk("CPU #%d not responding - cannot use it.\n",
1125 * Cleanup possible dangling ends...
1127 smpboot_restore_warm_reset_vector();
1130 * Allow the user to impress friends.
1132 Dprintk("Before bogomips.\n");
1133 for (cpu
= 0; cpu
< NR_CPUS
; cpu
++)
1134 if (cpu_isset(cpu
, cpu_callout_map
))
1135 bogosum
+= cpu_data
[cpu
].loops_per_jiffy
;
1137 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
1139 bogosum
/(500000/HZ
),
1140 (bogosum
/(5000/HZ
))%100);
1142 Dprintk("Before bogocount - setting activated=1.\n");
1145 printk(KERN_WARNING
"WARNING: SMP operation may be unreliable with B stepping processors.\n");
1148 * Don't taint if we are running SMP kernel on a single non-MP
1151 if (tainted
& TAINT_UNSAFE_SMP
) {
1153 printk (KERN_INFO
"WARNING: This combination of AMD processors is not suitable for SMP.\n");
1155 tainted
&= ~TAINT_UNSAFE_SMP
;
1158 Dprintk("Boot done.\n");
1161 * construct cpu_sibling_map[], so that we can tell sibling CPUs
1164 for (cpu
= 0; cpu
< NR_CPUS
; cpu
++) {
1165 cpus_clear(cpu_sibling_map
[cpu
]);
1166 cpus_clear(cpu_core_map
[cpu
]);
1169 cpu_set(0, cpu_sibling_map
[0]);
1170 cpu_set(0, cpu_core_map
[0]);
1172 smpboot_setup_io_apic();
1177 /* These are wrappers to interface to the new boot process. Someone
1178 who understands all this stuff should rewrite it properly. --RR 15/Jul/02 */
1179 void __init
native_smp_prepare_cpus(unsigned int max_cpus
)
1181 smp_commenced_mask
= cpumask_of_cpu(0);
1182 cpu_callin_map
= cpumask_of_cpu(0);
1184 smp_boot_cpus(max_cpus
);
1187 void __init
native_smp_prepare_boot_cpu(void)
1189 unsigned int cpu
= smp_processor_id();
1192 switch_to_new_gdt();
1194 cpu_set(cpu
, cpu_online_map
);
1195 cpu_set(cpu
, cpu_callout_map
);
1196 cpu_set(cpu
, cpu_present_map
);
1197 cpu_set(cpu
, cpu_possible_map
);
1198 __get_cpu_var(cpu_state
) = CPU_ONLINE
;
1201 #ifdef CONFIG_HOTPLUG_CPU
1203 remove_siblinginfo(int cpu
)
1206 struct cpuinfo_x86
*c
= cpu_data
;
1208 for_each_cpu_mask(sibling
, cpu_core_map
[cpu
]) {
1209 cpu_clear(cpu
, cpu_core_map
[sibling
]);
1211 * last thread sibling in this cpu core going down
1213 if (cpus_weight(cpu_sibling_map
[cpu
]) == 1)
1214 c
[sibling
].booted_cores
--;
1217 for_each_cpu_mask(sibling
, cpu_sibling_map
[cpu
])
1218 cpu_clear(cpu
, cpu_sibling_map
[sibling
]);
1219 cpus_clear(cpu_sibling_map
[cpu
]);
1220 cpus_clear(cpu_core_map
[cpu
]);
1221 c
[cpu
].phys_proc_id
= 0;
1222 c
[cpu
].cpu_core_id
= 0;
1223 cpu_clear(cpu
, cpu_sibling_setup_map
);
1226 int __cpu_disable(void)
1228 cpumask_t map
= cpu_online_map
;
1229 int cpu
= smp_processor_id();
1232 * Perhaps use cpufreq to drop frequency, but that could go
1233 * into generic code.
1235 * We won't take down the boot processor on i386 due to some
1236 * interrupts only being able to be serviced by the BSP.
1237 * Especially so if we're not using an IOAPIC -zwane
1241 if (nmi_watchdog
== NMI_LOCAL_APIC
)
1242 stop_apic_nmi_watchdog(NULL
);
1244 /* Allow any queued timer interrupts to get serviced */
1247 local_irq_disable();
1249 remove_siblinginfo(cpu
);
1251 cpu_clear(cpu
, map
);
1253 /* It's now safe to remove this processor from the online map */
1254 cpu_clear(cpu
, cpu_online_map
);
1258 void __cpu_die(unsigned int cpu
)
1260 /* We don't do anything here: idle task is faking death itself. */
1263 for (i
= 0; i
< 10; i
++) {
1264 /* They ack this in play_dead by setting CPU_DEAD */
1265 if (per_cpu(cpu_state
, cpu
) == CPU_DEAD
) {
1266 printk ("CPU %d is now offline\n", cpu
);
1267 if (1 == num_online_cpus())
1268 alternatives_smp_switch(0);
1273 printk(KERN_ERR
"CPU %u didn't die...\n", cpu
);
1275 #else /* ... !CONFIG_HOTPLUG_CPU */
1276 int __cpu_disable(void)
1281 void __cpu_die(unsigned int cpu
)
1283 /* We said "no" in __cpu_disable */
1286 #endif /* CONFIG_HOTPLUG_CPU */
1288 int __cpuinit
native_cpu_up(unsigned int cpu
)
1290 unsigned long flags
;
1291 #ifdef CONFIG_HOTPLUG_CPU
1295 * We do warm boot only on cpus that had booted earlier
1296 * Otherwise cold boot is all handled from smp_boot_cpus().
1297 * cpu_callin_map is set during AP kickstart process. Its reset
1298 * when a cpu is taken offline from cpu_exit_clear().
1300 if (!cpu_isset(cpu
, cpu_callin_map
))
1301 ret
= __smp_prepare_cpu(cpu
);
1307 /* In case one didn't come up */
1308 if (!cpu_isset(cpu
, cpu_callin_map
)) {
1309 printk(KERN_DEBUG
"skipping cpu%d, didn't come online\n", cpu
);
1313 per_cpu(cpu_state
, cpu
) = CPU_UP_PREPARE
;
1314 /* Unleash the CPU! */
1315 cpu_set(cpu
, smp_commenced_mask
);
1318 * Check TSC synchronization with the AP (keep irqs disabled
1321 local_irq_save(flags
);
1322 check_tsc_sync_source(cpu
);
1323 local_irq_restore(flags
);
1325 while (!cpu_isset(cpu
, cpu_online_map
)) {
1327 touch_nmi_watchdog();
1333 void __init
native_smp_cpus_done(unsigned int max_cpus
)
1335 #ifdef CONFIG_X86_IO_APIC
1336 setup_ioapic_dest();
1339 #ifndef CONFIG_HOTPLUG_CPU
1341 * Disable executability of the SMP trampoline:
1343 set_kernel_exec((unsigned long)trampoline_base
, trampoline_exec
);
1347 void __init
smp_intr_init(void)
1350 * IRQ0 must be given a fixed assignment and initialized,
1351 * because it's used before the IO-APIC is set up.
1353 set_intr_gate(FIRST_DEVICE_VECTOR
, interrupt
[0]);
1356 * The reschedule interrupt is a CPU-to-CPU reschedule-helper
1357 * IPI, driven by wakeup.
1359 set_intr_gate(RESCHEDULE_VECTOR
, reschedule_interrupt
);
1361 /* IPI for invalidation */
1362 set_intr_gate(INVALIDATE_TLB_VECTOR
, invalidate_interrupt
);
1364 /* IPI for generic function call */
1365 set_intr_gate(CALL_FUNCTION_VECTOR
, call_function_interrupt
);
1369 * If the BIOS enumerates physical processors before logical,
1370 * maxcpus=N at enumeration-time can be used to disable HT.
1372 static int __init
parse_maxcpus(char *arg
)
1374 extern unsigned int maxcpus
;
1376 maxcpus
= simple_strtoul(arg
, NULL
, 0);
1379 early_param("maxcpus", parse_maxcpus
);