arch/arm/mach-pxa/pxa3xx.c

   1 /*
   2  * linux/arch/arm/mach-pxa/pxa3xx.c
   3  *
   4  * code specific to pxa3xx aka Monahans
   5  *
   6  * Copyright (C) 2006 Marvell International Ltd.
   7  *
   8  * 2007-09-02: eric miao <eric.miao@marvell.com>
   9  *             initial version
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #include <linux/module.h>
  17 #include <linux/kernel.h>
  18 #include <linux/init.h>
  19 #include <linux/pm.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/irq.h>
  22 #include <linux/io.h>
  23
  24 #include <asm/hardware.h>
  25 #include <asm/arch/pxa3xx-regs.h>
  26 #include <asm/arch/ohci.h>
  27 #include <asm/arch/pm.h>
  28 #include <asm/arch/dma.h>
  29 #include <asm/arch/ssp.h>
  30
  31 #include "generic.h"
  32 #include "devices.h"
  33 #include "clock.h"
  34
  35 /* Crystal clock: 13MHz */
  36 #define BASE_CLK        13000000
  37
  38 /* Ring Oscillator Clock: 60MHz */
  39 #define RO_CLK          60000000
  40
  41 #define ACCR_D0CS       (1 << 26)
  42
  43 /* crystal frequency to static memory controller multiplier (SMCFS) */
  44 static unsigned char smcfs_mult[8] = { 6, 0, 8, 0, 0, 16, };
  45
  46 /* crystal frequency to HSIO bus frequency multiplier (HSS) */
  47 static unsigned char hss_mult[4] = { 8, 12, 16, 0 };
  48
  49 /*
  50  * Get the clock frequency as reflected by CCSR and the turbo flag.
  51  * We assume these values have been applied via a fcs.
  52  * If info is not 0 we also display the current settings.
  53  */
  54 unsigned int pxa3xx_get_clk_frequency_khz(int info)
  55 {
  56         unsigned long acsr, xclkcfg;
  57         unsigned int t, xl, xn, hss, ro, XL, XN, CLK, HSS;
  58
  59         /* Read XCLKCFG register turbo bit */
  60         __asm__ __volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg));
  61         t = xclkcfg & 0x1;
  62
  63         acsr = ACSR;
  64
  65         xl  = acsr & 0x1f;
  66         xn  = (acsr >> 8) & 0x7;
  67         hss = (acsr >> 14) & 0x3;
  68
  69         XL = xl * BASE_CLK;
  70         XN = xn * XL;
  71
  72         ro = acsr & ACCR_D0CS;
  73
  74         CLK = (ro) ? RO_CLK : ((t) ? XN : XL);
  75         HSS = (ro) ? RO_CLK : hss_mult[hss] * BASE_CLK;
  76
  77         if (info) {
  78                 pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n",
  79                         RO_CLK / 1000000, (RO_CLK % 1000000) / 10000,
  80                         (ro) ? "" : "in");
  81                 pr_info("Run Mode clock: %d.%02dMHz (*%d)\n",
  82                         XL / 1000000, (XL % 1000000) / 10000, xl);
  83                 pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n",
  84                         XN / 1000000, (XN % 1000000) / 10000, xn,
  85                         (t) ? "" : "in");
  86                 pr_info("HSIO bus clock: %d.%02dMHz\n",
  87                         HSS / 1000000, (HSS % 1000000) / 10000);
  88         }
  89
  90         return CLK / 1000;
  91 }
  92
  93 /*
  94  * Return the current static memory controller clock frequency
  95  * in units of 10kHz
  96  */
  97 unsigned int pxa3xx_get_memclk_frequency_10khz(void)
  98 {
  99         unsigned long acsr;
 100         unsigned int smcfs, clk = 0;
 101
 102         acsr = ACSR;
 103
 104         smcfs = (acsr >> 23) & 0x7;
 105         clk = (acsr & ACCR_D0CS) ? RO_CLK : smcfs_mult[smcfs] * BASE_CLK;
 106
 107         return (clk / 10000);
 108 }
 109
 110 /*
 111  * Return the current HSIO bus clock frequency
 112  */
 113 static unsigned long clk_pxa3xx_hsio_getrate(struct clk *clk)
 114 {
 115         unsigned long acsr;
 116         unsigned int hss, hsio_clk;
 117
 118         acsr = ACSR;
 119
 120         hss = (acsr >> 14) & 0x3;
 121         hsio_clk = (acsr & ACCR_D0CS) ? RO_CLK : hss_mult[hss] * BASE_CLK;
 122
 123         return hsio_clk;
 124 }
 125
 126 static void clk_pxa3xx_cken_enable(struct clk *clk)
 127 {
 128         unsigned long mask = 1ul << (clk->cken & 0x1f);
 129
 130         local_irq_disable();
 131
 132         if (clk->cken < 32)
 133                 CKENA |= mask;
 134         else
 135                 CKENB |= mask;
 136
 137         local_irq_enable();
 138 }
 139
 140 static void clk_pxa3xx_cken_disable(struct clk *clk)
 141 {
 142         unsigned long mask = 1ul << (clk->cken & 0x1f);
 143
 144         local_irq_disable();
 145
 146         if (clk->cken < 32)
 147                 CKENA &= ~mask;
 148         else
 149                 CKENB &= ~mask;
 150
 151         local_irq_enable();
 152 }
 153
 154 static const struct clkops clk_pxa3xx_cken_ops = {
 155         .enable         = clk_pxa3xx_cken_enable,
 156         .disable        = clk_pxa3xx_cken_disable,
 157 };
 158
 159 static const struct clkops clk_pxa3xx_hsio_ops = {
 160         .enable         = clk_pxa3xx_cken_enable,
 161         .disable        = clk_pxa3xx_cken_disable,
 162         .getrate        = clk_pxa3xx_hsio_getrate,
 163 };
 164
 165 #define PXA3xx_CKEN(_name, _cken, _rate, _delay, _dev)  \
 166         {                                               \
 167                 .name   = _name,                        \
 168                 .dev    = _dev,                         \
 169                 .ops    = &clk_pxa3xx_cken_ops,         \
 170                 .rate   = _rate,                        \
 171                 .cken   = CKEN_##_cken,                 \
 172                 .delay  = _delay,                       \
 173         }
 174
 175 #define PXA3xx_CK(_name, _cken, _ops, _dev)             \
 176         {                                               \
 177                 .name   = _name,                        \
 178                 .dev    = _dev,                         \
 179                 .ops    = _ops,                         \
 180                 .cken   = CKEN_##_cken,                 \
 181         }
 182
 183 static struct clk pxa3xx_clks[] = {
 184         PXA3xx_CK("LCDCLK", LCD,    &clk_pxa3xx_hsio_ops, &pxa_device_fb.dev),
 185         PXA3xx_CK("CAMCLK", CAMERA, &clk_pxa3xx_hsio_ops, NULL),
 186
 187         PXA3xx_CKEN("UARTCLK", FFUART, 14857000, 1, &pxa_device_ffuart.dev),
 188         PXA3xx_CKEN("UARTCLK", BTUART, 14857000, 1, &pxa_device_btuart.dev),
 189         PXA3xx_CKEN("UARTCLK", STUART, 14857000, 1, NULL),
 190
 191         PXA3xx_CKEN("I2CCLK", I2C,  32842000, 0, &pxa_device_i2c.dev),
 192         PXA3xx_CKEN("UDCCLK", UDC,  48000000, 5, &pxa_device_udc.dev),
 193         PXA3xx_CKEN("USBCLK", USBH, 48000000, 0, &pxa27x_device_ohci.dev),
 194
 195         PXA3xx_CKEN("SSPCLK", SSP1, 13000000, 0, &pxa27x_device_ssp1.dev),
 196         PXA3xx_CKEN("SSPCLK", SSP2, 13000000, 0, &pxa27x_device_ssp2.dev),
 197         PXA3xx_CKEN("SSPCLK", SSP3, 13000000, 0, &pxa27x_device_ssp3.dev),
 198         PXA3xx_CKEN("SSPCLK", SSP4, 13000000, 0, &pxa3xx_device_ssp4.dev),
 199
 200         PXA3xx_CKEN("MMCCLK", MMC1, 19500000, 0, &pxa_device_mci.dev),
 201         PXA3xx_CKEN("MMCCLK", MMC2, 19500000, 0, &pxa3xx_device_mci2.dev),
 202         PXA3xx_CKEN("MMCCLK", MMC3, 19500000, 0, &pxa3xx_device_mci3.dev),
 203 };
 204
 205 #ifdef CONFIG_PM
 206 #define SLEEP_SAVE_SIZE 4
 207
 208 #define ISRAM_START     0x5c000000
 209 #define ISRAM_SIZE      SZ_256K
 210
 211 static void __iomem *sram;
 212 static unsigned long wakeup_src;
 213
 214 static void pxa3xx_cpu_pm_save(unsigned long *sleep_save)
 215 {
 216         pr_debug("PM: CKENA=%08x CKENB=%08x\n", CKENA, CKENB);
 217
 218         if (CKENA & (1 << CKEN_USBH)) {
 219                 printk(KERN_ERR "PM: USB host clock not stopped?\n");
 220                 CKENA &= ~(1 << CKEN_USBH);
 221         }
 222 //      CKENA |= 1 << (CKEN_ISC & 31);
 223
 224         /*
 225          * Low power modes require the HSIO2 clock to be enabled.
 226          */
 227         CKENB |= 1 << (CKEN_HSIO2 & 31);
 228 }
 229
 230 static void pxa3xx_cpu_pm_restore(unsigned long *sleep_save)
 231 {
 232         CKENB &= ~(1 << (CKEN_HSIO2 & 31));
 233 }
 234
 235 /*
 236  * Enter a standby mode (S0D1C2 or S0D2C2).  Upon wakeup, the dynamic
 237  * memory controller has to be reinitialised, so we place some code
 238  * in the SRAM to perform this function.
 239  *
 240  * We disable FIQs across the standby - otherwise, we might receive a
 241  * FIQ while the SDRAM is unavailable.
 242  */
 243 static void pxa3xx_cpu_standby(unsigned int pwrmode)
 244 {
 245         extern const char pm_enter_standby_start[], pm_enter_standby_end[];
 246         void (*fn)(unsigned int) = (void __force *)(sram + 0x8000);
 247
 248         memcpy_toio(sram + 0x8000, pm_enter_standby_start,
 249                     pm_enter_standby_end - pm_enter_standby_start);
 250
 251         AD2D0SR = ~0;
 252         AD2D1SR = ~0;
 253         AD2D0ER = wakeup_src;
 254         AD2D1ER = 0;
 255         ASCR = ASCR;
 256         ARSR = ARSR;
 257
 258         local_fiq_disable();
 259         fn(pwrmode);
 260         local_fiq_enable();
 261
 262         AD2D0ER = 0;
 263         AD2D1ER = 0;
 264
 265         printk("PM: AD2D0SR=%08x ASCR=%08x\n", AD2D0SR, ASCR);
 266 }
 267
 268 static void pxa3xx_cpu_pm_enter(suspend_state_t state)
 269 {
 270         /*
 271          * Don't sleep if no wakeup sources are defined
 272          */
 273         if (wakeup_src == 0)
 274                 return;
 275
 276         switch (state) {
 277         case PM_SUSPEND_STANDBY:
 278                 pxa3xx_cpu_standby(PXA3xx_PM_S0D2C2);
 279                 break;
 280
 281         case PM_SUSPEND_MEM:
 282                 break;
 283         }
 284 }
 285
 286 static int pxa3xx_cpu_pm_valid(suspend_state_t state)
 287 {
 288         return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
 289 }
 290
 291 static struct pxa_cpu_pm_fns pxa3xx_cpu_pm_fns = {
 292         .save_size      = SLEEP_SAVE_SIZE,
 293         .save           = pxa3xx_cpu_pm_save,
 294         .restore        = pxa3xx_cpu_pm_restore,
 295         .valid          = pxa3xx_cpu_pm_valid,
 296         .enter          = pxa3xx_cpu_pm_enter,
 297 };
 298
 299 static void __init pxa3xx_init_pm(void)
 300 {
 301         sram = ioremap(ISRAM_START, ISRAM_SIZE);
 302         if (!sram) {
 303                 printk(KERN_ERR "Unable to map ISRAM: disabling standby/suspend\n");
 304                 return;
 305         }
 306
 307         /*
 308          * Since we copy wakeup code into the SRAM, we need to ensure
 309          * that it is preserved over the low power modes.  Note: bit 8
 310          * is undocumented in the developer manual, but must be set.
 311          */
 312         AD1R |= ADXR_L2 | ADXR_R0;
 313         AD2R |= ADXR_L2 | ADXR_R0;
 314         AD3R |= ADXR_L2 | ADXR_R0;
 315
 316         /*
 317          * Clear the resume enable registers.
 318          */
 319         AD1D0ER = 0;
 320         AD2D0ER = 0;
 321         AD2D1ER = 0;
 322         AD3ER = 0;
 323
 324         pxa_cpu_pm_fns = &pxa3xx_cpu_pm_fns;
 325 }
 326
 327 static int pxa3xx_set_wake(unsigned int irq, unsigned int on)
 328 {
 329         unsigned long flags, mask = 0;
 330
 331         switch (irq) {
 332         case IRQ_SSP3:
 333                 mask = ADXER_MFP_WSSP3;
 334                 break;
 335         case IRQ_MSL:
 336                 mask = ADXER_WMSL0;
 337                 break;
 338         case IRQ_USBH2:
 339         case IRQ_USBH1:
 340                 mask = ADXER_WUSBH;
 341                 break;
 342         case IRQ_KEYPAD:
 343                 mask = ADXER_WKP;
 344                 break;
 345         case IRQ_AC97:
 346                 mask = ADXER_MFP_WAC97;
 347                 break;
 348         case IRQ_USIM:
 349                 mask = ADXER_WUSIM0;
 350                 break;
 351         case IRQ_SSP2:
 352                 mask = ADXER_MFP_WSSP2;
 353                 break;
 354         case IRQ_I2C:
 355                 mask = ADXER_MFP_WI2C;
 356                 break;
 357         case IRQ_STUART:
 358                 mask = ADXER_MFP_WUART3;
 359                 break;
 360         case IRQ_BTUART:
 361                 mask = ADXER_MFP_WUART2;
 362                 break;
 363         case IRQ_FFUART:
 364                 mask = ADXER_MFP_WUART1;
 365                 break;
 366         case IRQ_MMC:
 367                 mask = ADXER_MFP_WMMC1;
 368                 break;
 369         case IRQ_SSP:
 370                 mask = ADXER_MFP_WSSP1;
 371                 break;
 372         case IRQ_RTCAlrm:
 373                 mask = ADXER_WRTC;
 374                 break;
 375         case IRQ_SSP4:
 376                 mask = ADXER_MFP_WSSP4;
 377                 break;
 378         case IRQ_TSI:
 379                 mask = ADXER_WTSI;
 380                 break;
 381         case IRQ_USIM2:
 382                 mask = ADXER_WUSIM1;
 383                 break;
 384         case IRQ_MMC2:
 385                 mask = ADXER_MFP_WMMC2;
 386                 break;
 387         case IRQ_NAND:
 388                 mask = ADXER_MFP_WFLASH;
 389                 break;
 390         case IRQ_USB2:
 391                 mask = ADXER_WUSB2;
 392                 break;
 393         case IRQ_WAKEUP0:
 394                 mask = ADXER_WEXTWAKE0;
 395                 break;
 396         case IRQ_WAKEUP1:
 397                 mask = ADXER_WEXTWAKE1;
 398                 break;
 399         case IRQ_MMC3:
 400                 mask = ADXER_MFP_GEN12;
 401                 break;
 402         }
 403
 404         local_irq_save(flags);
 405         if (on)
 406                 wakeup_src |= mask;
 407         else
 408                 wakeup_src &= ~mask;
 409         local_irq_restore(flags);
 410
 411         return 0;
 412 }
 413
 414 static void pxa3xx_init_irq_pm(void)
 415 {
 416         pxa_init_irq_set_wake(pxa3xx_set_wake);
 417 }
 418
 419 #else
 420 static inline void pxa3xx_init_pm(void) {}
 421 static inline void pxa3xx_init_irq_pm(void) {}
 422 #endif
 423
 424 void __init pxa3xx_init_irq(void)
 425 {
 426         /* enable CP6 access */
 427         u32 value;
 428         __asm__ __volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value));
 429         value |= (1 << 6);
 430         __asm__ __volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value));
 431
 432         pxa_init_irq_low();
 433         pxa_init_irq_high();
 434         pxa_init_irq_gpio(128);
 435         pxa3xx_init_irq_pm();
 436 }
 437
 438 /*
 439  * device registration specific to PXA3xx.
 440  */
 441
 442 static struct platform_device *devices[] __initdata = {
 443         &pxa_device_udc,
 444         &pxa_device_ffuart,
 445         &pxa_device_btuart,
 446         &pxa_device_stuart,
 447         &pxa_device_i2s,
 448         &pxa_device_rtc,
 449         &pxa27x_device_ssp1,
 450         &pxa27x_device_ssp2,
 451         &pxa27x_device_ssp3,
 452         &pxa3xx_device_ssp4,
 453 };
 454
 455 static int __init pxa3xx_init(void)
 456 {
 457         int ret = 0;
 458
 459         if (cpu_is_pxa3xx()) {
 460                 clks_register(pxa3xx_clks, ARRAY_SIZE(pxa3xx_clks));
 461
 462                 if ((ret = pxa_init_dma(32)))
 463                         return ret;
 464
 465                 pxa3xx_init_pm();
 466
 467                 return platform_add_devices(devices, ARRAY_SIZE(devices));
 468         }
 469         return 0;
 470 }
 471
 472 subsys_initcall(pxa3xx_init);