include/asm-xtensa/xtensa/config-linux_be/tie.h

   1 /*
   2  * xtensa/config/tie.h -- HAL definitions that are dependent on CORE and TIE configuration
   3  *
   4  *  This header file is sometimes referred to as the "compile-time HAL" or CHAL.
   5  *  It was generated for a specific Xtensa processor configuration,
   6  *  and furthermore for a specific set of TIE source files that extend
   7  *  basic core functionality.
   8  *
   9  *  Source for configuration-independent binaries (which link in a
  10  *  configuration-specific HAL library) must NEVER include this file.
  11  *  It is perfectly normal, however, for the HAL source itself to include this file.
  12  */
  13
  14 /*
  15  * Copyright (c) 2003 Tensilica, Inc.  All Rights Reserved.
  16  *
  17  * This program is free software; you can redistribute it and/or modify
  18  * it under the terms of version 2.1 of the GNU Lesser General Public
  19  * License as published by the Free Software Foundation.
  20  *
  21  * This program is distributed in the hope that it would be useful, but
  22  * WITHOUT ANY WARRANTY; without even the implied warranty of
  23  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  24  *
  25  * Further, this software is distributed without any warranty that it is
  26  * free of the rightful claim of any third person regarding infringement
  27  * or the like.  Any license provided herein, whether implied or
  28  * otherwise, applies only to this software file.  Patent licenses, if
  29  * any, provided herein do not apply to combinations of this program with
  30  * other software, or any other product whatsoever.
  31  *
  32  * You should have received a copy of the GNU Lesser General Public
  33  * License along with this program; if not, write the Free Software
  34  * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307,
  35  * USA.
  36  */
  37
  38
  39 #ifndef XTENSA_CONFIG_TIE_H
  40 #define XTENSA_CONFIG_TIE_H
  41
  42 #include <xtensa/hal.h>
  43
  44
  45 /*----------------------------------------------------------------------
  46                                 GENERAL
  47   ----------------------------------------------------------------------*/
  48
  49 /*
  50  *  Separators for macros that expand into arrays.
  51  *  These can be predefined by files that #include this one,
  52  *  when different separators are required.
  53  */
  54 /*  Element separator for macros that expand into 1-dimensional arrays:  */
  55 #ifndef XCHAL_SEP
  56 #define XCHAL_SEP                       ,
  57 #endif
  58 /*  Array separator for macros that expand into 2-dimensional arrays:  */
  59 #ifndef XCHAL_SEP2
  60 #define XCHAL_SEP2                      },{
  61 #endif
  62
  63
  64
  65
  66
  67
  68 /*----------------------------------------------------------------------
  69                         COPROCESSORS and EXTRA STATE
  70   ----------------------------------------------------------------------*/
  71
  72 #define XCHAL_CP_NUM                    0       /* number of coprocessors */
  73 #define XCHAL_CP_MAX                    0       /* max coprocessor id plus one (0 if none) */
  74 #define XCHAL_CP_MASK                   0x00    /* bitmask of coprocessors by id */
  75
  76 /*  Space for coprocessors' state save areas:  */
  77 #define XCHAL_CP0_SA_SIZE               0
  78 #define XCHAL_CP1_SA_SIZE               0
  79 #define XCHAL_CP2_SA_SIZE               0
  80 #define XCHAL_CP3_SA_SIZE               0
  81 #define XCHAL_CP4_SA_SIZE               0
  82 #define XCHAL_CP5_SA_SIZE               0
  83 #define XCHAL_CP6_SA_SIZE               0
  84 #define XCHAL_CP7_SA_SIZE               0
  85 /*  Minimum required alignments of CP state save areas:  */
  86 #define XCHAL_CP0_SA_ALIGN              1
  87 #define XCHAL_CP1_SA_ALIGN              1
  88 #define XCHAL_CP2_SA_ALIGN              1
  89 #define XCHAL_CP3_SA_ALIGN              1
  90 #define XCHAL_CP4_SA_ALIGN              1
  91 #define XCHAL_CP5_SA_ALIGN              1
  92 #define XCHAL_CP6_SA_ALIGN              1
  93 #define XCHAL_CP7_SA_ALIGN              1
  94
  95 /*  Indexing macros:  */
  96 #define _XCHAL_CP_SA_SIZE(n)            XCHAL_CP ## n ## _SA_SIZE
  97 #define XCHAL_CP_SA_SIZE(n)             _XCHAL_CP_SA_SIZE(n)    /* n = 0 .. 7 */
  98 #define _XCHAL_CP_SA_ALIGN(n)           XCHAL_CP ## n ## _SA_ALIGN
  99 #define XCHAL_CP_SA_ALIGN(n)            _XCHAL_CP_SA_ALIGN(n)   /* n = 0 .. 7 */
 100
 101
 102 /*  Space for "extra" state (user special registers and non-cp TIE) save area:  */
 103 #define XCHAL_EXTRA_SA_SIZE             0
 104 #define XCHAL_EXTRA_SA_ALIGN            1
 105
 106 /*  Total save area size (extra + all coprocessors)  */
 107 /*  (not useful until xthal_{save,restore}_all_extra() is implemented,  */
 108 /*   but included for Tor2 beta; doesn't account for alignment!):  */
 109 #define XCHAL_CPEXTRA_SA_SIZE_TOR2      0       /* Tor2Beta temporary definition -- do not use */
 110
 111 /*  Combined required alignment for all CP and EXTRA state save areas  */
 112 /*  (does not include required alignment for any base config registers):  */
 113 #define XCHAL_CPEXTRA_SA_ALIGN          1
 114
 115 /* ... */
 116
 117
 118 #ifdef __ASSEMBLER__
 119 /*
 120  *  Assembly-language specific definitions (assembly macros, etc.).
 121  */
 122 #include <xtensa/config/specreg.h>
 123
 124 /********************
 125  *  Macros to save and restore the non-coprocessor TIE portion of EXTRA state.
 126  */
 127
 128 /* (none) */
 129
 130
 131 /********************
 132  *  Macros to create functions that save and restore all EXTRA (non-coprocessor) state
 133  *  (does not include zero-overhead loop registers and non-optional registers).
 134  */
 135
 136         /*
 137          *  Macro that expands to the body of a function that
 138          *  stores the extra (non-coprocessor) optional/custom state.
 139          *      Entry:  a2 = ptr to save area in which to save extra state
 140          *      Exit:   any register a2-a15 (?) may have been clobbered.
 141          */
 142         .macro  xchal_extra_store_funcbody
 143         .endm
 144
 145
 146         /*
 147          *  Macro that expands to the body of a function that
 148          *  loads the extra (non-coprocessor) optional/custom state.
 149          *      Entry:  a2 = ptr to save area from which to restore extra state
 150          *      Exit:   any register a2-a15 (?) may have been clobbered.
 151          */
 152         .macro  xchal_extra_load_funcbody
 153         .endm
 154
 155
 156 /********************
 157  *  Macros to save and restore the state of each TIE coprocessor.
 158  */
 159
 160
 161
 162 /********************
 163  *  Macros to create functions that save and restore the state of *any* TIE coprocessor.
 164  */
 165
 166         /*
 167          *  Macro that expands to the body of a function
 168          *  that stores the selected coprocessor's state (registers etc).
 169          *      Entry:  a2 = ptr to save area in which to save cp state
 170          *              a3 = coprocessor number
 171          *      Exit:   any register a2-a15 (?) may have been clobbered.
 172          */
 173         .macro  xchal_cpi_store_funcbody
 174         .endm
 175
 176
 177         /*
 178          *  Macro that expands to the body of a function
 179          *  that loads the selected coprocessor's state (registers etc).
 180          *      Entry:  a2 = ptr to save area from which to restore cp state
 181          *              a3 = coprocessor number
 182          *      Exit:   any register a2-a15 (?) may have been clobbered.
 183          */
 184         .macro  xchal_cpi_load_funcbody
 185         .endm
 186
 187 #endif /*_ASMLANGUAGE*/
 188
 189
 190 /*
 191  *  Contents of save areas in terms of libdb register numbers.
 192  *  NOTE:  CONTENTS_LIBDB_{UREG,REGF} macros are not defined in this file;
 193  *  it is up to the user of this header file to define these macros
 194  *  usefully before each expansion of the CONTENTS_LIBDB macros.
 195  *  (Fields rsv[123] are reserved for future additions; they are currently
 196  *   set to zero but may be set to some useful values in the future.)
 197  *
 198  *      CONTENTS_LIBDB_SREG(libdbnum, offset, size, align, rsv1, name, sregnum, bitmask, rsv2, rsv3)
 199  *      CONTENTS_LIBDB_UREG(libdbnum, offset, size, align, rsv1, name, uregnum, bitmask, rsv2, rsv3)
 200  *      CONTENTS_LIBDB_REGF(libdbnum, offset, size, align, rsv1, name, index, numentries, contentsize, regname_base, regfile_name, rsv2, rsv3)
 201  */
 202
 203 #define XCHAL_EXTRA_SA_CONTENTS_LIBDB_NUM       0
 204 #define XCHAL_EXTRA_SA_CONTENTS_LIBDB   /* empty */
 205
 206 #define XCHAL_CP0_SA_CONTENTS_LIBDB_NUM 0
 207 #define XCHAL_CP0_SA_CONTENTS_LIBDB     /* empty */
 208
 209 #define XCHAL_CP1_SA_CONTENTS_LIBDB_NUM 0
 210 #define XCHAL_CP1_SA_CONTENTS_LIBDB     /* empty */
 211
 212 #define XCHAL_CP2_SA_CONTENTS_LIBDB_NUM 0
 213 #define XCHAL_CP2_SA_CONTENTS_LIBDB     /* empty */
 214
 215 #define XCHAL_CP3_SA_CONTENTS_LIBDB_NUM 0
 216 #define XCHAL_CP3_SA_CONTENTS_LIBDB     /* empty */
 217
 218 #define XCHAL_CP4_SA_CONTENTS_LIBDB_NUM 0
 219 #define XCHAL_CP4_SA_CONTENTS_LIBDB     /* empty */
 220
 221 #define XCHAL_CP5_SA_CONTENTS_LIBDB_NUM 0
 222 #define XCHAL_CP5_SA_CONTENTS_LIBDB     /* empty */
 223
 224 #define XCHAL_CP6_SA_CONTENTS_LIBDB_NUM 0
 225 #define XCHAL_CP6_SA_CONTENTS_LIBDB     /* empty */
 226
 227 #define XCHAL_CP7_SA_CONTENTS_LIBDB_NUM 0
 228 #define XCHAL_CP7_SA_CONTENTS_LIBDB     /* empty */
 229
 230
 231
 232
 233
 234
 235 /*----------------------------------------------------------------------
 236                                 MISC
 237   ----------------------------------------------------------------------*/
 238
 239 #if 0   /* is there something equivalent for user TIE? */
 240 #define XCHAL_CORE_ID                   "linux_be"      /* configuration's alphanumeric core identifier
 241                                                            (CoreID) set in the Xtensa Processor Generator */
 242
 243 #define XCHAL_BUILD_UNIQUE_ID           0x00003256      /* software build-unique ID (22-bit) */
 244
 245 /*  These definitions describe the hardware targeted by this software:  */
 246 #define XCHAL_HW_CONFIGID0              0xC103D1FF      /* config ID reg 0 value (upper 32 of 64 bits) */
 247 #define XCHAL_HW_CONFIGID1              0x00803256      /* config ID reg 1 value (lower 32 of 64 bits) */
 248 #define XCHAL_CONFIGID0                 XCHAL_HW_CONFIGID0      /* for backward compatibility only -- don't use! */
 249 #define XCHAL_CONFIGID1                 XCHAL_HW_CONFIGID1      /* for backward compatibility only -- don't use! */
 250 #define XCHAL_HW_RELEASE_MAJOR          1050    /* major release of targeted hardware */
 251 #define XCHAL_HW_RELEASE_MINOR          1       /* minor release of targeted hardware */
 252 #define XCHAL_HW_RELEASE_NAME           "T1050.1"       /* full release name of targeted hardware */
 253 #define XTHAL_HW_REL_T1050      1
 254 #define XTHAL_HW_REL_T1050_1    1
 255 #define XCHAL_HW_CONFIGID_RELIABLE      1
 256 #endif /*0*/
 257
 258
 259
 260 /*----------------------------------------------------------------------
 261                                 ISA
 262   ----------------------------------------------------------------------*/
 263
 264 #if 0   /* these probably don't belong here, but are related to or implemented using TIE */
 265 #define XCHAL_HAVE_BOOLEANS             0       /* 1 if booleans option configured, 0 otherwise */
 266 /*  Misc instructions:  */
 267 #define XCHAL_HAVE_MUL32                0       /* 1 if 32-bit integer multiply option configured, 0 otherwise */
 268 #define XCHAL_HAVE_MUL32_HIGH           0       /* 1 if MUL32 option includes MULUH and MULSH, 0 otherwise */
 269
 270 #define XCHAL_HAVE_FP                   0       /* 1 if floating point option configured, 0 otherwise */
 271 #endif /*0*/
 272
 273
 274 #endif /*XTENSA_CONFIG_TIE_H*/
 275