2 * linux/arch/arm/mach-integrator/integrator_cp.c
4 * Copyright (C) 2003 Deep Blue Solutions Ltd
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License.
10 #include <linux/types.h>
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/list.h>
14 #include <linux/platform_device.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/string.h>
17 #include <linux/sysdev.h>
18 #include <linux/amba/bus.h>
19 #include <linux/amba/kmi.h>
20 #include <linux/amba/clcd.h>
21 #include <linux/amba/mmci.h>
23 #include <linux/gfp.h>
24 #include <linux/clkdev.h>
26 #include <mach/hardware.h>
27 #include <mach/platform.h>
29 #include <asm/setup.h>
30 #include <asm/mach-types.h>
31 #include <asm/hardware/arm_timer.h>
32 #include <asm/hardware/icst.h>
37 #include <asm/mach/arch.h>
38 #include <asm/mach/flash.h>
39 #include <asm/mach/irq.h>
40 #include <asm/mach/map.h>
41 #include <asm/mach/time.h>
43 #include <asm/hardware/timer-sp.h>
45 #include <plat/clcd.h>
46 #include <plat/fpga-irq.h>
47 #include <plat/sched_clock.h>
51 #define INTCP_PA_FLASH_BASE 0x24000000
52 #define INTCP_FLASH_SIZE SZ_32M
54 #define INTCP_PA_CLCD_BASE 0xc0000000
56 #define INTCP_VA_CIC_BASE __io_address(INTEGRATOR_HDR_BASE + 0x40)
57 #define INTCP_VA_PIC_BASE __io_address(INTEGRATOR_IC_BASE)
58 #define INTCP_VA_SIC_BASE __io_address(INTEGRATOR_CP_SIC_BASE)
60 #define INTCP_ETH_SIZE 0x10
62 #define INTCP_VA_CTRL_BASE IO_ADDRESS(INTEGRATOR_CP_CTL_BASE)
63 #define INTCP_FLASHPROG 0x04
64 #define CINTEGRATOR_FLASHPROG_FLVPPEN (1 << 0)
65 #define CINTEGRATOR_FLASHPROG_FLWREN (1 << 1)
69 * f1000000 10000000 Core module registers
70 * f1100000 11000000 System controller registers
71 * f1200000 12000000 EBI registers
72 * f1300000 13000000 Counter/Timer
73 * f1400000 14000000 Interrupt controller
74 * f1600000 16000000 UART 0
75 * f1700000 17000000 UART 1
76 * f1a00000 1a000000 Debug LEDs
77 * fc900000 c9000000 GPIO
78 * fca00000 ca000000 SIC
79 * fcb00000 cb000000 CP system control
82 static struct map_desc intcp_io_desc
[] __initdata
= {
84 .virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE
),
85 .pfn
= __phys_to_pfn(INTEGRATOR_HDR_BASE
),
89 .virtual = IO_ADDRESS(INTEGRATOR_SC_BASE
),
90 .pfn
= __phys_to_pfn(INTEGRATOR_SC_BASE
),
94 .virtual = IO_ADDRESS(INTEGRATOR_EBI_BASE
),
95 .pfn
= __phys_to_pfn(INTEGRATOR_EBI_BASE
),
99 .virtual = IO_ADDRESS(INTEGRATOR_CT_BASE
),
100 .pfn
= __phys_to_pfn(INTEGRATOR_CT_BASE
),
104 .virtual = IO_ADDRESS(INTEGRATOR_IC_BASE
),
105 .pfn
= __phys_to_pfn(INTEGRATOR_IC_BASE
),
109 .virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE
),
110 .pfn
= __phys_to_pfn(INTEGRATOR_UART0_BASE
),
114 .virtual = IO_ADDRESS(INTEGRATOR_UART1_BASE
),
115 .pfn
= __phys_to_pfn(INTEGRATOR_UART1_BASE
),
119 .virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE
),
120 .pfn
= __phys_to_pfn(INTEGRATOR_DBG_BASE
),
124 .virtual = IO_ADDRESS(INTEGRATOR_CP_GPIO_BASE
),
125 .pfn
= __phys_to_pfn(INTEGRATOR_CP_GPIO_BASE
),
129 .virtual = IO_ADDRESS(INTEGRATOR_CP_SIC_BASE
),
130 .pfn
= __phys_to_pfn(INTEGRATOR_CP_SIC_BASE
),
134 .virtual = IO_ADDRESS(INTEGRATOR_CP_CTL_BASE
),
135 .pfn
= __phys_to_pfn(INTEGRATOR_CP_CTL_BASE
),
141 static void __init
intcp_map_io(void)
143 iotable_init(intcp_io_desc
, ARRAY_SIZE(intcp_io_desc
));
146 static struct fpga_irq_data cic_irq_data
= {
147 .base
= INTCP_VA_CIC_BASE
,
148 .irq_start
= IRQ_CIC_START
,
152 static struct fpga_irq_data pic_irq_data
= {
153 .base
= INTCP_VA_PIC_BASE
,
154 .irq_start
= IRQ_PIC_START
,
158 static struct fpga_irq_data sic_irq_data
= {
159 .base
= INTCP_VA_SIC_BASE
,
160 .irq_start
= IRQ_SIC_START
,
164 static void __init
intcp_init_irq(void)
166 u32 pic_mask
, sic_mask
;
168 pic_mask
= ~((~0u) << (11 - IRQ_PIC_START
));
169 pic_mask
|= (~((~0u) << (29 - 22))) << 22;
170 sic_mask
= ~((~0u) << (1 + IRQ_SIC_END
- IRQ_SIC_START
));
173 * Disable all interrupt sources
175 writel(0xffffffff, INTCP_VA_PIC_BASE
+ IRQ_ENABLE_CLEAR
);
176 writel(0xffffffff, INTCP_VA_PIC_BASE
+ FIQ_ENABLE_CLEAR
);
177 writel(0xffffffff, INTCP_VA_CIC_BASE
+ IRQ_ENABLE_CLEAR
);
178 writel(0xffffffff, INTCP_VA_CIC_BASE
+ FIQ_ENABLE_CLEAR
);
179 writel(sic_mask
, INTCP_VA_SIC_BASE
+ IRQ_ENABLE_CLEAR
);
180 writel(sic_mask
, INTCP_VA_SIC_BASE
+ FIQ_ENABLE_CLEAR
);
182 fpga_irq_init(-1, pic_mask
, &pic_irq_data
);
184 fpga_irq_init(-1, ~((~0u) << (1 + IRQ_CIC_END
- IRQ_CIC_START
)),
187 fpga_irq_init(IRQ_CP_CPPLDINT
, sic_mask
, &sic_irq_data
);
193 #define CM_LOCK (__io_address(INTEGRATOR_HDR_BASE)+INTEGRATOR_HDR_LOCK_OFFSET)
194 #define CM_AUXOSC (__io_address(INTEGRATOR_HDR_BASE)+0x1c)
196 static const struct icst_params cp_auxvco_params
= {
198 .vco_max
= ICST525_VCO_MAX_5V
,
199 .vco_min
= ICST525_VCO_MIN
,
204 .s2div
= icst525_s2div
,
205 .idx2s
= icst525_idx2s
,
208 static void cp_auxvco_set(struct clk
*clk
, struct icst_vco vco
)
212 val
= readl(clk
->vcoreg
) & ~0x7ffff;
213 val
|= vco
.v
| (vco
.r
<< 9) | (vco
.s
<< 16);
215 writel(0xa05f, CM_LOCK
);
216 writel(val
, clk
->vcoreg
);
220 static const struct clk_ops cp_auxclk_ops
= {
221 .round
= icst_clk_round
,
223 .setvco
= cp_auxvco_set
,
226 static struct clk cp_auxclk
= {
227 .ops
= &cp_auxclk_ops
,
228 .params
= &cp_auxvco_params
,
232 static struct clk_lookup cp_lookups
[] = {
242 static int intcp_flash_init(void)
246 val
= readl(INTCP_VA_CTRL_BASE
+ INTCP_FLASHPROG
);
247 val
|= CINTEGRATOR_FLASHPROG_FLWREN
;
248 writel(val
, INTCP_VA_CTRL_BASE
+ INTCP_FLASHPROG
);
253 static void intcp_flash_exit(void)
257 val
= readl(INTCP_VA_CTRL_BASE
+ INTCP_FLASHPROG
);
258 val
&= ~(CINTEGRATOR_FLASHPROG_FLVPPEN
|CINTEGRATOR_FLASHPROG_FLWREN
);
259 writel(val
, INTCP_VA_CTRL_BASE
+ INTCP_FLASHPROG
);
262 static void intcp_flash_set_vpp(int on
)
266 val
= readl(INTCP_VA_CTRL_BASE
+ INTCP_FLASHPROG
);
268 val
|= CINTEGRATOR_FLASHPROG_FLVPPEN
;
270 val
&= ~CINTEGRATOR_FLASHPROG_FLVPPEN
;
271 writel(val
, INTCP_VA_CTRL_BASE
+ INTCP_FLASHPROG
);
274 static struct flash_platform_data intcp_flash_data
= {
275 .map_name
= "cfi_probe",
277 .init
= intcp_flash_init
,
278 .exit
= intcp_flash_exit
,
279 .set_vpp
= intcp_flash_set_vpp
,
282 static struct resource intcp_flash_resource
= {
283 .start
= INTCP_PA_FLASH_BASE
,
284 .end
= INTCP_PA_FLASH_BASE
+ INTCP_FLASH_SIZE
- 1,
285 .flags
= IORESOURCE_MEM
,
288 static struct platform_device intcp_flash_device
= {
292 .platform_data
= &intcp_flash_data
,
295 .resource
= &intcp_flash_resource
,
298 static struct resource smc91x_resources
[] = {
300 .start
= INTEGRATOR_CP_ETH_BASE
,
301 .end
= INTEGRATOR_CP_ETH_BASE
+ INTCP_ETH_SIZE
- 1,
302 .flags
= IORESOURCE_MEM
,
305 .start
= IRQ_CP_ETHINT
,
306 .end
= IRQ_CP_ETHINT
,
307 .flags
= IORESOURCE_IRQ
,
311 static struct platform_device smc91x_device
= {
314 .num_resources
= ARRAY_SIZE(smc91x_resources
),
315 .resource
= smc91x_resources
,
318 static struct platform_device
*intcp_devs
[] __initdata
= {
324 * It seems that the card insertion interrupt remains active after
325 * we've acknowledged it. We therefore ignore the interrupt, and
326 * rely on reading it from the SIC. This also means that we must
327 * clear the latched interrupt.
329 static unsigned int mmc_status(struct device
*dev
)
331 unsigned int status
= readl(IO_ADDRESS(0xca000000 + 4));
332 writel(8, IO_ADDRESS(INTEGRATOR_CP_CTL_BASE
+ 8));
337 static struct mmci_platform_data mmc_data
= {
338 .ocr_mask
= MMC_VDD_32_33
|MMC_VDD_33_34
,
339 .status
= mmc_status
,
344 static struct amba_device mmc_device
= {
346 .init_name
= "mb:1c",
347 .platform_data
= &mmc_data
,
350 .start
= INTEGRATOR_CP_MMC_BASE
,
351 .end
= INTEGRATOR_CP_MMC_BASE
+ SZ_4K
- 1,
352 .flags
= IORESOURCE_MEM
,
354 .irq
= { IRQ_CP_MMCIINT0
, IRQ_CP_MMCIINT1
},
358 static struct amba_device aaci_device
= {
360 .init_name
= "mb:1d",
363 .start
= INTEGRATOR_CP_AACI_BASE
,
364 .end
= INTEGRATOR_CP_AACI_BASE
+ SZ_4K
- 1,
365 .flags
= IORESOURCE_MEM
,
367 .irq
= { IRQ_CP_AACIINT
, NO_IRQ
},
376 * Ensure VGA is selected.
378 static void cp_clcd_enable(struct clcd_fb
*fb
)
380 struct fb_var_screeninfo
*var
= &fb
->fb
.var
;
381 u32 val
= CM_CTRL_STATIC1
| CM_CTRL_STATIC2
;
383 if (var
->bits_per_pixel
<= 8 ||
384 (var
->bits_per_pixel
== 16 && var
->green
.length
== 5))
385 /* Pseudocolor, RGB555, BGR555 */
386 val
|= CM_CTRL_LCDMUXSEL_VGA555_TFT555
;
387 else if (fb
->fb
.var
.bits_per_pixel
<= 16)
388 /* truecolor RGB565 */
389 val
|= CM_CTRL_LCDMUXSEL_VGA565_TFT555
;
391 val
= 0; /* no idea for this, don't trust the docs */
393 cm_control(CM_CTRL_LCDMUXSEL_MASK
|
399 CM_CTRL_n24BITEN
, val
);
402 static int cp_clcd_setup(struct clcd_fb
*fb
)
404 fb
->panel
= versatile_clcd_get_panel("VGA");
408 return versatile_clcd_setup_dma(fb
, SZ_1M
);
411 static struct clcd_board clcd_data
= {
412 .name
= "Integrator/CP",
413 .caps
= CLCD_CAP_5551
| CLCD_CAP_RGB565
| CLCD_CAP_888
,
414 .check
= clcdfb_check
,
415 .decode
= clcdfb_decode
,
416 .enable
= cp_clcd_enable
,
417 .setup
= cp_clcd_setup
,
418 .mmap
= versatile_clcd_mmap_dma
,
419 .remove
= versatile_clcd_remove_dma
,
422 static struct amba_device clcd_device
= {
424 .init_name
= "mb:c0",
425 .coherent_dma_mask
= ~0,
426 .platform_data
= &clcd_data
,
429 .start
= INTCP_PA_CLCD_BASE
,
430 .end
= INTCP_PA_CLCD_BASE
+ SZ_4K
- 1,
431 .flags
= IORESOURCE_MEM
,
434 .irq
= { IRQ_CP_CLCDCINT
, NO_IRQ
},
438 static struct amba_device
*amba_devs
[] __initdata
= {
444 #define REFCOUNTER (__io_address(INTEGRATOR_HDR_BASE) + 0x28)
446 static void __init
intcp_init_early(void)
448 clkdev_add_table(cp_lookups
, ARRAY_SIZE(cp_lookups
));
450 integrator_init_early();
452 #ifdef CONFIG_PLAT_VERSATILE_SCHED_CLOCK
453 versatile_sched_clock_init(REFCOUNTER
, 24000000);
457 static void __init
intcp_init(void)
461 platform_add_devices(intcp_devs
, ARRAY_SIZE(intcp_devs
));
463 for (i
= 0; i
< ARRAY_SIZE(amba_devs
); i
++) {
464 struct amba_device
*d
= amba_devs
[i
];
465 amba_device_register(d
, &iomem_resource
);
469 #define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE)
470 #define TIMER1_VA_BASE __io_address(INTEGRATOR_TIMER1_BASE)
471 #define TIMER2_VA_BASE __io_address(INTEGRATOR_TIMER2_BASE)
473 static void __init
intcp_timer_init(void)
475 writel(0, TIMER0_VA_BASE
+ TIMER_CTRL
);
476 writel(0, TIMER1_VA_BASE
+ TIMER_CTRL
);
477 writel(0, TIMER2_VA_BASE
+ TIMER_CTRL
);
479 sp804_clocksource_init(TIMER2_VA_BASE
, "timer2");
480 sp804_clockevents_init(TIMER1_VA_BASE
, IRQ_TIMERINT1
);
483 static struct sys_timer cp_timer
= {
484 .init
= intcp_timer_init
,
487 MACHINE_START(CINTEGRATOR
, "ARM-IntegratorCP")
488 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
489 .boot_params
= 0x00000100,
490 .reserve
= integrator_reserve
,
491 .map_io
= intcp_map_io
,
492 .init_early
= intcp_init_early
,
493 .init_irq
= intcp_init_irq
,
495 .init_machine
= intcp_init
,