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KVM: Dynamically allocate vcpus
[linux-2.6/kvm.git] / drivers / kvm / svm.c
blob0feec8558599975d927cc641ecef76e7a43504c5
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 *
8 * Authors:
9 * Yaniv Kamay <yaniv@qumranet.com>
10 * Avi Kivity <avi@qumranet.com>
11 *
12 * This work is licensed under the terms of the GNU GPL, version 2. See
13 * the COPYING file in the top-level directory.
14 *
15 */
16
17 #include "kvm_svm.h"
18 #include "x86_emulate.h"
19
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/vmalloc.h>
23 #include <linux/highmem.h>
24 #include <linux/profile.h>
25 #include <linux/sched.h>
26
27 #include <asm/desc.h>
28
29 MODULE_AUTHOR("Qumranet");
30 MODULE_LICENSE("GPL");
31
32 #define IOPM_ALLOC_ORDER 2
33 #define MSRPM_ALLOC_ORDER 1
34
35 #define DB_VECTOR 1
36 #define UD_VECTOR 6
37 #define GP_VECTOR 13
38
39 #define DR7_GD_MASK (1 << 13)
40 #define DR6_BD_MASK (1 << 13)
41
42 #define SEG_TYPE_LDT 2
43 #define SEG_TYPE_BUSY_TSS16 3
44
45 #define KVM_EFER_LMA (1 << 10)
46 #define KVM_EFER_LME (1 << 8)
47
48 #define SVM_FEATURE_NPT (1 << 0)
49 #define SVM_FEATURE_LBRV (1 << 1)
50 #define SVM_DEATURE_SVML (1 << 2)
51
52 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
53 {
54 return container_of(vcpu, struct vcpu_svm, vcpu);
55 }
56
57 unsigned long iopm_base;
58 unsigned long msrpm_base;
59
60 struct kvm_ldttss_desc {
61 u16 limit0;
62 u16 base0;
63 unsigned base1 : 8, type : 5, dpl : 2, p : 1;
64 unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
65 u32 base3;
66 u32 zero1;
67 } __attribute__((packed));
68
69 struct svm_cpu_data {
70 int cpu;
71
72 u64 asid_generation;
73 u32 max_asid;
74 u32 next_asid;
75 struct kvm_ldttss_desc *tss_desc;
76
77 struct page *save_area;
78 };
79
80 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
81 static uint32_t svm_features;
82
83 struct svm_init_data {
84 int cpu;
85 int r;
86 };
87
88 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
89
90 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
91 #define MSRS_RANGE_SIZE 2048
92 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
93
94 #define MAX_INST_SIZE 15
95
96 static inline u32 svm_has(u32 feat)
97 {
98 return svm_features & feat;
99 }
100
101 static unsigned get_addr_size(struct kvm_vcpu *vcpu)
102 {
103 struct vmcb_save_area *sa = &to_svm(vcpu)->vmcb->save;
104 u16 cs_attrib;
105
106 if (!(sa->cr0 & X86_CR0_PE) || (sa->rflags & X86_EFLAGS_VM))
107 return 2;
108
109 cs_attrib = sa->cs.attrib;
110
111 return (cs_attrib & SVM_SELECTOR_L_MASK) ? 8 :
112 (cs_attrib & SVM_SELECTOR_DB_MASK) ? 4 : 2;
113 }
114
115 static inline u8 pop_irq(struct kvm_vcpu *vcpu)
116 {
117 int word_index = __ffs(vcpu->irq_summary);
118 int bit_index = __ffs(vcpu->irq_pending[word_index]);
119 int irq = word_index * BITS_PER_LONG + bit_index;
120
121 clear_bit(bit_index, &vcpu->irq_pending[word_index]);
122 if (!vcpu->irq_pending[word_index])
123 clear_bit(word_index, &vcpu->irq_summary);
124 return irq;
125 }
126
127 static inline void push_irq(struct kvm_vcpu *vcpu, u8 irq)
128 {
129 set_bit(irq, vcpu->irq_pending);
130 set_bit(irq / BITS_PER_LONG, &vcpu->irq_summary);
131 }
132
133 static inline void clgi(void)
134 {
135 asm volatile (SVM_CLGI);
136 }
137
138 static inline void stgi(void)
139 {
140 asm volatile (SVM_STGI);
141 }
142
143 static inline void invlpga(unsigned long addr, u32 asid)
144 {
145 asm volatile (SVM_INVLPGA :: "a"(addr), "c"(asid));
146 }
147
148 static inline unsigned long kvm_read_cr2(void)
149 {
150 unsigned long cr2;
151
152 asm volatile ("mov %%cr2, %0" : "=r" (cr2));
153 return cr2;
154 }
155
156 static inline void kvm_write_cr2(unsigned long val)
157 {
158 asm volatile ("mov %0, %%cr2" :: "r" (val));
159 }
160
161 static inline unsigned long read_dr6(void)
162 {
163 unsigned long dr6;
164
165 asm volatile ("mov %%dr6, %0" : "=r" (dr6));
166 return dr6;
167 }
168
169 static inline void write_dr6(unsigned long val)
170 {
171 asm volatile ("mov %0, %%dr6" :: "r" (val));
172 }
173
174 static inline unsigned long read_dr7(void)
175 {
176 unsigned long dr7;
177
178 asm volatile ("mov %%dr7, %0" : "=r" (dr7));
179 return dr7;
180 }
181
182 static inline void write_dr7(unsigned long val)
183 {
184 asm volatile ("mov %0, %%dr7" :: "r" (val));
185 }
186
187 static inline void force_new_asid(struct kvm_vcpu *vcpu)
188 {
189 to_svm(vcpu)->asid_generation--;
190 }
191
192 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
193 {
194 force_new_asid(vcpu);
195 }
196
197 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
198 {
199 if (!(efer & KVM_EFER_LMA))
200 efer &= ~KVM_EFER_LME;
201
202 to_svm(vcpu)->vmcb->save.efer = efer | MSR_EFER_SVME_MASK;
203 vcpu->shadow_efer = efer;
204 }
205
206 static void svm_inject_gp(struct kvm_vcpu *vcpu, unsigned error_code)
207 {
208 struct vcpu_svm *svm = to_svm(vcpu);
209
210 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID |
211 SVM_EVTINJ_VALID_ERR |
212 SVM_EVTINJ_TYPE_EXEPT |
213 GP_VECTOR;
214 svm->vmcb->control.event_inj_err = error_code;
215 }
216
217 static void inject_ud(struct kvm_vcpu *vcpu)
218 {
219 to_svm(vcpu)->vmcb->control.event_inj = SVM_EVTINJ_VALID |
220 SVM_EVTINJ_TYPE_EXEPT |
221 UD_VECTOR;
222 }
223
224 static int is_page_fault(uint32_t info)
225 {
226 info &= SVM_EVTINJ_VEC_MASK | SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
227 return info == (PF_VECTOR | SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_EXEPT);
228 }
229
230 static int is_external_interrupt(u32 info)
231 {
232 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
233 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
234 }
235
236 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
237 {
238 struct vcpu_svm *svm = to_svm(vcpu);
239
240 if (!svm->next_rip) {
241 printk(KERN_DEBUG "%s: NOP\n", __FUNCTION__);
242 return;
243 }
244 if (svm->next_rip - svm->vmcb->save.rip > 15) {
245 printk(KERN_ERR "%s: ip 0x%llx next 0x%llx\n",
246 __FUNCTION__,
247 svm->vmcb->save.rip,
248 svm->next_rip);
249 }
250
251 vcpu->rip = svm->vmcb->save.rip = svm->next_rip;
252 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
253
254 vcpu->interrupt_window_open = 1;
255 }
256
257 static int has_svm(void)
258 {
259 uint32_t eax, ebx, ecx, edx;
260
261 if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
262 printk(KERN_INFO "has_svm: not amd\n");
263 return 0;
264 }
265
266 cpuid(0x80000000, &eax, &ebx, &ecx, &edx);
267 if (eax < SVM_CPUID_FUNC) {
268 printk(KERN_INFO "has_svm: can't execute cpuid_8000000a\n");
269 return 0;
270 }
271
272 cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
273 if (!(ecx & (1 << SVM_CPUID_FEATURE_SHIFT))) {
274 printk(KERN_DEBUG "has_svm: svm not available\n");
275 return 0;
276 }
277 return 1;
278 }
279
280 static void svm_hardware_disable(void *garbage)
281 {
282 struct svm_cpu_data *svm_data
283 = per_cpu(svm_data, raw_smp_processor_id());
284
285 if (svm_data) {
286 uint64_t efer;
287
288 wrmsrl(MSR_VM_HSAVE_PA, 0);
289 rdmsrl(MSR_EFER, efer);
290 wrmsrl(MSR_EFER, efer & ~MSR_EFER_SVME_MASK);
291 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
292 __free_page(svm_data->save_area);
293 kfree(svm_data);
294 }
295 }
296
297 static void svm_hardware_enable(void *garbage)
298 {
299
300 struct svm_cpu_data *svm_data;
301 uint64_t efer;
302 #ifdef CONFIG_X86_64
303 struct desc_ptr gdt_descr;
304 #else
305 struct Xgt_desc_struct gdt_descr;
306 #endif
307 struct desc_struct *gdt;
308 int me = raw_smp_processor_id();
309
310 if (!has_svm()) {
311 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
312 return;
313 }
314 svm_data = per_cpu(svm_data, me);
315
316 if (!svm_data) {
317 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
318 me);
319 return;
320 }
321
322 svm_data->asid_generation = 1;
323 svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
324 svm_data->next_asid = svm_data->max_asid + 1;
325 svm_features = cpuid_edx(SVM_CPUID_FUNC);
326
327 asm volatile ( "sgdt %0" : "=m"(gdt_descr) );
328 gdt = (struct desc_struct *)gdt_descr.address;
329 svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
330
331 rdmsrl(MSR_EFER, efer);
332 wrmsrl(MSR_EFER, efer | MSR_EFER_SVME_MASK);
333
334 wrmsrl(MSR_VM_HSAVE_PA,
335 page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
336 }
337
338 static int svm_cpu_init(int cpu)
339 {
340 struct svm_cpu_data *svm_data;
341 int r;
342
343 svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
344 if (!svm_data)
345 return -ENOMEM;
346 svm_data->cpu = cpu;
347 svm_data->save_area = alloc_page(GFP_KERNEL);
348 r = -ENOMEM;
349 if (!svm_data->save_area)
350 goto err_1;
351
352 per_cpu(svm_data, cpu) = svm_data;
353
354 return 0;
355
356 err_1:
357 kfree(svm_data);
358 return r;
359
360 }
361
362 static int set_msr_interception(u32 *msrpm, unsigned msr,
363 int read, int write)
364 {
365 int i;
366
367 for (i = 0; i < NUM_MSR_MAPS; i++) {
368 if (msr >= msrpm_ranges[i] &&
369 msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
370 u32 msr_offset = (i * MSRS_IN_RANGE + msr -
371 msrpm_ranges[i]) * 2;
372
373 u32 *base = msrpm + (msr_offset / 32);
374 u32 msr_shift = msr_offset % 32;
375 u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
376 *base = (*base & ~(0x3 << msr_shift)) |
377 (mask << msr_shift);
378 return 1;
379 }
380 }
381 printk(KERN_DEBUG "%s: not found 0x%x\n", __FUNCTION__, msr);
382 return 0;
383 }
384
385 static __init int svm_hardware_setup(void)
386 {
387 int cpu;
388 struct page *iopm_pages;
389 struct page *msrpm_pages;
390 void *iopm_va, *msrpm_va;
391 int r;
392
393 kvm_emulator_want_group7_invlpg();
394
395 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
396
397 if (!iopm_pages)
398 return -ENOMEM;
399
400 iopm_va = page_address(iopm_pages);
401 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
402 clear_bit(0x80, iopm_va); /* allow direct access to PC debug port */
403 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
404
405
406 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
407
408 r = -ENOMEM;
409 if (!msrpm_pages)
410 goto err_1;
411
412 msrpm_va = page_address(msrpm_pages);
413 memset(msrpm_va, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
414 msrpm_base = page_to_pfn(msrpm_pages) << PAGE_SHIFT;
415
416 #ifdef CONFIG_X86_64
417 set_msr_interception(msrpm_va, MSR_GS_BASE, 1, 1);
418 set_msr_interception(msrpm_va, MSR_FS_BASE, 1, 1);
419 set_msr_interception(msrpm_va, MSR_KERNEL_GS_BASE, 1, 1);
420 set_msr_interception(msrpm_va, MSR_LSTAR, 1, 1);
421 set_msr_interception(msrpm_va, MSR_CSTAR, 1, 1);
422 set_msr_interception(msrpm_va, MSR_SYSCALL_MASK, 1, 1);
423 #endif
424 set_msr_interception(msrpm_va, MSR_K6_STAR, 1, 1);
425 set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_CS, 1, 1);
426 set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_ESP, 1, 1);
427 set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_EIP, 1, 1);
428
429 for_each_online_cpu(cpu) {
430 r = svm_cpu_init(cpu);
431 if (r)
432 goto err_2;
433 }
434 return 0;
435
436 err_2:
437 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
438 msrpm_base = 0;
439 err_1:
440 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
441 iopm_base = 0;
442 return r;
443 }
444
445 static __exit void svm_hardware_unsetup(void)
446 {
447 __free_pages(pfn_to_page(msrpm_base >> PAGE_SHIFT), MSRPM_ALLOC_ORDER);
448 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
449 iopm_base = msrpm_base = 0;
450 }
451
452 static void init_seg(struct vmcb_seg *seg)
453 {
454 seg->selector = 0;
455 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
456 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
457 seg->limit = 0xffff;
458 seg->base = 0;
459 }
460
461 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
462 {
463 seg->selector = 0;
464 seg->attrib = SVM_SELECTOR_P_MASK | type;
465 seg->limit = 0xffff;
466 seg->base = 0;
467 }
468
469 static void init_vmcb(struct vmcb *vmcb)
470 {
471 struct vmcb_control_area *control = &vmcb->control;
472 struct vmcb_save_area *save = &vmcb->save;
473
474 control->intercept_cr_read = INTERCEPT_CR0_MASK |
475 INTERCEPT_CR3_MASK |
476 INTERCEPT_CR4_MASK;
477
478 control->intercept_cr_write = INTERCEPT_CR0_MASK |
479 INTERCEPT_CR3_MASK |
480 INTERCEPT_CR4_MASK;
481
482 control->intercept_dr_read = INTERCEPT_DR0_MASK |
483 INTERCEPT_DR1_MASK |
484 INTERCEPT_DR2_MASK |
485 INTERCEPT_DR3_MASK;
486
487 control->intercept_dr_write = INTERCEPT_DR0_MASK |
488 INTERCEPT_DR1_MASK |
489 INTERCEPT_DR2_MASK |
490 INTERCEPT_DR3_MASK |
491 INTERCEPT_DR5_MASK |
492 INTERCEPT_DR7_MASK;
493
494 control->intercept_exceptions = 1 << PF_VECTOR;
495
496
497 control->intercept = (1ULL << INTERCEPT_INTR) |
498 (1ULL << INTERCEPT_NMI) |
499 (1ULL << INTERCEPT_SMI) |
500 /*
501 * selective cr0 intercept bug?
502 * 0: 0f 22 d8 mov %eax,%cr3
503 * 3: 0f 20 c0 mov %cr0,%eax
504 * 6: 0d 00 00 00 80 or $0x80000000,%eax
505 * b: 0f 22 c0 mov %eax,%cr0
506 * set cr3 ->interception
507 * get cr0 ->interception
508 * set cr0 -> no interception
509 */
510 /* (1ULL << INTERCEPT_SELECTIVE_CR0) | */
511 (1ULL << INTERCEPT_CPUID) |
512 (1ULL << INTERCEPT_HLT) |
513 (1ULL << INTERCEPT_INVLPGA) |
514 (1ULL << INTERCEPT_IOIO_PROT) |
515 (1ULL << INTERCEPT_MSR_PROT) |
516 (1ULL << INTERCEPT_TASK_SWITCH) |
517 (1ULL << INTERCEPT_SHUTDOWN) |
518 (1ULL << INTERCEPT_VMRUN) |
519 (1ULL << INTERCEPT_VMMCALL) |
520 (1ULL << INTERCEPT_VMLOAD) |
521 (1ULL << INTERCEPT_VMSAVE) |
522 (1ULL << INTERCEPT_STGI) |
523 (1ULL << INTERCEPT_CLGI) |
524 (1ULL << INTERCEPT_SKINIT) |
525 (1ULL << INTERCEPT_MONITOR) |
526 (1ULL << INTERCEPT_MWAIT);
527
528 control->iopm_base_pa = iopm_base;
529 control->msrpm_base_pa = msrpm_base;
530 control->tsc_offset = 0;
531 control->int_ctl = V_INTR_MASKING_MASK;
532
533 init_seg(&save->es);
534 init_seg(&save->ss);
535 init_seg(&save->ds);
536 init_seg(&save->fs);
537 init_seg(&save->gs);
538
539 save->cs.selector = 0xf000;
540 /* Executable/Readable Code Segment */
541 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
542 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
543 save->cs.limit = 0xffff;
544 /*
545 * cs.base should really be 0xffff0000, but vmx can't handle that, so
546 * be consistent with it.
547 *
548 * Replace when we have real mode working for vmx.
549 */
550 save->cs.base = 0xf0000;
551
552 save->gdtr.limit = 0xffff;
553 save->idtr.limit = 0xffff;
554
555 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
556 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
557
558 save->efer = MSR_EFER_SVME_MASK;
559
560 save->dr6 = 0xffff0ff0;
561 save->dr7 = 0x400;
562 save->rflags = 2;
563 save->rip = 0x0000fff0;
564
565 /*
566 * cr0 val on cpu init should be 0x60000010, we enable cpu
567 * cache by default. the orderly way is to enable cache in bios.
568 */
569 save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
570 save->cr4 = X86_CR4_PAE;
571 /* rdx = ?? */
572 }
573
574 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
575 {
576 struct vcpu_svm *svm;
577 struct page *page;
578 int err;
579
580 svm = kzalloc(sizeof *svm, GFP_KERNEL);
581 if (!svm) {
582 err = -ENOMEM;
583 goto out;
584 }
585
586 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
587 if (err)
588 goto free_svm;
589
590 page = alloc_page(GFP_KERNEL);
591 if (!page) {
592 err = -ENOMEM;
593 goto uninit;
594 }
595
596 svm->vmcb = page_address(page);
597 clear_page(svm->vmcb);
598 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
599 svm->asid_generation = 0;
600 memset(svm->db_regs, 0, sizeof(svm->db_regs));
601 init_vmcb(svm->vmcb);
602
603 fx_init(&svm->vcpu);
604 svm->vcpu.fpu_active = 1;
605 svm->vcpu.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
606 if (svm->vcpu.vcpu_id == 0)
607 svm->vcpu.apic_base |= MSR_IA32_APICBASE_BSP;
608
609 return &svm->vcpu;
610
611 uninit:
612 kvm_vcpu_uninit(&svm->vcpu);
613 free_svm:
614 kfree(svm);
615 out:
616 return ERR_PTR(err);
617 }
618
619 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
620 {
621 struct vcpu_svm *svm = to_svm(vcpu);
622
623 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
624 kvm_vcpu_uninit(vcpu);
625 kfree(svm);
626 }
627
628 static void svm_vcpu_load(struct kvm_vcpu *vcpu)
629 {
630 struct vcpu_svm *svm = to_svm(vcpu);
631 int cpu, i;
632
633 cpu = get_cpu();
634 if (unlikely(cpu != vcpu->cpu)) {
635 u64 tsc_this, delta;
636
637 /*
638 * Make sure that the guest sees a monotonically
639 * increasing TSC.
640 */
641 rdtscll(tsc_this);
642 delta = vcpu->host_tsc - tsc_this;
643 svm->vmcb->control.tsc_offset += delta;
644 vcpu->cpu = cpu;
645 }
646
647 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
648 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
649 }
650
651 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
652 {
653 struct vcpu_svm *svm = to_svm(vcpu);
654 int i;
655
656 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
657 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
658
659 rdtscll(vcpu->host_tsc);
660 put_cpu();
661 }
662
663 static void svm_vcpu_decache(struct kvm_vcpu *vcpu)
664 {
665 }
666
667 static void svm_cache_regs(struct kvm_vcpu *vcpu)
668 {
669 struct vcpu_svm *svm = to_svm(vcpu);
670
671 vcpu->regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
672 vcpu->regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
673 vcpu->rip = svm->vmcb->save.rip;
674 }
675
676 static void svm_decache_regs(struct kvm_vcpu *vcpu)
677 {
678 struct vcpu_svm *svm = to_svm(vcpu);
679 svm->vmcb->save.rax = vcpu->regs[VCPU_REGS_RAX];
680 svm->vmcb->save.rsp = vcpu->regs[VCPU_REGS_RSP];
681 svm->vmcb->save.rip = vcpu->rip;
682 }
683
684 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
685 {
686 return to_svm(vcpu)->vmcb->save.rflags;
687 }
688
689 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
690 {
691 to_svm(vcpu)->vmcb->save.rflags = rflags;
692 }
693
694 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
695 {
696 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
697
698 switch (seg) {
699 case VCPU_SREG_CS: return &save->cs;
700 case VCPU_SREG_DS: return &save->ds;
701 case VCPU_SREG_ES: return &save->es;
702 case VCPU_SREG_FS: return &save->fs;
703 case VCPU_SREG_GS: return &save->gs;
704 case VCPU_SREG_SS: return &save->ss;
705 case VCPU_SREG_TR: return &save->tr;
706 case VCPU_SREG_LDTR: return &save->ldtr;
707 }
708 BUG();
709 return NULL;
710 }
711
712 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
713 {
714 struct vmcb_seg *s = svm_seg(vcpu, seg);
715
716 return s->base;
717 }
718
719 static void svm_get_segment(struct kvm_vcpu *vcpu,
720 struct kvm_segment *var, int seg)
721 {
722 struct vmcb_seg *s = svm_seg(vcpu, seg);
723
724 var->base = s->base;
725 var->limit = s->limit;
726 var->selector = s->selector;
727 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
728 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
729 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
730 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
731 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
732 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
733 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
734 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
735 var->unusable = !var->present;
736 }
737
738 static void svm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
739 {
740 struct vmcb_seg *s = svm_seg(vcpu, VCPU_SREG_CS);
741
742 *db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
743 *l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
744 }
745
746 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
747 {
748 struct vcpu_svm *svm = to_svm(vcpu);
749
750 dt->limit = svm->vmcb->save.idtr.limit;
751 dt->base = svm->vmcb->save.idtr.base;
752 }
753
754 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
755 {
756 struct vcpu_svm *svm = to_svm(vcpu);
757
758 svm->vmcb->save.idtr.limit = dt->limit;
759 svm->vmcb->save.idtr.base = dt->base ;
760 }
761
762 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
763 {
764 struct vcpu_svm *svm = to_svm(vcpu);
765
766 dt->limit = svm->vmcb->save.gdtr.limit;
767 dt->base = svm->vmcb->save.gdtr.base;
768 }
769
770 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
771 {
772 struct vcpu_svm *svm = to_svm(vcpu);
773
774 svm->vmcb->save.gdtr.limit = dt->limit;
775 svm->vmcb->save.gdtr.base = dt->base ;
776 }
777
778 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
779 {
780 }
781
782 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
783 {
784 struct vcpu_svm *svm = to_svm(vcpu);
785
786 #ifdef CONFIG_X86_64
787 if (vcpu->shadow_efer & KVM_EFER_LME) {
788 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
789 vcpu->shadow_efer |= KVM_EFER_LMA;
790 svm->vmcb->save.efer |= KVM_EFER_LMA | KVM_EFER_LME;
791 }
792
793 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG) ) {
794 vcpu->shadow_efer &= ~KVM_EFER_LMA;
795 svm->vmcb->save.efer &= ~(KVM_EFER_LMA | KVM_EFER_LME);
796 }
797 }
798 #endif
799 if ((vcpu->cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
800 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
801 vcpu->fpu_active = 1;
802 }
803
804 vcpu->cr0 = cr0;
805 cr0 |= X86_CR0_PG | X86_CR0_WP;
806 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
807 svm->vmcb->save.cr0 = cr0;
808 }
809
810 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
811 {
812 vcpu->cr4 = cr4;
813 to_svm(vcpu)->vmcb->save.cr4 = cr4 | X86_CR4_PAE;
814 }
815
816 static void svm_set_segment(struct kvm_vcpu *vcpu,
817 struct kvm_segment *var, int seg)
818 {
819 struct vcpu_svm *svm = to_svm(vcpu);
820 struct vmcb_seg *s = svm_seg(vcpu, seg);
821
822 s->base = var->base;
823 s->limit = var->limit;
824 s->selector = var->selector;
825 if (var->unusable)
826 s->attrib = 0;
827 else {
828 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
829 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
830 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
831 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
832 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
833 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
834 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
835 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
836 }
837 if (seg == VCPU_SREG_CS)
838 svm->vmcb->save.cpl
839 = (svm->vmcb->save.cs.attrib
840 >> SVM_SELECTOR_DPL_SHIFT) & 3;
841
842 }
843
844 /* FIXME:
845
846 svm(vcpu)->vmcb->control.int_ctl &= ~V_TPR_MASK;
847 svm(vcpu)->vmcb->control.int_ctl |= (sregs->cr8 & V_TPR_MASK);
848
849 */
850
851 static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
852 {
853 return -EOPNOTSUPP;
854 }
855
856 static void load_host_msrs(struct kvm_vcpu *vcpu)
857 {
858 #ifdef CONFIG_X86_64
859 wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
860 #endif
861 }
862
863 static void save_host_msrs(struct kvm_vcpu *vcpu)
864 {
865 #ifdef CONFIG_X86_64
866 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
867 #endif
868 }
869
870 static void new_asid(struct kvm_vcpu *vcpu, struct svm_cpu_data *svm_data)
871 {
872 struct vcpu_svm *svm = to_svm(vcpu);
873
874 if (svm_data->next_asid > svm_data->max_asid) {
875 ++svm_data->asid_generation;
876 svm_data->next_asid = 1;
877 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
878 }
879
880 vcpu->cpu = svm_data->cpu;
881 svm->asid_generation = svm_data->asid_generation;
882 svm->vmcb->control.asid = svm_data->next_asid++;
883 }
884
885 static void svm_invlpg(struct kvm_vcpu *vcpu, gva_t address)
886 {
887 invlpga(address, to_svm(vcpu)->vmcb->control.asid); // is needed?
888 }
889
890 static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
891 {
892 return to_svm(vcpu)->db_regs[dr];
893 }
894
895 static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
896 int *exception)
897 {
898 struct vcpu_svm *svm = to_svm(vcpu);
899
900 *exception = 0;
901
902 if (svm->vmcb->save.dr7 & DR7_GD_MASK) {
903 svm->vmcb->save.dr7 &= ~DR7_GD_MASK;
904 svm->vmcb->save.dr6 |= DR6_BD_MASK;
905 *exception = DB_VECTOR;
906 return;
907 }
908
909 switch (dr) {
910 case 0 ... 3:
911 svm->db_regs[dr] = value;
912 return;
913 case 4 ... 5:
914 if (vcpu->cr4 & X86_CR4_DE) {
915 *exception = UD_VECTOR;
916 return;
917 }
918 case 7: {
919 if (value & ~((1ULL << 32) - 1)) {
920 *exception = GP_VECTOR;
921 return;
922 }
923 svm->vmcb->save.dr7 = value;
924 return;
925 }
926 default:
927 printk(KERN_DEBUG "%s: unexpected dr %u\n",
928 __FUNCTION__, dr);
929 *exception = UD_VECTOR;
930 return;
931 }
932 }
933
934 static int pf_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
935 {
936 struct vcpu_svm *svm = to_svm(vcpu);
937 u32 exit_int_info = svm->vmcb->control.exit_int_info;
938 u64 fault_address;
939 u32 error_code;
940 enum emulation_result er;
941 int r;
942
943 if (is_external_interrupt(exit_int_info))
944 push_irq(vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK);
945
946 spin_lock(&vcpu->kvm->lock);
947
948 fault_address = svm->vmcb->control.exit_info_2;
949 error_code = svm->vmcb->control.exit_info_1;
950 r = kvm_mmu_page_fault(vcpu, fault_address, error_code);
951 if (r < 0) {
952 spin_unlock(&vcpu->kvm->lock);
953 return r;
954 }
955 if (!r) {
956 spin_unlock(&vcpu->kvm->lock);
957 return 1;
958 }
959 er = emulate_instruction(vcpu, kvm_run, fault_address, error_code);
960 spin_unlock(&vcpu->kvm->lock);
961
962 switch (er) {
963 case EMULATE_DONE:
964 return 1;
965 case EMULATE_DO_MMIO:
966 ++vcpu->stat.mmio_exits;
967 return 0;
968 case EMULATE_FAIL:
969 vcpu_printf(vcpu, "%s: emulate fail\n", __FUNCTION__);
970 break;
971 default:
972 BUG();
973 }
974
975 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
976 return 0;
977 }
978
979 static int nm_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
980 {
981 struct vcpu_svm *svm = to_svm(vcpu);
982
983 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
984 if (!(vcpu->cr0 & X86_CR0_TS))
985 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
986 vcpu->fpu_active = 1;
987
988 return 1;
989 }
990
991 static int shutdown_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
992 {
993 struct vcpu_svm *svm = to_svm(vcpu);
994 /*
995 * VMCB is undefined after a SHUTDOWN intercept
996 * so reinitialize it.
997 */
998 clear_page(svm->vmcb);
999 init_vmcb(svm->vmcb);
1000
1001 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1002 return 0;
1003 }
1004
1005 static int io_get_override(struct kvm_vcpu *vcpu,
1006 struct vmcb_seg **seg,
1007 int *addr_override)
1008 {
1009 struct vcpu_svm *svm = to_svm(vcpu);
1010 u8 inst[MAX_INST_SIZE];
1011 unsigned ins_length;
1012 gva_t rip;
1013 int i;
1014
1015 rip = svm->vmcb->save.rip;
1016 ins_length = svm->next_rip - rip;
1017 rip += svm->vmcb->save.cs.base;
1018
1019 if (ins_length > MAX_INST_SIZE)
1020 printk(KERN_DEBUG
1021 "%s: inst length err, cs base 0x%llx rip 0x%llx "
1022 "next rip 0x%llx ins_length %u\n",
1023 __FUNCTION__,
1024 svm->vmcb->save.cs.base,
1025 svm->vmcb->save.rip,
1026 svm->vmcb->control.exit_info_2,
1027 ins_length);
1028
1029 if (kvm_read_guest(vcpu, rip, ins_length, inst) != ins_length)
1030 /* #PF */
1031 return 0;
1032
1033 *addr_override = 0;
1034 *seg = NULL;
1035 for (i = 0; i < ins_length; i++)
1036 switch (inst[i]) {
1037 case 0xf0:
1038 case 0xf2:
1039 case 0xf3:
1040 case 0x66:
1041 continue;
1042 case 0x67:
1043 *addr_override = 1;
1044 continue;
1045 case 0x2e:
1046 *seg = &svm->vmcb->save.cs;
1047 continue;
1048 case 0x36:
1049 *seg = &svm->vmcb->save.ss;
1050 continue;
1051 case 0x3e:
1052 *seg = &svm->vmcb->save.ds;
1053 continue;
1054 case 0x26:
1055 *seg = &svm->vmcb->save.es;
1056 continue;
1057 case 0x64:
1058 *seg = &svm->vmcb->save.fs;
1059 continue;
1060 case 0x65:
1061 *seg = &svm->vmcb->save.gs;
1062 continue;
1063 default:
1064 return 1;
1065 }
1066 printk(KERN_DEBUG "%s: unexpected\n", __FUNCTION__);
1067 return 0;
1068 }
1069
1070 static unsigned long io_adress(struct kvm_vcpu *vcpu, int ins, gva_t *address)
1071 {
1072 unsigned long addr_mask;
1073 unsigned long *reg;
1074 struct vmcb_seg *seg;
1075 int addr_override;
1076 struct vcpu_svm *svm = to_svm(vcpu);
1077 struct vmcb_save_area *save_area = &svm->vmcb->save;
1078 u16 cs_attrib = save_area->cs.attrib;
1079 unsigned addr_size = get_addr_size(vcpu);
1080
1081 if (!io_get_override(vcpu, &seg, &addr_override))
1082 return 0;
1083
1084 if (addr_override)
1085 addr_size = (addr_size == 2) ? 4: (addr_size >> 1);
1086
1087 if (ins) {
1088 reg = &vcpu->regs[VCPU_REGS_RDI];
1089 seg = &svm->vmcb->save.es;
1090 } else {
1091 reg = &vcpu->regs[VCPU_REGS_RSI];
1092 seg = (seg) ? seg : &svm->vmcb->save.ds;
1093 }
1094
1095 addr_mask = ~0ULL >> (64 - (addr_size * 8));
1096
1097 if ((cs_attrib & SVM_SELECTOR_L_MASK) &&
1098 !(svm->vmcb->save.rflags & X86_EFLAGS_VM)) {
1099 *address = (*reg & addr_mask);
1100 return addr_mask;
1101 }
1102
1103 if (!(seg->attrib & SVM_SELECTOR_P_SHIFT)) {
1104 svm_inject_gp(vcpu, 0);
1105 return 0;
1106 }
1107
1108 *address = (*reg & addr_mask) + seg->base;
1109 return addr_mask;
1110 }
1111
1112 static int io_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1113 {
1114 struct vcpu_svm *svm = to_svm(vcpu);
1115 u32 io_info = svm->vmcb->control.exit_info_1; //address size bug?
1116 int size, down, in, string, rep;
1117 unsigned port;
1118 unsigned long count;
1119 gva_t address = 0;
1120
1121 ++vcpu->stat.io_exits;
1122
1123 svm->next_rip = svm->vmcb->control.exit_info_2;
1124
1125 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1126 port = io_info >> 16;
1127 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1128 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1129 rep = (io_info & SVM_IOIO_REP_MASK) != 0;
1130 count = 1;
1131 down = (svm->vmcb->save.rflags & X86_EFLAGS_DF) != 0;
1132
1133 if (string) {
1134 unsigned addr_mask;
1135
1136 addr_mask = io_adress(vcpu, in, &address);
1137 if (!addr_mask) {
1138 printk(KERN_DEBUG "%s: get io address failed\n",
1139 __FUNCTION__);
1140 return 1;
1141 }
1142
1143 if (rep)
1144 count = vcpu->regs[VCPU_REGS_RCX] & addr_mask;
1145 }
1146 return kvm_setup_pio(vcpu, kvm_run, in, size, count, string, down,
1147 address, rep, port);
1148 }
1149
1150 static int nop_on_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1151 {
1152 return 1;
1153 }
1154
1155 static int halt_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1156 {
1157 struct vcpu_svm *svm = to_svm(vcpu);
1158
1159 svm->next_rip = svm->vmcb->save.rip + 1;
1160 skip_emulated_instruction(vcpu);
1161 return kvm_emulate_halt(vcpu);
1162 }
1163
1164 static int vmmcall_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1165 {
1166 struct vcpu_svm *svm = to_svm(vcpu);
1167
1168 svm->next_rip = svm->vmcb->save.rip + 3;
1169 skip_emulated_instruction(vcpu);
1170 return kvm_hypercall(vcpu, kvm_run);
1171 }
1172
1173 static int invalid_op_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1174 {
1175 inject_ud(vcpu);
1176 return 1;
1177 }
1178
1179 static int task_switch_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1180 {
1181 printk(KERN_DEBUG "%s: task swiche is unsupported\n", __FUNCTION__);
1182 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1183 return 0;
1184 }
1185
1186 static int cpuid_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1187 {
1188 struct vcpu_svm *svm = to_svm(vcpu);
1189
1190 svm->next_rip = svm->vmcb->save.rip + 2;
1191 kvm_emulate_cpuid(vcpu);
1192 return 1;
1193 }
1194
1195 static int emulate_on_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1196 {
1197 if (emulate_instruction(vcpu, NULL, 0, 0) != EMULATE_DONE)
1198 printk(KERN_ERR "%s: failed\n", __FUNCTION__);
1199 return 1;
1200 }
1201
1202 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
1203 {
1204 struct vcpu_svm *svm = to_svm(vcpu);
1205
1206 switch (ecx) {
1207 case MSR_IA32_TIME_STAMP_COUNTER: {
1208 u64 tsc;
1209
1210 rdtscll(tsc);
1211 *data = svm->vmcb->control.tsc_offset + tsc;
1212 break;
1213 }
1214 case MSR_K6_STAR:
1215 *data = svm->vmcb->save.star;
1216 break;
1217 #ifdef CONFIG_X86_64
1218 case MSR_LSTAR:
1219 *data = svm->vmcb->save.lstar;
1220 break;
1221 case MSR_CSTAR:
1222 *data = svm->vmcb->save.cstar;
1223 break;
1224 case MSR_KERNEL_GS_BASE:
1225 *data = svm->vmcb->save.kernel_gs_base;
1226 break;
1227 case MSR_SYSCALL_MASK:
1228 *data = svm->vmcb->save.sfmask;
1229 break;
1230 #endif
1231 case MSR_IA32_SYSENTER_CS:
1232 *data = svm->vmcb->save.sysenter_cs;
1233 break;
1234 case MSR_IA32_SYSENTER_EIP:
1235 *data = svm->vmcb->save.sysenter_eip;
1236 break;
1237 case MSR_IA32_SYSENTER_ESP:
1238 *data = svm->vmcb->save.sysenter_esp;
1239 break;
1240 default:
1241 return kvm_get_msr_common(vcpu, ecx, data);
1242 }
1243 return 0;
1244 }
1245
1246 static int rdmsr_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1247 {
1248 struct vcpu_svm *svm = to_svm(vcpu);
1249 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
1250 u64 data;
1251
1252 if (svm_get_msr(vcpu, ecx, &data))
1253 svm_inject_gp(vcpu, 0);
1254 else {
1255 svm->vmcb->save.rax = data & 0xffffffff;
1256 vcpu->regs[VCPU_REGS_RDX] = data >> 32;
1257 svm->next_rip = svm->vmcb->save.rip + 2;
1258 skip_emulated_instruction(vcpu);
1259 }
1260 return 1;
1261 }
1262
1263 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
1264 {
1265 struct vcpu_svm *svm = to_svm(vcpu);
1266
1267 switch (ecx) {
1268 case MSR_IA32_TIME_STAMP_COUNTER: {
1269 u64 tsc;
1270
1271 rdtscll(tsc);
1272 svm->vmcb->control.tsc_offset = data - tsc;
1273 break;
1274 }
1275 case MSR_K6_STAR:
1276 svm->vmcb->save.star = data;
1277 break;
1278 #ifdef CONFIG_X86_64
1279 case MSR_LSTAR:
1280 svm->vmcb->save.lstar = data;
1281 break;
1282 case MSR_CSTAR:
1283 svm->vmcb->save.cstar = data;
1284 break;
1285 case MSR_KERNEL_GS_BASE:
1286 svm->vmcb->save.kernel_gs_base = data;
1287 break;
1288 case MSR_SYSCALL_MASK:
1289 svm->vmcb->save.sfmask = data;
1290 break;
1291 #endif
1292 case MSR_IA32_SYSENTER_CS:
1293 svm->vmcb->save.sysenter_cs = data;
1294 break;
1295 case MSR_IA32_SYSENTER_EIP:
1296 svm->vmcb->save.sysenter_eip = data;
1297 break;
1298 case MSR_IA32_SYSENTER_ESP:
1299 svm->vmcb->save.sysenter_esp = data;
1300 break;
1301 default:
1302 return kvm_set_msr_common(vcpu, ecx, data);
1303 }
1304 return 0;
1305 }
1306
1307 static int wrmsr_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1308 {
1309 struct vcpu_svm *svm = to_svm(vcpu);
1310 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
1311 u64 data = (svm->vmcb->save.rax & -1u)
1312 | ((u64)(vcpu->regs[VCPU_REGS_RDX] & -1u) << 32);
1313 svm->next_rip = svm->vmcb->save.rip + 2;
1314 if (svm_set_msr(vcpu, ecx, data))
1315 svm_inject_gp(vcpu, 0);
1316 else
1317 skip_emulated_instruction(vcpu);
1318 return 1;
1319 }
1320
1321 static int msr_interception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1322 {
1323 if (to_svm(vcpu)->vmcb->control.exit_info_1)
1324 return wrmsr_interception(vcpu, kvm_run);
1325 else
1326 return rdmsr_interception(vcpu, kvm_run);
1327 }
1328
1329 static int interrupt_window_interception(struct kvm_vcpu *vcpu,
1330 struct kvm_run *kvm_run)
1331 {
1332 /*
1333 * If the user space waits to inject interrupts, exit as soon as
1334 * possible
1335 */
1336 if (kvm_run->request_interrupt_window &&
1337 !vcpu->irq_summary) {
1338 ++vcpu->stat.irq_window_exits;
1339 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
1340 return 0;
1341 }
1342
1343 return 1;
1344 }
1345
1346 static int (*svm_exit_handlers[])(struct kvm_vcpu *vcpu,
1347 struct kvm_run *kvm_run) = {
1348 [SVM_EXIT_READ_CR0] = emulate_on_interception,
1349 [SVM_EXIT_READ_CR3] = emulate_on_interception,
1350 [SVM_EXIT_READ_CR4] = emulate_on_interception,
1351 /* for now: */
1352 [SVM_EXIT_WRITE_CR0] = emulate_on_interception,
1353 [SVM_EXIT_WRITE_CR3] = emulate_on_interception,
1354 [SVM_EXIT_WRITE_CR4] = emulate_on_interception,
1355 [SVM_EXIT_READ_DR0] = emulate_on_interception,
1356 [SVM_EXIT_READ_DR1] = emulate_on_interception,
1357 [SVM_EXIT_READ_DR2] = emulate_on_interception,
1358 [SVM_EXIT_READ_DR3] = emulate_on_interception,
1359 [SVM_EXIT_WRITE_DR0] = emulate_on_interception,
1360 [SVM_EXIT_WRITE_DR1] = emulate_on_interception,
1361 [SVM_EXIT_WRITE_DR2] = emulate_on_interception,
1362 [SVM_EXIT_WRITE_DR3] = emulate_on_interception,
1363 [SVM_EXIT_WRITE_DR5] = emulate_on_interception,
1364 [SVM_EXIT_WRITE_DR7] = emulate_on_interception,
1365 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
1366 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
1367 [SVM_EXIT_INTR] = nop_on_interception,
1368 [SVM_EXIT_NMI] = nop_on_interception,
1369 [SVM_EXIT_SMI] = nop_on_interception,
1370 [SVM_EXIT_INIT] = nop_on_interception,
1371 [SVM_EXIT_VINTR] = interrupt_window_interception,
1372 /* [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception, */
1373 [SVM_EXIT_CPUID] = cpuid_interception,
1374 [SVM_EXIT_HLT] = halt_interception,
1375 [SVM_EXIT_INVLPG] = emulate_on_interception,
1376 [SVM_EXIT_INVLPGA] = invalid_op_interception,
1377 [SVM_EXIT_IOIO] = io_interception,
1378 [SVM_EXIT_MSR] = msr_interception,
1379 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
1380 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
1381 [SVM_EXIT_VMRUN] = invalid_op_interception,
1382 [SVM_EXIT_VMMCALL] = vmmcall_interception,
1383 [SVM_EXIT_VMLOAD] = invalid_op_interception,
1384 [SVM_EXIT_VMSAVE] = invalid_op_interception,
1385 [SVM_EXIT_STGI] = invalid_op_interception,
1386 [SVM_EXIT_CLGI] = invalid_op_interception,
1387 [SVM_EXIT_SKINIT] = invalid_op_interception,
1388 [SVM_EXIT_MONITOR] = invalid_op_interception,
1389 [SVM_EXIT_MWAIT] = invalid_op_interception,
1390 };
1391
1392
1393 static int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1394 {
1395 struct vcpu_svm *svm = to_svm(vcpu);
1396 u32 exit_code = svm->vmcb->control.exit_code;
1397
1398 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
1399 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR)
1400 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
1401 "exit_code 0x%x\n",
1402 __FUNCTION__, svm->vmcb->control.exit_int_info,
1403 exit_code);
1404
1405 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
1406 || svm_exit_handlers[exit_code] == 0) {
1407 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1408 kvm_run->hw.hardware_exit_reason = exit_code;
1409 return 0;
1410 }
1411
1412 return svm_exit_handlers[exit_code](vcpu, kvm_run);
1413 }
1414
1415 static void reload_tss(struct kvm_vcpu *vcpu)
1416 {
1417 int cpu = raw_smp_processor_id();
1418
1419 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1420 svm_data->tss_desc->type = 9; //available 32/64-bit TSS
1421 load_TR_desc();
1422 }
1423
1424 static void pre_svm_run(struct kvm_vcpu *vcpu)
1425 {
1426 struct vcpu_svm *svm = to_svm(vcpu);
1427 int cpu = raw_smp_processor_id();
1428
1429 struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1430
1431 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
1432 if (vcpu->cpu != cpu ||
1433 svm->asid_generation != svm_data->asid_generation)
1434 new_asid(vcpu, svm_data);
1435 }
1436
1437
1438 static inline void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
1439 {
1440 struct vmcb_control_area *control;
1441
1442 control = &to_svm(vcpu)->vmcb->control;
1443 control->int_vector = pop_irq(vcpu);
1444 control->int_ctl &= ~V_INTR_PRIO_MASK;
1445 control->int_ctl |= V_IRQ_MASK |
1446 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1447 }
1448
1449 static void kvm_reput_irq(struct kvm_vcpu *vcpu)
1450 {
1451 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
1452
1453 if (control->int_ctl & V_IRQ_MASK) {
1454 control->int_ctl &= ~V_IRQ_MASK;
1455 push_irq(vcpu, control->int_vector);
1456 }
1457
1458 vcpu->interrupt_window_open =
1459 !(control->int_state & SVM_INTERRUPT_SHADOW_MASK);
1460 }
1461
1462 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1463 struct kvm_run *kvm_run)
1464 {
1465 struct vcpu_svm *svm = to_svm(vcpu);
1466 struct vmcb_control_area *control = &svm->vmcb->control;
1467
1468 vcpu->interrupt_window_open =
1469 (!(control->int_state & SVM_INTERRUPT_SHADOW_MASK) &&
1470 (svm->vmcb->save.rflags & X86_EFLAGS_IF));
1471
1472 if (vcpu->interrupt_window_open && vcpu->irq_summary)
1473 /*
1474 * If interrupts enabled, and not blocked by sti or mov ss. Good.
1475 */
1476 kvm_do_inject_irq(vcpu);
1477
1478 /*
1479 * Interrupts blocked. Wait for unblock.
1480 */
1481 if (!vcpu->interrupt_window_open &&
1482 (vcpu->irq_summary || kvm_run->request_interrupt_window)) {
1483 control->intercept |= 1ULL << INTERCEPT_VINTR;
1484 } else
1485 control->intercept &= ~(1ULL << INTERCEPT_VINTR);
1486 }
1487
1488 static void post_kvm_run_save(struct kvm_vcpu *vcpu,
1489 struct kvm_run *kvm_run)
1490 {
1491 struct vcpu_svm *svm = to_svm(vcpu);
1492
1493 kvm_run->ready_for_interrupt_injection = (vcpu->interrupt_window_open &&
1494 vcpu->irq_summary == 0);
1495 kvm_run->if_flag = (svm->vmcb->save.rflags & X86_EFLAGS_IF) != 0;
1496 kvm_run->cr8 = vcpu->cr8;
1497 kvm_run->apic_base = vcpu->apic_base;
1498 }
1499
1500 /*
1501 * Check if userspace requested an interrupt window, and that the
1502 * interrupt window is open.
1503 *
1504 * No need to exit to userspace if we already have an interrupt queued.
1505 */
1506 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu,
1507 struct kvm_run *kvm_run)
1508 {
1509 return (!vcpu->irq_summary &&
1510 kvm_run->request_interrupt_window &&
1511 vcpu->interrupt_window_open &&
1512 (to_svm(vcpu)->vmcb->save.rflags & X86_EFLAGS_IF));
1513 }
1514
1515 static void save_db_regs(unsigned long *db_regs)
1516 {
1517 asm volatile ("mov %%dr0, %0" : "=r"(db_regs[0]));
1518 asm volatile ("mov %%dr1, %0" : "=r"(db_regs[1]));
1519 asm volatile ("mov %%dr2, %0" : "=r"(db_regs[2]));
1520 asm volatile ("mov %%dr3, %0" : "=r"(db_regs[3]));
1521 }
1522
1523 static void load_db_regs(unsigned long *db_regs)
1524 {
1525 asm volatile ("mov %0, %%dr0" : : "r"(db_regs[0]));
1526 asm volatile ("mov %0, %%dr1" : : "r"(db_regs[1]));
1527 asm volatile ("mov %0, %%dr2" : : "r"(db_regs[2]));
1528 asm volatile ("mov %0, %%dr3" : : "r"(db_regs[3]));
1529 }
1530
1531 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
1532 {
1533 force_new_asid(vcpu);
1534 }
1535
1536 static int svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1537 {
1538 struct vcpu_svm *svm = to_svm(vcpu);
1539 u16 fs_selector;
1540 u16 gs_selector;
1541 u16 ldt_selector;
1542 int r;
1543
1544 again:
1545 r = kvm_mmu_reload(vcpu);
1546 if (unlikely(r))
1547 return r;
1548
1549 if (!vcpu->mmio_read_completed)
1550 do_interrupt_requests(vcpu, kvm_run);
1551
1552 clgi();
1553
1554 vcpu->guest_mode = 1;
1555 if (vcpu->requests)
1556 if (test_and_clear_bit(KVM_TLB_FLUSH, &vcpu->requests))
1557 svm_flush_tlb(vcpu);
1558
1559 pre_svm_run(vcpu);
1560
1561 save_host_msrs(vcpu);
1562 fs_selector = read_fs();
1563 gs_selector = read_gs();
1564 ldt_selector = read_ldt();
1565 svm->host_cr2 = kvm_read_cr2();
1566 svm->host_dr6 = read_dr6();
1567 svm->host_dr7 = read_dr7();
1568 svm->vmcb->save.cr2 = vcpu->cr2;
1569
1570 if (svm->vmcb->save.dr7 & 0xff) {
1571 write_dr7(0);
1572 save_db_regs(svm->host_db_regs);
1573 load_db_regs(svm->db_regs);
1574 }
1575
1576 if (vcpu->fpu_active) {
1577 fx_save(vcpu->host_fx_image);
1578 fx_restore(vcpu->guest_fx_image);
1579 }
1580
1581 asm volatile (
1582 #ifdef CONFIG_X86_64
1583 "push %%rbx; push %%rcx; push %%rdx;"
1584 "push %%rsi; push %%rdi; push %%rbp;"
1585 "push %%r8; push %%r9; push %%r10; push %%r11;"
1586 "push %%r12; push %%r13; push %%r14; push %%r15;"
1587 #else
1588 "push %%ebx; push %%ecx; push %%edx;"
1589 "push %%esi; push %%edi; push %%ebp;"
1590 #endif
1591
1592 #ifdef CONFIG_X86_64
1593 "mov %c[rbx](%[svm]), %%rbx \n\t"
1594 "mov %c[rcx](%[svm]), %%rcx \n\t"
1595 "mov %c[rdx](%[svm]), %%rdx \n\t"
1596 "mov %c[rsi](%[svm]), %%rsi \n\t"
1597 "mov %c[rdi](%[svm]), %%rdi \n\t"
1598 "mov %c[rbp](%[svm]), %%rbp \n\t"
1599 "mov %c[r8](%[svm]), %%r8 \n\t"
1600 "mov %c[r9](%[svm]), %%r9 \n\t"
1601 "mov %c[r10](%[svm]), %%r10 \n\t"
1602 "mov %c[r11](%[svm]), %%r11 \n\t"
1603 "mov %c[r12](%[svm]), %%r12 \n\t"
1604 "mov %c[r13](%[svm]), %%r13 \n\t"
1605 "mov %c[r14](%[svm]), %%r14 \n\t"
1606 "mov %c[r15](%[svm]), %%r15 \n\t"
1607 #else
1608 "mov %c[rbx](%[svm]), %%ebx \n\t"
1609 "mov %c[rcx](%[svm]), %%ecx \n\t"
1610 "mov %c[rdx](%[svm]), %%edx \n\t"
1611 "mov %c[rsi](%[svm]), %%esi \n\t"
1612 "mov %c[rdi](%[svm]), %%edi \n\t"
1613 "mov %c[rbp](%[svm]), %%ebp \n\t"
1614 #endif
1615
1616 #ifdef CONFIG_X86_64
1617 /* Enter guest mode */
1618 "push %%rax \n\t"
1619 "mov %c[vmcb](%[svm]), %%rax \n\t"
1620 SVM_VMLOAD "\n\t"
1621 SVM_VMRUN "\n\t"
1622 SVM_VMSAVE "\n\t"
1623 "pop %%rax \n\t"
1624 #else
1625 /* Enter guest mode */
1626 "push %%eax \n\t"
1627 "mov %c[vmcb](%[svm]), %%eax \n\t"
1628 SVM_VMLOAD "\n\t"
1629 SVM_VMRUN "\n\t"
1630 SVM_VMSAVE "\n\t"
1631 "pop %%eax \n\t"
1632 #endif
1633
1634 /* Save guest registers, load host registers */
1635 #ifdef CONFIG_X86_64
1636 "mov %%rbx, %c[rbx](%[svm]) \n\t"
1637 "mov %%rcx, %c[rcx](%[svm]) \n\t"
1638 "mov %%rdx, %c[rdx](%[svm]) \n\t"
1639 "mov %%rsi, %c[rsi](%[svm]) \n\t"
1640 "mov %%rdi, %c[rdi](%[svm]) \n\t"
1641 "mov %%rbp, %c[rbp](%[svm]) \n\t"
1642 "mov %%r8, %c[r8](%[svm]) \n\t"
1643 "mov %%r9, %c[r9](%[svm]) \n\t"
1644 "mov %%r10, %c[r10](%[svm]) \n\t"
1645 "mov %%r11, %c[r11](%[svm]) \n\t"
1646 "mov %%r12, %c[r12](%[svm]) \n\t"
1647 "mov %%r13, %c[r13](%[svm]) \n\t"
1648 "mov %%r14, %c[r14](%[svm]) \n\t"
1649 "mov %%r15, %c[r15](%[svm]) \n\t"
1650
1651 "pop %%r15; pop %%r14; pop %%r13; pop %%r12;"
1652 "pop %%r11; pop %%r10; pop %%r9; pop %%r8;"
1653 "pop %%rbp; pop %%rdi; pop %%rsi;"
1654 "pop %%rdx; pop %%rcx; pop %%rbx; \n\t"
1655 #else
1656 "mov %%ebx, %c[rbx](%[svm]) \n\t"
1657 "mov %%ecx, %c[rcx](%[svm]) \n\t"
1658 "mov %%edx, %c[rdx](%[svm]) \n\t"
1659 "mov %%esi, %c[rsi](%[svm]) \n\t"
1660 "mov %%edi, %c[rdi](%[svm]) \n\t"
1661 "mov %%ebp, %c[rbp](%[svm]) \n\t"
1662
1663 "pop %%ebp; pop %%edi; pop %%esi;"
1664 "pop %%edx; pop %%ecx; pop %%ebx; \n\t"
1665 #endif
1666 :
1667 : [svm]"a"(svm),
1668 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
1669 [rbx]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RBX])),
1670 [rcx]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RCX])),
1671 [rdx]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RDX])),
1672 [rsi]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RSI])),
1673 [rdi]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RDI])),
1674 [rbp]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RBP]))
1675 #ifdef CONFIG_X86_64
1676 ,[r8 ]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R8])),
1677 [r9 ]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R9 ])),
1678 [r10]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R10])),
1679 [r11]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R11])),
1680 [r12]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R12])),
1681 [r13]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R13])),
1682 [r14]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R14])),
1683 [r15]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R15]))
1684 #endif
1685 : "cc", "memory" );
1686
1687 vcpu->guest_mode = 0;
1688
1689 if (vcpu->fpu_active) {
1690 fx_save(vcpu->guest_fx_image);
1691 fx_restore(vcpu->host_fx_image);
1692 }
1693
1694 if ((svm->vmcb->save.dr7 & 0xff))
1695 load_db_regs(svm->host_db_regs);
1696
1697 vcpu->cr2 = svm->vmcb->save.cr2;
1698
1699 write_dr6(svm->host_dr6);
1700 write_dr7(svm->host_dr7);
1701 kvm_write_cr2(svm->host_cr2);
1702
1703 load_fs(fs_selector);
1704 load_gs(gs_selector);
1705 load_ldt(ldt_selector);
1706 load_host_msrs(vcpu);
1707
1708 reload_tss(vcpu);
1709
1710 /*
1711 * Profile KVM exit RIPs:
1712 */
1713 if (unlikely(prof_on == KVM_PROFILING))
1714 profile_hit(KVM_PROFILING,
1715 (void *)(unsigned long)svm->vmcb->save.rip);
1716
1717 stgi();
1718
1719 kvm_reput_irq(vcpu);
1720
1721 svm->next_rip = 0;
1722
1723 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
1724 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
1725 kvm_run->fail_entry.hardware_entry_failure_reason
1726 = svm->vmcb->control.exit_code;
1727 post_kvm_run_save(vcpu, kvm_run);
1728 return 0;
1729 }
1730
1731 r = handle_exit(vcpu, kvm_run);
1732 if (r > 0) {
1733 if (signal_pending(current)) {
1734 ++vcpu->stat.signal_exits;
1735 post_kvm_run_save(vcpu, kvm_run);
1736 kvm_run->exit_reason = KVM_EXIT_INTR;
1737 return -EINTR;
1738 }
1739
1740 if (dm_request_for_irq_injection(vcpu, kvm_run)) {
1741 ++vcpu->stat.request_irq_exits;
1742 post_kvm_run_save(vcpu, kvm_run);
1743 kvm_run->exit_reason = KVM_EXIT_INTR;
1744 return -EINTR;
1745 }
1746 kvm_resched(vcpu);
1747 goto again;
1748 }
1749 post_kvm_run_save(vcpu, kvm_run);
1750 return r;
1751 }
1752
1753 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
1754 {
1755 struct vcpu_svm *svm = to_svm(vcpu);
1756
1757 svm->vmcb->save.cr3 = root;
1758 force_new_asid(vcpu);
1759
1760 if (vcpu->fpu_active) {
1761 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
1762 svm->vmcb->save.cr0 |= X86_CR0_TS;
1763 vcpu->fpu_active = 0;
1764 }
1765 }
1766
1767 static void svm_inject_page_fault(struct kvm_vcpu *vcpu,
1768 unsigned long addr,
1769 uint32_t err_code)
1770 {
1771 struct vcpu_svm *svm = to_svm(vcpu);
1772 uint32_t exit_int_info = svm->vmcb->control.exit_int_info;
1773
1774 ++vcpu->stat.pf_guest;
1775
1776 if (is_page_fault(exit_int_info)) {
1777
1778 svm->vmcb->control.event_inj_err = 0;
1779 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID |
1780 SVM_EVTINJ_VALID_ERR |
1781 SVM_EVTINJ_TYPE_EXEPT |
1782 DF_VECTOR;
1783 return;
1784 }
1785 vcpu->cr2 = addr;
1786 svm->vmcb->save.cr2 = addr;
1787 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID |
1788 SVM_EVTINJ_VALID_ERR |
1789 SVM_EVTINJ_TYPE_EXEPT |
1790 PF_VECTOR;
1791 svm->vmcb->control.event_inj_err = err_code;
1792 }
1793
1794
1795 static int is_disabled(void)
1796 {
1797 u64 vm_cr;
1798
1799 rdmsrl(MSR_VM_CR, vm_cr);
1800 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
1801 return 1;
1802
1803 return 0;
1804 }
1805
1806 static void
1807 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
1808 {
1809 /*
1810 * Patch in the VMMCALL instruction:
1811 */
1812 hypercall[0] = 0x0f;
1813 hypercall[1] = 0x01;
1814 hypercall[2] = 0xd9;
1815 hypercall[3] = 0xc3;
1816 }
1817
1818 static struct kvm_arch_ops svm_arch_ops = {
1819 .cpu_has_kvm_support = has_svm,
1820 .disabled_by_bios = is_disabled,
1821 .hardware_setup = svm_hardware_setup,
1822 .hardware_unsetup = svm_hardware_unsetup,
1823 .hardware_enable = svm_hardware_enable,
1824 .hardware_disable = svm_hardware_disable,
1825
1826 .vcpu_create = svm_create_vcpu,
1827 .vcpu_free = svm_free_vcpu,
1828
1829 .vcpu_load = svm_vcpu_load,
1830 .vcpu_put = svm_vcpu_put,
1831 .vcpu_decache = svm_vcpu_decache,
1832
1833 .set_guest_debug = svm_guest_debug,
1834 .get_msr = svm_get_msr,
1835 .set_msr = svm_set_msr,
1836 .get_segment_base = svm_get_segment_base,
1837 .get_segment = svm_get_segment,
1838 .set_segment = svm_set_segment,
1839 .get_cs_db_l_bits = svm_get_cs_db_l_bits,
1840 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
1841 .set_cr0 = svm_set_cr0,
1842 .set_cr3 = svm_set_cr3,
1843 .set_cr4 = svm_set_cr4,
1844 .set_efer = svm_set_efer,
1845 .get_idt = svm_get_idt,
1846 .set_idt = svm_set_idt,
1847 .get_gdt = svm_get_gdt,
1848 .set_gdt = svm_set_gdt,
1849 .get_dr = svm_get_dr,
1850 .set_dr = svm_set_dr,
1851 .cache_regs = svm_cache_regs,
1852 .decache_regs = svm_decache_regs,
1853 .get_rflags = svm_get_rflags,
1854 .set_rflags = svm_set_rflags,
1855
1856 .invlpg = svm_invlpg,
1857 .tlb_flush = svm_flush_tlb,
1858 .inject_page_fault = svm_inject_page_fault,
1859
1860 .inject_gp = svm_inject_gp,
1861
1862 .run = svm_vcpu_run,
1863 .skip_emulated_instruction = skip_emulated_instruction,
1864 .patch_hypercall = svm_patch_hypercall,
1865 };
1866
1867 static int __init svm_init(void)
1868 {
1869 return kvm_init_arch(&svm_arch_ops, THIS_MODULE);
1870 }
1871
1872 static void __exit svm_exit(void)
1873 {
1874 kvm_exit_arch();
1875 }
1876
1877 module_init(svm_init)
1878 module_exit(svm_exit)
kernel-based virtual machine