2 * PCI / PCI-X / PCI-Express support for 4xx parts
4 * Copyright 2007 Ben. Herrenschmidt <benh@kernel.crashing.org>, IBM Corp.
6 * Most PCI Express code is coming from Stefan Roese implementation for
7 * arch/ppc in the Denx tree, slightly reworked by me.
9 * Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de>
11 * Some of that comes itself from a previous implementation for 440SPE only
14 * Copyright (c) 2005 Cisco Systems. All rights reserved.
15 * Roland Dreier <rolandd@cisco.com>
21 #include <linux/kernel.h>
22 #include <linux/pci.h>
23 #include <linux/init.h>
25 #include <linux/bootmem.h>
26 #include <linux/delay.h>
29 #include <asm/pci-bridge.h>
30 #include <asm/machdep.h>
32 #include <asm/dcr-regs.h>
33 #include <mm/mmu_decl.h>
35 #include "ppc4xx_pci.h"
37 static int dma_offset_set
;
39 #define U64_TO_U32_LOW(val) ((u32)((val) & 0x00000000ffffffffULL))
40 #define U64_TO_U32_HIGH(val) ((u32)((val) >> 32))
42 #define RES_TO_U32_LOW(val) \
43 ((sizeof(resource_size_t) > sizeof(u32)) ? U64_TO_U32_LOW(val) : (val))
44 #define RES_TO_U32_HIGH(val) \
45 ((sizeof(resource_size_t) > sizeof(u32)) ? U64_TO_U32_HIGH(val) : (0))
47 static inline int ppc440spe_revA(void)
49 /* Catch both 440SPe variants, with and without RAID6 support */
50 if ((mfspr(SPRN_PVR
) & 0xffefffff) == 0x53421890)
56 static void fixup_ppc4xx_pci_bridge(struct pci_dev
*dev
)
58 struct pci_controller
*hose
;
61 if (dev
->devfn
!= 0 || dev
->bus
->self
!= NULL
)
64 hose
= pci_bus_to_host(dev
->bus
);
68 if (!of_device_is_compatible(hose
->dn
, "ibm,plb-pciex") &&
69 !of_device_is_compatible(hose
->dn
, "ibm,plb-pcix") &&
70 !of_device_is_compatible(hose
->dn
, "ibm,plb-pci"))
73 if (of_device_is_compatible(hose
->dn
, "ibm,plb440epx-pci") ||
74 of_device_is_compatible(hose
->dn
, "ibm,plb440grx-pci")) {
75 hose
->indirect_type
|= PPC_INDIRECT_TYPE_BROKEN_MRM
;
78 /* Hide the PCI host BARs from the kernel as their content doesn't
79 * fit well in the resource management
81 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++) {
82 dev
->resource
[i
].start
= dev
->resource
[i
].end
= 0;
83 dev
->resource
[i
].flags
= 0;
86 printk(KERN_INFO
"PCI: Hiding 4xx host bridge resources %s\n",
89 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID
, PCI_ANY_ID
, fixup_ppc4xx_pci_bridge
);
91 static int __init
ppc4xx_parse_dma_ranges(struct pci_controller
*hose
,
98 int pna
= of_n_addr_cells(hose
->dn
);
105 res
->flags
= IORESOURCE_MEM
| IORESOURCE_PREFETCH
;
107 /* Get dma-ranges property */
108 ranges
= of_get_property(hose
->dn
, "dma-ranges", &rlen
);
113 while ((rlen
-= np
* 4) >= 0) {
114 u32 pci_space
= ranges
[0];
115 u64 pci_addr
= of_read_number(ranges
+ 1, 2);
116 u64 cpu_addr
= of_translate_dma_address(hose
->dn
, ranges
+ 3);
117 size
= of_read_number(ranges
+ pna
+ 3, 2);
119 if (cpu_addr
== OF_BAD_ADDR
|| size
== 0)
122 /* We only care about memory */
123 if ((pci_space
& 0x03000000) != 0x02000000)
126 /* We currently only support memory at 0, and pci_addr
127 * within 32 bits space
129 if (cpu_addr
!= 0 || pci_addr
> 0xffffffff) {
130 printk(KERN_WARNING
"%s: Ignored unsupported dma range"
131 " 0x%016llx...0x%016llx -> 0x%016llx\n",
133 pci_addr
, pci_addr
+ size
- 1, cpu_addr
);
137 /* Check if not prefetchable */
138 if (!(pci_space
& 0x40000000))
139 res
->flags
&= ~IORESOURCE_PREFETCH
;
143 res
->start
= pci_addr
;
144 /* Beware of 32 bits resources */
145 if (sizeof(resource_size_t
) == sizeof(u32
) &&
146 (pci_addr
+ size
) > 0x100000000ull
)
147 res
->end
= 0xffffffff;
149 res
->end
= res
->start
+ size
- 1;
153 /* We only support one global DMA offset */
154 if (dma_offset_set
&& pci_dram_offset
!= res
->start
) {
155 printk(KERN_ERR
"%s: dma-ranges(s) mismatch\n",
156 hose
->dn
->full_name
);
160 /* Check that we can fit all of memory as we don't support
163 if (size
< total_memory
) {
164 printk(KERN_ERR
"%s: dma-ranges too small "
165 "(size=%llx total_memory=%llx)\n",
166 hose
->dn
->full_name
, size
, (u64
)total_memory
);
170 /* Check we are a power of 2 size and that base is a multiple of size*/
171 if ((size
& (size
- 1)) != 0 ||
172 (res
->start
& (size
- 1)) != 0) {
173 printk(KERN_ERR
"%s: dma-ranges unaligned\n",
174 hose
->dn
->full_name
);
178 /* Check that we are fully contained within 32 bits space */
179 if (res
->end
> 0xffffffff) {
180 printk(KERN_ERR
"%s: dma-ranges outside of 32 bits space\n",
181 hose
->dn
->full_name
);
186 pci_dram_offset
= res
->start
;
188 printk(KERN_INFO
"4xx PCI DMA offset set to 0x%08lx\n",
197 static int __init
ppc4xx_setup_one_pci_PMM(struct pci_controller
*hose
,
205 u32 ma
, pcila
, pciha
;
207 /* Hack warning ! The "old" PCI 2.x cell only let us configure the low
208 * 32-bit of incoming PLB addresses. The top 4 bits of the 36-bit
209 * address are actually hard wired to a value that appears to depend
210 * on the specific SoC. For example, it's 0 on 440EP and 1 on 440EPx.
212 * The trick here is we just crop those top bits and ignore them when
213 * programming the chip. That means the device-tree has to be right
214 * for the specific part used (we don't print a warning if it's wrong
215 * but on the other hand, you'll crash quickly enough), but at least
216 * this code should work whatever the hard coded value is
218 plb_addr
&= 0xffffffffull
;
220 /* Note: Due to the above hack, the test below doesn't actually test
221 * if you address is above 4G, but it tests that address and
222 * (address + size) are both contained in the same 4G
224 if ((plb_addr
+ size
) > 0xffffffffull
|| !is_power_of_2(size
) ||
225 size
< 0x1000 || (plb_addr
& (size
- 1)) != 0) {
226 printk(KERN_WARNING
"%s: Resource out of range\n",
227 hose
->dn
->full_name
);
230 ma
= (0xffffffffu
<< ilog2(size
)) | 1;
231 if (flags
& IORESOURCE_PREFETCH
)
234 pciha
= RES_TO_U32_HIGH(pci_addr
);
235 pcila
= RES_TO_U32_LOW(pci_addr
);
237 writel(plb_addr
, reg
+ PCIL0_PMM0LA
+ (0x10 * index
));
238 writel(pcila
, reg
+ PCIL0_PMM0PCILA
+ (0x10 * index
));
239 writel(pciha
, reg
+ PCIL0_PMM0PCIHA
+ (0x10 * index
));
240 writel(ma
, reg
+ PCIL0_PMM0MA
+ (0x10 * index
));
245 static void __init
ppc4xx_configure_pci_PMMs(struct pci_controller
*hose
,
248 int i
, j
, found_isa_hole
= 0;
250 /* Setup outbound memory windows */
251 for (i
= j
= 0; i
< 3; i
++) {
252 struct resource
*res
= &hose
->mem_resources
[i
];
254 /* we only care about memory windows */
255 if (!(res
->flags
& IORESOURCE_MEM
))
258 printk(KERN_WARNING
"%s: Too many ranges\n",
259 hose
->dn
->full_name
);
263 /* Configure the resource */
264 if (ppc4xx_setup_one_pci_PMM(hose
, reg
,
266 res
->start
- hose
->pci_mem_offset
,
267 res
->end
+ 1 - res
->start
,
272 /* If the resource PCI address is 0 then we have our
275 if (res
->start
== hose
->pci_mem_offset
)
280 /* Handle ISA memory hole if not already covered */
281 if (j
<= 2 && !found_isa_hole
&& hose
->isa_mem_size
)
282 if (ppc4xx_setup_one_pci_PMM(hose
, reg
, hose
->isa_mem_phys
, 0,
283 hose
->isa_mem_size
, 0, j
) == 0)
284 printk(KERN_INFO
"%s: Legacy ISA memory support enabled\n",
285 hose
->dn
->full_name
);
288 static void __init
ppc4xx_configure_pci_PTMs(struct pci_controller
*hose
,
290 const struct resource
*res
)
292 resource_size_t size
= res
->end
- res
->start
+ 1;
295 /* Calculate window size */
296 sa
= (0xffffffffu
<< ilog2(size
)) | 1;
299 /* RAM is always at 0 local for now */
300 writel(0, reg
+ PCIL0_PTM1LA
);
301 writel(sa
, reg
+ PCIL0_PTM1MS
);
303 /* Map on PCI side */
304 early_write_config_dword(hose
, hose
->first_busno
, 0,
305 PCI_BASE_ADDRESS_1
, res
->start
);
306 early_write_config_dword(hose
, hose
->first_busno
, 0,
307 PCI_BASE_ADDRESS_2
, 0x00000000);
308 early_write_config_word(hose
, hose
->first_busno
, 0,
309 PCI_COMMAND
, 0x0006);
312 static void __init
ppc4xx_probe_pci_bridge(struct device_node
*np
)
315 struct resource rsrc_cfg
;
316 struct resource rsrc_reg
;
317 struct resource dma_window
;
318 struct pci_controller
*hose
= NULL
;
319 void __iomem
*reg
= NULL
;
320 const int *bus_range
;
323 /* Check if device is enabled */
324 if (!of_device_is_available(np
)) {
325 printk(KERN_INFO
"%s: Port disabled via device-tree\n",
330 /* Fetch config space registers address */
331 if (of_address_to_resource(np
, 0, &rsrc_cfg
)) {
332 printk(KERN_ERR
"%s: Can't get PCI config register base !",
336 /* Fetch host bridge internal registers address */
337 if (of_address_to_resource(np
, 3, &rsrc_reg
)) {
338 printk(KERN_ERR
"%s: Can't get PCI internal register base !",
343 /* Check if primary bridge */
344 if (of_get_property(np
, "primary", NULL
))
347 /* Get bus range if any */
348 bus_range
= of_get_property(np
, "bus-range", NULL
);
351 reg
= ioremap(rsrc_reg
.start
, rsrc_reg
.end
+ 1 - rsrc_reg
.start
);
353 printk(KERN_ERR
"%s: Can't map registers !", np
->full_name
);
357 /* Allocate the host controller data structure */
358 hose
= pcibios_alloc_controller(np
);
362 hose
->first_busno
= bus_range
? bus_range
[0] : 0x0;
363 hose
->last_busno
= bus_range
? bus_range
[1] : 0xff;
365 /* Setup config space */
366 setup_indirect_pci(hose
, rsrc_cfg
.start
, rsrc_cfg
.start
+ 0x4, 0);
368 /* Disable all windows */
369 writel(0, reg
+ PCIL0_PMM0MA
);
370 writel(0, reg
+ PCIL0_PMM1MA
);
371 writel(0, reg
+ PCIL0_PMM2MA
);
372 writel(0, reg
+ PCIL0_PTM1MS
);
373 writel(0, reg
+ PCIL0_PTM2MS
);
375 /* Parse outbound mapping resources */
376 pci_process_bridge_OF_ranges(hose
, np
, primary
);
378 /* Parse inbound mapping resources */
379 if (ppc4xx_parse_dma_ranges(hose
, reg
, &dma_window
) != 0)
382 /* Configure outbound ranges POMs */
383 ppc4xx_configure_pci_PMMs(hose
, reg
);
385 /* Configure inbound ranges PIMs */
386 ppc4xx_configure_pci_PTMs(hose
, reg
, &dma_window
);
388 /* We don't need the registers anymore */
394 pcibios_free_controller(hose
);
403 static int __init
ppc4xx_setup_one_pcix_POM(struct pci_controller
*hose
,
411 u32 lah
, lal
, pciah
, pcial
, sa
;
413 if (!is_power_of_2(size
) || size
< 0x1000 ||
414 (plb_addr
& (size
- 1)) != 0) {
415 printk(KERN_WARNING
"%s: Resource out of range\n",
416 hose
->dn
->full_name
);
420 /* Calculate register values */
421 lah
= RES_TO_U32_HIGH(plb_addr
);
422 lal
= RES_TO_U32_LOW(plb_addr
);
423 pciah
= RES_TO_U32_HIGH(pci_addr
);
424 pcial
= RES_TO_U32_LOW(pci_addr
);
425 sa
= (0xffffffffu
<< ilog2(size
)) | 0x1;
427 /* Program register values */
429 writel(lah
, reg
+ PCIX0_POM0LAH
);
430 writel(lal
, reg
+ PCIX0_POM0LAL
);
431 writel(pciah
, reg
+ PCIX0_POM0PCIAH
);
432 writel(pcial
, reg
+ PCIX0_POM0PCIAL
);
433 writel(sa
, reg
+ PCIX0_POM0SA
);
435 writel(lah
, reg
+ PCIX0_POM1LAH
);
436 writel(lal
, reg
+ PCIX0_POM1LAL
);
437 writel(pciah
, reg
+ PCIX0_POM1PCIAH
);
438 writel(pcial
, reg
+ PCIX0_POM1PCIAL
);
439 writel(sa
, reg
+ PCIX0_POM1SA
);
445 static void __init
ppc4xx_configure_pcix_POMs(struct pci_controller
*hose
,
448 int i
, j
, found_isa_hole
= 0;
450 /* Setup outbound memory windows */
451 for (i
= j
= 0; i
< 3; i
++) {
452 struct resource
*res
= &hose
->mem_resources
[i
];
454 /* we only care about memory windows */
455 if (!(res
->flags
& IORESOURCE_MEM
))
458 printk(KERN_WARNING
"%s: Too many ranges\n",
459 hose
->dn
->full_name
);
463 /* Configure the resource */
464 if (ppc4xx_setup_one_pcix_POM(hose
, reg
,
466 res
->start
- hose
->pci_mem_offset
,
467 res
->end
+ 1 - res
->start
,
472 /* If the resource PCI address is 0 then we have our
475 if (res
->start
== hose
->pci_mem_offset
)
480 /* Handle ISA memory hole if not already covered */
481 if (j
<= 1 && !found_isa_hole
&& hose
->isa_mem_size
)
482 if (ppc4xx_setup_one_pcix_POM(hose
, reg
, hose
->isa_mem_phys
, 0,
483 hose
->isa_mem_size
, 0, j
) == 0)
484 printk(KERN_INFO
"%s: Legacy ISA memory support enabled\n",
485 hose
->dn
->full_name
);
488 static void __init
ppc4xx_configure_pcix_PIMs(struct pci_controller
*hose
,
490 const struct resource
*res
,
494 resource_size_t size
= res
->end
- res
->start
+ 1;
497 /* RAM is always at 0 */
498 writel(0x00000000, reg
+ PCIX0_PIM0LAH
);
499 writel(0x00000000, reg
+ PCIX0_PIM0LAL
);
501 /* Calculate window size */
502 sa
= (0xffffffffu
<< ilog2(size
)) | 1;
504 if (res
->flags
& IORESOURCE_PREFETCH
)
508 writel(sa
, reg
+ PCIX0_PIM0SA
);
510 writel(0xffffffff, reg
+ PCIX0_PIM0SAH
);
512 /* Map on PCI side */
513 writel(0x00000000, reg
+ PCIX0_BAR0H
);
514 writel(res
->start
, reg
+ PCIX0_BAR0L
);
515 writew(0x0006, reg
+ PCIX0_COMMAND
);
518 static void __init
ppc4xx_probe_pcix_bridge(struct device_node
*np
)
520 struct resource rsrc_cfg
;
521 struct resource rsrc_reg
;
522 struct resource dma_window
;
523 struct pci_controller
*hose
= NULL
;
524 void __iomem
*reg
= NULL
;
525 const int *bus_range
;
526 int big_pim
= 0, msi
= 0, primary
= 0;
528 /* Fetch config space registers address */
529 if (of_address_to_resource(np
, 0, &rsrc_cfg
)) {
530 printk(KERN_ERR
"%s:Can't get PCI-X config register base !",
534 /* Fetch host bridge internal registers address */
535 if (of_address_to_resource(np
, 3, &rsrc_reg
)) {
536 printk(KERN_ERR
"%s: Can't get PCI-X internal register base !",
541 /* Check if it supports large PIMs (440GX) */
542 if (of_get_property(np
, "large-inbound-windows", NULL
))
545 /* Check if we should enable MSIs inbound hole */
546 if (of_get_property(np
, "enable-msi-hole", NULL
))
549 /* Check if primary bridge */
550 if (of_get_property(np
, "primary", NULL
))
553 /* Get bus range if any */
554 bus_range
= of_get_property(np
, "bus-range", NULL
);
557 reg
= ioremap(rsrc_reg
.start
, rsrc_reg
.end
+ 1 - rsrc_reg
.start
);
559 printk(KERN_ERR
"%s: Can't map registers !", np
->full_name
);
563 /* Allocate the host controller data structure */
564 hose
= pcibios_alloc_controller(np
);
568 hose
->first_busno
= bus_range
? bus_range
[0] : 0x0;
569 hose
->last_busno
= bus_range
? bus_range
[1] : 0xff;
571 /* Setup config space */
572 setup_indirect_pci(hose
, rsrc_cfg
.start
, rsrc_cfg
.start
+ 0x4,
573 PPC_INDIRECT_TYPE_SET_CFG_TYPE
);
575 /* Disable all windows */
576 writel(0, reg
+ PCIX0_POM0SA
);
577 writel(0, reg
+ PCIX0_POM1SA
);
578 writel(0, reg
+ PCIX0_POM2SA
);
579 writel(0, reg
+ PCIX0_PIM0SA
);
580 writel(0, reg
+ PCIX0_PIM1SA
);
581 writel(0, reg
+ PCIX0_PIM2SA
);
583 writel(0, reg
+ PCIX0_PIM0SAH
);
584 writel(0, reg
+ PCIX0_PIM2SAH
);
587 /* Parse outbound mapping resources */
588 pci_process_bridge_OF_ranges(hose
, np
, primary
);
590 /* Parse inbound mapping resources */
591 if (ppc4xx_parse_dma_ranges(hose
, reg
, &dma_window
) != 0)
594 /* Configure outbound ranges POMs */
595 ppc4xx_configure_pcix_POMs(hose
, reg
);
597 /* Configure inbound ranges PIMs */
598 ppc4xx_configure_pcix_PIMs(hose
, reg
, &dma_window
, big_pim
, msi
);
600 /* We don't need the registers anymore */
606 pcibios_free_controller(hose
);
611 #ifdef CONFIG_PPC4xx_PCI_EXPRESS
614 * 4xx PCI-Express part
616 * We support 3 parts currently based on the compatible property:
618 * ibm,plb-pciex-440spe
619 * ibm,plb-pciex-405ex
620 * ibm,plb-pciex-460ex
622 * Anything else will be rejected for now as they are all subtly
623 * different unfortunately.
627 #define MAX_PCIE_BUS_MAPPED 0x40
629 struct ppc4xx_pciex_port
631 struct pci_controller
*hose
;
632 struct device_node
*node
;
637 unsigned int sdr_base
;
639 struct resource cfg_space
;
640 struct resource utl_regs
;
641 void __iomem
*utl_base
;
644 static struct ppc4xx_pciex_port
*ppc4xx_pciex_ports
;
645 static unsigned int ppc4xx_pciex_port_count
;
647 struct ppc4xx_pciex_hwops
649 int (*core_init
)(struct device_node
*np
);
650 int (*port_init_hw
)(struct ppc4xx_pciex_port
*port
);
651 int (*setup_utl
)(struct ppc4xx_pciex_port
*port
);
654 static struct ppc4xx_pciex_hwops
*ppc4xx_pciex_hwops
;
658 /* Check various reset bits of the 440SPe PCIe core */
659 static int __init
ppc440spe_pciex_check_reset(struct device_node
*np
)
661 u32 valPE0
, valPE1
, valPE2
;
664 /* SDR0_PEGPLLLCT1 reset */
665 if (!(mfdcri(SDR0
, PESDR0_PLLLCT1
) & 0x01000000)) {
667 * the PCIe core was probably already initialised
668 * by firmware - let's re-reset RCSSET regs
670 * -- Shouldn't we also re-reset the whole thing ? -- BenH
672 pr_debug("PCIE: SDR0_PLLLCT1 already reset.\n");
673 mtdcri(SDR0
, PESDR0_440SPE_RCSSET
, 0x01010000);
674 mtdcri(SDR0
, PESDR1_440SPE_RCSSET
, 0x01010000);
675 mtdcri(SDR0
, PESDR2_440SPE_RCSSET
, 0x01010000);
678 valPE0
= mfdcri(SDR0
, PESDR0_440SPE_RCSSET
);
679 valPE1
= mfdcri(SDR0
, PESDR1_440SPE_RCSSET
);
680 valPE2
= mfdcri(SDR0
, PESDR2_440SPE_RCSSET
);
682 /* SDR0_PExRCSSET rstgu */
683 if (!(valPE0
& 0x01000000) ||
684 !(valPE1
& 0x01000000) ||
685 !(valPE2
& 0x01000000)) {
686 printk(KERN_INFO
"PCIE: SDR0_PExRCSSET rstgu error\n");
690 /* SDR0_PExRCSSET rstdl */
691 if (!(valPE0
& 0x00010000) ||
692 !(valPE1
& 0x00010000) ||
693 !(valPE2
& 0x00010000)) {
694 printk(KERN_INFO
"PCIE: SDR0_PExRCSSET rstdl error\n");
698 /* SDR0_PExRCSSET rstpyn */
699 if ((valPE0
& 0x00001000) ||
700 (valPE1
& 0x00001000) ||
701 (valPE2
& 0x00001000)) {
702 printk(KERN_INFO
"PCIE: SDR0_PExRCSSET rstpyn error\n");
706 /* SDR0_PExRCSSET hldplb */
707 if ((valPE0
& 0x10000000) ||
708 (valPE1
& 0x10000000) ||
709 (valPE2
& 0x10000000)) {
710 printk(KERN_INFO
"PCIE: SDR0_PExRCSSET hldplb error\n");
714 /* SDR0_PExRCSSET rdy */
715 if ((valPE0
& 0x00100000) ||
716 (valPE1
& 0x00100000) ||
717 (valPE2
& 0x00100000)) {
718 printk(KERN_INFO
"PCIE: SDR0_PExRCSSET rdy error\n");
722 /* SDR0_PExRCSSET shutdown */
723 if ((valPE0
& 0x00000100) ||
724 (valPE1
& 0x00000100) ||
725 (valPE2
& 0x00000100)) {
726 printk(KERN_INFO
"PCIE: SDR0_PExRCSSET shutdown error\n");
733 /* Global PCIe core initializations for 440SPe core */
734 static int __init
ppc440spe_pciex_core_init(struct device_node
*np
)
738 /* Set PLL clock receiver to LVPECL */
739 dcri_clrset(SDR0
, PESDR0_PLLLCT1
, 0, 1 << 28);
741 /* Shouldn't we do all the calibration stuff etc... here ? */
742 if (ppc440spe_pciex_check_reset(np
))
745 if (!(mfdcri(SDR0
, PESDR0_PLLLCT2
) & 0x10000)) {
746 printk(KERN_INFO
"PCIE: PESDR_PLLCT2 resistance calibration "
748 mfdcri(SDR0
, PESDR0_PLLLCT2
));
752 /* De-assert reset of PCIe PLL, wait for lock */
753 dcri_clrset(SDR0
, PESDR0_PLLLCT1
, 1 << 24, 0);
757 if (!(mfdcri(SDR0
, PESDR0_PLLLCT3
) & 0x10000000)) {
764 printk(KERN_INFO
"PCIE: VCO output not locked\n");
768 pr_debug("PCIE initialization OK\n");
773 static int ppc440spe_pciex_init_port_hw(struct ppc4xx_pciex_port
*port
)
778 val
= PTYPE_LEGACY_ENDPOINT
<< 20;
780 val
= PTYPE_ROOT_PORT
<< 20;
782 if (port
->index
== 0)
783 val
|= LNKW_X8
<< 12;
785 val
|= LNKW_X4
<< 12;
787 mtdcri(SDR0
, port
->sdr_base
+ PESDRn_DLPSET
, val
);
788 mtdcri(SDR0
, port
->sdr_base
+ PESDRn_UTLSET1
, 0x20222222);
789 if (ppc440spe_revA())
790 mtdcri(SDR0
, port
->sdr_base
+ PESDRn_UTLSET2
, 0x11000000);
791 mtdcri(SDR0
, port
->sdr_base
+ PESDRn_440SPE_HSSL0SET1
, 0x35000000);
792 mtdcri(SDR0
, port
->sdr_base
+ PESDRn_440SPE_HSSL1SET1
, 0x35000000);
793 mtdcri(SDR0
, port
->sdr_base
+ PESDRn_440SPE_HSSL2SET1
, 0x35000000);
794 mtdcri(SDR0
, port
->sdr_base
+ PESDRn_440SPE_HSSL3SET1
, 0x35000000);
795 if (port
->index
== 0) {
796 mtdcri(SDR0
, port
->sdr_base
+ PESDRn_440SPE_HSSL4SET1
,
798 mtdcri(SDR0
, port
->sdr_base
+ PESDRn_440SPE_HSSL5SET1
,
800 mtdcri(SDR0
, port
->sdr_base
+ PESDRn_440SPE_HSSL6SET1
,
802 mtdcri(SDR0
, port
->sdr_base
+ PESDRn_440SPE_HSSL7SET1
,
805 dcri_clrset(SDR0
, port
->sdr_base
+ PESDRn_RCSSET
,
806 (1 << 24) | (1 << 16), 1 << 12);
811 static int ppc440speA_pciex_init_port_hw(struct ppc4xx_pciex_port
*port
)
813 return ppc440spe_pciex_init_port_hw(port
);
816 static int ppc440speB_pciex_init_port_hw(struct ppc4xx_pciex_port
*port
)
818 int rc
= ppc440spe_pciex_init_port_hw(port
);
825 static int ppc440speA_pciex_init_utl(struct ppc4xx_pciex_port
*port
)
827 /* XXX Check what that value means... I hate magic */
828 dcr_write(port
->dcrs
, DCRO_PEGPL_SPECIAL
, 0x68782800);
831 * Set buffer allocations and then assert VRB and TXE.
833 out_be32(port
->utl_base
+ PEUTL_OUTTR
, 0x08000000);
834 out_be32(port
->utl_base
+ PEUTL_INTR
, 0x02000000);
835 out_be32(port
->utl_base
+ PEUTL_OPDBSZ
, 0x10000000);
836 out_be32(port
->utl_base
+ PEUTL_PBBSZ
, 0x53000000);
837 out_be32(port
->utl_base
+ PEUTL_IPHBSZ
, 0x08000000);
838 out_be32(port
->utl_base
+ PEUTL_IPDBSZ
, 0x10000000);
839 out_be32(port
->utl_base
+ PEUTL_RCIRQEN
, 0x00f00000);
840 out_be32(port
->utl_base
+ PEUTL_PCTL
, 0x80800066);
845 static int ppc440speB_pciex_init_utl(struct ppc4xx_pciex_port
*port
)
847 /* Report CRS to the operating system */
848 out_be32(port
->utl_base
+ PEUTL_PBCTL
, 0x08000000);
853 static struct ppc4xx_pciex_hwops ppc440speA_pcie_hwops __initdata
=
855 .core_init
= ppc440spe_pciex_core_init
,
856 .port_init_hw
= ppc440speA_pciex_init_port_hw
,
857 .setup_utl
= ppc440speA_pciex_init_utl
,
860 static struct ppc4xx_pciex_hwops ppc440speB_pcie_hwops __initdata
=
862 .core_init
= ppc440spe_pciex_core_init
,
863 .port_init_hw
= ppc440speB_pciex_init_port_hw
,
864 .setup_utl
= ppc440speB_pciex_init_utl
,
867 static int __init
ppc460ex_pciex_core_init(struct device_node
*np
)
869 /* Nothing to do, return 2 ports */
873 static int ppc460ex_pciex_init_port_hw(struct ppc4xx_pciex_port
*port
)
879 val
= PTYPE_LEGACY_ENDPOINT
<< 20;
881 val
= PTYPE_ROOT_PORT
<< 20;
883 if (port
->index
== 0) {
884 val
|= LNKW_X1
<< 12;
885 utlset1
= 0x20000000;
887 val
|= LNKW_X4
<< 12;
888 utlset1
= 0x20101101;
891 mtdcri(SDR0
, port
->sdr_base
+ PESDRn_DLPSET
, val
);
892 mtdcri(SDR0
, port
->sdr_base
+ PESDRn_UTLSET1
, utlset1
);
893 mtdcri(SDR0
, port
->sdr_base
+ PESDRn_UTLSET2
, 0x01210000);
895 switch (port
->index
) {
897 mtdcri(SDR0
, PESDR0_460EX_L0CDRCTL
, 0x00003230);
898 mtdcri(SDR0
, PESDR0_460EX_L0DRV
, 0x00000130);
899 mtdcri(SDR0
, PESDR0_460EX_L0CLK
, 0x00000006);
901 mtdcri(SDR0
, PESDR0_460EX_PHY_CTL_RST
,0x10000000);
905 mtdcri(SDR0
, PESDR1_460EX_L0CDRCTL
, 0x00003230);
906 mtdcri(SDR0
, PESDR1_460EX_L1CDRCTL
, 0x00003230);
907 mtdcri(SDR0
, PESDR1_460EX_L2CDRCTL
, 0x00003230);
908 mtdcri(SDR0
, PESDR1_460EX_L3CDRCTL
, 0x00003230);
909 mtdcri(SDR0
, PESDR1_460EX_L0DRV
, 0x00000130);
910 mtdcri(SDR0
, PESDR1_460EX_L1DRV
, 0x00000130);
911 mtdcri(SDR0
, PESDR1_460EX_L2DRV
, 0x00000130);
912 mtdcri(SDR0
, PESDR1_460EX_L3DRV
, 0x00000130);
913 mtdcri(SDR0
, PESDR1_460EX_L0CLK
, 0x00000006);
914 mtdcri(SDR0
, PESDR1_460EX_L1CLK
, 0x00000006);
915 mtdcri(SDR0
, PESDR1_460EX_L2CLK
, 0x00000006);
916 mtdcri(SDR0
, PESDR1_460EX_L3CLK
, 0x00000006);
918 mtdcri(SDR0
, PESDR1_460EX_PHY_CTL_RST
,0x10000000);
922 mtdcri(SDR0
, port
->sdr_base
+ PESDRn_RCSSET
,
923 mfdcri(SDR0
, port
->sdr_base
+ PESDRn_RCSSET
) |
924 (PESDRx_RCSSET_RSTGU
| PESDRx_RCSSET_RSTPYN
));
926 /* Poll for PHY reset */
927 /* XXX FIXME add timeout */
928 switch (port
->index
) {
930 while (!(mfdcri(SDR0
, PESDR0_460EX_RSTSTA
) & 0x1))
934 while (!(mfdcri(SDR0
, PESDR1_460EX_RSTSTA
) & 0x1))
939 mtdcri(SDR0
, port
->sdr_base
+ PESDRn_RCSSET
,
940 (mfdcri(SDR0
, port
->sdr_base
+ PESDRn_RCSSET
) &
941 ~(PESDRx_RCSSET_RSTGU
| PESDRx_RCSSET_RSTDL
)) |
942 PESDRx_RCSSET_RSTPYN
);
949 static int ppc460ex_pciex_init_utl(struct ppc4xx_pciex_port
*port
)
951 dcr_write(port
->dcrs
, DCRO_PEGPL_SPECIAL
, 0x0);
954 * Set buffer allocations and then assert VRB and TXE.
956 out_be32(port
->utl_base
+ PEUTL_PBCTL
, 0x0800000c);
957 out_be32(port
->utl_base
+ PEUTL_OUTTR
, 0x08000000);
958 out_be32(port
->utl_base
+ PEUTL_INTR
, 0x02000000);
959 out_be32(port
->utl_base
+ PEUTL_OPDBSZ
, 0x04000000);
960 out_be32(port
->utl_base
+ PEUTL_PBBSZ
, 0x00000000);
961 out_be32(port
->utl_base
+ PEUTL_IPHBSZ
, 0x02000000);
962 out_be32(port
->utl_base
+ PEUTL_IPDBSZ
, 0x04000000);
963 out_be32(port
->utl_base
+ PEUTL_RCIRQEN
,0x00f00000);
964 out_be32(port
->utl_base
+ PEUTL_PCTL
, 0x80800066);
969 static struct ppc4xx_pciex_hwops ppc460ex_pcie_hwops __initdata
=
971 .core_init
= ppc460ex_pciex_core_init
,
972 .port_init_hw
= ppc460ex_pciex_init_port_hw
,
973 .setup_utl
= ppc460ex_pciex_init_utl
,
976 #endif /* CONFIG_44x */
980 static int __init
ppc405ex_pciex_core_init(struct device_node
*np
)
982 /* Nothing to do, return 2 ports */
986 static void ppc405ex_pcie_phy_reset(struct ppc4xx_pciex_port
*port
)
988 /* Assert the PE0_PHY reset */
989 mtdcri(SDR0
, port
->sdr_base
+ PESDRn_RCSSET
, 0x01010000);
992 /* deassert the PE0_hotreset */
994 mtdcri(SDR0
, port
->sdr_base
+ PESDRn_RCSSET
, 0x01111000);
996 mtdcri(SDR0
, port
->sdr_base
+ PESDRn_RCSSET
, 0x01101000);
998 /* poll for phy !reset */
999 /* XXX FIXME add timeout */
1000 while (!(mfdcri(SDR0
, port
->sdr_base
+ PESDRn_405EX_PHYSTA
) & 0x00001000))
1003 /* deassert the PE0_gpl_utl_reset */
1004 mtdcri(SDR0
, port
->sdr_base
+ PESDRn_RCSSET
, 0x00101000);
1007 static int ppc405ex_pciex_init_port_hw(struct ppc4xx_pciex_port
*port
)
1012 val
= PTYPE_LEGACY_ENDPOINT
;
1014 val
= PTYPE_ROOT_PORT
;
1016 mtdcri(SDR0
, port
->sdr_base
+ PESDRn_DLPSET
,
1017 1 << 24 | val
<< 20 | LNKW_X1
<< 12);
1019 mtdcri(SDR0
, port
->sdr_base
+ PESDRn_UTLSET1
, 0x00000000);
1020 mtdcri(SDR0
, port
->sdr_base
+ PESDRn_UTLSET2
, 0x01010000);
1021 mtdcri(SDR0
, port
->sdr_base
+ PESDRn_405EX_PHYSET1
, 0x720F0000);
1022 mtdcri(SDR0
, port
->sdr_base
+ PESDRn_405EX_PHYSET2
, 0x70600003);
1025 * Only reset the PHY when no link is currently established.
1026 * This is for the Atheros PCIe board which has problems to establish
1027 * the link (again) after this PHY reset. All other currently tested
1028 * PCIe boards don't show this problem.
1029 * This has to be re-tested and fixed in a later release!
1031 val
= mfdcri(SDR0
, port
->sdr_base
+ PESDRn_LOOP
);
1032 if (!(val
& 0x00001000))
1033 ppc405ex_pcie_phy_reset(port
);
1035 dcr_write(port
->dcrs
, DCRO_PEGPL_CFG
, 0x10000000); /* guarded on */
1037 port
->has_ibpre
= 1;
1042 static int ppc405ex_pciex_init_utl(struct ppc4xx_pciex_port
*port
)
1044 dcr_write(port
->dcrs
, DCRO_PEGPL_SPECIAL
, 0x0);
1047 * Set buffer allocations and then assert VRB and TXE.
1049 out_be32(port
->utl_base
+ PEUTL_OUTTR
, 0x02000000);
1050 out_be32(port
->utl_base
+ PEUTL_INTR
, 0x02000000);
1051 out_be32(port
->utl_base
+ PEUTL_OPDBSZ
, 0x04000000);
1052 out_be32(port
->utl_base
+ PEUTL_PBBSZ
, 0x21000000);
1053 out_be32(port
->utl_base
+ PEUTL_IPHBSZ
, 0x02000000);
1054 out_be32(port
->utl_base
+ PEUTL_IPDBSZ
, 0x04000000);
1055 out_be32(port
->utl_base
+ PEUTL_RCIRQEN
, 0x00f00000);
1056 out_be32(port
->utl_base
+ PEUTL_PCTL
, 0x80800066);
1058 out_be32(port
->utl_base
+ PEUTL_PBCTL
, 0x08000000);
1063 static struct ppc4xx_pciex_hwops ppc405ex_pcie_hwops __initdata
=
1065 .core_init
= ppc405ex_pciex_core_init
,
1066 .port_init_hw
= ppc405ex_pciex_init_port_hw
,
1067 .setup_utl
= ppc405ex_pciex_init_utl
,
1070 #endif /* CONFIG_40x */
1073 /* Check that the core has been initied and if not, do it */
1074 static int __init
ppc4xx_pciex_check_core_init(struct device_node
*np
)
1076 static int core_init
;
1077 int count
= -ENODEV
;
1083 if (of_device_is_compatible(np
, "ibm,plb-pciex-440spe")) {
1084 if (ppc440spe_revA())
1085 ppc4xx_pciex_hwops
= &ppc440speA_pcie_hwops
;
1087 ppc4xx_pciex_hwops
= &ppc440speB_pcie_hwops
;
1089 if (of_device_is_compatible(np
, "ibm,plb-pciex-460ex"))
1090 ppc4xx_pciex_hwops
= &ppc460ex_pcie_hwops
;
1091 #endif /* CONFIG_44x */
1093 if (of_device_is_compatible(np
, "ibm,plb-pciex-405ex"))
1094 ppc4xx_pciex_hwops
= &ppc405ex_pcie_hwops
;
1096 if (ppc4xx_pciex_hwops
== NULL
) {
1097 printk(KERN_WARNING
"PCIE: unknown host type %s\n",
1102 count
= ppc4xx_pciex_hwops
->core_init(np
);
1104 ppc4xx_pciex_ports
=
1105 kzalloc(count
* sizeof(struct ppc4xx_pciex_port
),
1107 if (ppc4xx_pciex_ports
) {
1108 ppc4xx_pciex_port_count
= count
;
1111 printk(KERN_WARNING
"PCIE: failed to allocate ports array\n");
1117 static void __init
ppc4xx_pciex_port_init_mapping(struct ppc4xx_pciex_port
*port
)
1119 /* We map PCI Express configuration based on the reg property */
1120 dcr_write(port
->dcrs
, DCRO_PEGPL_CFGBAH
,
1121 RES_TO_U32_HIGH(port
->cfg_space
.start
));
1122 dcr_write(port
->dcrs
, DCRO_PEGPL_CFGBAL
,
1123 RES_TO_U32_LOW(port
->cfg_space
.start
));
1125 /* XXX FIXME: Use size from reg property. For now, map 512M */
1126 dcr_write(port
->dcrs
, DCRO_PEGPL_CFGMSK
, 0xe0000001);
1128 /* We map UTL registers based on the reg property */
1129 dcr_write(port
->dcrs
, DCRO_PEGPL_REGBAH
,
1130 RES_TO_U32_HIGH(port
->utl_regs
.start
));
1131 dcr_write(port
->dcrs
, DCRO_PEGPL_REGBAL
,
1132 RES_TO_U32_LOW(port
->utl_regs
.start
));
1134 /* XXX FIXME: Use size from reg property */
1135 dcr_write(port
->dcrs
, DCRO_PEGPL_REGMSK
, 0x00007001);
1137 /* Disable all other outbound windows */
1138 dcr_write(port
->dcrs
, DCRO_PEGPL_OMR1MSKL
, 0);
1139 dcr_write(port
->dcrs
, DCRO_PEGPL_OMR2MSKL
, 0);
1140 dcr_write(port
->dcrs
, DCRO_PEGPL_OMR3MSKL
, 0);
1141 dcr_write(port
->dcrs
, DCRO_PEGPL_MSGMSK
, 0);
1144 static int __init
ppc4xx_pciex_wait_on_sdr(struct ppc4xx_pciex_port
*port
,
1145 unsigned int sdr_offset
,
1152 while(timeout_ms
--) {
1153 val
= mfdcri(SDR0
, port
->sdr_base
+ sdr_offset
);
1154 if ((val
& mask
) == value
) {
1155 pr_debug("PCIE%d: Wait on SDR %x success with tm %d (%08x)\n",
1156 port
->index
, sdr_offset
, timeout_ms
, val
);
1164 static int __init
ppc4xx_pciex_port_init(struct ppc4xx_pciex_port
*port
)
1169 if (ppc4xx_pciex_hwops
->port_init_hw
)
1170 rc
= ppc4xx_pciex_hwops
->port_init_hw(port
);
1174 printk(KERN_INFO
"PCIE%d: Checking link...\n",
1177 /* Wait for reset to complete */
1178 if (ppc4xx_pciex_wait_on_sdr(port
, PESDRn_RCSSTS
, 1 << 20, 0, 10)) {
1179 printk(KERN_WARNING
"PCIE%d: PGRST failed\n",
1184 /* Check for card presence detect if supported, if not, just wait for
1185 * link unconditionally.
1187 * note that we don't fail if there is no link, we just filter out
1188 * config space accesses. That way, it will be easier to implement
1191 if (!port
->has_ibpre
||
1192 !ppc4xx_pciex_wait_on_sdr(port
, PESDRn_LOOP
,
1193 1 << 28, 1 << 28, 100)) {
1195 "PCIE%d: Device detected, waiting for link...\n",
1197 if (ppc4xx_pciex_wait_on_sdr(port
, PESDRn_LOOP
,
1198 0x1000, 0x1000, 2000))
1200 "PCIE%d: Link up failed\n", port
->index
);
1203 "PCIE%d: link is up !\n", port
->index
);
1207 printk(KERN_INFO
"PCIE%d: No device detected.\n", port
->index
);
1210 * Initialize mapping: disable all regions and configure
1211 * CFG and REG regions based on resources in the device tree
1213 ppc4xx_pciex_port_init_mapping(port
);
1218 port
->utl_base
= ioremap(port
->utl_regs
.start
, 0x100);
1219 BUG_ON(port
->utl_base
== NULL
);
1222 * Setup UTL registers --BenH.
1224 if (ppc4xx_pciex_hwops
->setup_utl
)
1225 ppc4xx_pciex_hwops
->setup_utl(port
);
1228 * Check for VC0 active and assert RDY.
1231 ppc4xx_pciex_wait_on_sdr(port
, PESDRn_RCSSTS
,
1232 1 << 16, 1 << 16, 5000)) {
1233 printk(KERN_INFO
"PCIE%d: VC0 not active\n", port
->index
);
1237 dcri_clrset(SDR0
, port
->sdr_base
+ PESDRn_RCSSET
, 0, 1 << 20);
1243 static int ppc4xx_pciex_validate_bdf(struct ppc4xx_pciex_port
*port
,
1244 struct pci_bus
*bus
,
1249 /* Endpoint can not generate upstream(remote) config cycles */
1250 if (port
->endpoint
&& bus
->number
!= port
->hose
->first_busno
)
1251 return PCIBIOS_DEVICE_NOT_FOUND
;
1253 /* Check we are within the mapped range */
1254 if (bus
->number
> port
->hose
->last_busno
) {
1256 printk(KERN_WARNING
"Warning! Probing bus %u"
1257 " out of range !\n", bus
->number
);
1260 return PCIBIOS_DEVICE_NOT_FOUND
;
1263 /* The root complex has only one device / function */
1264 if (bus
->number
== port
->hose
->first_busno
&& devfn
!= 0)
1265 return PCIBIOS_DEVICE_NOT_FOUND
;
1267 /* The other side of the RC has only one device as well */
1268 if (bus
->number
== (port
->hose
->first_busno
+ 1) &&
1269 PCI_SLOT(devfn
) != 0)
1270 return PCIBIOS_DEVICE_NOT_FOUND
;
1272 /* Check if we have a link */
1273 if ((bus
->number
!= port
->hose
->first_busno
) && !port
->link
)
1274 return PCIBIOS_DEVICE_NOT_FOUND
;
1279 static void __iomem
*ppc4xx_pciex_get_config_base(struct ppc4xx_pciex_port
*port
,
1280 struct pci_bus
*bus
,
1285 /* Remove the casts when we finally remove the stupid volatile
1286 * in struct pci_controller
1288 if (bus
->number
== port
->hose
->first_busno
)
1289 return (void __iomem
*)port
->hose
->cfg_addr
;
1291 relbus
= bus
->number
- (port
->hose
->first_busno
+ 1);
1292 return (void __iomem
*)port
->hose
->cfg_data
+
1293 ((relbus
<< 20) | (devfn
<< 12));
1296 static int ppc4xx_pciex_read_config(struct pci_bus
*bus
, unsigned int devfn
,
1297 int offset
, int len
, u32
*val
)
1299 struct pci_controller
*hose
= pci_bus_to_host(bus
);
1300 struct ppc4xx_pciex_port
*port
=
1301 &ppc4xx_pciex_ports
[hose
->indirect_type
];
1305 BUG_ON(hose
!= port
->hose
);
1307 if (ppc4xx_pciex_validate_bdf(port
, bus
, devfn
) != 0)
1308 return PCIBIOS_DEVICE_NOT_FOUND
;
1310 addr
= ppc4xx_pciex_get_config_base(port
, bus
, devfn
);
1313 * Reading from configuration space of non-existing device can
1314 * generate transaction errors. For the read duration we suppress
1315 * assertion of machine check exceptions to avoid those.
1317 gpl_cfg
= dcr_read(port
->dcrs
, DCRO_PEGPL_CFG
);
1318 dcr_write(port
->dcrs
, DCRO_PEGPL_CFG
, gpl_cfg
| GPL_DMER_MASK_DISA
);
1320 /* Make sure no CRS is recorded */
1321 out_be32(port
->utl_base
+ PEUTL_RCSTA
, 0x00040000);
1325 *val
= in_8((u8
*)(addr
+ offset
));
1328 *val
= in_le16((u16
*)(addr
+ offset
));
1331 *val
= in_le32((u32
*)(addr
+ offset
));
1335 pr_debug("pcie-config-read: bus=%3d [%3d..%3d] devfn=0x%04x"
1336 " offset=0x%04x len=%d, addr=0x%p val=0x%08x\n",
1337 bus
->number
, hose
->first_busno
, hose
->last_busno
,
1338 devfn
, offset
, len
, addr
+ offset
, *val
);
1340 /* Check for CRS (440SPe rev B does that for us but heh ..) */
1341 if (in_be32(port
->utl_base
+ PEUTL_RCSTA
) & 0x00040000) {
1342 pr_debug("Got CRS !\n");
1343 if (len
!= 4 || offset
!= 0)
1344 return PCIBIOS_DEVICE_NOT_FOUND
;
1348 dcr_write(port
->dcrs
, DCRO_PEGPL_CFG
, gpl_cfg
);
1350 return PCIBIOS_SUCCESSFUL
;
1353 static int ppc4xx_pciex_write_config(struct pci_bus
*bus
, unsigned int devfn
,
1354 int offset
, int len
, u32 val
)
1356 struct pci_controller
*hose
= pci_bus_to_host(bus
);
1357 struct ppc4xx_pciex_port
*port
=
1358 &ppc4xx_pciex_ports
[hose
->indirect_type
];
1362 if (ppc4xx_pciex_validate_bdf(port
, bus
, devfn
) != 0)
1363 return PCIBIOS_DEVICE_NOT_FOUND
;
1365 addr
= ppc4xx_pciex_get_config_base(port
, bus
, devfn
);
1368 * Reading from configuration space of non-existing device can
1369 * generate transaction errors. For the read duration we suppress
1370 * assertion of machine check exceptions to avoid those.
1372 gpl_cfg
= dcr_read(port
->dcrs
, DCRO_PEGPL_CFG
);
1373 dcr_write(port
->dcrs
, DCRO_PEGPL_CFG
, gpl_cfg
| GPL_DMER_MASK_DISA
);
1375 pr_debug("pcie-config-write: bus=%3d [%3d..%3d] devfn=0x%04x"
1376 " offset=0x%04x len=%d, addr=0x%p val=0x%08x\n",
1377 bus
->number
, hose
->first_busno
, hose
->last_busno
,
1378 devfn
, offset
, len
, addr
+ offset
, val
);
1382 out_8((u8
*)(addr
+ offset
), val
);
1385 out_le16((u16
*)(addr
+ offset
), val
);
1388 out_le32((u32
*)(addr
+ offset
), val
);
1392 dcr_write(port
->dcrs
, DCRO_PEGPL_CFG
, gpl_cfg
);
1394 return PCIBIOS_SUCCESSFUL
;
1397 static struct pci_ops ppc4xx_pciex_pci_ops
=
1399 .read
= ppc4xx_pciex_read_config
,
1400 .write
= ppc4xx_pciex_write_config
,
1403 static int __init
ppc4xx_setup_one_pciex_POM(struct ppc4xx_pciex_port
*port
,
1404 struct pci_controller
*hose
,
1405 void __iomem
*mbase
,
1412 u32 lah
, lal
, pciah
, pcial
, sa
;
1414 if (!is_power_of_2(size
) ||
1415 (index
< 2 && size
< 0x100000) ||
1416 (index
== 2 && size
< 0x100) ||
1417 (plb_addr
& (size
- 1)) != 0) {
1418 printk(KERN_WARNING
"%s: Resource out of range\n",
1419 hose
->dn
->full_name
);
1423 /* Calculate register values */
1424 lah
= RES_TO_U32_HIGH(plb_addr
);
1425 lal
= RES_TO_U32_LOW(plb_addr
);
1426 pciah
= RES_TO_U32_HIGH(pci_addr
);
1427 pcial
= RES_TO_U32_LOW(pci_addr
);
1428 sa
= (0xffffffffu
<< ilog2(size
)) | 0x1;
1430 /* Program register values */
1433 out_le32(mbase
+ PECFG_POM0LAH
, pciah
);
1434 out_le32(mbase
+ PECFG_POM0LAL
, pcial
);
1435 dcr_write(port
->dcrs
, DCRO_PEGPL_OMR1BAH
, lah
);
1436 dcr_write(port
->dcrs
, DCRO_PEGPL_OMR1BAL
, lal
);
1437 dcr_write(port
->dcrs
, DCRO_PEGPL_OMR1MSKH
, 0x7fffffff);
1438 /* Note that 3 here means enabled | single region */
1439 dcr_write(port
->dcrs
, DCRO_PEGPL_OMR1MSKL
, sa
| 3);
1442 out_le32(mbase
+ PECFG_POM1LAH
, pciah
);
1443 out_le32(mbase
+ PECFG_POM1LAL
, pcial
);
1444 dcr_write(port
->dcrs
, DCRO_PEGPL_OMR2BAH
, lah
);
1445 dcr_write(port
->dcrs
, DCRO_PEGPL_OMR2BAL
, lal
);
1446 dcr_write(port
->dcrs
, DCRO_PEGPL_OMR2MSKH
, 0x7fffffff);
1447 /* Note that 3 here means enabled | single region */
1448 dcr_write(port
->dcrs
, DCRO_PEGPL_OMR2MSKL
, sa
| 3);
1451 out_le32(mbase
+ PECFG_POM2LAH
, pciah
);
1452 out_le32(mbase
+ PECFG_POM2LAL
, pcial
);
1453 dcr_write(port
->dcrs
, DCRO_PEGPL_OMR3BAH
, lah
);
1454 dcr_write(port
->dcrs
, DCRO_PEGPL_OMR3BAL
, lal
);
1455 dcr_write(port
->dcrs
, DCRO_PEGPL_OMR3MSKH
, 0x7fffffff);
1456 /* Note that 3 here means enabled | IO space !!! */
1457 dcr_write(port
->dcrs
, DCRO_PEGPL_OMR3MSKL
, sa
| 3);
1464 static void __init
ppc4xx_configure_pciex_POMs(struct ppc4xx_pciex_port
*port
,
1465 struct pci_controller
*hose
,
1466 void __iomem
*mbase
)
1468 int i
, j
, found_isa_hole
= 0;
1470 /* Setup outbound memory windows */
1471 for (i
= j
= 0; i
< 3; i
++) {
1472 struct resource
*res
= &hose
->mem_resources
[i
];
1474 /* we only care about memory windows */
1475 if (!(res
->flags
& IORESOURCE_MEM
))
1478 printk(KERN_WARNING
"%s: Too many ranges\n",
1479 port
->node
->full_name
);
1483 /* Configure the resource */
1484 if (ppc4xx_setup_one_pciex_POM(port
, hose
, mbase
,
1486 res
->start
- hose
->pci_mem_offset
,
1487 res
->end
+ 1 - res
->start
,
1492 /* If the resource PCI address is 0 then we have our
1495 if (res
->start
== hose
->pci_mem_offset
)
1500 /* Handle ISA memory hole if not already covered */
1501 if (j
<= 1 && !found_isa_hole
&& hose
->isa_mem_size
)
1502 if (ppc4xx_setup_one_pciex_POM(port
, hose
, mbase
,
1503 hose
->isa_mem_phys
, 0,
1504 hose
->isa_mem_size
, 0, j
) == 0)
1505 printk(KERN_INFO
"%s: Legacy ISA memory support enabled\n",
1506 hose
->dn
->full_name
);
1508 /* Configure IO, always 64K starting at 0. We hard wire it to 64K !
1509 * Note also that it -has- to be region index 2 on this HW
1511 if (hose
->io_resource
.flags
& IORESOURCE_IO
)
1512 ppc4xx_setup_one_pciex_POM(port
, hose
, mbase
,
1513 hose
->io_base_phys
, 0,
1514 0x10000, IORESOURCE_IO
, 2);
1517 static void __init
ppc4xx_configure_pciex_PIMs(struct ppc4xx_pciex_port
*port
,
1518 struct pci_controller
*hose
,
1519 void __iomem
*mbase
,
1520 struct resource
*res
)
1522 resource_size_t size
= res
->end
- res
->start
+ 1;
1525 if (port
->endpoint
) {
1526 resource_size_t ep_addr
= 0;
1527 resource_size_t ep_size
= 32 << 20;
1529 /* Currently we map a fixed 64MByte window to PLB address
1530 * 0 (SDRAM). This should probably be configurable via a dts
1534 /* Calculate window size */
1535 sa
= (0xffffffffffffffffull
<< ilog2(ep_size
));
1538 out_le32(mbase
+ PECFG_BAR0HMPA
, RES_TO_U32_HIGH(sa
));
1539 out_le32(mbase
+ PECFG_BAR0LMPA
, RES_TO_U32_LOW(sa
) |
1540 PCI_BASE_ADDRESS_MEM_TYPE_64
);
1542 /* Disable BAR1 & BAR2 */
1543 out_le32(mbase
+ PECFG_BAR1MPA
, 0);
1544 out_le32(mbase
+ PECFG_BAR2HMPA
, 0);
1545 out_le32(mbase
+ PECFG_BAR2LMPA
, 0);
1547 out_le32(mbase
+ PECFG_PIM01SAH
, RES_TO_U32_HIGH(sa
));
1548 out_le32(mbase
+ PECFG_PIM01SAL
, RES_TO_U32_LOW(sa
));
1550 out_le32(mbase
+ PCI_BASE_ADDRESS_0
, RES_TO_U32_LOW(ep_addr
));
1551 out_le32(mbase
+ PCI_BASE_ADDRESS_1
, RES_TO_U32_HIGH(ep_addr
));
1553 /* Calculate window size */
1554 sa
= (0xffffffffffffffffull
<< ilog2(size
));
1555 if (res
->flags
& IORESOURCE_PREFETCH
)
1558 out_le32(mbase
+ PECFG_BAR0HMPA
, RES_TO_U32_HIGH(sa
));
1559 out_le32(mbase
+ PECFG_BAR0LMPA
, RES_TO_U32_LOW(sa
));
1561 /* The setup of the split looks weird to me ... let's see
1564 out_le32(mbase
+ PECFG_PIM0LAL
, 0x00000000);
1565 out_le32(mbase
+ PECFG_PIM0LAH
, 0x00000000);
1566 out_le32(mbase
+ PECFG_PIM1LAL
, 0x00000000);
1567 out_le32(mbase
+ PECFG_PIM1LAH
, 0x00000000);
1568 out_le32(mbase
+ PECFG_PIM01SAH
, 0xffff0000);
1569 out_le32(mbase
+ PECFG_PIM01SAL
, 0x00000000);
1571 out_le32(mbase
+ PCI_BASE_ADDRESS_0
, RES_TO_U32_LOW(res
->start
));
1572 out_le32(mbase
+ PCI_BASE_ADDRESS_1
, RES_TO_U32_HIGH(res
->start
));
1575 /* Enable inbound mapping */
1576 out_le32(mbase
+ PECFG_PIMEN
, 0x1);
1578 /* Enable I/O, Mem, and Busmaster cycles */
1579 out_le16(mbase
+ PCI_COMMAND
,
1580 in_le16(mbase
+ PCI_COMMAND
) |
1581 PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
);
1584 static void __init
ppc4xx_pciex_port_setup_hose(struct ppc4xx_pciex_port
*port
)
1586 struct resource dma_window
;
1587 struct pci_controller
*hose
= NULL
;
1588 const int *bus_range
;
1589 int primary
= 0, busses
;
1590 void __iomem
*mbase
= NULL
, *cfg_data
= NULL
;
1594 /* Check if primary bridge */
1595 if (of_get_property(port
->node
, "primary", NULL
))
1598 /* Get bus range if any */
1599 bus_range
= of_get_property(port
->node
, "bus-range", NULL
);
1601 /* Allocate the host controller data structure */
1602 hose
= pcibios_alloc_controller(port
->node
);
1606 /* We stick the port number in "indirect_type" so the config space
1607 * ops can retrieve the port data structure easily
1609 hose
->indirect_type
= port
->index
;
1612 hose
->first_busno
= bus_range
? bus_range
[0] : 0x0;
1613 hose
->last_busno
= bus_range
? bus_range
[1] : 0xff;
1615 /* Because of how big mapping the config space is (1M per bus), we
1616 * limit how many busses we support. In the long run, we could replace
1617 * that with something akin to kmap_atomic instead. We set aside 1 bus
1618 * for the host itself too.
1620 busses
= hose
->last_busno
- hose
->first_busno
; /* This is off by 1 */
1621 if (busses
> MAX_PCIE_BUS_MAPPED
) {
1622 busses
= MAX_PCIE_BUS_MAPPED
;
1623 hose
->last_busno
= hose
->first_busno
+ busses
;
1626 if (!port
->endpoint
) {
1627 /* Only map the external config space in cfg_data for
1628 * PCIe root-complexes. External space is 1M per bus
1630 cfg_data
= ioremap(port
->cfg_space
.start
+
1631 (hose
->first_busno
+ 1) * 0x100000,
1633 if (cfg_data
== NULL
) {
1634 printk(KERN_ERR
"%s: Can't map external config space !",
1635 port
->node
->full_name
);
1638 hose
->cfg_data
= cfg_data
;
1641 /* Always map the host config space in cfg_addr.
1642 * Internal space is 4K
1644 mbase
= ioremap(port
->cfg_space
.start
+ 0x10000000, 0x1000);
1645 if (mbase
== NULL
) {
1646 printk(KERN_ERR
"%s: Can't map internal config space !",
1647 port
->node
->full_name
);
1650 hose
->cfg_addr
= mbase
;
1652 pr_debug("PCIE %s, bus %d..%d\n", port
->node
->full_name
,
1653 hose
->first_busno
, hose
->last_busno
);
1654 pr_debug(" config space mapped at: root @0x%p, other @0x%p\n",
1655 hose
->cfg_addr
, hose
->cfg_data
);
1657 /* Setup config space */
1658 hose
->ops
= &ppc4xx_pciex_pci_ops
;
1660 mbase
= (void __iomem
*)hose
->cfg_addr
;
1662 if (!port
->endpoint
) {
1664 * Set bus numbers on our root port
1666 out_8(mbase
+ PCI_PRIMARY_BUS
, hose
->first_busno
);
1667 out_8(mbase
+ PCI_SECONDARY_BUS
, hose
->first_busno
+ 1);
1668 out_8(mbase
+ PCI_SUBORDINATE_BUS
, hose
->last_busno
);
1672 * OMRs are already reset, also disable PIMs
1674 out_le32(mbase
+ PECFG_PIMEN
, 0);
1676 /* Parse outbound mapping resources */
1677 pci_process_bridge_OF_ranges(hose
, port
->node
, primary
);
1679 /* Parse inbound mapping resources */
1680 if (ppc4xx_parse_dma_ranges(hose
, mbase
, &dma_window
) != 0)
1683 /* Configure outbound ranges POMs */
1684 ppc4xx_configure_pciex_POMs(port
, hose
, mbase
);
1686 /* Configure inbound ranges PIMs */
1687 ppc4xx_configure_pciex_PIMs(port
, hose
, mbase
, &dma_window
);
1689 /* The root complex doesn't show up if we don't set some vendor
1690 * and device IDs into it. The defaults below are the same bogus
1691 * one that the initial code in arch/ppc had. This can be
1692 * overwritten by setting the "vendor-id/device-id" properties
1693 * in the pciex node.
1696 /* Get the (optional) vendor-/device-id from the device-tree */
1697 pval
= of_get_property(port
->node
, "vendor-id", NULL
);
1701 if (!port
->endpoint
)
1702 val
= 0xaaa0 + port
->index
;
1704 val
= 0xeee0 + port
->index
;
1706 out_le16(mbase
+ 0x200, val
);
1708 pval
= of_get_property(port
->node
, "device-id", NULL
);
1712 if (!port
->endpoint
)
1713 val
= 0xbed0 + port
->index
;
1715 val
= 0xfed0 + port
->index
;
1717 out_le16(mbase
+ 0x202, val
);
1719 if (!port
->endpoint
) {
1720 /* Set Class Code to PCI-PCI bridge and Revision Id to 1 */
1721 out_le32(mbase
+ 0x208, 0x06040001);
1723 printk(KERN_INFO
"PCIE%d: successfully set as root-complex\n",
1726 /* Set Class Code to Processor/PPC */
1727 out_le32(mbase
+ 0x208, 0x0b200001);
1729 printk(KERN_INFO
"PCIE%d: successfully set as endpoint\n",
1736 pcibios_free_controller(hose
);
1743 static void __init
ppc4xx_probe_pciex_bridge(struct device_node
*np
)
1745 struct ppc4xx_pciex_port
*port
;
1751 /* First, proceed to core initialization as we assume there's
1752 * only one PCIe core in the system
1754 if (ppc4xx_pciex_check_core_init(np
))
1757 /* Get the port number from the device-tree */
1758 pval
= of_get_property(np
, "port", NULL
);
1760 printk(KERN_ERR
"PCIE: Can't find port number for %s\n",
1765 if (portno
>= ppc4xx_pciex_port_count
) {
1766 printk(KERN_ERR
"PCIE: port number out of range for %s\n",
1770 port
= &ppc4xx_pciex_ports
[portno
];
1771 port
->index
= portno
;
1774 * Check if device is enabled
1776 if (!of_device_is_available(np
)) {
1777 printk(KERN_INFO
"PCIE%d: Port disabled via device-tree\n", port
->index
);
1781 port
->node
= of_node_get(np
);
1782 pval
= of_get_property(np
, "sdr-base", NULL
);
1784 printk(KERN_ERR
"PCIE: missing sdr-base for %s\n",
1788 port
->sdr_base
= *pval
;
1790 /* Check if device_type property is set to "pci" or "pci-endpoint".
1791 * Resulting from this setup this PCIe port will be configured
1792 * as root-complex or as endpoint.
1794 val
= of_get_property(port
->node
, "device_type", NULL
);
1795 if (!strcmp(val
, "pci-endpoint")) {
1797 } else if (!strcmp(val
, "pci")) {
1800 printk(KERN_ERR
"PCIE: missing or incorrect device_type for %s\n",
1805 /* Fetch config space registers address */
1806 if (of_address_to_resource(np
, 0, &port
->cfg_space
)) {
1807 printk(KERN_ERR
"%s: Can't get PCI-E config space !",
1811 /* Fetch host bridge internal registers address */
1812 if (of_address_to_resource(np
, 1, &port
->utl_regs
)) {
1813 printk(KERN_ERR
"%s: Can't get UTL register base !",
1819 dcrs
= dcr_resource_start(np
, 0);
1821 printk(KERN_ERR
"%s: Can't get DCR register base !",
1825 port
->dcrs
= dcr_map(np
, dcrs
, dcr_resource_len(np
, 0));
1827 /* Initialize the port specific registers */
1828 if (ppc4xx_pciex_port_init(port
)) {
1829 printk(KERN_WARNING
"PCIE%d: Port init failed\n", port
->index
);
1833 /* Setup the linux hose data structure */
1834 ppc4xx_pciex_port_setup_hose(port
);
1837 #endif /* CONFIG_PPC4xx_PCI_EXPRESS */
1839 static int __init
ppc4xx_pci_find_bridges(void)
1841 struct device_node
*np
;
1843 ppc_pci_flags
|= PPC_PCI_ENABLE_PROC_DOMAINS
| PPC_PCI_COMPAT_DOMAIN_0
;
1845 #ifdef CONFIG_PPC4xx_PCI_EXPRESS
1846 for_each_compatible_node(np
, NULL
, "ibm,plb-pciex")
1847 ppc4xx_probe_pciex_bridge(np
);
1849 for_each_compatible_node(np
, NULL
, "ibm,plb-pcix")
1850 ppc4xx_probe_pcix_bridge(np
);
1851 for_each_compatible_node(np
, NULL
, "ibm,plb-pci")
1852 ppc4xx_probe_pci_bridge(np
);
1856 arch_initcall(ppc4xx_pci_find_bridges
);