2 * Copyright 2004-2008 Analog Devices Inc.
4 * Licensed under the GPL-2 or later.
7 #include <linux/linkage.h>
8 #include <asm/blackfin.h>
15 [--SP] = ( R7:0, P5:0 );
31 call _test_pll_locked;
46 call _test_pll_locked;
49 ( R7:0, P5:0 ) = [SP++];
53 ENTRY(_hibernate_mode)
54 [--SP] = ( R7:0, P5:0 );
73 ENDPROC(_hibernate_mode)
76 [--SP] = ( R7:0, P5:0 );
90 call _set_dram_srfs; /* Set SDRAM Self Refresh */
96 W[P0] = R0.l; /* Set Max VCO to SCLK divider */
101 R0.L = (CONFIG_MIN_VCO_HZ/CONFIG_CLKIN_HZ) << 9;
102 W[P0] = R0.l; /* Set Min CLKIN to VCO multiplier */
107 call _test_pll_locked;
117 R2 = DEPOSIT(R7, R1);
118 W[P0] = R2; /* Set Min Core Voltage */
123 call _test_pll_locked;
128 call _set_sic_iwr; /* Set Awake from IDLE */
134 W[P0] = R0.L; /* Turn CCLK OFF */
138 call _test_pll_locked;
141 R1 = IWR_DISABLE_ALL;
142 R2 = IWR_DISABLE_ALL;
144 call _set_sic_iwr; /* Set Awake from IDLE PLL */
153 call _test_pll_locked;
157 W[P0]= R6; /* Restore CCLK and SCLK divider */
161 w[p0] = R5; /* Restore VCO multiplier */
163 call _test_pll_locked;
165 call _unset_dram_srfs; /* SDRAM Self Refresh Off */
170 ( R7:0, P5:0 ) = [SP++];
172 ENDPROC(_sleep_deeper)
174 ENTRY(_set_dram_srfs)
175 /* set the dram to self refresh mode */
177 #if defined(EBIU_RSTCTL) /* DDR */
178 P0.H = hi(EBIU_RSTCTL);
179 P0.L = lo(EBIU_RSTCTL);
181 BITSET(R2, 3); /* SRREQ enter self-refresh mode */
189 P0.L = lo(EBIU_SDGCTL);
190 P0.H = hi(EBIU_SDGCTL);
192 BITSET(R2, 24); /* SRFS enter self-refresh mode */
196 P0.L = lo(EBIU_SDSTAT);
197 P0.H = hi(EBIU_SDSTAT);
201 cc = BITTST(R2, 1); /* SDSRA poll self-refresh status */
204 P0.L = lo(EBIU_SDGCTL);
205 P0.H = hi(EBIU_SDGCTL);
207 BITCLR(R2, 0); /* SCTLE disable CLKOUT */
211 ENDPROC(_set_dram_srfs)
213 ENTRY(_unset_dram_srfs)
214 /* set the dram out of self refresh mode */
215 #if defined(EBIU_RSTCTL) /* DDR */
216 P0.H = hi(EBIU_RSTCTL);
217 P0.L = lo(EBIU_RSTCTL);
219 BITCLR(R2, 3); /* clear SRREQ bit */
221 #elif defined(EBIU_SDGCTL) /* SDRAM */
223 P0.L = lo(EBIU_SDGCTL); /* release CLKOUT from self-refresh */
224 P0.H = hi(EBIU_SDGCTL);
226 BITSET(R2, 0); /* SCTLE enable CLKOUT */
230 P0.L = lo(EBIU_SDGCTL); /* release SDRAM from self-refresh */
231 P0.H = hi(EBIU_SDGCTL);
233 BITCLR(R2, 24); /* clear SRFS bit */
238 ENDPROC(_unset_dram_srfs)
241 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) || \
242 defined(CONFIG_BF538) || defined(CONFIG_BF539) || defined(CONFIG_BF51x)
248 #if defined(CONFIG_BF54x)
261 ENDPROC(_set_sic_iwr)
263 ENTRY(_test_pll_locked)
271 ENDPROC(_test_pll_locked)
276 [--SP] = ( R7:0, P5:0 );
278 /* Save System MMRs */
284 PM_SYS_PUSH(SIC_IMASK0)
287 PM_SYS_PUSH(SIC_IMASK1)
290 PM_SYS_PUSH(SIC_IMASK2)
293 PM_SYS_PUSH(SIC_IMASK)
296 PM_SYS_PUSH(SICA_IMASK0)
299 PM_SYS_PUSH(SICA_IMASK1)
302 PM_SYS_PUSH(SIC_IAR0)
303 PM_SYS_PUSH(SIC_IAR1)
304 PM_SYS_PUSH(SIC_IAR2)
307 PM_SYS_PUSH(SIC_IAR3)
310 PM_SYS_PUSH(SIC_IAR4)
311 PM_SYS_PUSH(SIC_IAR5)
312 PM_SYS_PUSH(SIC_IAR6)
315 PM_SYS_PUSH(SIC_IAR7)
318 PM_SYS_PUSH(SIC_IAR8)
319 PM_SYS_PUSH(SIC_IAR9)
320 PM_SYS_PUSH(SIC_IAR10)
321 PM_SYS_PUSH(SIC_IAR11)
325 PM_SYS_PUSH(SICA_IAR0)
326 PM_SYS_PUSH(SICA_IAR1)
327 PM_SYS_PUSH(SICA_IAR2)
328 PM_SYS_PUSH(SICA_IAR3)
329 PM_SYS_PUSH(SICA_IAR4)
330 PM_SYS_PUSH(SICA_IAR5)
331 PM_SYS_PUSH(SICA_IAR6)
332 PM_SYS_PUSH(SICA_IAR7)
339 PM_SYS_PUSH(SIC_IWR0)
342 PM_SYS_PUSH(SIC_IWR1)
345 PM_SYS_PUSH(SIC_IWR2)
348 PM_SYS_PUSH(SICA_IWR0)
351 PM_SYS_PUSH(SICA_IWR1)
355 PM_SYS_PUSH(PINT0_MASK_SET)
356 PM_SYS_PUSH(PINT1_MASK_SET)
357 PM_SYS_PUSH(PINT2_MASK_SET)
358 PM_SYS_PUSH(PINT3_MASK_SET)
359 PM_SYS_PUSH(PINT0_ASSIGN)
360 PM_SYS_PUSH(PINT1_ASSIGN)
361 PM_SYS_PUSH(PINT2_ASSIGN)
362 PM_SYS_PUSH(PINT3_ASSIGN)
363 PM_SYS_PUSH(PINT0_INVERT_SET)
364 PM_SYS_PUSH(PINT1_INVERT_SET)
365 PM_SYS_PUSH(PINT2_INVERT_SET)
366 PM_SYS_PUSH(PINT3_INVERT_SET)
367 PM_SYS_PUSH(PINT0_EDGE_SET)
368 PM_SYS_PUSH(PINT1_EDGE_SET)
369 PM_SYS_PUSH(PINT2_EDGE_SET)
370 PM_SYS_PUSH(PINT3_EDGE_SET)
373 PM_SYS_PUSH(EBIU_AMBCTL0)
374 PM_SYS_PUSH(EBIU_AMBCTL1)
375 PM_SYS_PUSH16(EBIU_AMGCTL)
378 PM_SYS_PUSH(EBIU_MBSCTL)
379 PM_SYS_PUSH(EBIU_MODE)
380 PM_SYS_PUSH(EBIU_FCTL)
384 PM_SYS_PUSH16(PORTCIO_DIR)
385 PM_SYS_PUSH16(PORTCIO_INEN)
386 PM_SYS_PUSH16(PORTCIO)
387 PM_SYS_PUSH16(PORTCIO_FER)
388 PM_SYS_PUSH16(PORTDIO_DIR)
389 PM_SYS_PUSH16(PORTDIO_INEN)
390 PM_SYS_PUSH16(PORTDIO)
391 PM_SYS_PUSH16(PORTDIO_FER)
392 PM_SYS_PUSH16(PORTEIO_DIR)
393 PM_SYS_PUSH16(PORTEIO_INEN)
394 PM_SYS_PUSH16(PORTEIO)
395 PM_SYS_PUSH16(PORTEIO_FER)
401 P0.H = hi(SRAM_BASE_ADDRESS);
402 P0.L = lo(SRAM_BASE_ADDRESS);
404 PM_PUSH(DMEM_CONTROL)
415 PM_PUSH(DCPLB_ADDR10)
416 PM_PUSH(DCPLB_ADDR11)
417 PM_PUSH(DCPLB_ADDR12)
418 PM_PUSH(DCPLB_ADDR13)
419 PM_PUSH(DCPLB_ADDR14)
420 PM_PUSH(DCPLB_ADDR15)
431 PM_PUSH(DCPLB_DATA10)
432 PM_PUSH(DCPLB_DATA11)
433 PM_PUSH(DCPLB_DATA12)
434 PM_PUSH(DCPLB_DATA13)
435 PM_PUSH(DCPLB_DATA14)
436 PM_PUSH(DCPLB_DATA15)
437 PM_PUSH(IMEM_CONTROL)
448 PM_PUSH(ICPLB_ADDR10)
449 PM_PUSH(ICPLB_ADDR11)
450 PM_PUSH(ICPLB_ADDR12)
451 PM_PUSH(ICPLB_ADDR13)
452 PM_PUSH(ICPLB_ADDR14)
453 PM_PUSH(ICPLB_ADDR15)
464 PM_PUSH(ICPLB_DATA10)
465 PM_PUSH(ICPLB_DATA11)
466 PM_PUSH(ICPLB_DATA12)
467 PM_PUSH(ICPLB_DATA13)
468 PM_PUSH(ICPLB_DATA14)
469 PM_PUSH(ICPLB_DATA15)
495 /* Save Core Registers */
497 [--sp] = ( R7:0, P5:0 );
544 /* Save Magic, return address and Stack Pointer */
547 R0.H = 0xDEAD; /* Hibernate Magic */
549 [P0++] = R0; /* Store Hibernate Magic */
550 R0.H = .Lpm_resume_here;
551 R0.L = .Lpm_resume_here;
552 [P0++] = R0; /* Save Return Address */
553 [P0++] = SP; /* Save Stack Pointer */
554 P0.H = _hibernate_mode;
555 P0.L = _hibernate_mode;
557 call (P0); /* Goodbye */
561 /* Restore Core Registers */
608 ( R7 : 0, P5 : 0) = [ SP ++ ];
611 /* Restore Core MMRs */
704 /* Restore System MMRs */
711 PM_SYS_POP16(PORTEIO_FER)
712 PM_SYS_POP16(PORTEIO)
713 PM_SYS_POP16(PORTEIO_INEN)
714 PM_SYS_POP16(PORTEIO_DIR)
715 PM_SYS_POP16(PORTDIO_FER)
716 PM_SYS_POP16(PORTDIO)
717 PM_SYS_POP16(PORTDIO_INEN)
718 PM_SYS_POP16(PORTDIO_DIR)
719 PM_SYS_POP16(PORTCIO_FER)
720 PM_SYS_POP16(PORTCIO)
721 PM_SYS_POP16(PORTCIO_INEN)
722 PM_SYS_POP16(PORTCIO_DIR)
726 PM_SYS_POP(EBIU_FCTL)
727 PM_SYS_POP(EBIU_MODE)
728 PM_SYS_POP(EBIU_MBSCTL)
730 PM_SYS_POP16(EBIU_AMGCTL)
731 PM_SYS_POP(EBIU_AMBCTL1)
732 PM_SYS_POP(EBIU_AMBCTL0)
735 PM_SYS_POP(PINT3_EDGE_SET)
736 PM_SYS_POP(PINT2_EDGE_SET)
737 PM_SYS_POP(PINT1_EDGE_SET)
738 PM_SYS_POP(PINT0_EDGE_SET)
739 PM_SYS_POP(PINT3_INVERT_SET)
740 PM_SYS_POP(PINT2_INVERT_SET)
741 PM_SYS_POP(PINT1_INVERT_SET)
742 PM_SYS_POP(PINT0_INVERT_SET)
743 PM_SYS_POP(PINT3_ASSIGN)
744 PM_SYS_POP(PINT2_ASSIGN)
745 PM_SYS_POP(PINT1_ASSIGN)
746 PM_SYS_POP(PINT0_ASSIGN)
747 PM_SYS_POP(PINT3_MASK_SET)
748 PM_SYS_POP(PINT2_MASK_SET)
749 PM_SYS_POP(PINT1_MASK_SET)
750 PM_SYS_POP(PINT0_MASK_SET)
754 PM_SYS_POP(SICA_IWR1)
757 PM_SYS_POP(SICA_IWR0)
773 PM_SYS_POP(SICA_IAR7)
774 PM_SYS_POP(SICA_IAR6)
775 PM_SYS_POP(SICA_IAR5)
776 PM_SYS_POP(SICA_IAR4)
777 PM_SYS_POP(SICA_IAR3)
778 PM_SYS_POP(SICA_IAR2)
779 PM_SYS_POP(SICA_IAR1)
780 PM_SYS_POP(SICA_IAR0)
784 PM_SYS_POP(SIC_IAR11)
785 PM_SYS_POP(SIC_IAR10)
806 PM_SYS_POP(SICA_IMASK1)
809 PM_SYS_POP(SICA_IMASK0)
812 PM_SYS_POP(SIC_IMASK)
815 PM_SYS_POP(SIC_IMASK2)
818 PM_SYS_POP(SIC_IMASK1)
821 PM_SYS_POP(SIC_IMASK0)
824 [--sp] = RETI; /* Clear Global Interrupt Disable */
828 ( R7:0, P5:0 ) = [SP++];
830 ENDPROC(_do_hibernate)