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KVM: Fix guest sysenter on vmx
[linux-2.6/kvm.git] / drivers / net / ns83820.c
blob9ec6e9e54f47781b99d8c4402bc6930bd0807f6c
1 #define VERSION "0.22"
2 /* ns83820.c by Benjamin LaHaise with contributions.
3 *
4 * Questions/comments/discussion to linux-ns83820@kvack.org.
5 *
6 * $Revision: 1.34.2.23 $
7 *
8 * Copyright 2001 Benjamin LaHaise.
9 * Copyright 2001, 2002 Red Hat.
10 *
11 * Mmmm, chocolate vanilla mocha...
12 *
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
27 *
28 *
29 * ChangeLog
30 * =========
31 * 20010414 0.1 - created
32 * 20010622 0.2 - basic rx and tx.
33 * 20010711 0.3 - added duplex and link state detection support.
34 * 20010713 0.4 - zero copy, no hangs.
35 * 0.5 - 64 bit dma support (davem will hate me for this)
36 * - disable jumbo frames to avoid tx hangs
37 * - work around tx deadlocks on my 1.02 card via
38 * fiddling with TXCFG
39 * 20010810 0.6 - use pci dma api for ringbuffers, work on ia64
40 * 20010816 0.7 - misc cleanups
41 * 20010826 0.8 - fix critical zero copy bugs
42 * 0.9 - internal experiment
43 * 20010827 0.10 - fix ia64 unaligned access.
44 * 20010906 0.11 - accept all packets with checksum errors as
45 * otherwise fragments get lost
46 * - fix >> 32 bugs
47 * 0.12 - add statistics counters
48 * - add allmulti/promisc support
49 * 20011009 0.13 - hotplug support, other smaller pci api cleanups
50 * 20011204 0.13a - optical transceiver support added
51 * by Michael Clark <michael@metaparadigm.com>
52 * 20011205 0.13b - call register_netdev earlier in initialization
53 * suppress duplicate link status messages
54 * 20011117 0.14 - ethtool GDRVINFO, GLINK support from jgarzik
55 * 20011204 0.15 get ppc (big endian) working
56 * 20011218 0.16 various cleanups
57 * 20020310 0.17 speedups
58 * 20020610 0.18 - actually use the pci dma api for highmem
59 * - remove pci latency register fiddling
60 * 0.19 - better bist support
61 * - add ihr and reset_phy parameters
62 * - gmii bus probing
63 * - fix missed txok introduced during performance
64 * tuning
65 * 0.20 - fix stupid RFEN thinko. i am such a smurf.
66 * 20040828 0.21 - add hardware vlan accleration
67 * by Neil Horman <nhorman@redhat.com>
68 * 20050406 0.22 - improved DAC ifdefs from Andi Kleen
69 * - removal of dead code from Adrian Bunk
70 * - fix half duplex collision behaviour
71 * Driver Overview
72 * ===============
73 *
74 * This driver was originally written for the National Semiconductor
75 * 83820 chip, a 10/100/1000 Mbps 64 bit PCI ethernet NIC. Hopefully
76 * this code will turn out to be a) clean, b) correct, and c) fast.
77 * With that in mind, I'm aiming to split the code up as much as
78 * reasonably possible. At present there are X major sections that
79 * break down into a) packet receive, b) packet transmit, c) link
80 * management, d) initialization and configuration. Where possible,
81 * these code paths are designed to run in parallel.
82 *
83 * This driver has been tested and found to work with the following
84 * cards (in no particular order):
85 *
86 * Cameo SOHO-GA2000T SOHO-GA2500T
87 * D-Link DGE-500T
88 * PureData PDP8023Z-TG
89 * SMC SMC9452TX SMC9462TX
90 * Netgear GA621
91 *
92 * Special thanks to SMC for providing hardware to test this driver on.
93 *
94 * Reports of success or failure would be greatly appreciated.
95 */
96 //#define dprintk printk
97 #define dprintk(x...) do { } while (0)
98
99 #include <linux/module.h>
100 #include <linux/moduleparam.h>
101 #include <linux/types.h>
102 #include <linux/pci.h>
103 #include <linux/dma-mapping.h>
104 #include <linux/netdevice.h>
105 #include <linux/etherdevice.h>
106 #include <linux/delay.h>
107 #include <linux/smp_lock.h>
108 #include <linux/workqueue.h>
109 #include <linux/init.h>
110 #include <linux/ip.h> /* for iph */
111 #include <linux/in.h> /* for IPPROTO_... */
112 #include <linux/compiler.h>
113 #include <linux/prefetch.h>
114 #include <linux/ethtool.h>
115 #include <linux/timer.h>
116 #include <linux/if_vlan.h>
117 #include <linux/rtnetlink.h>
118 #include <linux/jiffies.h>
119
120 #include <asm/io.h>
121 #include <asm/uaccess.h>
122 #include <asm/system.h>
123
124 #define DRV_NAME "ns83820"
125
126 /* Global parameters. See module_param near the bottom. */
127 static int ihr = 2;
128 static int reset_phy = 0;
129 static int lnksts = 0; /* CFG_LNKSTS bit polarity */
130
131 /* Dprintk is used for more interesting debug events */
132 #undef Dprintk
133 #define Dprintk dprintk
134
135 /* tunables */
136 #define RX_BUF_SIZE 1500 /* 8192 */
137 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
138 #define NS83820_VLAN_ACCEL_SUPPORT
139 #endif
140
141 /* Must not exceed ~65000. */
142 #define NR_RX_DESC 64
143 #define NR_TX_DESC 128
144
145 /* not tunable */
146 #define REAL_RX_BUF_SIZE (RX_BUF_SIZE + 14) /* rx/tx mac addr + type */
147
148 #define MIN_TX_DESC_FREE 8
149
150 /* register defines */
151 #define CFGCS 0x04
152
153 #define CR_TXE 0x00000001
154 #define CR_TXD 0x00000002
155 /* Ramit : Here's a tip, don't do a RXD immediately followed by an RXE
156 * The Receive engine skips one descriptor and moves
157 * onto the next one!! */
158 #define CR_RXE 0x00000004
159 #define CR_RXD 0x00000008
160 #define CR_TXR 0x00000010
161 #define CR_RXR 0x00000020
162 #define CR_SWI 0x00000080
163 #define CR_RST 0x00000100
164
165 #define PTSCR_EEBIST_FAIL 0x00000001
166 #define PTSCR_EEBIST_EN 0x00000002
167 #define PTSCR_EELOAD_EN 0x00000004
168 #define PTSCR_RBIST_FAIL 0x000001b8
169 #define PTSCR_RBIST_DONE 0x00000200
170 #define PTSCR_RBIST_EN 0x00000400
171 #define PTSCR_RBIST_RST 0x00002000
172
173 #define MEAR_EEDI 0x00000001
174 #define MEAR_EEDO 0x00000002
175 #define MEAR_EECLK 0x00000004
176 #define MEAR_EESEL 0x00000008
177 #define MEAR_MDIO 0x00000010
178 #define MEAR_MDDIR 0x00000020
179 #define MEAR_MDC 0x00000040
180
181 #define ISR_TXDESC3 0x40000000
182 #define ISR_TXDESC2 0x20000000
183 #define ISR_TXDESC1 0x10000000
184 #define ISR_TXDESC0 0x08000000
185 #define ISR_RXDESC3 0x04000000
186 #define ISR_RXDESC2 0x02000000
187 #define ISR_RXDESC1 0x01000000
188 #define ISR_RXDESC0 0x00800000
189 #define ISR_TXRCMP 0x00400000
190 #define ISR_RXRCMP 0x00200000
191 #define ISR_DPERR 0x00100000
192 #define ISR_SSERR 0x00080000
193 #define ISR_RMABT 0x00040000
194 #define ISR_RTABT 0x00020000
195 #define ISR_RXSOVR 0x00010000
196 #define ISR_HIBINT 0x00008000
197 #define ISR_PHY 0x00004000
198 #define ISR_PME 0x00002000
199 #define ISR_SWI 0x00001000
200 #define ISR_MIB 0x00000800
201 #define ISR_TXURN 0x00000400
202 #define ISR_TXIDLE 0x00000200
203 #define ISR_TXERR 0x00000100
204 #define ISR_TXDESC 0x00000080
205 #define ISR_TXOK 0x00000040
206 #define ISR_RXORN 0x00000020
207 #define ISR_RXIDLE 0x00000010
208 #define ISR_RXEARLY 0x00000008
209 #define ISR_RXERR 0x00000004
210 #define ISR_RXDESC 0x00000002
211 #define ISR_RXOK 0x00000001
212
213 #define TXCFG_CSI 0x80000000
214 #define TXCFG_HBI 0x40000000
215 #define TXCFG_MLB 0x20000000
216 #define TXCFG_ATP 0x10000000
217 #define TXCFG_ECRETRY 0x00800000
218 #define TXCFG_BRST_DIS 0x00080000
219 #define TXCFG_MXDMA1024 0x00000000
220 #define TXCFG_MXDMA512 0x00700000
221 #define TXCFG_MXDMA256 0x00600000
222 #define TXCFG_MXDMA128 0x00500000
223 #define TXCFG_MXDMA64 0x00400000
224 #define TXCFG_MXDMA32 0x00300000
225 #define TXCFG_MXDMA16 0x00200000
226 #define TXCFG_MXDMA8 0x00100000
227
228 #define CFG_LNKSTS 0x80000000
229 #define CFG_SPDSTS 0x60000000
230 #define CFG_SPDSTS1 0x40000000
231 #define CFG_SPDSTS0 0x20000000
232 #define CFG_DUPSTS 0x10000000
233 #define CFG_TBI_EN 0x01000000
234 #define CFG_MODE_1000 0x00400000
235 /* Ramit : Dont' ever use AUTO_1000, it never works and is buggy.
236 * Read the Phy response and then configure the MAC accordingly */
237 #define CFG_AUTO_1000 0x00200000
238 #define CFG_PINT_CTL 0x001c0000
239 #define CFG_PINT_DUPSTS 0x00100000
240 #define CFG_PINT_LNKSTS 0x00080000
241 #define CFG_PINT_SPDSTS 0x00040000
242 #define CFG_TMRTEST 0x00020000
243 #define CFG_MRM_DIS 0x00010000
244 #define CFG_MWI_DIS 0x00008000
245 #define CFG_T64ADDR 0x00004000
246 #define CFG_PCI64_DET 0x00002000
247 #define CFG_DATA64_EN 0x00001000
248 #define CFG_M64ADDR 0x00000800
249 #define CFG_PHY_RST 0x00000400
250 #define CFG_PHY_DIS 0x00000200
251 #define CFG_EXTSTS_EN 0x00000100
252 #define CFG_REQALG 0x00000080
253 #define CFG_SB 0x00000040
254 #define CFG_POW 0x00000020
255 #define CFG_EXD 0x00000010
256 #define CFG_PESEL 0x00000008
257 #define CFG_BROM_DIS 0x00000004
258 #define CFG_EXT_125 0x00000002
259 #define CFG_BEM 0x00000001
260
261 #define EXTSTS_UDPPKT 0x00200000
262 #define EXTSTS_TCPPKT 0x00080000
263 #define EXTSTS_IPPKT 0x00020000
264 #define EXTSTS_VPKT 0x00010000
265 #define EXTSTS_VTG_MASK 0x0000ffff
266
267 #define SPDSTS_POLARITY (CFG_SPDSTS1 | CFG_SPDSTS0 | CFG_DUPSTS | (lnksts ? CFG_LNKSTS : 0))
268
269 #define MIBC_MIBS 0x00000008
270 #define MIBC_ACLR 0x00000004
271 #define MIBC_FRZ 0x00000002
272 #define MIBC_WRN 0x00000001
273
274 #define PCR_PSEN (1 << 31)
275 #define PCR_PS_MCAST (1 << 30)
276 #define PCR_PS_DA (1 << 29)
277 #define PCR_STHI_8 (3 << 23)
278 #define PCR_STLO_4 (1 << 23)
279 #define PCR_FFHI_8K (3 << 21)
280 #define PCR_FFLO_4K (1 << 21)
281 #define PCR_PAUSE_CNT 0xFFFE
282
283 #define RXCFG_AEP 0x80000000
284 #define RXCFG_ARP 0x40000000
285 #define RXCFG_STRIPCRC 0x20000000
286 #define RXCFG_RX_FD 0x10000000
287 #define RXCFG_ALP 0x08000000
288 #define RXCFG_AIRL 0x04000000
289 #define RXCFG_MXDMA512 0x00700000
290 #define RXCFG_DRTH 0x0000003e
291 #define RXCFG_DRTH0 0x00000002
292
293 #define RFCR_RFEN 0x80000000
294 #define RFCR_AAB 0x40000000
295 #define RFCR_AAM 0x20000000
296 #define RFCR_AAU 0x10000000
297 #define RFCR_APM 0x08000000
298 #define RFCR_APAT 0x07800000
299 #define RFCR_APAT3 0x04000000
300 #define RFCR_APAT2 0x02000000
301 #define RFCR_APAT1 0x01000000
302 #define RFCR_APAT0 0x00800000
303 #define RFCR_AARP 0x00400000
304 #define RFCR_MHEN 0x00200000
305 #define RFCR_UHEN 0x00100000
306 #define RFCR_ULM 0x00080000
307
308 #define VRCR_RUDPE 0x00000080
309 #define VRCR_RTCPE 0x00000040
310 #define VRCR_RIPE 0x00000020
311 #define VRCR_IPEN 0x00000010
312 #define VRCR_DUTF 0x00000008
313 #define VRCR_DVTF 0x00000004
314 #define VRCR_VTREN 0x00000002
315 #define VRCR_VTDEN 0x00000001
316
317 #define VTCR_PPCHK 0x00000008
318 #define VTCR_GCHK 0x00000004
319 #define VTCR_VPPTI 0x00000002
320 #define VTCR_VGTI 0x00000001
321
322 #define CR 0x00
323 #define CFG 0x04
324 #define MEAR 0x08
325 #define PTSCR 0x0c
326 #define ISR 0x10
327 #define IMR 0x14
328 #define IER 0x18
329 #define IHR 0x1c
330 #define TXDP 0x20
331 #define TXDP_HI 0x24
332 #define TXCFG 0x28
333 #define GPIOR 0x2c
334 #define RXDP 0x30
335 #define RXDP_HI 0x34
336 #define RXCFG 0x38
337 #define PQCR 0x3c
338 #define WCSR 0x40
339 #define PCR 0x44
340 #define RFCR 0x48
341 #define RFDR 0x4c
342
343 #define SRR 0x58
344
345 #define VRCR 0xbc
346 #define VTCR 0xc0
347 #define VDR 0xc4
348 #define CCSR 0xcc
349
350 #define TBICR 0xe0
351 #define TBISR 0xe4
352 #define TANAR 0xe8
353 #define TANLPAR 0xec
354 #define TANER 0xf0
355 #define TESR 0xf4
356
357 #define TBICR_MR_AN_ENABLE 0x00001000
358 #define TBICR_MR_RESTART_AN 0x00000200
359
360 #define TBISR_MR_LINK_STATUS 0x00000020
361 #define TBISR_MR_AN_COMPLETE 0x00000004
362
363 #define TANAR_PS2 0x00000100
364 #define TANAR_PS1 0x00000080
365 #define TANAR_HALF_DUP 0x00000040
366 #define TANAR_FULL_DUP 0x00000020
367
368 #define GPIOR_GP5_OE 0x00000200
369 #define GPIOR_GP4_OE 0x00000100
370 #define GPIOR_GP3_OE 0x00000080
371 #define GPIOR_GP2_OE 0x00000040
372 #define GPIOR_GP1_OE 0x00000020
373 #define GPIOR_GP3_OUT 0x00000004
374 #define GPIOR_GP1_OUT 0x00000001
375
376 #define LINK_AUTONEGOTIATE 0x01
377 #define LINK_DOWN 0x02
378 #define LINK_UP 0x04
379
380 #define HW_ADDR_LEN sizeof(dma_addr_t)
381 #define desc_addr_set(desc, addr) \
382 do { \
383 ((desc)[0] = cpu_to_le32(addr)); \
384 if (HW_ADDR_LEN == 8) \
385 (desc)[1] = cpu_to_le32(((u64)addr) >> 32); \
386 } while(0)
387 #define desc_addr_get(desc) \
388 (le32_to_cpu((desc)[0]) | \
389 (HW_ADDR_LEN == 8 ? ((dma_addr_t)le32_to_cpu((desc)[1]))<<32 : 0))
390
391 #define DESC_LINK 0
392 #define DESC_BUFPTR (DESC_LINK + HW_ADDR_LEN/4)
393 #define DESC_CMDSTS (DESC_BUFPTR + HW_ADDR_LEN/4)
394 #define DESC_EXTSTS (DESC_CMDSTS + 4/4)
395
396 #define CMDSTS_OWN 0x80000000
397 #define CMDSTS_MORE 0x40000000
398 #define CMDSTS_INTR 0x20000000
399 #define CMDSTS_ERR 0x10000000
400 #define CMDSTS_OK 0x08000000
401 #define CMDSTS_RUNT 0x00200000
402 #define CMDSTS_LEN_MASK 0x0000ffff
403
404 #define CMDSTS_DEST_MASK 0x01800000
405 #define CMDSTS_DEST_SELF 0x00800000
406 #define CMDSTS_DEST_MULTI 0x01000000
407
408 #define DESC_SIZE 8 /* Should be cache line sized */
409
410 struct rx_info {
411 spinlock_t lock;
412 int up;
413 long idle;
414
415 struct sk_buff *skbs[NR_RX_DESC];
416
417 __le32 *next_rx_desc;
418 u16 next_rx, next_empty;
419
420 __le32 *descs;
421 dma_addr_t phy_descs;
422 };
423
424
425 struct ns83820 {
426 struct net_device_stats stats;
427 u8 __iomem *base;
428
429 struct pci_dev *pci_dev;
430 struct net_device *ndev;
431
432 #ifdef NS83820_VLAN_ACCEL_SUPPORT
433 struct vlan_group *vlgrp;
434 #endif
435
436 struct rx_info rx_info;
437 struct tasklet_struct rx_tasklet;
438
439 unsigned ihr;
440 struct work_struct tq_refill;
441
442 /* protects everything below. irqsave when using. */
443 spinlock_t misc_lock;
444
445 u32 CFG_cache;
446
447 u32 MEAR_cache;
448 u32 IMR_cache;
449
450 unsigned linkstate;
451
452 spinlock_t tx_lock;
453
454 u16 tx_done_idx;
455 u16 tx_idx;
456 volatile u16 tx_free_idx; /* idx of free desc chain */
457 u16 tx_intr_idx;
458
459 atomic_t nr_tx_skbs;
460 struct sk_buff *tx_skbs[NR_TX_DESC];
461
462 char pad[16] __attribute__((aligned(16)));
463 __le32 *tx_descs;
464 dma_addr_t tx_phy_descs;
465
466 struct timer_list tx_watchdog;
467 };
468
469 static inline struct ns83820 *PRIV(struct net_device *dev)
470 {
471 return netdev_priv(dev);
472 }
473
474 #define __kick_rx(dev) writel(CR_RXE, dev->base + CR)
475
476 static inline void kick_rx(struct net_device *ndev)
477 {
478 struct ns83820 *dev = PRIV(ndev);
479 dprintk("kick_rx: maybe kicking\n");
480 if (test_and_clear_bit(0, &dev->rx_info.idle)) {
481 dprintk("actually kicking\n");
482 writel(dev->rx_info.phy_descs +
483 (4 * DESC_SIZE * dev->rx_info.next_rx),
484 dev->base + RXDP);
485 if (dev->rx_info.next_rx == dev->rx_info.next_empty)
486 printk(KERN_DEBUG "%s: uh-oh: next_rx == next_empty???\n",
487 ndev->name);
488 __kick_rx(dev);
489 }
490 }
491
492 //free = (tx_done_idx + NR_TX_DESC-2 - free_idx) % NR_TX_DESC
493 #define start_tx_okay(dev) \
494 (((NR_TX_DESC-2 + dev->tx_done_idx - dev->tx_free_idx) % NR_TX_DESC) > MIN_TX_DESC_FREE)
495
496
497 #ifdef NS83820_VLAN_ACCEL_SUPPORT
498 static void ns83820_vlan_rx_register(struct net_device *ndev, struct vlan_group *grp)
499 {
500 struct ns83820 *dev = PRIV(ndev);
501
502 spin_lock_irq(&dev->misc_lock);
503 spin_lock(&dev->tx_lock);
504
505 dev->vlgrp = grp;
506
507 spin_unlock(&dev->tx_lock);
508 spin_unlock_irq(&dev->misc_lock);
509 }
510
511 static void ns83820_vlan_rx_kill_vid(struct net_device *ndev, unsigned short vid)
512 {
513 struct ns83820 *dev = PRIV(ndev);
514
515 spin_lock_irq(&dev->misc_lock);
516 spin_lock(&dev->tx_lock);
517 vlan_group_set_device(dev->vlgrp, vid, NULL);
518 spin_unlock(&dev->tx_lock);
519 spin_unlock_irq(&dev->misc_lock);
520 }
521 #endif
522
523 /* Packet Receiver
524 *
525 * The hardware supports linked lists of receive descriptors for
526 * which ownership is transfered back and forth by means of an
527 * ownership bit. While the hardware does support the use of a
528 * ring for receive descriptors, we only make use of a chain in
529 * an attempt to reduce bus traffic under heavy load scenarios.
530 * This will also make bugs a bit more obvious. The current code
531 * only makes use of a single rx chain; I hope to implement
532 * priority based rx for version 1.0. Goal: even under overload
533 * conditions, still route realtime traffic with as low jitter as
534 * possible.
535 */
536 static inline void build_rx_desc(struct ns83820 *dev, __le32 *desc, dma_addr_t link, dma_addr_t buf, u32 cmdsts, u32 extsts)
537 {
538 desc_addr_set(desc + DESC_LINK, link);
539 desc_addr_set(desc + DESC_BUFPTR, buf);
540 desc[DESC_EXTSTS] = cpu_to_le32(extsts);
541 mb();
542 desc[DESC_CMDSTS] = cpu_to_le32(cmdsts);
543 }
544
545 #define nr_rx_empty(dev) ((NR_RX_DESC-2 + dev->rx_info.next_rx - dev->rx_info.next_empty) % NR_RX_DESC)
546 static inline int ns83820_add_rx_skb(struct ns83820 *dev, struct sk_buff *skb)
547 {
548 unsigned next_empty;
549 u32 cmdsts;
550 __le32 *sg;
551 dma_addr_t buf;
552
553 next_empty = dev->rx_info.next_empty;
554
555 /* don't overrun last rx marker */
556 if (unlikely(nr_rx_empty(dev) <= 2)) {
557 kfree_skb(skb);
558 return 1;
559 }
560
561 #if 0
562 dprintk("next_empty[%d] nr_used[%d] next_rx[%d]\n",
563 dev->rx_info.next_empty,
564 dev->rx_info.nr_used,
565 dev->rx_info.next_rx
566 );
567 #endif
568
569 sg = dev->rx_info.descs + (next_empty * DESC_SIZE);
570 BUG_ON(NULL != dev->rx_info.skbs[next_empty]);
571 dev->rx_info.skbs[next_empty] = skb;
572
573 dev->rx_info.next_empty = (next_empty + 1) % NR_RX_DESC;
574 cmdsts = REAL_RX_BUF_SIZE | CMDSTS_INTR;
575 buf = pci_map_single(dev->pci_dev, skb->data,
576 REAL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
577 build_rx_desc(dev, sg, 0, buf, cmdsts, 0);
578 /* update link of previous rx */
579 if (likely(next_empty != dev->rx_info.next_rx))
580 dev->rx_info.descs[((NR_RX_DESC + next_empty - 1) % NR_RX_DESC) * DESC_SIZE] = cpu_to_le32(dev->rx_info.phy_descs + (next_empty * DESC_SIZE * 4));
581
582 return 0;
583 }
584
585 static inline int rx_refill(struct net_device *ndev, gfp_t gfp)
586 {
587 struct ns83820 *dev = PRIV(ndev);
588 unsigned i;
589 unsigned long flags = 0;
590
591 if (unlikely(nr_rx_empty(dev) <= 2))
592 return 0;
593
594 dprintk("rx_refill(%p)\n", ndev);
595 if (gfp == GFP_ATOMIC)
596 spin_lock_irqsave(&dev->rx_info.lock, flags);
597 for (i=0; i<NR_RX_DESC; i++) {
598 struct sk_buff *skb;
599 long res;
600 /* extra 16 bytes for alignment */
601 skb = __dev_alloc_skb(REAL_RX_BUF_SIZE+16, gfp);
602 if (unlikely(!skb))
603 break;
604
605 res = (long)skb->data & 0xf;
606 res = 0x10 - res;
607 res &= 0xf;
608 skb_reserve(skb, res);
609
610 skb->dev = ndev;
611 if (gfp != GFP_ATOMIC)
612 spin_lock_irqsave(&dev->rx_info.lock, flags);
613 res = ns83820_add_rx_skb(dev, skb);
614 if (gfp != GFP_ATOMIC)
615 spin_unlock_irqrestore(&dev->rx_info.lock, flags);
616 if (res) {
617 i = 1;
618 break;
619 }
620 }
621 if (gfp == GFP_ATOMIC)
622 spin_unlock_irqrestore(&dev->rx_info.lock, flags);
623
624 return i ? 0 : -ENOMEM;
625 }
626
627 static void FASTCALL(rx_refill_atomic(struct net_device *ndev));
628 static void fastcall rx_refill_atomic(struct net_device *ndev)
629 {
630 rx_refill(ndev, GFP_ATOMIC);
631 }
632
633 /* REFILL */
634 static inline void queue_refill(struct work_struct *work)
635 {
636 struct ns83820 *dev = container_of(work, struct ns83820, tq_refill);
637 struct net_device *ndev = dev->ndev;
638
639 rx_refill(ndev, GFP_KERNEL);
640 if (dev->rx_info.up)
641 kick_rx(ndev);
642 }
643
644 static inline void clear_rx_desc(struct ns83820 *dev, unsigned i)
645 {
646 build_rx_desc(dev, dev->rx_info.descs + (DESC_SIZE * i), 0, 0, CMDSTS_OWN, 0);
647 }
648
649 static void FASTCALL(phy_intr(struct net_device *ndev));
650 static void fastcall phy_intr(struct net_device *ndev)
651 {
652 struct ns83820 *dev = PRIV(ndev);
653 static const char *speeds[] = { "10", "100", "1000", "1000(?)", "1000F" };
654 u32 cfg, new_cfg;
655 u32 tbisr, tanar, tanlpar;
656 int speed, fullduplex, newlinkstate;
657
658 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
659
660 if (dev->CFG_cache & CFG_TBI_EN) {
661 /* we have an optical transceiver */
662 tbisr = readl(dev->base + TBISR);
663 tanar = readl(dev->base + TANAR);
664 tanlpar = readl(dev->base + TANLPAR);
665 dprintk("phy_intr: tbisr=%08x, tanar=%08x, tanlpar=%08x\n",
666 tbisr, tanar, tanlpar);
667
668 if ( (fullduplex = (tanlpar & TANAR_FULL_DUP)
669 && (tanar & TANAR_FULL_DUP)) ) {
670
671 /* both of us are full duplex */
672 writel(readl(dev->base + TXCFG)
673 | TXCFG_CSI | TXCFG_HBI | TXCFG_ATP,
674 dev->base + TXCFG);
675 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
676 dev->base + RXCFG);
677 /* Light up full duplex LED */
678 writel(readl(dev->base + GPIOR) | GPIOR_GP1_OUT,
679 dev->base + GPIOR);
680
681 } else if(((tanlpar & TANAR_HALF_DUP)
682 && (tanar & TANAR_HALF_DUP))
683 || ((tanlpar & TANAR_FULL_DUP)
684 && (tanar & TANAR_HALF_DUP))
685 || ((tanlpar & TANAR_HALF_DUP)
686 && (tanar & TANAR_FULL_DUP))) {
687
688 /* one or both of us are half duplex */
689 writel((readl(dev->base + TXCFG)
690 & ~(TXCFG_CSI | TXCFG_HBI)) | TXCFG_ATP,
691 dev->base + TXCFG);
692 writel(readl(dev->base + RXCFG) & ~RXCFG_RX_FD,
693 dev->base + RXCFG);
694 /* Turn off full duplex LED */
695 writel(readl(dev->base + GPIOR) & ~GPIOR_GP1_OUT,
696 dev->base + GPIOR);
697 }
698
699 speed = 4; /* 1000F */
700
701 } else {
702 /* we have a copper transceiver */
703 new_cfg = dev->CFG_cache & ~(CFG_SB | CFG_MODE_1000 | CFG_SPDSTS);
704
705 if (cfg & CFG_SPDSTS1)
706 new_cfg |= CFG_MODE_1000;
707 else
708 new_cfg &= ~CFG_MODE_1000;
709
710 speed = ((cfg / CFG_SPDSTS0) & 3);
711 fullduplex = (cfg & CFG_DUPSTS);
712
713 if (fullduplex) {
714 new_cfg |= CFG_SB;
715 writel(readl(dev->base + TXCFG)
716 | TXCFG_CSI | TXCFG_HBI,
717 dev->base + TXCFG);
718 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD,
719 dev->base + RXCFG);
720 } else {
721 writel(readl(dev->base + TXCFG)
722 & ~(TXCFG_CSI | TXCFG_HBI),
723 dev->base + TXCFG);
724 writel(readl(dev->base + RXCFG) & ~(RXCFG_RX_FD),
725 dev->base + RXCFG);
726 }
727
728 if ((cfg & CFG_LNKSTS) &&
729 ((new_cfg ^ dev->CFG_cache) != 0)) {
730 writel(new_cfg, dev->base + CFG);
731 dev->CFG_cache = new_cfg;
732 }
733
734 dev->CFG_cache &= ~CFG_SPDSTS;
735 dev->CFG_cache |= cfg & CFG_SPDSTS;
736 }
737
738 newlinkstate = (cfg & CFG_LNKSTS) ? LINK_UP : LINK_DOWN;
739
740 if (newlinkstate & LINK_UP
741 && dev->linkstate != newlinkstate) {
742 netif_start_queue(ndev);
743 netif_wake_queue(ndev);
744 printk(KERN_INFO "%s: link now %s mbps, %s duplex and up.\n",
745 ndev->name,
746 speeds[speed],
747 fullduplex ? "full" : "half");
748 } else if (newlinkstate & LINK_DOWN
749 && dev->linkstate != newlinkstate) {
750 netif_stop_queue(ndev);
751 printk(KERN_INFO "%s: link now down.\n", ndev->name);
752 }
753
754 dev->linkstate = newlinkstate;
755 }
756
757 static int ns83820_setup_rx(struct net_device *ndev)
758 {
759 struct ns83820 *dev = PRIV(ndev);
760 unsigned i;
761 int ret;
762
763 dprintk("ns83820_setup_rx(%p)\n", ndev);
764
765 dev->rx_info.idle = 1;
766 dev->rx_info.next_rx = 0;
767 dev->rx_info.next_rx_desc = dev->rx_info.descs;
768 dev->rx_info.next_empty = 0;
769
770 for (i=0; i<NR_RX_DESC; i++)
771 clear_rx_desc(dev, i);
772
773 writel(0, dev->base + RXDP_HI);
774 writel(dev->rx_info.phy_descs, dev->base + RXDP);
775
776 ret = rx_refill(ndev, GFP_KERNEL);
777 if (!ret) {
778 dprintk("starting receiver\n");
779 /* prevent the interrupt handler from stomping on us */
780 spin_lock_irq(&dev->rx_info.lock);
781
782 writel(0x0001, dev->base + CCSR);
783 writel(0, dev->base + RFCR);
784 writel(0x7fc00000, dev->base + RFCR);
785 writel(0xffc00000, dev->base + RFCR);
786
787 dev->rx_info.up = 1;
788
789 phy_intr(ndev);
790
791 /* Okay, let it rip */
792 spin_lock_irq(&dev->misc_lock);
793 dev->IMR_cache |= ISR_PHY;
794 dev->IMR_cache |= ISR_RXRCMP;
795 //dev->IMR_cache |= ISR_RXERR;
796 //dev->IMR_cache |= ISR_RXOK;
797 dev->IMR_cache |= ISR_RXORN;
798 dev->IMR_cache |= ISR_RXSOVR;
799 dev->IMR_cache |= ISR_RXDESC;
800 dev->IMR_cache |= ISR_RXIDLE;
801 dev->IMR_cache |= ISR_TXDESC;
802 dev->IMR_cache |= ISR_TXIDLE;
803
804 writel(dev->IMR_cache, dev->base + IMR);
805 writel(1, dev->base + IER);
806 spin_unlock(&dev->misc_lock);
807
808 kick_rx(ndev);
809
810 spin_unlock_irq(&dev->rx_info.lock);
811 }
812 return ret;
813 }
814
815 static void ns83820_cleanup_rx(struct ns83820 *dev)
816 {
817 unsigned i;
818 unsigned long flags;
819
820 dprintk("ns83820_cleanup_rx(%p)\n", dev);
821
822 /* disable receive interrupts */
823 spin_lock_irqsave(&dev->misc_lock, flags);
824 dev->IMR_cache &= ~(ISR_RXOK | ISR_RXDESC | ISR_RXERR | ISR_RXEARLY | ISR_RXIDLE);
825 writel(dev->IMR_cache, dev->base + IMR);
826 spin_unlock_irqrestore(&dev->misc_lock, flags);
827
828 /* synchronize with the interrupt handler and kill it */
829 dev->rx_info.up = 0;
830 synchronize_irq(dev->pci_dev->irq);
831
832 /* touch the pci bus... */
833 readl(dev->base + IMR);
834
835 /* assumes the transmitter is already disabled and reset */
836 writel(0, dev->base + RXDP_HI);
837 writel(0, dev->base + RXDP);
838
839 for (i=0; i<NR_RX_DESC; i++) {
840 struct sk_buff *skb = dev->rx_info.skbs[i];
841 dev->rx_info.skbs[i] = NULL;
842 clear_rx_desc(dev, i);
843 if (skb)
844 kfree_skb(skb);
845 }
846 }
847
848 static void FASTCALL(ns83820_rx_kick(struct net_device *ndev));
849 static void fastcall ns83820_rx_kick(struct net_device *ndev)
850 {
851 struct ns83820 *dev = PRIV(ndev);
852 /*if (nr_rx_empty(dev) >= NR_RX_DESC/4)*/ {
853 if (dev->rx_info.up) {
854 rx_refill_atomic(ndev);
855 kick_rx(ndev);
856 }
857 }
858
859 if (dev->rx_info.up && nr_rx_empty(dev) > NR_RX_DESC*3/4)
860 schedule_work(&dev->tq_refill);
861 else
862 kick_rx(ndev);
863 if (dev->rx_info.idle)
864 printk(KERN_DEBUG "%s: BAD\n", ndev->name);
865 }
866
867 /* rx_irq
868 *
869 */
870 static void FASTCALL(rx_irq(struct net_device *ndev));
871 static void fastcall rx_irq(struct net_device *ndev)
872 {
873 struct ns83820 *dev = PRIV(ndev);
874 struct rx_info *info = &dev->rx_info;
875 unsigned next_rx;
876 int rx_rc, len;
877 u32 cmdsts;
878 __le32 *desc;
879 unsigned long flags;
880 int nr = 0;
881
882 dprintk("rx_irq(%p)\n", ndev);
883 dprintk("rxdp: %08x, descs: %08lx next_rx[%d]: %p next_empty[%d]: %p\n",
884 readl(dev->base + RXDP),
885 (long)(dev->rx_info.phy_descs),
886 (int)dev->rx_info.next_rx,
887 (dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_rx)),
888 (int)dev->rx_info.next_empty,
889 (dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_empty))
890 );
891
892 spin_lock_irqsave(&info->lock, flags);
893 if (!info->up)
894 goto out;
895
896 dprintk("walking descs\n");
897 next_rx = info->next_rx;
898 desc = info->next_rx_desc;
899 while ((CMDSTS_OWN & (cmdsts = le32_to_cpu(desc[DESC_CMDSTS]))) &&
900 (cmdsts != CMDSTS_OWN)) {
901 struct sk_buff *skb;
902 u32 extsts = le32_to_cpu(desc[DESC_EXTSTS]);
903 dma_addr_t bufptr = desc_addr_get(desc + DESC_BUFPTR);
904
905 dprintk("cmdsts: %08x\n", cmdsts);
906 dprintk("link: %08x\n", cpu_to_le32(desc[DESC_LINK]));
907 dprintk("extsts: %08x\n", extsts);
908
909 skb = info->skbs[next_rx];
910 info->skbs[next_rx] = NULL;
911 info->next_rx = (next_rx + 1) % NR_RX_DESC;
912
913 mb();
914 clear_rx_desc(dev, next_rx);
915
916 pci_unmap_single(dev->pci_dev, bufptr,
917 RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
918 len = cmdsts & CMDSTS_LEN_MASK;
919 #ifdef NS83820_VLAN_ACCEL_SUPPORT
920 /* NH: As was mentioned below, this chip is kinda
921 * brain dead about vlan tag stripping. Frames
922 * that are 64 bytes with a vlan header appended
923 * like arp frames, or pings, are flagged as Runts
924 * when the tag is stripped and hardware. This
925 * also means that the OK bit in the descriptor
926 * is cleared when the frame comes in so we have
927 * to do a specific length check here to make sure
928 * the frame would have been ok, had we not stripped
929 * the tag.
930 */
931 if (likely((CMDSTS_OK & cmdsts) ||
932 ((cmdsts & CMDSTS_RUNT) && len >= 56))) {
933 #else
934 if (likely(CMDSTS_OK & cmdsts)) {
935 #endif
936 skb_put(skb, len);
937 if (unlikely(!skb))
938 goto netdev_mangle_me_harder_failed;
939 if (cmdsts & CMDSTS_DEST_MULTI)
940 dev->stats.multicast ++;
941 dev->stats.rx_packets ++;
942 dev->stats.rx_bytes += len;
943 if ((extsts & 0x002a0000) && !(extsts & 0x00540000)) {
944 skb->ip_summed = CHECKSUM_UNNECESSARY;
945 } else {
946 skb->ip_summed = CHECKSUM_NONE;
947 }
948 skb->protocol = eth_type_trans(skb, ndev);
949 #ifdef NS83820_VLAN_ACCEL_SUPPORT
950 if(extsts & EXTSTS_VPKT) {
951 unsigned short tag;
952 tag = ntohs(extsts & EXTSTS_VTG_MASK);
953 rx_rc = vlan_hwaccel_rx(skb,dev->vlgrp,tag);
954 } else {
955 rx_rc = netif_rx(skb);
956 }
957 #else
958 rx_rc = netif_rx(skb);
959 #endif
960 if (NET_RX_DROP == rx_rc) {
961 netdev_mangle_me_harder_failed:
962 dev->stats.rx_dropped ++;
963 }
964 } else {
965 kfree_skb(skb);
966 }
967
968 nr++;
969 next_rx = info->next_rx;
970 desc = info->descs + (DESC_SIZE * next_rx);
971 }
972 info->next_rx = next_rx;
973 info->next_rx_desc = info->descs + (DESC_SIZE * next_rx);
974
975 out:
976 if (0 && !nr) {
977 Dprintk("dazed: cmdsts_f: %08x\n", cmdsts);
978 }
979
980 spin_unlock_irqrestore(&info->lock, flags);
981 }
982
983 static void rx_action(unsigned long _dev)
984 {
985 struct net_device *ndev = (void *)_dev;
986 struct ns83820 *dev = PRIV(ndev);
987 rx_irq(ndev);
988 writel(ihr, dev->base + IHR);
989
990 spin_lock_irq(&dev->misc_lock);
991 dev->IMR_cache |= ISR_RXDESC;
992 writel(dev->IMR_cache, dev->base + IMR);
993 spin_unlock_irq(&dev->misc_lock);
994
995 rx_irq(ndev);
996 ns83820_rx_kick(ndev);
997 }
998
999 /* Packet Transmit code
1000 */
1001 static inline void kick_tx(struct ns83820 *dev)
1002 {
1003 dprintk("kick_tx(%p): tx_idx=%d free_idx=%d\n",
1004 dev, dev->tx_idx, dev->tx_free_idx);
1005 writel(CR_TXE, dev->base + CR);
1006 }
1007
1008 /* No spinlock needed on the transmit irq path as the interrupt handler is
1009 * serialized.
1010 */
1011 static void do_tx_done(struct net_device *ndev)
1012 {
1013 struct ns83820 *dev = PRIV(ndev);
1014 u32 cmdsts, tx_done_idx;
1015 __le32 *desc;
1016
1017 dprintk("do_tx_done(%p)\n", ndev);
1018 tx_done_idx = dev->tx_done_idx;
1019 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1020
1021 dprintk("tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1022 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
1023 while ((tx_done_idx != dev->tx_free_idx) &&
1024 !(CMDSTS_OWN & (cmdsts = le32_to_cpu(desc[DESC_CMDSTS]))) ) {
1025 struct sk_buff *skb;
1026 unsigned len;
1027 dma_addr_t addr;
1028
1029 if (cmdsts & CMDSTS_ERR)
1030 dev->stats.tx_errors ++;
1031 if (cmdsts & CMDSTS_OK)
1032 dev->stats.tx_packets ++;
1033 if (cmdsts & CMDSTS_OK)
1034 dev->stats.tx_bytes += cmdsts & 0xffff;
1035
1036 dprintk("tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1037 tx_done_idx, dev->tx_free_idx, cmdsts);
1038 skb = dev->tx_skbs[tx_done_idx];
1039 dev->tx_skbs[tx_done_idx] = NULL;
1040 dprintk("done(%p)\n", skb);
1041
1042 len = cmdsts & CMDSTS_LEN_MASK;
1043 addr = desc_addr_get(desc + DESC_BUFPTR);
1044 if (skb) {
1045 pci_unmap_single(dev->pci_dev,
1046 addr,
1047 len,
1048 PCI_DMA_TODEVICE);
1049 dev_kfree_skb_irq(skb);
1050 atomic_dec(&dev->nr_tx_skbs);
1051 } else
1052 pci_unmap_page(dev->pci_dev,
1053 addr,
1054 len,
1055 PCI_DMA_TODEVICE);
1056
1057 tx_done_idx = (tx_done_idx + 1) % NR_TX_DESC;
1058 dev->tx_done_idx = tx_done_idx;
1059 desc[DESC_CMDSTS] = cpu_to_le32(0);
1060 mb();
1061 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1062 }
1063
1064 /* Allow network stack to resume queueing packets after we've
1065 * finished transmitting at least 1/4 of the packets in the queue.
1066 */
1067 if (netif_queue_stopped(ndev) && start_tx_okay(dev)) {
1068 dprintk("start_queue(%p)\n", ndev);
1069 netif_start_queue(ndev);
1070 netif_wake_queue(ndev);
1071 }
1072 }
1073
1074 static void ns83820_cleanup_tx(struct ns83820 *dev)
1075 {
1076 unsigned i;
1077
1078 for (i=0; i<NR_TX_DESC; i++) {
1079 struct sk_buff *skb = dev->tx_skbs[i];
1080 dev->tx_skbs[i] = NULL;
1081 if (skb) {
1082 __le32 *desc = dev->tx_descs + (i * DESC_SIZE);
1083 pci_unmap_single(dev->pci_dev,
1084 desc_addr_get(desc + DESC_BUFPTR),
1085 le32_to_cpu(desc[DESC_CMDSTS]) & CMDSTS_LEN_MASK,
1086 PCI_DMA_TODEVICE);
1087 dev_kfree_skb_irq(skb);
1088 atomic_dec(&dev->nr_tx_skbs);
1089 }
1090 }
1091
1092 memset(dev->tx_descs, 0, NR_TX_DESC * DESC_SIZE * 4);
1093 }
1094
1095 /* transmit routine. This code relies on the network layer serializing
1096 * its calls in, but will run happily in parallel with the interrupt
1097 * handler. This code currently has provisions for fragmenting tx buffers
1098 * while trying to track down a bug in either the zero copy code or
1099 * the tx fifo (hence the MAX_FRAG_LEN).
1100 */
1101 static int ns83820_hard_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1102 {
1103 struct ns83820 *dev = PRIV(ndev);
1104 u32 free_idx, cmdsts, extsts;
1105 int nr_free, nr_frags;
1106 unsigned tx_done_idx, last_idx;
1107 dma_addr_t buf;
1108 unsigned len;
1109 skb_frag_t *frag;
1110 int stopped = 0;
1111 int do_intr = 0;
1112 volatile __le32 *first_desc;
1113
1114 dprintk("ns83820_hard_start_xmit\n");
1115
1116 nr_frags = skb_shinfo(skb)->nr_frags;
1117 again:
1118 if (unlikely(dev->CFG_cache & CFG_LNKSTS)) {
1119 netif_stop_queue(ndev);
1120 if (unlikely(dev->CFG_cache & CFG_LNKSTS))
1121 return 1;
1122 netif_start_queue(ndev);
1123 }
1124
1125 last_idx = free_idx = dev->tx_free_idx;
1126 tx_done_idx = dev->tx_done_idx;
1127 nr_free = (tx_done_idx + NR_TX_DESC-2 - free_idx) % NR_TX_DESC;
1128 nr_free -= 1;
1129 if (nr_free <= nr_frags) {
1130 dprintk("stop_queue - not enough(%p)\n", ndev);
1131 netif_stop_queue(ndev);
1132
1133 /* Check again: we may have raced with a tx done irq */
1134 if (dev->tx_done_idx != tx_done_idx) {
1135 dprintk("restart queue(%p)\n", ndev);
1136 netif_start_queue(ndev);
1137 goto again;
1138 }
1139 return 1;
1140 }
1141
1142 if (free_idx == dev->tx_intr_idx) {
1143 do_intr = 1;
1144 dev->tx_intr_idx = (dev->tx_intr_idx + NR_TX_DESC/4) % NR_TX_DESC;
1145 }
1146
1147 nr_free -= nr_frags;
1148 if (nr_free < MIN_TX_DESC_FREE) {
1149 dprintk("stop_queue - last entry(%p)\n", ndev);
1150 netif_stop_queue(ndev);
1151 stopped = 1;
1152 }
1153
1154 frag = skb_shinfo(skb)->frags;
1155 if (!nr_frags)
1156 frag = NULL;
1157 extsts = 0;
1158 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1159 extsts |= EXTSTS_IPPKT;
1160 if (IPPROTO_TCP == skb->nh.iph->protocol)
1161 extsts |= EXTSTS_TCPPKT;
1162 else if (IPPROTO_UDP == skb->nh.iph->protocol)
1163 extsts |= EXTSTS_UDPPKT;
1164 }
1165
1166 #ifdef NS83820_VLAN_ACCEL_SUPPORT
1167 if(vlan_tx_tag_present(skb)) {
1168 /* fetch the vlan tag info out of the
1169 * ancilliary data if the vlan code
1170 * is using hw vlan acceleration
1171 */
1172 short tag = vlan_tx_tag_get(skb);
1173 extsts |= (EXTSTS_VPKT | htons(tag));
1174 }
1175 #endif
1176
1177 len = skb->len;
1178 if (nr_frags)
1179 len -= skb->data_len;
1180 buf = pci_map_single(dev->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
1181
1182 first_desc = dev->tx_descs + (free_idx * DESC_SIZE);
1183
1184 for (;;) {
1185 volatile __le32 *desc = dev->tx_descs + (free_idx * DESC_SIZE);
1186
1187 dprintk("frag[%3u]: %4u @ 0x%08Lx\n", free_idx, len,
1188 (unsigned long long)buf);
1189 last_idx = free_idx;
1190 free_idx = (free_idx + 1) % NR_TX_DESC;
1191 desc[DESC_LINK] = cpu_to_le32(dev->tx_phy_descs + (free_idx * DESC_SIZE * 4));
1192 desc_addr_set(desc + DESC_BUFPTR, buf);
1193 desc[DESC_EXTSTS] = cpu_to_le32(extsts);
1194
1195 cmdsts = ((nr_frags) ? CMDSTS_MORE : do_intr ? CMDSTS_INTR : 0);
1196 cmdsts |= (desc == first_desc) ? 0 : CMDSTS_OWN;
1197 cmdsts |= len;
1198 desc[DESC_CMDSTS] = cpu_to_le32(cmdsts);
1199
1200 if (!nr_frags)
1201 break;
1202
1203 buf = pci_map_page(dev->pci_dev, frag->page,
1204 frag->page_offset,
1205 frag->size, PCI_DMA_TODEVICE);
1206 dprintk("frag: buf=%08Lx page=%08lx offset=%08lx\n",
1207 (long long)buf, (long) page_to_pfn(frag->page),
1208 frag->page_offset);
1209 len = frag->size;
1210 frag++;
1211 nr_frags--;
1212 }
1213 dprintk("done pkt\n");
1214
1215 spin_lock_irq(&dev->tx_lock);
1216 dev->tx_skbs[last_idx] = skb;
1217 first_desc[DESC_CMDSTS] |= cpu_to_le32(CMDSTS_OWN);
1218 dev->tx_free_idx = free_idx;
1219 atomic_inc(&dev->nr_tx_skbs);
1220 spin_unlock_irq(&dev->tx_lock);
1221
1222 kick_tx(dev);
1223
1224 /* Check again: we may have raced with a tx done irq */
1225 if (stopped && (dev->tx_done_idx != tx_done_idx) && start_tx_okay(dev))
1226 netif_start_queue(ndev);
1227
1228 /* set the transmit start time to catch transmit timeouts */
1229 ndev->trans_start = jiffies;
1230 return 0;
1231 }
1232
1233 static void ns83820_update_stats(struct ns83820 *dev)
1234 {
1235 u8 __iomem *base = dev->base;
1236
1237 /* the DP83820 will freeze counters, so we need to read all of them */
1238 dev->stats.rx_errors += readl(base + 0x60) & 0xffff;
1239 dev->stats.rx_crc_errors += readl(base + 0x64) & 0xffff;
1240 dev->stats.rx_missed_errors += readl(base + 0x68) & 0xffff;
1241 dev->stats.rx_frame_errors += readl(base + 0x6c) & 0xffff;
1242 /*dev->stats.rx_symbol_errors +=*/ readl(base + 0x70);
1243 dev->stats.rx_length_errors += readl(base + 0x74) & 0xffff;
1244 dev->stats.rx_length_errors += readl(base + 0x78) & 0xffff;
1245 /*dev->stats.rx_badopcode_errors += */ readl(base + 0x7c);
1246 /*dev->stats.rx_pause_count += */ readl(base + 0x80);
1247 /*dev->stats.tx_pause_count += */ readl(base + 0x84);
1248 dev->stats.tx_carrier_errors += readl(base + 0x88) & 0xff;
1249 }
1250
1251 static struct net_device_stats *ns83820_get_stats(struct net_device *ndev)
1252 {
1253 struct ns83820 *dev = PRIV(ndev);
1254
1255 /* somewhat overkill */
1256 spin_lock_irq(&dev->misc_lock);
1257 ns83820_update_stats(dev);
1258 spin_unlock_irq(&dev->misc_lock);
1259
1260 return &dev->stats;
1261 }
1262
1263 static void ns83820_get_drvinfo(struct net_device *ndev, struct ethtool_drvinfo *info)
1264 {
1265 struct ns83820 *dev = PRIV(ndev);
1266 strcpy(info->driver, "ns83820");
1267 strcpy(info->version, VERSION);
1268 strcpy(info->bus_info, pci_name(dev->pci_dev));
1269 }
1270
1271 static u32 ns83820_get_link(struct net_device *ndev)
1272 {
1273 struct ns83820 *dev = PRIV(ndev);
1274 u32 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY;
1275 return cfg & CFG_LNKSTS ? 1 : 0;
1276 }
1277
1278 static const struct ethtool_ops ops = {
1279 .get_drvinfo = ns83820_get_drvinfo,
1280 .get_link = ns83820_get_link
1281 };
1282
1283 /* this function is called in irq context from the ISR */
1284 static void ns83820_mib_isr(struct ns83820 *dev)
1285 {
1286 unsigned long flags;
1287 spin_lock_irqsave(&dev->misc_lock, flags);
1288 ns83820_update_stats(dev);
1289 spin_unlock_irqrestore(&dev->misc_lock, flags);
1290 }
1291
1292 static void ns83820_do_isr(struct net_device *ndev, u32 isr);
1293 static irqreturn_t ns83820_irq(int foo, void *data)
1294 {
1295 struct net_device *ndev = data;
1296 struct ns83820 *dev = PRIV(ndev);
1297 u32 isr;
1298 dprintk("ns83820_irq(%p)\n", ndev);
1299
1300 dev->ihr = 0;
1301
1302 isr = readl(dev->base + ISR);
1303 dprintk("irq: %08x\n", isr);
1304 ns83820_do_isr(ndev, isr);
1305 return IRQ_HANDLED;
1306 }
1307
1308 static void ns83820_do_isr(struct net_device *ndev, u32 isr)
1309 {
1310 struct ns83820 *dev = PRIV(ndev);
1311 unsigned long flags;
1312
1313 #ifdef DEBUG
1314 if (isr & ~(ISR_PHY | ISR_RXDESC | ISR_RXEARLY | ISR_RXOK | ISR_RXERR | ISR_TXIDLE | ISR_TXOK | ISR_TXDESC))
1315 Dprintk("odd isr? 0x%08x\n", isr);
1316 #endif
1317
1318 if (ISR_RXIDLE & isr) {
1319 dev->rx_info.idle = 1;
1320 Dprintk("oh dear, we are idle\n");
1321 ns83820_rx_kick(ndev);
1322 }
1323
1324 if ((ISR_RXDESC | ISR_RXOK) & isr) {
1325 prefetch(dev->rx_info.next_rx_desc);
1326
1327 spin_lock_irqsave(&dev->misc_lock, flags);
1328 dev->IMR_cache &= ~(ISR_RXDESC | ISR_RXOK);
1329 writel(dev->IMR_cache, dev->base + IMR);
1330 spin_unlock_irqrestore(&dev->misc_lock, flags);
1331
1332 tasklet_schedule(&dev->rx_tasklet);
1333 //rx_irq(ndev);
1334 //writel(4, dev->base + IHR);
1335 }
1336
1337 if ((ISR_RXIDLE | ISR_RXORN | ISR_RXDESC | ISR_RXOK | ISR_RXERR) & isr)
1338 ns83820_rx_kick(ndev);
1339
1340 if (unlikely(ISR_RXSOVR & isr)) {
1341 //printk("overrun: rxsovr\n");
1342 dev->stats.rx_fifo_errors ++;
1343 }
1344
1345 if (unlikely(ISR_RXORN & isr)) {
1346 //printk("overrun: rxorn\n");
1347 dev->stats.rx_fifo_errors ++;
1348 }
1349
1350 if ((ISR_RXRCMP & isr) && dev->rx_info.up)
1351 writel(CR_RXE, dev->base + CR);
1352
1353 if (ISR_TXIDLE & isr) {
1354 u32 txdp;
1355 txdp = readl(dev->base + TXDP);
1356 dprintk("txdp: %08x\n", txdp);
1357 txdp -= dev->tx_phy_descs;
1358 dev->tx_idx = txdp / (DESC_SIZE * 4);
1359 if (dev->tx_idx >= NR_TX_DESC) {
1360 printk(KERN_ALERT "%s: BUG -- txdp out of range\n", ndev->name);
1361 dev->tx_idx = 0;
1362 }
1363 /* The may have been a race between a pci originated read
1364 * and the descriptor update from the cpu. Just in case,
1365 * kick the transmitter if the hardware thinks it is on a
1366 * different descriptor than we are.
1367 */
1368 if (dev->tx_idx != dev->tx_free_idx)
1369 kick_tx(dev);
1370 }
1371
1372 /* Defer tx ring processing until more than a minimum amount of
1373 * work has accumulated
1374 */
1375 if ((ISR_TXDESC | ISR_TXIDLE | ISR_TXOK | ISR_TXERR) & isr) {
1376 spin_lock_irqsave(&dev->tx_lock, flags);
1377 do_tx_done(ndev);
1378 spin_unlock_irqrestore(&dev->tx_lock, flags);
1379
1380 /* Disable TxOk if there are no outstanding tx packets.
1381 */
1382 if ((dev->tx_done_idx == dev->tx_free_idx) &&
1383 (dev->IMR_cache & ISR_TXOK)) {
1384 spin_lock_irqsave(&dev->misc_lock, flags);
1385 dev->IMR_cache &= ~ISR_TXOK;
1386 writel(dev->IMR_cache, dev->base + IMR);
1387 spin_unlock_irqrestore(&dev->misc_lock, flags);
1388 }
1389 }
1390
1391 /* The TxIdle interrupt can come in before the transmit has
1392 * completed. Normally we reap packets off of the combination
1393 * of TxDesc and TxIdle and leave TxOk disabled (since it
1394 * occurs on every packet), but when no further irqs of this
1395 * nature are expected, we must enable TxOk.
1396 */
1397 if ((ISR_TXIDLE & isr) && (dev->tx_done_idx != dev->tx_free_idx)) {
1398 spin_lock_irqsave(&dev->misc_lock, flags);
1399 dev->IMR_cache |= ISR_TXOK;
1400 writel(dev->IMR_cache, dev->base + IMR);
1401 spin_unlock_irqrestore(&dev->misc_lock, flags);
1402 }
1403
1404 /* MIB interrupt: one of the statistics counters is about to overflow */
1405 if (unlikely(ISR_MIB & isr))
1406 ns83820_mib_isr(dev);
1407
1408 /* PHY: Link up/down/negotiation state change */
1409 if (unlikely(ISR_PHY & isr))
1410 phy_intr(ndev);
1411
1412 #if 0 /* Still working on the interrupt mitigation strategy */
1413 if (dev->ihr)
1414 writel(dev->ihr, dev->base + IHR);
1415 #endif
1416 }
1417
1418 static void ns83820_do_reset(struct ns83820 *dev, u32 which)
1419 {
1420 Dprintk("resetting chip...\n");
1421 writel(which, dev->base + CR);
1422 do {
1423 schedule();
1424 } while (readl(dev->base + CR) & which);
1425 Dprintk("okay!\n");
1426 }
1427
1428 static int ns83820_stop(struct net_device *ndev)
1429 {
1430 struct ns83820 *dev = PRIV(ndev);
1431
1432 /* FIXME: protect against interrupt handler? */
1433 del_timer_sync(&dev->tx_watchdog);
1434
1435 /* disable interrupts */
1436 writel(0, dev->base + IMR);
1437 writel(0, dev->base + IER);
1438 readl(dev->base + IER);
1439
1440 dev->rx_info.up = 0;
1441 synchronize_irq(dev->pci_dev->irq);
1442
1443 ns83820_do_reset(dev, CR_RST);
1444
1445 synchronize_irq(dev->pci_dev->irq);
1446
1447 spin_lock_irq(&dev->misc_lock);
1448 dev->IMR_cache &= ~(ISR_TXURN | ISR_TXIDLE | ISR_TXERR | ISR_TXDESC | ISR_TXOK);
1449 spin_unlock_irq(&dev->misc_lock);
1450
1451 ns83820_cleanup_rx(dev);
1452 ns83820_cleanup_tx(dev);
1453
1454 return 0;
1455 }
1456
1457 static void ns83820_tx_timeout(struct net_device *ndev)
1458 {
1459 struct ns83820 *dev = PRIV(ndev);
1460 u32 tx_done_idx;
1461 __le32 *desc;
1462 unsigned long flags;
1463
1464 spin_lock_irqsave(&dev->tx_lock, flags);
1465
1466 tx_done_idx = dev->tx_done_idx;
1467 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1468
1469 printk(KERN_INFO "%s: tx_timeout: tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1470 ndev->name,
1471 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
1472
1473 #if defined(DEBUG)
1474 {
1475 u32 isr;
1476 isr = readl(dev->base + ISR);
1477 printk("irq: %08x imr: %08x\n", isr, dev->IMR_cache);
1478 ns83820_do_isr(ndev, isr);
1479 }
1480 #endif
1481
1482 do_tx_done(ndev);
1483
1484 tx_done_idx = dev->tx_done_idx;
1485 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE);
1486
1487 printk(KERN_INFO "%s: after: tx_done_idx=%d free_idx=%d cmdsts=%08x\n",
1488 ndev->name,
1489 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS]));
1490
1491 spin_unlock_irqrestore(&dev->tx_lock, flags);
1492 }
1493
1494 static void ns83820_tx_watch(unsigned long data)
1495 {
1496 struct net_device *ndev = (void *)data;
1497 struct ns83820 *dev = PRIV(ndev);
1498
1499 #if defined(DEBUG)
1500 printk("ns83820_tx_watch: %u %u %d\n",
1501 dev->tx_done_idx, dev->tx_free_idx, atomic_read(&dev->nr_tx_skbs)
1502 );
1503 #endif
1504
1505 if (time_after(jiffies, ndev->trans_start + 1*HZ) &&
1506 dev->tx_done_idx != dev->tx_free_idx) {
1507 printk(KERN_DEBUG "%s: ns83820_tx_watch: %u %u %d\n",
1508 ndev->name,
1509 dev->tx_done_idx, dev->tx_free_idx,
1510 atomic_read(&dev->nr_tx_skbs));
1511 ns83820_tx_timeout(ndev);
1512 }
1513
1514 mod_timer(&dev->tx_watchdog, jiffies + 2*HZ);
1515 }
1516
1517 static int ns83820_open(struct net_device *ndev)
1518 {
1519 struct ns83820 *dev = PRIV(ndev);
1520 unsigned i;
1521 u32 desc;
1522 int ret;
1523
1524 dprintk("ns83820_open\n");
1525
1526 writel(0, dev->base + PQCR);
1527
1528 ret = ns83820_setup_rx(ndev);
1529 if (ret)
1530 goto failed;
1531
1532 memset(dev->tx_descs, 0, 4 * NR_TX_DESC * DESC_SIZE);
1533 for (i=0; i<NR_TX_DESC; i++) {
1534 dev->tx_descs[(i * DESC_SIZE) + DESC_LINK]
1535 = cpu_to_le32(
1536 dev->tx_phy_descs
1537 + ((i+1) % NR_TX_DESC) * DESC_SIZE * 4);
1538 }
1539
1540 dev->tx_idx = 0;
1541 dev->tx_done_idx = 0;
1542 desc = dev->tx_phy_descs;
1543 writel(0, dev->base + TXDP_HI);
1544 writel(desc, dev->base + TXDP);
1545
1546 init_timer(&dev->tx_watchdog);
1547 dev->tx_watchdog.data = (unsigned long)ndev;
1548 dev->tx_watchdog.function = ns83820_tx_watch;
1549 mod_timer(&dev->tx_watchdog, jiffies + 2*HZ);
1550
1551 netif_start_queue(ndev); /* FIXME: wait for phy to come up */
1552
1553 return 0;
1554
1555 failed:
1556 ns83820_stop(ndev);
1557 return ret;
1558 }
1559
1560 static void ns83820_getmac(struct ns83820 *dev, u8 *mac)
1561 {
1562 unsigned i;
1563 for (i=0; i<3; i++) {
1564 u32 data;
1565
1566 /* Read from the perfect match memory: this is loaded by
1567 * the chip from the EEPROM via the EELOAD self test.
1568 */
1569 writel(i*2, dev->base + RFCR);
1570 data = readl(dev->base + RFDR);
1571
1572 *mac++ = data;
1573 *mac++ = data >> 8;
1574 }
1575 }
1576
1577 static int ns83820_change_mtu(struct net_device *ndev, int new_mtu)
1578 {
1579 if (new_mtu > RX_BUF_SIZE)
1580 return -EINVAL;
1581 ndev->mtu = new_mtu;
1582 return 0;
1583 }
1584
1585 static void ns83820_set_multicast(struct net_device *ndev)
1586 {
1587 struct ns83820 *dev = PRIV(ndev);
1588 u8 __iomem *rfcr = dev->base + RFCR;
1589 u32 and_mask = 0xffffffff;
1590 u32 or_mask = 0;
1591 u32 val;
1592
1593 if (ndev->flags & IFF_PROMISC)
1594 or_mask |= RFCR_AAU | RFCR_AAM;
1595 else
1596 and_mask &= ~(RFCR_AAU | RFCR_AAM);
1597
1598 if (ndev->flags & IFF_ALLMULTI)
1599 or_mask |= RFCR_AAM;
1600 else
1601 and_mask &= ~RFCR_AAM;
1602
1603 spin_lock_irq(&dev->misc_lock);
1604 val = (readl(rfcr) & and_mask) | or_mask;
1605 /* Ramit : RFCR Write Fix doc says RFEN must be 0 modify other bits */
1606 writel(val & ~RFCR_RFEN, rfcr);
1607 writel(val, rfcr);
1608 spin_unlock_irq(&dev->misc_lock);
1609 }
1610
1611 static void ns83820_run_bist(struct net_device *ndev, const char *name, u32 enable, u32 done, u32 fail)
1612 {
1613 struct ns83820 *dev = PRIV(ndev);
1614 int timed_out = 0;
1615 unsigned long start;
1616 u32 status;
1617 int loops = 0;
1618
1619 dprintk("%s: start %s\n", ndev->name, name);
1620
1621 start = jiffies;
1622
1623 writel(enable, dev->base + PTSCR);
1624 for (;;) {
1625 loops++;
1626 status = readl(dev->base + PTSCR);
1627 if (!(status & enable))
1628 break;
1629 if (status & done)
1630 break;
1631 if (status & fail)
1632 break;
1633 if (time_after_eq(jiffies, start + HZ)) {
1634 timed_out = 1;
1635 break;
1636 }
1637 schedule_timeout_uninterruptible(1);
1638 }
1639
1640 if (status & fail)
1641 printk(KERN_INFO "%s: %s failed! (0x%08x & 0x%08x)\n",
1642 ndev->name, name, status, fail);
1643 else if (timed_out)
1644 printk(KERN_INFO "%s: run_bist %s timed out! (%08x)\n",
1645 ndev->name, name, status);
1646
1647 dprintk("%s: done %s in %d loops\n", ndev->name, name, loops);
1648 }
1649
1650 #ifdef PHY_CODE_IS_FINISHED
1651 static void ns83820_mii_write_bit(struct ns83820 *dev, int bit)
1652 {
1653 /* drive MDC low */
1654 dev->MEAR_cache &= ~MEAR_MDC;
1655 writel(dev->MEAR_cache, dev->base + MEAR);
1656 readl(dev->base + MEAR);
1657
1658 /* enable output, set bit */
1659 dev->MEAR_cache |= MEAR_MDDIR;
1660 if (bit)
1661 dev->MEAR_cache |= MEAR_MDIO;
1662 else
1663 dev->MEAR_cache &= ~MEAR_MDIO;
1664
1665 /* set the output bit */
1666 writel(dev->MEAR_cache, dev->base + MEAR);
1667 readl(dev->base + MEAR);
1668
1669 /* Wait. Max clock rate is 2.5MHz, this way we come in under 1MHz */
1670 udelay(1);
1671
1672 /* drive MDC high causing the data bit to be latched */
1673 dev->MEAR_cache |= MEAR_MDC;
1674 writel(dev->MEAR_cache, dev->base + MEAR);
1675 readl(dev->base + MEAR);
1676
1677 /* Wait again... */
1678 udelay(1);
1679 }
1680
1681 static int ns83820_mii_read_bit(struct ns83820 *dev)
1682 {
1683 int bit;
1684
1685 /* drive MDC low, disable output */
1686 dev->MEAR_cache &= ~MEAR_MDC;
1687 dev->MEAR_cache &= ~MEAR_MDDIR;
1688 writel(dev->MEAR_cache, dev->base + MEAR);
1689 readl(dev->base + MEAR);
1690
1691 /* Wait. Max clock rate is 2.5MHz, this way we come in under 1MHz */
1692 udelay(1);
1693
1694 /* drive MDC high causing the data bit to be latched */
1695 bit = (readl(dev->base + MEAR) & MEAR_MDIO) ? 1 : 0;
1696 dev->MEAR_cache |= MEAR_MDC;
1697 writel(dev->MEAR_cache, dev->base + MEAR);
1698
1699 /* Wait again... */
1700 udelay(1);
1701
1702 return bit;
1703 }
1704
1705 static unsigned ns83820_mii_read_reg(struct ns83820 *dev, unsigned phy, unsigned reg)
1706 {
1707 unsigned data = 0;
1708 int i;
1709
1710 /* read some garbage so that we eventually sync up */
1711 for (i=0; i<64; i++)
1712 ns83820_mii_read_bit(dev);
1713
1714 ns83820_mii_write_bit(dev, 0); /* start */
1715 ns83820_mii_write_bit(dev, 1);
1716 ns83820_mii_write_bit(dev, 1); /* opcode read */
1717 ns83820_mii_write_bit(dev, 0);
1718
1719 /* write out the phy address: 5 bits, msb first */
1720 for (i=0; i<5; i++)
1721 ns83820_mii_write_bit(dev, phy & (0x10 >> i));
1722
1723 /* write out the register address, 5 bits, msb first */
1724 for (i=0; i<5; i++)
1725 ns83820_mii_write_bit(dev, reg & (0x10 >> i));
1726
1727 ns83820_mii_read_bit(dev); /* turn around cycles */
1728 ns83820_mii_read_bit(dev);
1729
1730 /* read in the register data, 16 bits msb first */
1731 for (i=0; i<16; i++) {
1732 data <<= 1;
1733 data |= ns83820_mii_read_bit(dev);
1734 }
1735
1736 return data;
1737 }
1738
1739 static unsigned ns83820_mii_write_reg(struct ns83820 *dev, unsigned phy, unsigned reg, unsigned data)
1740 {
1741 int i;
1742
1743 /* read some garbage so that we eventually sync up */
1744 for (i=0; i<64; i++)
1745 ns83820_mii_read_bit(dev);
1746
1747 ns83820_mii_write_bit(dev, 0); /* start */
1748 ns83820_mii_write_bit(dev, 1);
1749 ns83820_mii_write_bit(dev, 0); /* opcode read */
1750 ns83820_mii_write_bit(dev, 1);
1751
1752 /* write out the phy address: 5 bits, msb first */
1753 for (i=0; i<5; i++)
1754 ns83820_mii_write_bit(dev, phy & (0x10 >> i));
1755
1756 /* write out the register address, 5 bits, msb first */
1757 for (i=0; i<5; i++)
1758 ns83820_mii_write_bit(dev, reg & (0x10 >> i));
1759
1760 ns83820_mii_read_bit(dev); /* turn around cycles */
1761 ns83820_mii_read_bit(dev);
1762
1763 /* read in the register data, 16 bits msb first */
1764 for (i=0; i<16; i++)
1765 ns83820_mii_write_bit(dev, (data >> (15 - i)) & 1);
1766
1767 return data;
1768 }
1769
1770 static void ns83820_probe_phy(struct net_device *ndev)
1771 {
1772 struct ns83820 *dev = PRIV(ndev);
1773 static int first;
1774 int i;
1775 #define MII_PHYIDR1 0x02
1776 #define MII_PHYIDR2 0x03
1777
1778 #if 0
1779 if (!first) {
1780 unsigned tmp;
1781 ns83820_mii_read_reg(dev, 1, 0x09);
1782 ns83820_mii_write_reg(dev, 1, 0x10, 0x0d3e);
1783
1784 tmp = ns83820_mii_read_reg(dev, 1, 0x00);
1785 ns83820_mii_write_reg(dev, 1, 0x00, tmp | 0x8000);
1786 udelay(1300);
1787 ns83820_mii_read_reg(dev, 1, 0x09);
1788 }
1789 #endif
1790 first = 1;
1791
1792 for (i=1; i<2; i++) {
1793 int j;
1794 unsigned a, b;
1795 a = ns83820_mii_read_reg(dev, i, MII_PHYIDR1);
1796 b = ns83820_mii_read_reg(dev, i, MII_PHYIDR2);
1797
1798 //printk("%s: phy %d: 0x%04x 0x%04x\n",
1799 // ndev->name, i, a, b);
1800
1801 for (j=0; j<0x16; j+=4) {
1802 dprintk("%s: [0x%02x] %04x %04x %04x %04x\n",
1803 ndev->name, j,
1804 ns83820_mii_read_reg(dev, i, 0 + j),
1805 ns83820_mii_read_reg(dev, i, 1 + j),
1806 ns83820_mii_read_reg(dev, i, 2 + j),
1807 ns83820_mii_read_reg(dev, i, 3 + j)
1808 );
1809 }
1810 }
1811 {
1812 unsigned a, b;
1813 /* read firmware version: memory addr is 0x8402 and 0x8403 */
1814 ns83820_mii_write_reg(dev, 1, 0x16, 0x000d);
1815 ns83820_mii_write_reg(dev, 1, 0x1e, 0x810e);
1816 a = ns83820_mii_read_reg(dev, 1, 0x1d);
1817
1818 ns83820_mii_write_reg(dev, 1, 0x16, 0x000d);
1819 ns83820_mii_write_reg(dev, 1, 0x1e, 0x810e);
1820 b = ns83820_mii_read_reg(dev, 1, 0x1d);
1821 dprintk("version: 0x%04x 0x%04x\n", a, b);
1822 }
1823 }
1824 #endif
1825
1826 static int __devinit ns83820_init_one(struct pci_dev *pci_dev, const struct pci_device_id *id)
1827 {
1828 struct net_device *ndev;
1829 struct ns83820 *dev;
1830 long addr;
1831 int err;
1832 int using_dac = 0;
1833
1834 /* See if we can set the dma mask early on; failure is fatal. */
1835 if (sizeof(dma_addr_t) == 8 &&
1836 !pci_set_dma_mask(pci_dev, DMA_64BIT_MASK)) {
1837 using_dac = 1;
1838 } else if (!pci_set_dma_mask(pci_dev, DMA_32BIT_MASK)) {
1839 using_dac = 0;
1840 } else {
1841 dev_warn(&pci_dev->dev, "pci_set_dma_mask failed!\n");
1842 return -ENODEV;
1843 }
1844
1845 ndev = alloc_etherdev(sizeof(struct ns83820));
1846 dev = PRIV(ndev);
1847 dev->ndev = ndev;
1848 err = -ENOMEM;
1849 if (!dev)
1850 goto out;
1851
1852 spin_lock_init(&dev->rx_info.lock);
1853 spin_lock_init(&dev->tx_lock);
1854 spin_lock_init(&dev->misc_lock);
1855 dev->pci_dev = pci_dev;
1856
1857 SET_MODULE_OWNER(ndev);
1858 SET_NETDEV_DEV(ndev, &pci_dev->dev);
1859
1860 INIT_WORK(&dev->tq_refill, queue_refill);
1861 tasklet_init(&dev->rx_tasklet, rx_action, (unsigned long)ndev);
1862
1863 err = pci_enable_device(pci_dev);
1864 if (err) {
1865 dev_info(&pci_dev->dev, "pci_enable_dev failed: %d\n", err);
1866 goto out_free;
1867 }
1868
1869 pci_set_master(pci_dev);
1870 addr = pci_resource_start(pci_dev, 1);
1871 dev->base = ioremap_nocache(addr, PAGE_SIZE);
1872 dev->tx_descs = pci_alloc_consistent(pci_dev,
1873 4 * DESC_SIZE * NR_TX_DESC, &dev->tx_phy_descs);
1874 dev->rx_info.descs = pci_alloc_consistent(pci_dev,
1875 4 * DESC_SIZE * NR_RX_DESC, &dev->rx_info.phy_descs);
1876 err = -ENOMEM;
1877 if (!dev->base || !dev->tx_descs || !dev->rx_info.descs)
1878 goto out_disable;
1879
1880 dprintk("%p: %08lx %p: %08lx\n",
1881 dev->tx_descs, (long)dev->tx_phy_descs,
1882 dev->rx_info.descs, (long)dev->rx_info.phy_descs);
1883
1884 /* disable interrupts */
1885 writel(0, dev->base + IMR);
1886 writel(0, dev->base + IER);
1887 readl(dev->base + IER);
1888
1889 dev->IMR_cache = 0;
1890
1891 err = request_irq(pci_dev->irq, ns83820_irq, IRQF_SHARED,
1892 DRV_NAME, ndev);
1893 if (err) {
1894 dev_info(&pci_dev->dev, "unable to register irq %d, err %d\n",
1895 pci_dev->irq, err);
1896 goto out_disable;
1897 }
1898
1899 /*
1900 * FIXME: we are holding rtnl_lock() over obscenely long area only
1901 * because some of the setup code uses dev->name. It's Wrong(tm) -
1902 * we should be using driver-specific names for all that stuff.
1903 * For now that will do, but we really need to come back and kill
1904 * most of the dev_alloc_name() users later.
1905 */
1906 rtnl_lock();
1907 err = dev_alloc_name(ndev, ndev->name);
1908 if (err < 0) {
1909 dev_info(&pci_dev->dev, "unable to get netdev name: %d\n", err);
1910 goto out_free_irq;
1911 }
1912
1913 printk("%s: ns83820.c: 0x22c: %08x, subsystem: %04x:%04x\n",
1914 ndev->name, le32_to_cpu(readl(dev->base + 0x22c)),
1915 pci_dev->subsystem_vendor, pci_dev->subsystem_device);
1916
1917 ndev->open = ns83820_open;
1918 ndev->stop = ns83820_stop;
1919 ndev->hard_start_xmit = ns83820_hard_start_xmit;
1920 ndev->get_stats = ns83820_get_stats;
1921 ndev->change_mtu = ns83820_change_mtu;
1922 ndev->set_multicast_list = ns83820_set_multicast;
1923 SET_ETHTOOL_OPS(ndev, &ops);
1924 ndev->tx_timeout = ns83820_tx_timeout;
1925 ndev->watchdog_timeo = 5 * HZ;
1926 pci_set_drvdata(pci_dev, ndev);
1927
1928 ns83820_do_reset(dev, CR_RST);
1929
1930 /* Must reset the ram bist before running it */
1931 writel(PTSCR_RBIST_RST, dev->base + PTSCR);
1932 ns83820_run_bist(ndev, "sram bist", PTSCR_RBIST_EN,
1933 PTSCR_RBIST_DONE, PTSCR_RBIST_FAIL);
1934 ns83820_run_bist(ndev, "eeprom bist", PTSCR_EEBIST_EN, 0,
1935 PTSCR_EEBIST_FAIL);
1936 ns83820_run_bist(ndev, "eeprom load", PTSCR_EELOAD_EN, 0, 0);
1937
1938 /* I love config registers */
1939 dev->CFG_cache = readl(dev->base + CFG);
1940
1941 if ((dev->CFG_cache & CFG_PCI64_DET)) {
1942 printk(KERN_INFO "%s: detected 64 bit PCI data bus.\n",
1943 ndev->name);
1944 /*dev->CFG_cache |= CFG_DATA64_EN;*/
1945 if (!(dev->CFG_cache & CFG_DATA64_EN))
1946 printk(KERN_INFO "%s: EEPROM did not enable 64 bit bus. Disabled.\n",
1947 ndev->name);
1948 } else
1949 dev->CFG_cache &= ~(CFG_DATA64_EN);
1950
1951 dev->CFG_cache &= (CFG_TBI_EN | CFG_MRM_DIS | CFG_MWI_DIS |
1952 CFG_T64ADDR | CFG_DATA64_EN | CFG_EXT_125 |
1953 CFG_M64ADDR);
1954 dev->CFG_cache |= CFG_PINT_DUPSTS | CFG_PINT_LNKSTS | CFG_PINT_SPDSTS |
1955 CFG_EXTSTS_EN | CFG_EXD | CFG_PESEL;
1956 dev->CFG_cache |= CFG_REQALG;
1957 dev->CFG_cache |= CFG_POW;
1958 dev->CFG_cache |= CFG_TMRTEST;
1959
1960 /* When compiled with 64 bit addressing, we must always enable
1961 * the 64 bit descriptor format.
1962 */
1963 if (sizeof(dma_addr_t) == 8)
1964 dev->CFG_cache |= CFG_M64ADDR;
1965 if (using_dac)
1966 dev->CFG_cache |= CFG_T64ADDR;
1967
1968 /* Big endian mode does not seem to do what the docs suggest */
1969 dev->CFG_cache &= ~CFG_BEM;
1970
1971 /* setup optical transceiver if we have one */
1972 if (dev->CFG_cache & CFG_TBI_EN) {
1973 printk(KERN_INFO "%s: enabling optical transceiver\n",
1974 ndev->name);
1975 writel(readl(dev->base + GPIOR) | 0x3e8, dev->base + GPIOR);
1976
1977 /* setup auto negotiation feature advertisement */
1978 writel(readl(dev->base + TANAR)
1979 | TANAR_HALF_DUP | TANAR_FULL_DUP,
1980 dev->base + TANAR);
1981
1982 /* start auto negotiation */
1983 writel(TBICR_MR_AN_ENABLE | TBICR_MR_RESTART_AN,
1984 dev->base + TBICR);
1985 writel(TBICR_MR_AN_ENABLE, dev->base + TBICR);
1986 dev->linkstate = LINK_AUTONEGOTIATE;
1987
1988 dev->CFG_cache |= CFG_MODE_1000;
1989 }
1990
1991 writel(dev->CFG_cache, dev->base + CFG);
1992 dprintk("CFG: %08x\n", dev->CFG_cache);
1993
1994 if (reset_phy) {
1995 printk(KERN_INFO "%s: resetting phy\n", ndev->name);
1996 writel(dev->CFG_cache | CFG_PHY_RST, dev->base + CFG);
1997 msleep(10);
1998 writel(dev->CFG_cache, dev->base + CFG);
1999 }
2000
2001 #if 0 /* Huh? This sets the PCI latency register. Should be done via
2002 * the PCI layer. FIXME.
2003 */
2004 if (readl(dev->base + SRR))
2005 writel(readl(dev->base+0x20c) | 0xfe00, dev->base + 0x20c);
2006 #endif
2007
2008 /* Note! The DMA burst size interacts with packet
2009 * transmission, such that the largest packet that
2010 * can be transmitted is 8192 - FLTH - burst size.
2011 * If only the transmit fifo was larger...
2012 */
2013 /* Ramit : 1024 DMA is not a good idea, it ends up banging
2014 * some DELL and COMPAQ SMP systems */
2015 writel(TXCFG_CSI | TXCFG_HBI | TXCFG_ATP | TXCFG_MXDMA512
2016 | ((1600 / 32) * 0x100),
2017 dev->base + TXCFG);
2018
2019 /* Flush the interrupt holdoff timer */
2020 writel(0x000, dev->base + IHR);
2021 writel(0x100, dev->base + IHR);
2022 writel(0x000, dev->base + IHR);
2023
2024 /* Set Rx to full duplex, don't accept runt, errored, long or length
2025 * range errored packets. Use 512 byte DMA.
2026 */
2027 /* Ramit : 1024 DMA is not a good idea, it ends up banging
2028 * some DELL and COMPAQ SMP systems
2029 * Turn on ALP, only we are accpeting Jumbo Packets */
2030 writel(RXCFG_AEP | RXCFG_ARP | RXCFG_AIRL | RXCFG_RX_FD
2031 | RXCFG_STRIPCRC
2032 //| RXCFG_ALP
2033 | (RXCFG_MXDMA512) | 0, dev->base + RXCFG);
2034
2035 /* Disable priority queueing */
2036 writel(0, dev->base + PQCR);
2037
2038 /* Enable IP checksum validation and detetion of VLAN headers.
2039 * Note: do not set the reject options as at least the 0x102
2040 * revision of the chip does not properly accept IP fragments
2041 * at least for UDP.
2042 */
2043 /* Ramit : Be sure to turn on RXCFG_ARP if VLAN's are enabled, since
2044 * the MAC it calculates the packetsize AFTER stripping the VLAN
2045 * header, and if a VLAN Tagged packet of 64 bytes is received (like
2046 * a ping with a VLAN header) then the card, strips the 4 byte VLAN
2047 * tag and then checks the packet size, so if RXCFG_ARP is not enabled,
2048 * it discrards it!. These guys......
2049 * also turn on tag stripping if hardware acceleration is enabled
2050 */
2051 #ifdef NS83820_VLAN_ACCEL_SUPPORT
2052 #define VRCR_INIT_VALUE (VRCR_IPEN|VRCR_VTDEN|VRCR_VTREN)
2053 #else
2054 #define VRCR_INIT_VALUE (VRCR_IPEN|VRCR_VTDEN)
2055 #endif
2056 writel(VRCR_INIT_VALUE, dev->base + VRCR);
2057
2058 /* Enable per-packet TCP/UDP/IP checksumming
2059 * and per packet vlan tag insertion if
2060 * vlan hardware acceleration is enabled
2061 */
2062 #ifdef NS83820_VLAN_ACCEL_SUPPORT
2063 #define VTCR_INIT_VALUE (VTCR_PPCHK|VTCR_VPPTI)
2064 #else
2065 #define VTCR_INIT_VALUE VTCR_PPCHK
2066 #endif
2067 writel(VTCR_INIT_VALUE, dev->base + VTCR);
2068
2069 /* Ramit : Enable async and sync pause frames */
2070 /* writel(0, dev->base + PCR); */
2071 writel((PCR_PS_MCAST | PCR_PS_DA | PCR_PSEN | PCR_FFLO_4K |
2072 PCR_FFHI_8K | PCR_STLO_4 | PCR_STHI_8 | PCR_PAUSE_CNT),
2073 dev->base + PCR);
2074
2075 /* Disable Wake On Lan */
2076 writel(0, dev->base + WCSR);
2077
2078 ns83820_getmac(dev, ndev->dev_addr);
2079
2080 /* Yes, we support dumb IP checksum on transmit */
2081 ndev->features |= NETIF_F_SG;
2082 ndev->features |= NETIF_F_IP_CSUM;
2083
2084 #ifdef NS83820_VLAN_ACCEL_SUPPORT
2085 /* We also support hardware vlan acceleration */
2086 ndev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2087 ndev->vlan_rx_register = ns83820_vlan_rx_register;
2088 ndev->vlan_rx_kill_vid = ns83820_vlan_rx_kill_vid;
2089 #endif
2090
2091 if (using_dac) {
2092 printk(KERN_INFO "%s: using 64 bit addressing.\n",
2093 ndev->name);
2094 ndev->features |= NETIF_F_HIGHDMA;
2095 }
2096
2097 printk(KERN_INFO "%s: ns83820 v" VERSION ": DP83820 v%u.%u: %02x:%02x:%02x:%02x:%02x:%02x io=0x%08lx irq=%d f=%s\n",
2098 ndev->name,
2099 (unsigned)readl(dev->base + SRR) >> 8,
2100 (unsigned)readl(dev->base + SRR) & 0xff,
2101 ndev->dev_addr[0], ndev->dev_addr[1],
2102 ndev->dev_addr[2], ndev->dev_addr[3],
2103 ndev->dev_addr[4], ndev->dev_addr[5],
2104 addr, pci_dev->irq,
2105 (ndev->features & NETIF_F_HIGHDMA) ? "h,sg" : "sg"
2106 );
2107
2108 #ifdef PHY_CODE_IS_FINISHED
2109 ns83820_probe_phy(ndev);
2110 #endif
2111
2112 err = register_netdevice(ndev);
2113 if (err) {
2114 printk(KERN_INFO "ns83820: unable to register netdev: %d\n", err);
2115 goto out_cleanup;
2116 }
2117 rtnl_unlock();
2118
2119 return 0;
2120
2121 out_cleanup:
2122 writel(0, dev->base + IMR); /* paranoia */
2123 writel(0, dev->base + IER);
2124 readl(dev->base + IER);
2125 out_free_irq:
2126 rtnl_unlock();
2127 free_irq(pci_dev->irq, ndev);
2128 out_disable:
2129 if (dev->base)
2130 iounmap(dev->base);
2131 pci_free_consistent(pci_dev, 4 * DESC_SIZE * NR_TX_DESC, dev->tx_descs, dev->tx_phy_descs);
2132 pci_free_consistent(pci_dev, 4 * DESC_SIZE * NR_RX_DESC, dev->rx_info.descs, dev->rx_info.phy_descs);
2133 pci_disable_device(pci_dev);
2134 out_free:
2135 free_netdev(ndev);
2136 pci_set_drvdata(pci_dev, NULL);
2137 out:
2138 return err;
2139 }
2140
2141 static void __devexit ns83820_remove_one(struct pci_dev *pci_dev)
2142 {
2143 struct net_device *ndev = pci_get_drvdata(pci_dev);
2144 struct ns83820 *dev = PRIV(ndev); /* ok even if NULL */
2145
2146 if (!ndev) /* paranoia */
2147 return;
2148
2149 writel(0, dev->base + IMR); /* paranoia */
2150 writel(0, dev->base + IER);
2151 readl(dev->base + IER);
2152
2153 unregister_netdev(ndev);
2154 free_irq(dev->pci_dev->irq, ndev);
2155 iounmap(dev->base);
2156 pci_free_consistent(dev->pci_dev, 4 * DESC_SIZE * NR_TX_DESC,
2157 dev->tx_descs, dev->tx_phy_descs);
2158 pci_free_consistent(dev->pci_dev, 4 * DESC_SIZE * NR_RX_DESC,
2159 dev->rx_info.descs, dev->rx_info.phy_descs);
2160 pci_disable_device(dev->pci_dev);
2161 free_netdev(ndev);
2162 pci_set_drvdata(pci_dev, NULL);
2163 }
2164
2165 static struct pci_device_id ns83820_pci_tbl[] = {
2166 { 0x100b, 0x0022, PCI_ANY_ID, PCI_ANY_ID, 0, .driver_data = 0, },
2167 { 0, },
2168 };
2169
2170 static struct pci_driver driver = {
2171 .name = "ns83820",
2172 .id_table = ns83820_pci_tbl,
2173 .probe = ns83820_init_one,
2174 .remove = __devexit_p(ns83820_remove_one),
2175 #if 0 /* FIXME: implement */
2176 .suspend = ,
2177 .resume = ,
2178 #endif
2179 };
2180
2181
2182 static int __init ns83820_init(void)
2183 {
2184 printk(KERN_INFO "ns83820.c: National Semiconductor DP83820 10/100/1000 driver.\n");
2185 return pci_register_driver(&driver);
2186 }
2187
2188 static void __exit ns83820_exit(void)
2189 {
2190 pci_unregister_driver(&driver);
2191 }
2192
2193 MODULE_AUTHOR("Benjamin LaHaise <bcrl@kvack.org>");
2194 MODULE_DESCRIPTION("National Semiconductor DP83820 10/100/1000 driver");
2195 MODULE_LICENSE("GPL");
2196
2197 MODULE_DEVICE_TABLE(pci, ns83820_pci_tbl);
2198
2199 module_param(lnksts, int, 0);
2200 MODULE_PARM_DESC(lnksts, "Polarity of LNKSTS bit");
2201
2202 module_param(ihr, int, 0);
2203 MODULE_PARM_DESC(ihr, "Time in 100 us increments to delay interrupts (range 0-127)");
2204
2205 module_param(reset_phy, int, 0);
2206 MODULE_PARM_DESC(reset_phy, "Set to 1 to reset the PHY on startup");
2207
2208 module_init(ns83820_init);
2209 module_exit(ns83820_exit);
kernel-based virtual machine