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Merge branch 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied...
[linux-2.6/kvm.git] / drivers / firewire / ohci.c
blob9f627e758cfc503eb6a56b51c4f0fdd413ef4b32
1 /*
2 * Driver for OHCI 1394 controllers
3 *
4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21 #include <linux/compiler.h>
22 #include <linux/delay.h>
23 #include <linux/device.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/firewire.h>
26 #include <linux/firewire-constants.h>
27 #include <linux/init.h>
28 #include <linux/interrupt.h>
29 #include <linux/io.h>
30 #include <linux/kernel.h>
31 #include <linux/list.h>
32 #include <linux/mm.h>
33 #include <linux/module.h>
34 #include <linux/moduleparam.h>
35 #include <linux/pci.h>
36 #include <linux/pci_ids.h>
37 #include <linux/slab.h>
38 #include <linux/spinlock.h>
39 #include <linux/string.h>
40
41 #include <asm/byteorder.h>
42 #include <asm/page.h>
43 #include <asm/system.h>
44
45 #ifdef CONFIG_PPC_PMAC
46 #include <asm/pmac_feature.h>
47 #endif
48
49 #include "core.h"
50 #include "ohci.h"
51
52 #define DESCRIPTOR_OUTPUT_MORE 0
53 #define DESCRIPTOR_OUTPUT_LAST (1 << 12)
54 #define DESCRIPTOR_INPUT_MORE (2 << 12)
55 #define DESCRIPTOR_INPUT_LAST (3 << 12)
56 #define DESCRIPTOR_STATUS (1 << 11)
57 #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
58 #define DESCRIPTOR_PING (1 << 7)
59 #define DESCRIPTOR_YY (1 << 6)
60 #define DESCRIPTOR_NO_IRQ (0 << 4)
61 #define DESCRIPTOR_IRQ_ERROR (1 << 4)
62 #define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
63 #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
64 #define DESCRIPTOR_WAIT (3 << 0)
65
66 struct descriptor {
67 __le16 req_count;
68 __le16 control;
69 __le32 data_address;
70 __le32 branch_address;
71 __le16 res_count;
72 __le16 transfer_status;
73 } __attribute__((aligned(16)));
74
75 #define CONTROL_SET(regs) (regs)
76 #define CONTROL_CLEAR(regs) ((regs) + 4)
77 #define COMMAND_PTR(regs) ((regs) + 12)
78 #define CONTEXT_MATCH(regs) ((regs) + 16)
79
80 struct ar_buffer {
81 struct descriptor descriptor;
82 struct ar_buffer *next;
83 __le32 data[0];
84 };
85
86 struct ar_context {
87 struct fw_ohci *ohci;
88 struct ar_buffer *current_buffer;
89 struct ar_buffer *last_buffer;
90 void *pointer;
91 u32 regs;
92 struct tasklet_struct tasklet;
93 };
94
95 struct context;
96
97 typedef int (*descriptor_callback_t)(struct context *ctx,
98 struct descriptor *d,
99 struct descriptor *last);
100
101 /*
102 * A buffer that contains a block of DMA-able coherent memory used for
103 * storing a portion of a DMA descriptor program.
104 */
105 struct descriptor_buffer {
106 struct list_head list;
107 dma_addr_t buffer_bus;
108 size_t buffer_size;
109 size_t used;
110 struct descriptor buffer[0];
111 };
112
113 struct context {
114 struct fw_ohci *ohci;
115 u32 regs;
116 int total_allocation;
117
118 /*
119 * List of page-sized buffers for storing DMA descriptors.
120 * Head of list contains buffers in use and tail of list contains
121 * free buffers.
122 */
123 struct list_head buffer_list;
124
125 /*
126 * Pointer to a buffer inside buffer_list that contains the tail
127 * end of the current DMA program.
128 */
129 struct descriptor_buffer *buffer_tail;
130
131 /*
132 * The descriptor containing the branch address of the first
133 * descriptor that has not yet been filled by the device.
134 */
135 struct descriptor *last;
136
137 /*
138 * The last descriptor in the DMA program. It contains the branch
139 * address that must be updated upon appending a new descriptor.
140 */
141 struct descriptor *prev;
142
143 descriptor_callback_t callback;
144
145 struct tasklet_struct tasklet;
146 };
147
148 #define IT_HEADER_SY(v) ((v) << 0)
149 #define IT_HEADER_TCODE(v) ((v) << 4)
150 #define IT_HEADER_CHANNEL(v) ((v) << 8)
151 #define IT_HEADER_TAG(v) ((v) << 14)
152 #define IT_HEADER_SPEED(v) ((v) << 16)
153 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
154
155 struct iso_context {
156 struct fw_iso_context base;
157 struct context context;
158 int excess_bytes;
159 void *header;
160 size_t header_length;
161 };
162
163 #define CONFIG_ROM_SIZE 1024
164
165 struct fw_ohci {
166 struct fw_card card;
167
168 __iomem char *registers;
169 int node_id;
170 int generation;
171 int request_generation; /* for timestamping incoming requests */
172 unsigned quirks;
173
174 /*
175 * Spinlock for accessing fw_ohci data. Never call out of
176 * this driver with this lock held.
177 */
178 spinlock_t lock;
179
180 struct ar_context ar_request_ctx;
181 struct ar_context ar_response_ctx;
182 struct context at_request_ctx;
183 struct context at_response_ctx;
184
185 u32 it_context_mask;
186 struct iso_context *it_context_list;
187 u64 ir_context_channels;
188 u32 ir_context_mask;
189 struct iso_context *ir_context_list;
190
191 __be32 *config_rom;
192 dma_addr_t config_rom_bus;
193 __be32 *next_config_rom;
194 dma_addr_t next_config_rom_bus;
195 __be32 next_header;
196
197 __le32 *self_id_cpu;
198 dma_addr_t self_id_bus;
199 struct tasklet_struct bus_reset_tasklet;
200
201 u32 self_id_buffer[512];
202 };
203
204 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
205 {
206 return container_of(card, struct fw_ohci, card);
207 }
208
209 #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
210 #define IR_CONTEXT_BUFFER_FILL 0x80000000
211 #define IR_CONTEXT_ISOCH_HEADER 0x40000000
212 #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
213 #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
214 #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
215
216 #define CONTEXT_RUN 0x8000
217 #define CONTEXT_WAKE 0x1000
218 #define CONTEXT_DEAD 0x0800
219 #define CONTEXT_ACTIVE 0x0400
220
221 #define OHCI1394_MAX_AT_REQ_RETRIES 0xf
222 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2
223 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
224
225 #define OHCI1394_REGISTER_SIZE 0x800
226 #define OHCI_LOOP_COUNT 500
227 #define OHCI1394_PCI_HCI_Control 0x40
228 #define SELF_ID_BUF_SIZE 0x800
229 #define OHCI_TCODE_PHY_PACKET 0x0e
230 #define OHCI_VERSION_1_1 0x010010
231
232 static char ohci_driver_name[] = KBUILD_MODNAME;
233
234 #define PCI_DEVICE_ID_TI_TSB12LV22 0x8009
235
236 #define QUIRK_CYCLE_TIMER 1
237 #define QUIRK_RESET_PACKET 2
238 #define QUIRK_BE_HEADERS 4
239 #define QUIRK_NO_1394A 8
240
241 /* In case of multiple matches in ohci_quirks[], only the first one is used. */
242 static const struct {
243 unsigned short vendor, device, flags;
244 } ohci_quirks[] = {
245 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, QUIRK_CYCLE_TIMER |
246 QUIRK_RESET_PACKET |
247 QUIRK_NO_1394A},
248 {PCI_VENDOR_ID_TI, PCI_ANY_ID, QUIRK_RESET_PACKET},
249 {PCI_VENDOR_ID_AL, PCI_ANY_ID, QUIRK_CYCLE_TIMER},
250 {PCI_VENDOR_ID_NEC, PCI_ANY_ID, QUIRK_CYCLE_TIMER},
251 {PCI_VENDOR_ID_VIA, PCI_ANY_ID, QUIRK_CYCLE_TIMER},
252 {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, QUIRK_BE_HEADERS},
253 };
254
255 /* This overrides anything that was found in ohci_quirks[]. */
256 static int param_quirks;
257 module_param_named(quirks, param_quirks, int, 0644);
258 MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
259 ", nonatomic cycle timer = " __stringify(QUIRK_CYCLE_TIMER)
260 ", reset packet generation = " __stringify(QUIRK_RESET_PACKET)
261 ", AR/selfID endianess = " __stringify(QUIRK_BE_HEADERS)
262 ", no 1394a enhancements = " __stringify(QUIRK_NO_1394A)
263 ")");
264
265 #define OHCI_PARAM_DEBUG_AT_AR 1
266 #define OHCI_PARAM_DEBUG_SELFIDS 2
267 #define OHCI_PARAM_DEBUG_IRQS 4
268 #define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */
269
270 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
271
272 static int param_debug;
273 module_param_named(debug, param_debug, int, 0644);
274 MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
275 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR)
276 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS)
277 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS)
278 ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
279 ", or a combination, or all = -1)");
280
281 static void log_irqs(u32 evt)
282 {
283 if (likely(!(param_debug &
284 (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
285 return;
286
287 if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
288 !(evt & OHCI1394_busReset))
289 return;
290
291 fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
292 evt & OHCI1394_selfIDComplete ? " selfID" : "",
293 evt & OHCI1394_RQPkt ? " AR_req" : "",
294 evt & OHCI1394_RSPkt ? " AR_resp" : "",
295 evt & OHCI1394_reqTxComplete ? " AT_req" : "",
296 evt & OHCI1394_respTxComplete ? " AT_resp" : "",
297 evt & OHCI1394_isochRx ? " IR" : "",
298 evt & OHCI1394_isochTx ? " IT" : "",
299 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "",
300 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "",
301 evt & OHCI1394_cycleInconsistent ? " cycleInconsistent" : "",
302 evt & OHCI1394_regAccessFail ? " regAccessFail" : "",
303 evt & OHCI1394_busReset ? " busReset" : "",
304 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
305 OHCI1394_RSPkt | OHCI1394_reqTxComplete |
306 OHCI1394_respTxComplete | OHCI1394_isochRx |
307 OHCI1394_isochTx | OHCI1394_postedWriteErr |
308 OHCI1394_cycleTooLong | OHCI1394_cycleInconsistent |
309 OHCI1394_regAccessFail | OHCI1394_busReset)
310 ? " ?" : "");
311 }
312
313 static const char *speed[] = {
314 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta",
315 };
316 static const char *power[] = {
317 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W",
318 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W",
319 };
320 static const char port[] = { '.', '-', 'p', 'c', };
321
322 static char _p(u32 *s, int shift)
323 {
324 return port[*s >> shift & 3];
325 }
326
327 static void log_selfids(int node_id, int generation, int self_id_count, u32 *s)
328 {
329 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
330 return;
331
332 fw_notify("%d selfIDs, generation %d, local node ID %04x\n",
333 self_id_count, generation, node_id);
334
335 for (; self_id_count--; ++s)
336 if ((*s & 1 << 23) == 0)
337 fw_notify("selfID 0: %08x, phy %d [%c%c%c] "
338 "%s gc=%d %s %s%s%s\n",
339 *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
340 speed[*s >> 14 & 3], *s >> 16 & 63,
341 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
342 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
343 else
344 fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
345 *s, *s >> 24 & 63,
346 _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
347 _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2));
348 }
349
350 static const char *evts[] = {
351 [0x00] = "evt_no_status", [0x01] = "-reserved-",
352 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack",
353 [0x04] = "evt_underrun", [0x05] = "evt_overrun",
354 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
355 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset",
356 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err",
357 [0x0c] = "-reserved-", [0x0d] = "-reserved-",
358 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed",
359 [0x10] = "-reserved-", [0x11] = "ack_complete",
360 [0x12] = "ack_pending ", [0x13] = "-reserved-",
361 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A",
362 [0x16] = "ack_busy_B", [0x17] = "-reserved-",
363 [0x18] = "-reserved-", [0x19] = "-reserved-",
364 [0x1a] = "-reserved-", [0x1b] = "ack_tardy",
365 [0x1c] = "-reserved-", [0x1d] = "ack_data_error",
366 [0x1e] = "ack_type_error", [0x1f] = "-reserved-",
367 [0x20] = "pending/cancelled",
368 };
369 static const char *tcodes[] = {
370 [0x0] = "QW req", [0x1] = "BW req",
371 [0x2] = "W resp", [0x3] = "-reserved-",
372 [0x4] = "QR req", [0x5] = "BR req",
373 [0x6] = "QR resp", [0x7] = "BR resp",
374 [0x8] = "cycle start", [0x9] = "Lk req",
375 [0xa] = "async stream packet", [0xb] = "Lk resp",
376 [0xc] = "-reserved-", [0xd] = "-reserved-",
377 [0xe] = "link internal", [0xf] = "-reserved-",
378 };
379 static const char *phys[] = {
380 [0x0] = "phy config packet", [0x1] = "link-on packet",
381 [0x2] = "self-id packet", [0x3] = "-reserved-",
382 };
383
384 static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
385 {
386 int tcode = header[0] >> 4 & 0xf;
387 char specific[12];
388
389 if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
390 return;
391
392 if (unlikely(evt >= ARRAY_SIZE(evts)))
393 evt = 0x1f;
394
395 if (evt == OHCI1394_evt_bus_reset) {
396 fw_notify("A%c evt_bus_reset, generation %d\n",
397 dir, (header[2] >> 16) & 0xff);
398 return;
399 }
400
401 if (header[0] == ~header[1]) {
402 fw_notify("A%c %s, %s, %08x\n",
403 dir, evts[evt], phys[header[0] >> 30 & 0x3], header[0]);
404 return;
405 }
406
407 switch (tcode) {
408 case 0x0: case 0x6: case 0x8:
409 snprintf(specific, sizeof(specific), " = %08x",
410 be32_to_cpu((__force __be32)header[3]));
411 break;
412 case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
413 snprintf(specific, sizeof(specific), " %x,%x",
414 header[3] >> 16, header[3] & 0xffff);
415 break;
416 default:
417 specific[0] = '\0';
418 }
419
420 switch (tcode) {
421 case 0xe: case 0xa:
422 fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]);
423 break;
424 case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
425 fw_notify("A%c spd %x tl %02x, "
426 "%04x -> %04x, %s, "
427 "%s, %04x%08x%s\n",
428 dir, speed, header[0] >> 10 & 0x3f,
429 header[1] >> 16, header[0] >> 16, evts[evt],
430 tcodes[tcode], header[1] & 0xffff, header[2], specific);
431 break;
432 default:
433 fw_notify("A%c spd %x tl %02x, "
434 "%04x -> %04x, %s, "
435 "%s%s\n",
436 dir, speed, header[0] >> 10 & 0x3f,
437 header[1] >> 16, header[0] >> 16, evts[evt],
438 tcodes[tcode], specific);
439 }
440 }
441
442 #else
443
444 #define param_debug 0
445 static inline void log_irqs(u32 evt) {}
446 static inline void log_selfids(int node_id, int generation, int self_id_count, u32 *s) {}
447 static inline void log_ar_at_event(char dir, int speed, u32 *header, int evt) {}
448
449 #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
450
451 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
452 {
453 writel(data, ohci->registers + offset);
454 }
455
456 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
457 {
458 return readl(ohci->registers + offset);
459 }
460
461 static inline void flush_writes(const struct fw_ohci *ohci)
462 {
463 /* Do a dummy read to flush writes. */
464 reg_read(ohci, OHCI1394_Version);
465 }
466
467 static int read_phy_reg(struct fw_ohci *ohci, int addr)
468 {
469 u32 val;
470 int i;
471
472 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
473 for (i = 0; i < 10; i++) {
474 val = reg_read(ohci, OHCI1394_PhyControl);
475 if (val & OHCI1394_PhyControl_ReadDone)
476 return OHCI1394_PhyControl_ReadData(val);
477
478 msleep(1);
479 }
480 fw_error("failed to read phy reg\n");
481
482 return -EBUSY;
483 }
484
485 static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
486 {
487 int i;
488
489 reg_write(ohci, OHCI1394_PhyControl,
490 OHCI1394_PhyControl_Write(addr, val));
491 for (i = 0; i < 100; i++) {
492 val = reg_read(ohci, OHCI1394_PhyControl);
493 if (!(val & OHCI1394_PhyControl_WritePending))
494 return 0;
495
496 msleep(1);
497 }
498 fw_error("failed to write phy reg\n");
499
500 return -EBUSY;
501 }
502
503 static int ohci_update_phy_reg(struct fw_card *card, int addr,
504 int clear_bits, int set_bits)
505 {
506 struct fw_ohci *ohci = fw_ohci(card);
507 int ret;
508
509 ret = read_phy_reg(ohci, addr);
510 if (ret < 0)
511 return ret;
512
513 /*
514 * The interrupt status bits are cleared by writing a one bit.
515 * Avoid clearing them unless explicitly requested in set_bits.
516 */
517 if (addr == 5)
518 clear_bits |= PHY_INT_STATUS_BITS;
519
520 return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
521 }
522
523 static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr)
524 {
525 int ret;
526
527 ret = ohci_update_phy_reg(&ohci->card, 7, PHY_PAGE_SELECT, page << 5);
528 if (ret < 0)
529 return ret;
530
531 return read_phy_reg(ohci, addr);
532 }
533
534 static int ar_context_add_page(struct ar_context *ctx)
535 {
536 struct device *dev = ctx->ohci->card.device;
537 struct ar_buffer *ab;
538 dma_addr_t uninitialized_var(ab_bus);
539 size_t offset;
540
541 ab = dma_alloc_coherent(dev, PAGE_SIZE, &ab_bus, GFP_ATOMIC);
542 if (ab == NULL)
543 return -ENOMEM;
544
545 ab->next = NULL;
546 memset(&ab->descriptor, 0, sizeof(ab->descriptor));
547 ab->descriptor.control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
548 DESCRIPTOR_STATUS |
549 DESCRIPTOR_BRANCH_ALWAYS);
550 offset = offsetof(struct ar_buffer, data);
551 ab->descriptor.req_count = cpu_to_le16(PAGE_SIZE - offset);
552 ab->descriptor.data_address = cpu_to_le32(ab_bus + offset);
553 ab->descriptor.res_count = cpu_to_le16(PAGE_SIZE - offset);
554 ab->descriptor.branch_address = 0;
555
556 ctx->last_buffer->descriptor.branch_address = cpu_to_le32(ab_bus | 1);
557 ctx->last_buffer->next = ab;
558 ctx->last_buffer = ab;
559
560 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
561 flush_writes(ctx->ohci);
562
563 return 0;
564 }
565
566 static void ar_context_release(struct ar_context *ctx)
567 {
568 struct ar_buffer *ab, *ab_next;
569 size_t offset;
570 dma_addr_t ab_bus;
571
572 for (ab = ctx->current_buffer; ab; ab = ab_next) {
573 ab_next = ab->next;
574 offset = offsetof(struct ar_buffer, data);
575 ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
576 dma_free_coherent(ctx->ohci->card.device, PAGE_SIZE,
577 ab, ab_bus);
578 }
579 }
580
581 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
582 #define cond_le32_to_cpu(v) \
583 (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
584 #else
585 #define cond_le32_to_cpu(v) le32_to_cpu(v)
586 #endif
587
588 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
589 {
590 struct fw_ohci *ohci = ctx->ohci;
591 struct fw_packet p;
592 u32 status, length, tcode;
593 int evt;
594
595 p.header[0] = cond_le32_to_cpu(buffer[0]);
596 p.header[1] = cond_le32_to_cpu(buffer[1]);
597 p.header[2] = cond_le32_to_cpu(buffer[2]);
598
599 tcode = (p.header[0] >> 4) & 0x0f;
600 switch (tcode) {
601 case TCODE_WRITE_QUADLET_REQUEST:
602 case TCODE_READ_QUADLET_RESPONSE:
603 p.header[3] = (__force __u32) buffer[3];
604 p.header_length = 16;
605 p.payload_length = 0;
606 break;
607
608 case TCODE_READ_BLOCK_REQUEST :
609 p.header[3] = cond_le32_to_cpu(buffer[3]);
610 p.header_length = 16;
611 p.payload_length = 0;
612 break;
613
614 case TCODE_WRITE_BLOCK_REQUEST:
615 case TCODE_READ_BLOCK_RESPONSE:
616 case TCODE_LOCK_REQUEST:
617 case TCODE_LOCK_RESPONSE:
618 p.header[3] = cond_le32_to_cpu(buffer[3]);
619 p.header_length = 16;
620 p.payload_length = p.header[3] >> 16;
621 break;
622
623 case TCODE_WRITE_RESPONSE:
624 case TCODE_READ_QUADLET_REQUEST:
625 case OHCI_TCODE_PHY_PACKET:
626 p.header_length = 12;
627 p.payload_length = 0;
628 break;
629
630 default:
631 /* FIXME: Stop context, discard everything, and restart? */
632 p.header_length = 0;
633 p.payload_length = 0;
634 }
635
636 p.payload = (void *) buffer + p.header_length;
637
638 /* FIXME: What to do about evt_* errors? */
639 length = (p.header_length + p.payload_length + 3) / 4;
640 status = cond_le32_to_cpu(buffer[length]);
641 evt = (status >> 16) & 0x1f;
642
643 p.ack = evt - 16;
644 p.speed = (status >> 21) & 0x7;
645 p.timestamp = status & 0xffff;
646 p.generation = ohci->request_generation;
647
648 log_ar_at_event('R', p.speed, p.header, evt);
649
650 /*
651 * The OHCI bus reset handler synthesizes a phy packet with
652 * the new generation number when a bus reset happens (see
653 * section 8.4.2.3). This helps us determine when a request
654 * was received and make sure we send the response in the same
655 * generation. We only need this for requests; for responses
656 * we use the unique tlabel for finding the matching
657 * request.
658 *
659 * Alas some chips sometimes emit bus reset packets with a
660 * wrong generation. We set the correct generation for these
661 * at a slightly incorrect time (in bus_reset_tasklet).
662 */
663 if (evt == OHCI1394_evt_bus_reset) {
664 if (!(ohci->quirks & QUIRK_RESET_PACKET))
665 ohci->request_generation = (p.header[2] >> 16) & 0xff;
666 } else if (ctx == &ohci->ar_request_ctx) {
667 fw_core_handle_request(&ohci->card, &p);
668 } else {
669 fw_core_handle_response(&ohci->card, &p);
670 }
671
672 return buffer + length + 1;
673 }
674
675 static void ar_context_tasklet(unsigned long data)
676 {
677 struct ar_context *ctx = (struct ar_context *)data;
678 struct fw_ohci *ohci = ctx->ohci;
679 struct ar_buffer *ab;
680 struct descriptor *d;
681 void *buffer, *end;
682
683 ab = ctx->current_buffer;
684 d = &ab->descriptor;
685
686 if (d->res_count == 0) {
687 size_t size, rest, offset;
688 dma_addr_t start_bus;
689 void *start;
690
691 /*
692 * This descriptor is finished and we may have a
693 * packet split across this and the next buffer. We
694 * reuse the page for reassembling the split packet.
695 */
696
697 offset = offsetof(struct ar_buffer, data);
698 start = buffer = ab;
699 start_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
700
701 ab = ab->next;
702 d = &ab->descriptor;
703 size = buffer + PAGE_SIZE - ctx->pointer;
704 rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count);
705 memmove(buffer, ctx->pointer, size);
706 memcpy(buffer + size, ab->data, rest);
707 ctx->current_buffer = ab;
708 ctx->pointer = (void *) ab->data + rest;
709 end = buffer + size + rest;
710
711 while (buffer < end)
712 buffer = handle_ar_packet(ctx, buffer);
713
714 dma_free_coherent(ohci->card.device, PAGE_SIZE,
715 start, start_bus);
716 ar_context_add_page(ctx);
717 } else {
718 buffer = ctx->pointer;
719 ctx->pointer = end =
720 (void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count);
721
722 while (buffer < end)
723 buffer = handle_ar_packet(ctx, buffer);
724 }
725 }
726
727 static int ar_context_init(struct ar_context *ctx,
728 struct fw_ohci *ohci, u32 regs)
729 {
730 struct ar_buffer ab;
731
732 ctx->regs = regs;
733 ctx->ohci = ohci;
734 ctx->last_buffer = &ab;
735 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
736
737 ar_context_add_page(ctx);
738 ar_context_add_page(ctx);
739 ctx->current_buffer = ab.next;
740 ctx->pointer = ctx->current_buffer->data;
741
742 return 0;
743 }
744
745 static void ar_context_run(struct ar_context *ctx)
746 {
747 struct ar_buffer *ab = ctx->current_buffer;
748 dma_addr_t ab_bus;
749 size_t offset;
750
751 offset = offsetof(struct ar_buffer, data);
752 ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
753
754 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ab_bus | 1);
755 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
756 flush_writes(ctx->ohci);
757 }
758
759 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
760 {
761 int b, key;
762
763 b = (le16_to_cpu(d->control) & DESCRIPTOR_BRANCH_ALWAYS) >> 2;
764 key = (le16_to_cpu(d->control) & DESCRIPTOR_KEY_IMMEDIATE) >> 8;
765
766 /* figure out which descriptor the branch address goes in */
767 if (z == 2 && (b == 3 || key == 2))
768 return d;
769 else
770 return d + z - 1;
771 }
772
773 static void context_tasklet(unsigned long data)
774 {
775 struct context *ctx = (struct context *) data;
776 struct descriptor *d, *last;
777 u32 address;
778 int z;
779 struct descriptor_buffer *desc;
780
781 desc = list_entry(ctx->buffer_list.next,
782 struct descriptor_buffer, list);
783 last = ctx->last;
784 while (last->branch_address != 0) {
785 struct descriptor_buffer *old_desc = desc;
786 address = le32_to_cpu(last->branch_address);
787 z = address & 0xf;
788 address &= ~0xf;
789
790 /* If the branch address points to a buffer outside of the
791 * current buffer, advance to the next buffer. */
792 if (address < desc->buffer_bus ||
793 address >= desc->buffer_bus + desc->used)
794 desc = list_entry(desc->list.next,
795 struct descriptor_buffer, list);
796 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
797 last = find_branch_descriptor(d, z);
798
799 if (!ctx->callback(ctx, d, last))
800 break;
801
802 if (old_desc != desc) {
803 /* If we've advanced to the next buffer, move the
804 * previous buffer to the free list. */
805 unsigned long flags;
806 old_desc->used = 0;
807 spin_lock_irqsave(&ctx->ohci->lock, flags);
808 list_move_tail(&old_desc->list, &ctx->buffer_list);
809 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
810 }
811 ctx->last = last;
812 }
813 }
814
815 /*
816 * Allocate a new buffer and add it to the list of free buffers for this
817 * context. Must be called with ohci->lock held.
818 */
819 static int context_add_buffer(struct context *ctx)
820 {
821 struct descriptor_buffer *desc;
822 dma_addr_t uninitialized_var(bus_addr);
823 int offset;
824
825 /*
826 * 16MB of descriptors should be far more than enough for any DMA
827 * program. This will catch run-away userspace or DoS attacks.
828 */
829 if (ctx->total_allocation >= 16*1024*1024)
830 return -ENOMEM;
831
832 desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
833 &bus_addr, GFP_ATOMIC);
834 if (!desc)
835 return -ENOMEM;
836
837 offset = (void *)&desc->buffer - (void *)desc;
838 desc->buffer_size = PAGE_SIZE - offset;
839 desc->buffer_bus = bus_addr + offset;
840 desc->used = 0;
841
842 list_add_tail(&desc->list, &ctx->buffer_list);
843 ctx->total_allocation += PAGE_SIZE;
844
845 return 0;
846 }
847
848 static int context_init(struct context *ctx, struct fw_ohci *ohci,
849 u32 regs, descriptor_callback_t callback)
850 {
851 ctx->ohci = ohci;
852 ctx->regs = regs;
853 ctx->total_allocation = 0;
854
855 INIT_LIST_HEAD(&ctx->buffer_list);
856 if (context_add_buffer(ctx) < 0)
857 return -ENOMEM;
858
859 ctx->buffer_tail = list_entry(ctx->buffer_list.next,
860 struct descriptor_buffer, list);
861
862 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
863 ctx->callback = callback;
864
865 /*
866 * We put a dummy descriptor in the buffer that has a NULL
867 * branch address and looks like it's been sent. That way we
868 * have a descriptor to append DMA programs to.
869 */
870 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
871 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
872 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
873 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
874 ctx->last = ctx->buffer_tail->buffer;
875 ctx->prev = ctx->buffer_tail->buffer;
876
877 return 0;
878 }
879
880 static void context_release(struct context *ctx)
881 {
882 struct fw_card *card = &ctx->ohci->card;
883 struct descriptor_buffer *desc, *tmp;
884
885 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
886 dma_free_coherent(card->device, PAGE_SIZE, desc,
887 desc->buffer_bus -
888 ((void *)&desc->buffer - (void *)desc));
889 }
890
891 /* Must be called with ohci->lock held */
892 static struct descriptor *context_get_descriptors(struct context *ctx,
893 int z, dma_addr_t *d_bus)
894 {
895 struct descriptor *d = NULL;
896 struct descriptor_buffer *desc = ctx->buffer_tail;
897
898 if (z * sizeof(*d) > desc->buffer_size)
899 return NULL;
900
901 if (z * sizeof(*d) > desc->buffer_size - desc->used) {
902 /* No room for the descriptor in this buffer, so advance to the
903 * next one. */
904
905 if (desc->list.next == &ctx->buffer_list) {
906 /* If there is no free buffer next in the list,
907 * allocate one. */
908 if (context_add_buffer(ctx) < 0)
909 return NULL;
910 }
911 desc = list_entry(desc->list.next,
912 struct descriptor_buffer, list);
913 ctx->buffer_tail = desc;
914 }
915
916 d = desc->buffer + desc->used / sizeof(*d);
917 memset(d, 0, z * sizeof(*d));
918 *d_bus = desc->buffer_bus + desc->used;
919
920 return d;
921 }
922
923 static void context_run(struct context *ctx, u32 extra)
924 {
925 struct fw_ohci *ohci = ctx->ohci;
926
927 reg_write(ohci, COMMAND_PTR(ctx->regs),
928 le32_to_cpu(ctx->last->branch_address));
929 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
930 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
931 flush_writes(ohci);
932 }
933
934 static void context_append(struct context *ctx,
935 struct descriptor *d, int z, int extra)
936 {
937 dma_addr_t d_bus;
938 struct descriptor_buffer *desc = ctx->buffer_tail;
939
940 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
941
942 desc->used += (z + extra) * sizeof(*d);
943 ctx->prev->branch_address = cpu_to_le32(d_bus | z);
944 ctx->prev = find_branch_descriptor(d, z);
945
946 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
947 flush_writes(ctx->ohci);
948 }
949
950 static void context_stop(struct context *ctx)
951 {
952 u32 reg;
953 int i;
954
955 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
956 flush_writes(ctx->ohci);
957
958 for (i = 0; i < 10; i++) {
959 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
960 if ((reg & CONTEXT_ACTIVE) == 0)
961 return;
962
963 mdelay(1);
964 }
965 fw_error("Error: DMA context still active (0x%08x)\n", reg);
966 }
967
968 struct driver_data {
969 struct fw_packet *packet;
970 };
971
972 /*
973 * This function apppends a packet to the DMA queue for transmission.
974 * Must always be called with the ochi->lock held to ensure proper
975 * generation handling and locking around packet queue manipulation.
976 */
977 static int at_context_queue_packet(struct context *ctx,
978 struct fw_packet *packet)
979 {
980 struct fw_ohci *ohci = ctx->ohci;
981 dma_addr_t d_bus, uninitialized_var(payload_bus);
982 struct driver_data *driver_data;
983 struct descriptor *d, *last;
984 __le32 *header;
985 int z, tcode;
986 u32 reg;
987
988 d = context_get_descriptors(ctx, 4, &d_bus);
989 if (d == NULL) {
990 packet->ack = RCODE_SEND_ERROR;
991 return -1;
992 }
993
994 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
995 d[0].res_count = cpu_to_le16(packet->timestamp);
996
997 /*
998 * The DMA format for asyncronous link packets is different
999 * from the IEEE1394 layout, so shift the fields around
1000 * accordingly. If header_length is 8, it's a PHY packet, to
1001 * which we need to prepend an extra quadlet.
1002 */
1003
1004 header = (__le32 *) &d[1];
1005 switch (packet->header_length) {
1006 case 16:
1007 case 12:
1008 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1009 (packet->speed << 16));
1010 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
1011 (packet->header[0] & 0xffff0000));
1012 header[2] = cpu_to_le32(packet->header[2]);
1013
1014 tcode = (packet->header[0] >> 4) & 0x0f;
1015 if (TCODE_IS_BLOCK_PACKET(tcode))
1016 header[3] = cpu_to_le32(packet->header[3]);
1017 else
1018 header[3] = (__force __le32) packet->header[3];
1019
1020 d[0].req_count = cpu_to_le16(packet->header_length);
1021 break;
1022
1023 case 8:
1024 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
1025 (packet->speed << 16));
1026 header[1] = cpu_to_le32(packet->header[0]);
1027 header[2] = cpu_to_le32(packet->header[1]);
1028 d[0].req_count = cpu_to_le16(12);
1029 break;
1030
1031 case 4:
1032 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1033 (packet->speed << 16));
1034 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
1035 d[0].req_count = cpu_to_le16(8);
1036 break;
1037
1038 default:
1039 /* BUG(); */
1040 packet->ack = RCODE_SEND_ERROR;
1041 return -1;
1042 }
1043
1044 driver_data = (struct driver_data *) &d[3];
1045 driver_data->packet = packet;
1046 packet->driver_data = driver_data;
1047
1048 if (packet->payload_length > 0) {
1049 payload_bus =
1050 dma_map_single(ohci->card.device, packet->payload,
1051 packet->payload_length, DMA_TO_DEVICE);
1052 if (dma_mapping_error(ohci->card.device, payload_bus)) {
1053 packet->ack = RCODE_SEND_ERROR;
1054 return -1;
1055 }
1056 packet->payload_bus = payload_bus;
1057 packet->payload_mapped = true;
1058
1059 d[2].req_count = cpu_to_le16(packet->payload_length);
1060 d[2].data_address = cpu_to_le32(payload_bus);
1061 last = &d[2];
1062 z = 3;
1063 } else {
1064 last = &d[0];
1065 z = 2;
1066 }
1067
1068 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1069 DESCRIPTOR_IRQ_ALWAYS |
1070 DESCRIPTOR_BRANCH_ALWAYS);
1071
1072 /*
1073 * If the controller and packet generations don't match, we need to
1074 * bail out and try again. If IntEvent.busReset is set, the AT context
1075 * is halted, so appending to the context and trying to run it is
1076 * futile. Most controllers do the right thing and just flush the AT
1077 * queue (per section 7.2.3.2 of the OHCI 1.1 specification), but
1078 * some controllers (like a JMicron JMB381 PCI-e) misbehave and wind
1079 * up stalling out. So we just bail out in software and try again
1080 * later, and everyone is happy.
1081 * FIXME: Document how the locking works.
1082 */
1083 if (ohci->generation != packet->generation ||
1084 reg_read(ohci, OHCI1394_IntEventSet) & OHCI1394_busReset) {
1085 if (packet->payload_mapped)
1086 dma_unmap_single(ohci->card.device, payload_bus,
1087 packet->payload_length, DMA_TO_DEVICE);
1088 packet->ack = RCODE_GENERATION;
1089 return -1;
1090 }
1091
1092 context_append(ctx, d, z, 4 - z);
1093
1094 /* If the context isn't already running, start it up. */
1095 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
1096 if ((reg & CONTEXT_RUN) == 0)
1097 context_run(ctx, 0);
1098
1099 return 0;
1100 }
1101
1102 static int handle_at_packet(struct context *context,
1103 struct descriptor *d,
1104 struct descriptor *last)
1105 {
1106 struct driver_data *driver_data;
1107 struct fw_packet *packet;
1108 struct fw_ohci *ohci = context->ohci;
1109 int evt;
1110
1111 if (last->transfer_status == 0)
1112 /* This descriptor isn't done yet, stop iteration. */
1113 return 0;
1114
1115 driver_data = (struct driver_data *) &d[3];
1116 packet = driver_data->packet;
1117 if (packet == NULL)
1118 /* This packet was cancelled, just continue. */
1119 return 1;
1120
1121 if (packet->payload_mapped)
1122 dma_unmap_single(ohci->card.device, packet->payload_bus,
1123 packet->payload_length, DMA_TO_DEVICE);
1124
1125 evt = le16_to_cpu(last->transfer_status) & 0x1f;
1126 packet->timestamp = le16_to_cpu(last->res_count);
1127
1128 log_ar_at_event('T', packet->speed, packet->header, evt);
1129
1130 switch (evt) {
1131 case OHCI1394_evt_timeout:
1132 /* Async response transmit timed out. */
1133 packet->ack = RCODE_CANCELLED;
1134 break;
1135
1136 case OHCI1394_evt_flushed:
1137 /*
1138 * The packet was flushed should give same error as
1139 * when we try to use a stale generation count.
1140 */
1141 packet->ack = RCODE_GENERATION;
1142 break;
1143
1144 case OHCI1394_evt_missing_ack:
1145 /*
1146 * Using a valid (current) generation count, but the
1147 * node is not on the bus or not sending acks.
1148 */
1149 packet->ack = RCODE_NO_ACK;
1150 break;
1151
1152 case ACK_COMPLETE + 0x10:
1153 case ACK_PENDING + 0x10:
1154 case ACK_BUSY_X + 0x10:
1155 case ACK_BUSY_A + 0x10:
1156 case ACK_BUSY_B + 0x10:
1157 case ACK_DATA_ERROR + 0x10:
1158 case ACK_TYPE_ERROR + 0x10:
1159 packet->ack = evt - 0x10;
1160 break;
1161
1162 default:
1163 packet->ack = RCODE_SEND_ERROR;
1164 break;
1165 }
1166
1167 packet->callback(packet, &ohci->card, packet->ack);
1168
1169 return 1;
1170 }
1171
1172 #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
1173 #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
1174 #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
1175 #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
1176 #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
1177
1178 static void handle_local_rom(struct fw_ohci *ohci,
1179 struct fw_packet *packet, u32 csr)
1180 {
1181 struct fw_packet response;
1182 int tcode, length, i;
1183
1184 tcode = HEADER_GET_TCODE(packet->header[0]);
1185 if (TCODE_IS_BLOCK_PACKET(tcode))
1186 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1187 else
1188 length = 4;
1189
1190 i = csr - CSR_CONFIG_ROM;
1191 if (i + length > CONFIG_ROM_SIZE) {
1192 fw_fill_response(&response, packet->header,
1193 RCODE_ADDRESS_ERROR, NULL, 0);
1194 } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1195 fw_fill_response(&response, packet->header,
1196 RCODE_TYPE_ERROR, NULL, 0);
1197 } else {
1198 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1199 (void *) ohci->config_rom + i, length);
1200 }
1201
1202 fw_core_handle_response(&ohci->card, &response);
1203 }
1204
1205 static void handle_local_lock(struct fw_ohci *ohci,
1206 struct fw_packet *packet, u32 csr)
1207 {
1208 struct fw_packet response;
1209 int tcode, length, ext_tcode, sel, try;
1210 __be32 *payload, lock_old;
1211 u32 lock_arg, lock_data;
1212
1213 tcode = HEADER_GET_TCODE(packet->header[0]);
1214 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1215 payload = packet->payload;
1216 ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1217
1218 if (tcode == TCODE_LOCK_REQUEST &&
1219 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1220 lock_arg = be32_to_cpu(payload[0]);
1221 lock_data = be32_to_cpu(payload[1]);
1222 } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1223 lock_arg = 0;
1224 lock_data = 0;
1225 } else {
1226 fw_fill_response(&response, packet->header,
1227 RCODE_TYPE_ERROR, NULL, 0);
1228 goto out;
1229 }
1230
1231 sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1232 reg_write(ohci, OHCI1394_CSRData, lock_data);
1233 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1234 reg_write(ohci, OHCI1394_CSRControl, sel);
1235
1236 for (try = 0; try < 20; try++)
1237 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) {
1238 lock_old = cpu_to_be32(reg_read(ohci,
1239 OHCI1394_CSRData));
1240 fw_fill_response(&response, packet->header,
1241 RCODE_COMPLETE,
1242 &lock_old, sizeof(lock_old));
1243 goto out;
1244 }
1245
1246 fw_error("swap not done (CSR lock timeout)\n");
1247 fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0);
1248
1249 out:
1250 fw_core_handle_response(&ohci->card, &response);
1251 }
1252
1253 static void handle_local_request(struct context *ctx, struct fw_packet *packet)
1254 {
1255 u64 offset, csr;
1256
1257 if (ctx == &ctx->ohci->at_request_ctx) {
1258 packet->ack = ACK_PENDING;
1259 packet->callback(packet, &ctx->ohci->card, packet->ack);
1260 }
1261
1262 offset =
1263 ((unsigned long long)
1264 HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1265 packet->header[2];
1266 csr = offset - CSR_REGISTER_BASE;
1267
1268 /* Handle config rom reads. */
1269 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1270 handle_local_rom(ctx->ohci, packet, csr);
1271 else switch (csr) {
1272 case CSR_BUS_MANAGER_ID:
1273 case CSR_BANDWIDTH_AVAILABLE:
1274 case CSR_CHANNELS_AVAILABLE_HI:
1275 case CSR_CHANNELS_AVAILABLE_LO:
1276 handle_local_lock(ctx->ohci, packet, csr);
1277 break;
1278 default:
1279 if (ctx == &ctx->ohci->at_request_ctx)
1280 fw_core_handle_request(&ctx->ohci->card, packet);
1281 else
1282 fw_core_handle_response(&ctx->ohci->card, packet);
1283 break;
1284 }
1285
1286 if (ctx == &ctx->ohci->at_response_ctx) {
1287 packet->ack = ACK_COMPLETE;
1288 packet->callback(packet, &ctx->ohci->card, packet->ack);
1289 }
1290 }
1291
1292 static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
1293 {
1294 unsigned long flags;
1295 int ret;
1296
1297 spin_lock_irqsave(&ctx->ohci->lock, flags);
1298
1299 if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1300 ctx->ohci->generation == packet->generation) {
1301 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1302 handle_local_request(ctx, packet);
1303 return;
1304 }
1305
1306 ret = at_context_queue_packet(ctx, packet);
1307 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1308
1309 if (ret < 0)
1310 packet->callback(packet, &ctx->ohci->card, packet->ack);
1311
1312 }
1313
1314 static void bus_reset_tasklet(unsigned long data)
1315 {
1316 struct fw_ohci *ohci = (struct fw_ohci *)data;
1317 int self_id_count, i, j, reg;
1318 int generation, new_generation;
1319 unsigned long flags;
1320 void *free_rom = NULL;
1321 dma_addr_t free_rom_bus = 0;
1322
1323 reg = reg_read(ohci, OHCI1394_NodeID);
1324 if (!(reg & OHCI1394_NodeID_idValid)) {
1325 fw_notify("node ID not valid, new bus reset in progress\n");
1326 return;
1327 }
1328 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1329 fw_notify("malconfigured bus\n");
1330 return;
1331 }
1332 ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1333 OHCI1394_NodeID_nodeNumber);
1334
1335 reg = reg_read(ohci, OHCI1394_SelfIDCount);
1336 if (reg & OHCI1394_SelfIDCount_selfIDError) {
1337 fw_notify("inconsistent self IDs\n");
1338 return;
1339 }
1340 /*
1341 * The count in the SelfIDCount register is the number of
1342 * bytes in the self ID receive buffer. Since we also receive
1343 * the inverted quadlets and a header quadlet, we shift one
1344 * bit extra to get the actual number of self IDs.
1345 */
1346 self_id_count = (reg >> 3) & 0xff;
1347 if (self_id_count == 0 || self_id_count > 252) {
1348 fw_notify("inconsistent self IDs\n");
1349 return;
1350 }
1351 generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
1352 rmb();
1353
1354 for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1355 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1356 fw_notify("inconsistent self IDs\n");
1357 return;
1358 }
1359 ohci->self_id_buffer[j] =
1360 cond_le32_to_cpu(ohci->self_id_cpu[i]);
1361 }
1362 rmb();
1363
1364 /*
1365 * Check the consistency of the self IDs we just read. The
1366 * problem we face is that a new bus reset can start while we
1367 * read out the self IDs from the DMA buffer. If this happens,
1368 * the DMA buffer will be overwritten with new self IDs and we
1369 * will read out inconsistent data. The OHCI specification
1370 * (section 11.2) recommends a technique similar to
1371 * linux/seqlock.h, where we remember the generation of the
1372 * self IDs in the buffer before reading them out and compare
1373 * it to the current generation after reading them out. If
1374 * the two generations match we know we have a consistent set
1375 * of self IDs.
1376 */
1377
1378 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1379 if (new_generation != generation) {
1380 fw_notify("recursive bus reset detected, "
1381 "discarding self ids\n");
1382 return;
1383 }
1384
1385 /* FIXME: Document how the locking works. */
1386 spin_lock_irqsave(&ohci->lock, flags);
1387
1388 ohci->generation = generation;
1389 context_stop(&ohci->at_request_ctx);
1390 context_stop(&ohci->at_response_ctx);
1391 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1392
1393 if (ohci->quirks & QUIRK_RESET_PACKET)
1394 ohci->request_generation = generation;
1395
1396 /*
1397 * This next bit is unrelated to the AT context stuff but we
1398 * have to do it under the spinlock also. If a new config rom
1399 * was set up before this reset, the old one is now no longer
1400 * in use and we can free it. Update the config rom pointers
1401 * to point to the current config rom and clear the
1402 * next_config_rom pointer so a new update can take place.
1403 */
1404
1405 if (ohci->next_config_rom != NULL) {
1406 if (ohci->next_config_rom != ohci->config_rom) {
1407 free_rom = ohci->config_rom;
1408 free_rom_bus = ohci->config_rom_bus;
1409 }
1410 ohci->config_rom = ohci->next_config_rom;
1411 ohci->config_rom_bus = ohci->next_config_rom_bus;
1412 ohci->next_config_rom = NULL;
1413
1414 /*
1415 * Restore config_rom image and manually update
1416 * config_rom registers. Writing the header quadlet
1417 * will indicate that the config rom is ready, so we
1418 * do that last.
1419 */
1420 reg_write(ohci, OHCI1394_BusOptions,
1421 be32_to_cpu(ohci->config_rom[2]));
1422 ohci->config_rom[0] = ohci->next_header;
1423 reg_write(ohci, OHCI1394_ConfigROMhdr,
1424 be32_to_cpu(ohci->next_header));
1425 }
1426
1427 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1428 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
1429 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
1430 #endif
1431
1432 spin_unlock_irqrestore(&ohci->lock, flags);
1433
1434 if (free_rom)
1435 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1436 free_rom, free_rom_bus);
1437
1438 log_selfids(ohci->node_id, generation,
1439 self_id_count, ohci->self_id_buffer);
1440
1441 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
1442 self_id_count, ohci->self_id_buffer);
1443 }
1444
1445 static irqreturn_t irq_handler(int irq, void *data)
1446 {
1447 struct fw_ohci *ohci = data;
1448 u32 event, iso_event;
1449 int i;
1450
1451 event = reg_read(ohci, OHCI1394_IntEventClear);
1452
1453 if (!event || !~event)
1454 return IRQ_NONE;
1455
1456 /* busReset must not be cleared yet, see OHCI 1.1 clause 7.2.3.2 */
1457 reg_write(ohci, OHCI1394_IntEventClear, event & ~OHCI1394_busReset);
1458 log_irqs(event);
1459
1460 if (event & OHCI1394_selfIDComplete)
1461 tasklet_schedule(&ohci->bus_reset_tasklet);
1462
1463 if (event & OHCI1394_RQPkt)
1464 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
1465
1466 if (event & OHCI1394_RSPkt)
1467 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
1468
1469 if (event & OHCI1394_reqTxComplete)
1470 tasklet_schedule(&ohci->at_request_ctx.tasklet);
1471
1472 if (event & OHCI1394_respTxComplete)
1473 tasklet_schedule(&ohci->at_response_ctx.tasklet);
1474
1475 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
1476 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
1477
1478 while (iso_event) {
1479 i = ffs(iso_event) - 1;
1480 tasklet_schedule(&ohci->ir_context_list[i].context.tasklet);
1481 iso_event &= ~(1 << i);
1482 }
1483
1484 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
1485 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
1486
1487 while (iso_event) {
1488 i = ffs(iso_event) - 1;
1489 tasklet_schedule(&ohci->it_context_list[i].context.tasklet);
1490 iso_event &= ~(1 << i);
1491 }
1492
1493 if (unlikely(event & OHCI1394_regAccessFail))
1494 fw_error("Register access failure - "
1495 "please notify linux1394-devel@lists.sf.net\n");
1496
1497 if (unlikely(event & OHCI1394_postedWriteErr))
1498 fw_error("PCI posted write error\n");
1499
1500 if (unlikely(event & OHCI1394_cycleTooLong)) {
1501 if (printk_ratelimit())
1502 fw_notify("isochronous cycle too long\n");
1503 reg_write(ohci, OHCI1394_LinkControlSet,
1504 OHCI1394_LinkControl_cycleMaster);
1505 }
1506
1507 if (unlikely(event & OHCI1394_cycleInconsistent)) {
1508 /*
1509 * We need to clear this event bit in order to make
1510 * cycleMatch isochronous I/O work. In theory we should
1511 * stop active cycleMatch iso contexts now and restart
1512 * them at least two cycles later. (FIXME?)
1513 */
1514 if (printk_ratelimit())
1515 fw_notify("isochronous cycle inconsistent\n");
1516 }
1517
1518 return IRQ_HANDLED;
1519 }
1520
1521 static int software_reset(struct fw_ohci *ohci)
1522 {
1523 int i;
1524
1525 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1526
1527 for (i = 0; i < OHCI_LOOP_COUNT; i++) {
1528 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1529 OHCI1394_HCControl_softReset) == 0)
1530 return 0;
1531 msleep(1);
1532 }
1533
1534 return -EBUSY;
1535 }
1536
1537 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
1538 {
1539 size_t size = length * 4;
1540
1541 memcpy(dest, src, size);
1542 if (size < CONFIG_ROM_SIZE)
1543 memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
1544 }
1545
1546 static int configure_1394a_enhancements(struct fw_ohci *ohci)
1547 {
1548 bool enable_1394a;
1549 int ret, clear, set, offset;
1550
1551 /* Check if the driver should configure link and PHY. */
1552 if (!(reg_read(ohci, OHCI1394_HCControlSet) &
1553 OHCI1394_HCControl_programPhyEnable))
1554 return 0;
1555
1556 /* Paranoia: check whether the PHY supports 1394a, too. */
1557 enable_1394a = false;
1558 ret = read_phy_reg(ohci, 2);
1559 if (ret < 0)
1560 return ret;
1561 if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) {
1562 ret = read_paged_phy_reg(ohci, 1, 8);
1563 if (ret < 0)
1564 return ret;
1565 if (ret >= 1)
1566 enable_1394a = true;
1567 }
1568
1569 if (ohci->quirks & QUIRK_NO_1394A)
1570 enable_1394a = false;
1571
1572 /* Configure PHY and link consistently. */
1573 if (enable_1394a) {
1574 clear = 0;
1575 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
1576 } else {
1577 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
1578 set = 0;
1579 }
1580 ret = ohci_update_phy_reg(&ohci->card, 5, clear, set);
1581 if (ret < 0)
1582 return ret;
1583
1584 if (enable_1394a)
1585 offset = OHCI1394_HCControlSet;
1586 else
1587 offset = OHCI1394_HCControlClear;
1588 reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
1589
1590 /* Clean up: configuration has been taken care of. */
1591 reg_write(ohci, OHCI1394_HCControlClear,
1592 OHCI1394_HCControl_programPhyEnable);
1593
1594 return 0;
1595 }
1596
1597 static int ohci_enable(struct fw_card *card,
1598 const __be32 *config_rom, size_t length)
1599 {
1600 struct fw_ohci *ohci = fw_ohci(card);
1601 struct pci_dev *dev = to_pci_dev(card->device);
1602 u32 lps;
1603 int i, ret;
1604
1605 if (software_reset(ohci)) {
1606 fw_error("Failed to reset ohci card.\n");
1607 return -EBUSY;
1608 }
1609
1610 /*
1611 * Now enable LPS, which we need in order to start accessing
1612 * most of the registers. In fact, on some cards (ALI M5251),
1613 * accessing registers in the SClk domain without LPS enabled
1614 * will lock up the machine. Wait 50msec to make sure we have
1615 * full link enabled. However, with some cards (well, at least
1616 * a JMicron PCIe card), we have to try again sometimes.
1617 */
1618 reg_write(ohci, OHCI1394_HCControlSet,
1619 OHCI1394_HCControl_LPS |
1620 OHCI1394_HCControl_postedWriteEnable);
1621 flush_writes(ohci);
1622
1623 for (lps = 0, i = 0; !lps && i < 3; i++) {
1624 msleep(50);
1625 lps = reg_read(ohci, OHCI1394_HCControlSet) &
1626 OHCI1394_HCControl_LPS;
1627 }
1628
1629 if (!lps) {
1630 fw_error("Failed to set Link Power Status\n");
1631 return -EIO;
1632 }
1633
1634 reg_write(ohci, OHCI1394_HCControlClear,
1635 OHCI1394_HCControl_noByteSwapData);
1636
1637 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
1638 reg_write(ohci, OHCI1394_LinkControlClear,
1639 OHCI1394_LinkControl_rcvPhyPkt);
1640 reg_write(ohci, OHCI1394_LinkControlSet,
1641 OHCI1394_LinkControl_rcvSelfID |
1642 OHCI1394_LinkControl_cycleTimerEnable |
1643 OHCI1394_LinkControl_cycleMaster);
1644
1645 reg_write(ohci, OHCI1394_ATRetries,
1646 OHCI1394_MAX_AT_REQ_RETRIES |
1647 (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
1648 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8));
1649
1650 ar_context_run(&ohci->ar_request_ctx);
1651 ar_context_run(&ohci->ar_response_ctx);
1652
1653 reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
1654 reg_write(ohci, OHCI1394_IntEventClear, ~0);
1655 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
1656 reg_write(ohci, OHCI1394_IntMaskSet,
1657 OHCI1394_selfIDComplete |
1658 OHCI1394_RQPkt | OHCI1394_RSPkt |
1659 OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
1660 OHCI1394_isochRx | OHCI1394_isochTx |
1661 OHCI1394_postedWriteErr | OHCI1394_cycleTooLong |
1662 OHCI1394_cycleInconsistent | OHCI1394_regAccessFail |
1663 OHCI1394_masterIntEnable);
1664 if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
1665 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_busReset);
1666
1667 ret = configure_1394a_enhancements(ohci);
1668 if (ret < 0)
1669 return ret;
1670
1671 /* Activate link_on bit and contender bit in our self ID packets.*/
1672 ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER);
1673 if (ret < 0)
1674 return ret;
1675
1676 /*
1677 * When the link is not yet enabled, the atomic config rom
1678 * update mechanism described below in ohci_set_config_rom()
1679 * is not active. We have to update ConfigRomHeader and
1680 * BusOptions manually, and the write to ConfigROMmap takes
1681 * effect immediately. We tie this to the enabling of the
1682 * link, so we have a valid config rom before enabling - the
1683 * OHCI requires that ConfigROMhdr and BusOptions have valid
1684 * values before enabling.
1685 *
1686 * However, when the ConfigROMmap is written, some controllers
1687 * always read back quadlets 0 and 2 from the config rom to
1688 * the ConfigRomHeader and BusOptions registers on bus reset.
1689 * They shouldn't do that in this initial case where the link
1690 * isn't enabled. This means we have to use the same
1691 * workaround here, setting the bus header to 0 and then write
1692 * the right values in the bus reset tasklet.
1693 */
1694
1695 if (config_rom) {
1696 ohci->next_config_rom =
1697 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1698 &ohci->next_config_rom_bus,
1699 GFP_KERNEL);
1700 if (ohci->next_config_rom == NULL)
1701 return -ENOMEM;
1702
1703 copy_config_rom(ohci->next_config_rom, config_rom, length);
1704 } else {
1705 /*
1706 * In the suspend case, config_rom is NULL, which
1707 * means that we just reuse the old config rom.
1708 */
1709 ohci->next_config_rom = ohci->config_rom;
1710 ohci->next_config_rom_bus = ohci->config_rom_bus;
1711 }
1712
1713 ohci->next_header = ohci->next_config_rom[0];
1714 ohci->next_config_rom[0] = 0;
1715 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
1716 reg_write(ohci, OHCI1394_BusOptions,
1717 be32_to_cpu(ohci->next_config_rom[2]));
1718 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
1719
1720 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
1721
1722 if (request_irq(dev->irq, irq_handler,
1723 IRQF_SHARED, ohci_driver_name, ohci)) {
1724 fw_error("Failed to allocate shared interrupt %d.\n",
1725 dev->irq);
1726 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1727 ohci->config_rom, ohci->config_rom_bus);
1728 return -EIO;
1729 }
1730
1731 reg_write(ohci, OHCI1394_HCControlSet,
1732 OHCI1394_HCControl_linkEnable |
1733 OHCI1394_HCControl_BIBimageValid);
1734 flush_writes(ohci);
1735
1736 /*
1737 * We are ready to go, initiate bus reset to finish the
1738 * initialization.
1739 */
1740
1741 fw_core_initiate_bus_reset(&ohci->card, 1);
1742
1743 return 0;
1744 }
1745
1746 static int ohci_set_config_rom(struct fw_card *card,
1747 const __be32 *config_rom, size_t length)
1748 {
1749 struct fw_ohci *ohci;
1750 unsigned long flags;
1751 int ret = -EBUSY;
1752 __be32 *next_config_rom;
1753 dma_addr_t uninitialized_var(next_config_rom_bus);
1754
1755 ohci = fw_ohci(card);
1756
1757 /*
1758 * When the OHCI controller is enabled, the config rom update
1759 * mechanism is a bit tricky, but easy enough to use. See
1760 * section 5.5.6 in the OHCI specification.
1761 *
1762 * The OHCI controller caches the new config rom address in a
1763 * shadow register (ConfigROMmapNext) and needs a bus reset
1764 * for the changes to take place. When the bus reset is
1765 * detected, the controller loads the new values for the
1766 * ConfigRomHeader and BusOptions registers from the specified
1767 * config rom and loads ConfigROMmap from the ConfigROMmapNext
1768 * shadow register. All automatically and atomically.
1769 *
1770 * Now, there's a twist to this story. The automatic load of
1771 * ConfigRomHeader and BusOptions doesn't honor the
1772 * noByteSwapData bit, so with a be32 config rom, the
1773 * controller will load be32 values in to these registers
1774 * during the atomic update, even on litte endian
1775 * architectures. The workaround we use is to put a 0 in the
1776 * header quadlet; 0 is endian agnostic and means that the
1777 * config rom isn't ready yet. In the bus reset tasklet we
1778 * then set up the real values for the two registers.
1779 *
1780 * We use ohci->lock to avoid racing with the code that sets
1781 * ohci->next_config_rom to NULL (see bus_reset_tasklet).
1782 */
1783
1784 next_config_rom =
1785 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1786 &next_config_rom_bus, GFP_KERNEL);
1787 if (next_config_rom == NULL)
1788 return -ENOMEM;
1789
1790 spin_lock_irqsave(&ohci->lock, flags);
1791
1792 if (ohci->next_config_rom == NULL) {
1793 ohci->next_config_rom = next_config_rom;
1794 ohci->next_config_rom_bus = next_config_rom_bus;
1795
1796 copy_config_rom(ohci->next_config_rom, config_rom, length);
1797
1798 ohci->next_header = config_rom[0];
1799 ohci->next_config_rom[0] = 0;
1800
1801 reg_write(ohci, OHCI1394_ConfigROMmap,
1802 ohci->next_config_rom_bus);
1803 ret = 0;
1804 }
1805
1806 spin_unlock_irqrestore(&ohci->lock, flags);
1807
1808 /*
1809 * Now initiate a bus reset to have the changes take
1810 * effect. We clean up the old config rom memory and DMA
1811 * mappings in the bus reset tasklet, since the OHCI
1812 * controller could need to access it before the bus reset
1813 * takes effect.
1814 */
1815 if (ret == 0)
1816 fw_core_initiate_bus_reset(&ohci->card, 1);
1817 else
1818 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1819 next_config_rom, next_config_rom_bus);
1820
1821 return ret;
1822 }
1823
1824 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
1825 {
1826 struct fw_ohci *ohci = fw_ohci(card);
1827
1828 at_context_transmit(&ohci->at_request_ctx, packet);
1829 }
1830
1831 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
1832 {
1833 struct fw_ohci *ohci = fw_ohci(card);
1834
1835 at_context_transmit(&ohci->at_response_ctx, packet);
1836 }
1837
1838 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
1839 {
1840 struct fw_ohci *ohci = fw_ohci(card);
1841 struct context *ctx = &ohci->at_request_ctx;
1842 struct driver_data *driver_data = packet->driver_data;
1843 int ret = -ENOENT;
1844
1845 tasklet_disable(&ctx->tasklet);
1846
1847 if (packet->ack != 0)
1848 goto out;
1849
1850 if (packet->payload_mapped)
1851 dma_unmap_single(ohci->card.device, packet->payload_bus,
1852 packet->payload_length, DMA_TO_DEVICE);
1853
1854 log_ar_at_event('T', packet->speed, packet->header, 0x20);
1855 driver_data->packet = NULL;
1856 packet->ack = RCODE_CANCELLED;
1857 packet->callback(packet, &ohci->card, packet->ack);
1858 ret = 0;
1859 out:
1860 tasklet_enable(&ctx->tasklet);
1861
1862 return ret;
1863 }
1864
1865 static int ohci_enable_phys_dma(struct fw_card *card,
1866 int node_id, int generation)
1867 {
1868 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1869 return 0;
1870 #else
1871 struct fw_ohci *ohci = fw_ohci(card);
1872 unsigned long flags;
1873 int n, ret = 0;
1874
1875 /*
1876 * FIXME: Make sure this bitmask is cleared when we clear the busReset
1877 * interrupt bit. Clear physReqResourceAllBuses on bus reset.
1878 */
1879
1880 spin_lock_irqsave(&ohci->lock, flags);
1881
1882 if (ohci->generation != generation) {
1883 ret = -ESTALE;
1884 goto out;
1885 }
1886
1887 /*
1888 * Note, if the node ID contains a non-local bus ID, physical DMA is
1889 * enabled for _all_ nodes on remote buses.
1890 */
1891
1892 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
1893 if (n < 32)
1894 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
1895 else
1896 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
1897
1898 flush_writes(ohci);
1899 out:
1900 spin_unlock_irqrestore(&ohci->lock, flags);
1901
1902 return ret;
1903 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
1904 }
1905
1906 static u32 cycle_timer_ticks(u32 cycle_timer)
1907 {
1908 u32 ticks;
1909
1910 ticks = cycle_timer & 0xfff;
1911 ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
1912 ticks += (3072 * 8000) * (cycle_timer >> 25);
1913
1914 return ticks;
1915 }
1916
1917 /*
1918 * Some controllers exhibit one or more of the following bugs when updating the
1919 * iso cycle timer register:
1920 * - When the lowest six bits are wrapping around to zero, a read that happens
1921 * at the same time will return garbage in the lowest ten bits.
1922 * - When the cycleOffset field wraps around to zero, the cycleCount field is
1923 * not incremented for about 60 ns.
1924 * - Occasionally, the entire register reads zero.
1925 *
1926 * To catch these, we read the register three times and ensure that the
1927 * difference between each two consecutive reads is approximately the same, i.e.
1928 * less than twice the other. Furthermore, any negative difference indicates an
1929 * error. (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
1930 * execute, so we have enough precision to compute the ratio of the differences.)
1931 */
1932 static u32 ohci_get_cycle_time(struct fw_card *card)
1933 {
1934 struct fw_ohci *ohci = fw_ohci(card);
1935 u32 c0, c1, c2;
1936 u32 t0, t1, t2;
1937 s32 diff01, diff12;
1938 int i;
1939
1940 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1941
1942 if (ohci->quirks & QUIRK_CYCLE_TIMER) {
1943 i = 0;
1944 c1 = c2;
1945 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1946 do {
1947 c0 = c1;
1948 c1 = c2;
1949 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1950 t0 = cycle_timer_ticks(c0);
1951 t1 = cycle_timer_ticks(c1);
1952 t2 = cycle_timer_ticks(c2);
1953 diff01 = t1 - t0;
1954 diff12 = t2 - t1;
1955 } while ((diff01 <= 0 || diff12 <= 0 ||
1956 diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
1957 && i++ < 20);
1958 }
1959
1960 return c2;
1961 }
1962
1963 static void copy_iso_headers(struct iso_context *ctx, void *p)
1964 {
1965 int i = ctx->header_length;
1966
1967 if (i + ctx->base.header_size > PAGE_SIZE)
1968 return;
1969
1970 /*
1971 * The iso header is byteswapped to little endian by
1972 * the controller, but the remaining header quadlets
1973 * are big endian. We want to present all the headers
1974 * as big endian, so we have to swap the first quadlet.
1975 */
1976 if (ctx->base.header_size > 0)
1977 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
1978 if (ctx->base.header_size > 4)
1979 *(u32 *) (ctx->header + i + 4) = __swab32(*(u32 *) p);
1980 if (ctx->base.header_size > 8)
1981 memcpy(ctx->header + i + 8, p + 8, ctx->base.header_size - 8);
1982 ctx->header_length += ctx->base.header_size;
1983 }
1984
1985 static int handle_ir_packet_per_buffer(struct context *context,
1986 struct descriptor *d,
1987 struct descriptor *last)
1988 {
1989 struct iso_context *ctx =
1990 container_of(context, struct iso_context, context);
1991 struct descriptor *pd;
1992 __le32 *ir_header;
1993 void *p;
1994
1995 for (pd = d; pd <= last; pd++) {
1996 if (pd->transfer_status)
1997 break;
1998 }
1999 if (pd > last)
2000 /* Descriptor(s) not done yet, stop iteration */
2001 return 0;
2002
2003 p = last + 1;
2004 copy_iso_headers(ctx, p);
2005
2006 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2007 ir_header = (__le32 *) p;
2008 ctx->base.callback(&ctx->base,
2009 le32_to_cpu(ir_header[0]) & 0xffff,
2010 ctx->header_length, ctx->header,
2011 ctx->base.callback_data);
2012 ctx->header_length = 0;
2013 }
2014
2015 return 1;
2016 }
2017
2018 static int handle_it_packet(struct context *context,
2019 struct descriptor *d,
2020 struct descriptor *last)
2021 {
2022 struct iso_context *ctx =
2023 container_of(context, struct iso_context, context);
2024 int i;
2025 struct descriptor *pd;
2026
2027 for (pd = d; pd <= last; pd++)
2028 if (pd->transfer_status)
2029 break;
2030 if (pd > last)
2031 /* Descriptor(s) not done yet, stop iteration */
2032 return 0;
2033
2034 i = ctx->header_length;
2035 if (i + 4 < PAGE_SIZE) {
2036 /* Present this value as big-endian to match the receive code */
2037 *(__be32 *)(ctx->header + i) = cpu_to_be32(
2038 ((u32)le16_to_cpu(pd->transfer_status) << 16) |
2039 le16_to_cpu(pd->res_count));
2040 ctx->header_length += 4;
2041 }
2042 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2043 ctx->base.callback(&ctx->base, le16_to_cpu(last->res_count),
2044 ctx->header_length, ctx->header,
2045 ctx->base.callback_data);
2046 ctx->header_length = 0;
2047 }
2048 return 1;
2049 }
2050
2051 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
2052 int type, int channel, size_t header_size)
2053 {
2054 struct fw_ohci *ohci = fw_ohci(card);
2055 struct iso_context *ctx, *list;
2056 descriptor_callback_t callback;
2057 u64 *channels, dont_care = ~0ULL;
2058 u32 *mask, regs;
2059 unsigned long flags;
2060 int index, ret = -ENOMEM;
2061
2062 if (type == FW_ISO_CONTEXT_TRANSMIT) {
2063 channels = &dont_care;
2064 mask = &ohci->it_context_mask;
2065 list = ohci->it_context_list;
2066 callback = handle_it_packet;
2067 } else {
2068 channels = &ohci->ir_context_channels;
2069 mask = &ohci->ir_context_mask;
2070 list = ohci->ir_context_list;
2071 callback = handle_ir_packet_per_buffer;
2072 }
2073
2074 spin_lock_irqsave(&ohci->lock, flags);
2075 index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
2076 if (index >= 0) {
2077 *channels &= ~(1ULL << channel);
2078 *mask &= ~(1 << index);
2079 }
2080 spin_unlock_irqrestore(&ohci->lock, flags);
2081
2082 if (index < 0)
2083 return ERR_PTR(-EBUSY);
2084
2085 if (type == FW_ISO_CONTEXT_TRANSMIT)
2086 regs = OHCI1394_IsoXmitContextBase(index);
2087 else
2088 regs = OHCI1394_IsoRcvContextBase(index);
2089
2090 ctx = &list[index];
2091 memset(ctx, 0, sizeof(*ctx));
2092 ctx->header_length = 0;
2093 ctx->header = (void *) __get_free_page(GFP_KERNEL);
2094 if (ctx->header == NULL)
2095 goto out;
2096
2097 ret = context_init(&ctx->context, ohci, regs, callback);
2098 if (ret < 0)
2099 goto out_with_header;
2100
2101 return &ctx->base;
2102
2103 out_with_header:
2104 free_page((unsigned long)ctx->header);
2105 out:
2106 spin_lock_irqsave(&ohci->lock, flags);
2107 *mask |= 1 << index;
2108 spin_unlock_irqrestore(&ohci->lock, flags);
2109
2110 return ERR_PTR(ret);
2111 }
2112
2113 static int ohci_start_iso(struct fw_iso_context *base,
2114 s32 cycle, u32 sync, u32 tags)
2115 {
2116 struct iso_context *ctx = container_of(base, struct iso_context, base);
2117 struct fw_ohci *ohci = ctx->context.ohci;
2118 u32 control, match;
2119 int index;
2120
2121 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
2122 index = ctx - ohci->it_context_list;
2123 match = 0;
2124 if (cycle >= 0)
2125 match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
2126 (cycle & 0x7fff) << 16;
2127
2128 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
2129 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
2130 context_run(&ctx->context, match);
2131 } else {
2132 index = ctx - ohci->ir_context_list;
2133 control = IR_CONTEXT_ISOCH_HEADER;
2134 match = (tags << 28) | (sync << 8) | ctx->base.channel;
2135 if (cycle >= 0) {
2136 match |= (cycle & 0x07fff) << 12;
2137 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
2138 }
2139
2140 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
2141 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
2142 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
2143 context_run(&ctx->context, control);
2144 }
2145
2146 return 0;
2147 }
2148
2149 static int ohci_stop_iso(struct fw_iso_context *base)
2150 {
2151 struct fw_ohci *ohci = fw_ohci(base->card);
2152 struct iso_context *ctx = container_of(base, struct iso_context, base);
2153 int index;
2154
2155 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
2156 index = ctx - ohci->it_context_list;
2157 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
2158 } else {
2159 index = ctx - ohci->ir_context_list;
2160 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
2161 }
2162 flush_writes(ohci);
2163 context_stop(&ctx->context);
2164
2165 return 0;
2166 }
2167
2168 static void ohci_free_iso_context(struct fw_iso_context *base)
2169 {
2170 struct fw_ohci *ohci = fw_ohci(base->card);
2171 struct iso_context *ctx = container_of(base, struct iso_context, base);
2172 unsigned long flags;
2173 int index;
2174
2175 ohci_stop_iso(base);
2176 context_release(&ctx->context);
2177 free_page((unsigned long)ctx->header);
2178
2179 spin_lock_irqsave(&ohci->lock, flags);
2180
2181 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
2182 index = ctx - ohci->it_context_list;
2183 ohci->it_context_mask |= 1 << index;
2184 } else {
2185 index = ctx - ohci->ir_context_list;
2186 ohci->ir_context_mask |= 1 << index;
2187 ohci->ir_context_channels |= 1ULL << base->channel;
2188 }
2189
2190 spin_unlock_irqrestore(&ohci->lock, flags);
2191 }
2192
2193 static int ohci_queue_iso_transmit(struct fw_iso_context *base,
2194 struct fw_iso_packet *packet,
2195 struct fw_iso_buffer *buffer,
2196 unsigned long payload)
2197 {
2198 struct iso_context *ctx = container_of(base, struct iso_context, base);
2199 struct descriptor *d, *last, *pd;
2200 struct fw_iso_packet *p;
2201 __le32 *header;
2202 dma_addr_t d_bus, page_bus;
2203 u32 z, header_z, payload_z, irq;
2204 u32 payload_index, payload_end_index, next_page_index;
2205 int page, end_page, i, length, offset;
2206
2207 p = packet;
2208 payload_index = payload;
2209
2210 if (p->skip)
2211 z = 1;
2212 else
2213 z = 2;
2214 if (p->header_length > 0)
2215 z++;
2216
2217 /* Determine the first page the payload isn't contained in. */
2218 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
2219 if (p->payload_length > 0)
2220 payload_z = end_page - (payload_index >> PAGE_SHIFT);
2221 else
2222 payload_z = 0;
2223
2224 z += payload_z;
2225
2226 /* Get header size in number of descriptors. */
2227 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
2228
2229 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
2230 if (d == NULL)
2231 return -ENOMEM;
2232
2233 if (!p->skip) {
2234 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
2235 d[0].req_count = cpu_to_le16(8);
2236 /*
2237 * Link the skip address to this descriptor itself. This causes
2238 * a context to skip a cycle whenever lost cycles or FIFO
2239 * overruns occur, without dropping the data. The application
2240 * should then decide whether this is an error condition or not.
2241 * FIXME: Make the context's cycle-lost behaviour configurable?
2242 */
2243 d[0].branch_address = cpu_to_le32(d_bus | z);
2244
2245 header = (__le32 *) &d[1];
2246 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
2247 IT_HEADER_TAG(p->tag) |
2248 IT_HEADER_TCODE(TCODE_STREAM_DATA) |
2249 IT_HEADER_CHANNEL(ctx->base.channel) |
2250 IT_HEADER_SPEED(ctx->base.speed));
2251 header[1] =
2252 cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
2253 p->payload_length));
2254 }
2255
2256 if (p->header_length > 0) {
2257 d[2].req_count = cpu_to_le16(p->header_length);
2258 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
2259 memcpy(&d[z], p->header, p->header_length);
2260 }
2261
2262 pd = d + z - payload_z;
2263 payload_end_index = payload_index + p->payload_length;
2264 for (i = 0; i < payload_z; i++) {
2265 page = payload_index >> PAGE_SHIFT;
2266 offset = payload_index & ~PAGE_MASK;
2267 next_page_index = (page + 1) << PAGE_SHIFT;
2268 length =
2269 min(next_page_index, payload_end_index) - payload_index;
2270 pd[i].req_count = cpu_to_le16(length);
2271
2272 page_bus = page_private(buffer->pages[page]);
2273 pd[i].data_address = cpu_to_le32(page_bus + offset);
2274
2275 payload_index += length;
2276 }
2277
2278 if (p->interrupt)
2279 irq = DESCRIPTOR_IRQ_ALWAYS;
2280 else
2281 irq = DESCRIPTOR_NO_IRQ;
2282
2283 last = z == 2 ? d : d + z - 1;
2284 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
2285 DESCRIPTOR_STATUS |
2286 DESCRIPTOR_BRANCH_ALWAYS |
2287 irq);
2288
2289 context_append(&ctx->context, d, z, header_z);
2290
2291 return 0;
2292 }
2293
2294 static int ohci_queue_iso_receive_packet_per_buffer(struct fw_iso_context *base,
2295 struct fw_iso_packet *packet,
2296 struct fw_iso_buffer *buffer,
2297 unsigned long payload)
2298 {
2299 struct iso_context *ctx = container_of(base, struct iso_context, base);
2300 struct descriptor *d, *pd;
2301 struct fw_iso_packet *p = packet;
2302 dma_addr_t d_bus, page_bus;
2303 u32 z, header_z, rest;
2304 int i, j, length;
2305 int page, offset, packet_count, header_size, payload_per_buffer;
2306
2307 /*
2308 * The OHCI controller puts the isochronous header and trailer in the
2309 * buffer, so we need at least 8 bytes.
2310 */
2311 packet_count = p->header_length / ctx->base.header_size;
2312 header_size = max(ctx->base.header_size, (size_t)8);
2313
2314 /* Get header size in number of descriptors. */
2315 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2316 page = payload >> PAGE_SHIFT;
2317 offset = payload & ~PAGE_MASK;
2318 payload_per_buffer = p->payload_length / packet_count;
2319
2320 for (i = 0; i < packet_count; i++) {
2321 /* d points to the header descriptor */
2322 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
2323 d = context_get_descriptors(&ctx->context,
2324 z + header_z, &d_bus);
2325 if (d == NULL)
2326 return -ENOMEM;
2327
2328 d->control = cpu_to_le16(DESCRIPTOR_STATUS |
2329 DESCRIPTOR_INPUT_MORE);
2330 if (p->skip && i == 0)
2331 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2332 d->req_count = cpu_to_le16(header_size);
2333 d->res_count = d->req_count;
2334 d->transfer_status = 0;
2335 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
2336
2337 rest = payload_per_buffer;
2338 pd = d;
2339 for (j = 1; j < z; j++) {
2340 pd++;
2341 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2342 DESCRIPTOR_INPUT_MORE);
2343
2344 if (offset + rest < PAGE_SIZE)
2345 length = rest;
2346 else
2347 length = PAGE_SIZE - offset;
2348 pd->req_count = cpu_to_le16(length);
2349 pd->res_count = pd->req_count;
2350 pd->transfer_status = 0;
2351
2352 page_bus = page_private(buffer->pages[page]);
2353 pd->data_address = cpu_to_le32(page_bus + offset);
2354
2355 offset = (offset + length) & ~PAGE_MASK;
2356 rest -= length;
2357 if (offset == 0)
2358 page++;
2359 }
2360 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2361 DESCRIPTOR_INPUT_LAST |
2362 DESCRIPTOR_BRANCH_ALWAYS);
2363 if (p->interrupt && i == packet_count - 1)
2364 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2365
2366 context_append(&ctx->context, d, z, header_z);
2367 }
2368
2369 return 0;
2370 }
2371
2372 static int ohci_queue_iso(struct fw_iso_context *base,
2373 struct fw_iso_packet *packet,
2374 struct fw_iso_buffer *buffer,
2375 unsigned long payload)
2376 {
2377 struct iso_context *ctx = container_of(base, struct iso_context, base);
2378 unsigned long flags;
2379 int ret;
2380
2381 spin_lock_irqsave(&ctx->context.ohci->lock, flags);
2382 if (base->type == FW_ISO_CONTEXT_TRANSMIT)
2383 ret = ohci_queue_iso_transmit(base, packet, buffer, payload);
2384 else
2385 ret = ohci_queue_iso_receive_packet_per_buffer(base, packet,
2386 buffer, payload);
2387 spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
2388
2389 return ret;
2390 }
2391
2392 static const struct fw_card_driver ohci_driver = {
2393 .enable = ohci_enable,
2394 .update_phy_reg = ohci_update_phy_reg,
2395 .set_config_rom = ohci_set_config_rom,
2396 .send_request = ohci_send_request,
2397 .send_response = ohci_send_response,
2398 .cancel_packet = ohci_cancel_packet,
2399 .enable_phys_dma = ohci_enable_phys_dma,
2400 .get_cycle_time = ohci_get_cycle_time,
2401
2402 .allocate_iso_context = ohci_allocate_iso_context,
2403 .free_iso_context = ohci_free_iso_context,
2404 .queue_iso = ohci_queue_iso,
2405 .start_iso = ohci_start_iso,
2406 .stop_iso = ohci_stop_iso,
2407 };
2408
2409 #ifdef CONFIG_PPC_PMAC
2410 static void pmac_ohci_on(struct pci_dev *dev)
2411 {
2412 if (machine_is(powermac)) {
2413 struct device_node *ofn = pci_device_to_OF_node(dev);
2414
2415 if (ofn) {
2416 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
2417 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
2418 }
2419 }
2420 }
2421
2422 static void pmac_ohci_off(struct pci_dev *dev)
2423 {
2424 if (machine_is(powermac)) {
2425 struct device_node *ofn = pci_device_to_OF_node(dev);
2426
2427 if (ofn) {
2428 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
2429 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
2430 }
2431 }
2432 }
2433 #else
2434 static inline void pmac_ohci_on(struct pci_dev *dev) {}
2435 static inline void pmac_ohci_off(struct pci_dev *dev) {}
2436 #endif /* CONFIG_PPC_PMAC */
2437
2438 static int __devinit pci_probe(struct pci_dev *dev,
2439 const struct pci_device_id *ent)
2440 {
2441 struct fw_ohci *ohci;
2442 u32 bus_options, max_receive, link_speed, version, link_enh;
2443 u64 guid;
2444 int i, err, n_ir, n_it;
2445 size_t size;
2446
2447 ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
2448 if (ohci == NULL) {
2449 err = -ENOMEM;
2450 goto fail;
2451 }
2452
2453 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
2454
2455 pmac_ohci_on(dev);
2456
2457 err = pci_enable_device(dev);
2458 if (err) {
2459 fw_error("Failed to enable OHCI hardware\n");
2460 goto fail_free;
2461 }
2462
2463 pci_set_master(dev);
2464 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
2465 pci_set_drvdata(dev, ohci);
2466
2467 spin_lock_init(&ohci->lock);
2468
2469 tasklet_init(&ohci->bus_reset_tasklet,
2470 bus_reset_tasklet, (unsigned long)ohci);
2471
2472 err = pci_request_region(dev, 0, ohci_driver_name);
2473 if (err) {
2474 fw_error("MMIO resource unavailable\n");
2475 goto fail_disable;
2476 }
2477
2478 ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
2479 if (ohci->registers == NULL) {
2480 fw_error("Failed to remap registers\n");
2481 err = -ENXIO;
2482 goto fail_iomem;
2483 }
2484
2485 for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++)
2486 if (ohci_quirks[i].vendor == dev->vendor &&
2487 (ohci_quirks[i].device == dev->device ||
2488 ohci_quirks[i].device == (unsigned short)PCI_ANY_ID)) {
2489 ohci->quirks = ohci_quirks[i].flags;
2490 break;
2491 }
2492 if (param_quirks)
2493 ohci->quirks = param_quirks;
2494
2495 /* TI OHCI-Lynx and compatible: set recommended configuration bits. */
2496 if (dev->vendor == PCI_VENDOR_ID_TI) {
2497 pci_read_config_dword(dev, PCI_CFG_TI_LinkEnh, &link_enh);
2498
2499 /* adjust latency of ATx FIFO: use 1.7 KB threshold */
2500 link_enh &= ~TI_LinkEnh_atx_thresh_mask;
2501 link_enh |= TI_LinkEnh_atx_thresh_1_7K;
2502
2503 /* use priority arbitration for asynchronous responses */
2504 link_enh |= TI_LinkEnh_enab_unfair;
2505
2506 /* required for aPhyEnhanceEnable to work */
2507 link_enh |= TI_LinkEnh_enab_accel;
2508
2509 pci_write_config_dword(dev, PCI_CFG_TI_LinkEnh, link_enh);
2510 }
2511
2512 ar_context_init(&ohci->ar_request_ctx, ohci,
2513 OHCI1394_AsReqRcvContextControlSet);
2514
2515 ar_context_init(&ohci->ar_response_ctx, ohci,
2516 OHCI1394_AsRspRcvContextControlSet);
2517
2518 context_init(&ohci->at_request_ctx, ohci,
2519 OHCI1394_AsReqTrContextControlSet, handle_at_packet);
2520
2521 context_init(&ohci->at_response_ctx, ohci,
2522 OHCI1394_AsRspTrContextControlSet, handle_at_packet);
2523
2524 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
2525 ohci->ir_context_channels = ~0ULL;
2526 ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
2527 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
2528 n_ir = hweight32(ohci->ir_context_mask);
2529 size = sizeof(struct iso_context) * n_ir;
2530 ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
2531
2532 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
2533 ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
2534 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
2535 n_it = hweight32(ohci->it_context_mask);
2536 size = sizeof(struct iso_context) * n_it;
2537 ohci->it_context_list = kzalloc(size, GFP_KERNEL);
2538
2539 if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
2540 err = -ENOMEM;
2541 goto fail_contexts;
2542 }
2543
2544 /* self-id dma buffer allocation */
2545 ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device,
2546 SELF_ID_BUF_SIZE,
2547 &ohci->self_id_bus,
2548 GFP_KERNEL);
2549 if (ohci->self_id_cpu == NULL) {
2550 err = -ENOMEM;
2551 goto fail_contexts;
2552 }
2553
2554 bus_options = reg_read(ohci, OHCI1394_BusOptions);
2555 max_receive = (bus_options >> 12) & 0xf;
2556 link_speed = bus_options & 0x7;
2557 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
2558 reg_read(ohci, OHCI1394_GUIDLo);
2559
2560 err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
2561 if (err)
2562 goto fail_self_id;
2563
2564 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2565 fw_notify("Added fw-ohci device %s, OHCI v%x.%x, "
2566 "%d IR + %d IT contexts, quirks 0x%x\n",
2567 dev_name(&dev->dev), version >> 16, version & 0xff,
2568 n_ir, n_it, ohci->quirks);
2569
2570 return 0;
2571
2572 fail_self_id:
2573 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2574 ohci->self_id_cpu, ohci->self_id_bus);
2575 fail_contexts:
2576 kfree(ohci->ir_context_list);
2577 kfree(ohci->it_context_list);
2578 context_release(&ohci->at_response_ctx);
2579 context_release(&ohci->at_request_ctx);
2580 ar_context_release(&ohci->ar_response_ctx);
2581 ar_context_release(&ohci->ar_request_ctx);
2582 pci_iounmap(dev, ohci->registers);
2583 fail_iomem:
2584 pci_release_region(dev, 0);
2585 fail_disable:
2586 pci_disable_device(dev);
2587 fail_free:
2588 kfree(&ohci->card);
2589 pmac_ohci_off(dev);
2590 fail:
2591 if (err == -ENOMEM)
2592 fw_error("Out of memory\n");
2593
2594 return err;
2595 }
2596
2597 static void pci_remove(struct pci_dev *dev)
2598 {
2599 struct fw_ohci *ohci;
2600
2601 ohci = pci_get_drvdata(dev);
2602 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2603 flush_writes(ohci);
2604 fw_core_remove_card(&ohci->card);
2605
2606 /*
2607 * FIXME: Fail all pending packets here, now that the upper
2608 * layers can't queue any more.
2609 */
2610
2611 software_reset(ohci);
2612 free_irq(dev->irq, ohci);
2613
2614 if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
2615 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2616 ohci->next_config_rom, ohci->next_config_rom_bus);
2617 if (ohci->config_rom)
2618 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2619 ohci->config_rom, ohci->config_rom_bus);
2620 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2621 ohci->self_id_cpu, ohci->self_id_bus);
2622 ar_context_release(&ohci->ar_request_ctx);
2623 ar_context_release(&ohci->ar_response_ctx);
2624 context_release(&ohci->at_request_ctx);
2625 context_release(&ohci->at_response_ctx);
2626 kfree(ohci->it_context_list);
2627 kfree(ohci->ir_context_list);
2628 pci_iounmap(dev, ohci->registers);
2629 pci_release_region(dev, 0);
2630 pci_disable_device(dev);
2631 kfree(&ohci->card);
2632 pmac_ohci_off(dev);
2633
2634 fw_notify("Removed fw-ohci device.\n");
2635 }
2636
2637 #ifdef CONFIG_PM
2638 static int pci_suspend(struct pci_dev *dev, pm_message_t state)
2639 {
2640 struct fw_ohci *ohci = pci_get_drvdata(dev);
2641 int err;
2642
2643 software_reset(ohci);
2644 free_irq(dev->irq, ohci);
2645 err = pci_save_state(dev);
2646 if (err) {
2647 fw_error("pci_save_state failed\n");
2648 return err;
2649 }
2650 err = pci_set_power_state(dev, pci_choose_state(dev, state));
2651 if (err)
2652 fw_error("pci_set_power_state failed with %d\n", err);
2653 pmac_ohci_off(dev);
2654
2655 return 0;
2656 }
2657
2658 static int pci_resume(struct pci_dev *dev)
2659 {
2660 struct fw_ohci *ohci = pci_get_drvdata(dev);
2661 int err;
2662
2663 pmac_ohci_on(dev);
2664 pci_set_power_state(dev, PCI_D0);
2665 pci_restore_state(dev);
2666 err = pci_enable_device(dev);
2667 if (err) {
2668 fw_error("pci_enable_device failed\n");
2669 return err;
2670 }
2671
2672 return ohci_enable(&ohci->card, NULL, 0);
2673 }
2674 #endif
2675
2676 static const struct pci_device_id pci_table[] = {
2677 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
2678 { }
2679 };
2680
2681 MODULE_DEVICE_TABLE(pci, pci_table);
2682
2683 static struct pci_driver fw_ohci_pci_driver = {
2684 .name = ohci_driver_name,
2685 .id_table = pci_table,
2686 .probe = pci_probe,
2687 .remove = pci_remove,
2688 #ifdef CONFIG_PM
2689 .resume = pci_resume,
2690 .suspend = pci_suspend,
2691 #endif
2692 };
2693
2694 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
2695 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
2696 MODULE_LICENSE("GPL");
2697
2698 /* Provide a module alias so root-on-sbp2 initrds don't break. */
2699 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
2700 MODULE_ALIAS("ohci1394");
2701 #endif
2702
2703 static int __init fw_ohci_init(void)
2704 {
2705 return pci_register_driver(&fw_ohci_pci_driver);
2706 }
2707
2708 static void __exit fw_ohci_cleanup(void)
2709 {
2710 pci_unregister_driver(&fw_ohci_pci_driver);
2711 }
2712
2713 module_init(fw_ohci_init);
2714 module_exit(fw_ohci_cleanup);
kernel-based virtual machine