drivers/mmc/host/sdhci.h

   1 /*
   2  *  linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver
   3  *
   4  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or (at
   9  * your option) any later version.
  10  */
  11 #ifndef __SDHCI_H
  12 #define __SDHCI_H
  13
  14 #include <linux/scatterlist.h>
  15 #include <linux/compiler.h>
  16 #include <linux/types.h>
  17 #include <linux/io.h>
  18
  19 /*
  20  * Controller registers
  21  */
  22
  23 #define SDHCI_DMA_ADDRESS       0x00
  24
  25 #define SDHCI_BLOCK_SIZE        0x04
  26 #define  SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
  27
  28 #define SDHCI_BLOCK_COUNT       0x06
  29
  30 #define SDHCI_ARGUMENT          0x08
  31
  32 #define SDHCI_TRANSFER_MODE     0x0C
  33 #define  SDHCI_TRNS_DMA         0x01
  34 #define  SDHCI_TRNS_BLK_CNT_EN  0x02
  35 #define  SDHCI_TRNS_ACMD12      0x04
  36 #define  SDHCI_TRNS_READ        0x10
  37 #define  SDHCI_TRNS_MULTI       0x20
  38
  39 #define SDHCI_COMMAND           0x0E
  40 #define  SDHCI_CMD_RESP_MASK    0x03
  41 #define  SDHCI_CMD_CRC          0x08
  42 #define  SDHCI_CMD_INDEX        0x10
  43 #define  SDHCI_CMD_DATA         0x20
  44
  45 #define  SDHCI_CMD_RESP_NONE    0x00
  46 #define  SDHCI_CMD_RESP_LONG    0x01
  47 #define  SDHCI_CMD_RESP_SHORT   0x02
  48 #define  SDHCI_CMD_RESP_SHORT_BUSY 0x03
  49
  50 #define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
  51
  52 #define SDHCI_RESPONSE          0x10
  53
  54 #define SDHCI_BUFFER            0x20
  55
  56 #define SDHCI_PRESENT_STATE     0x24
  57 #define  SDHCI_CMD_INHIBIT      0x00000001
  58 #define  SDHCI_DATA_INHIBIT     0x00000002
  59 #define  SDHCI_DOING_WRITE      0x00000100
  60 #define  SDHCI_DOING_READ       0x00000200
  61 #define  SDHCI_SPACE_AVAILABLE  0x00000400
  62 #define  SDHCI_DATA_AVAILABLE   0x00000800
  63 #define  SDHCI_CARD_PRESENT     0x00010000
  64 #define  SDHCI_WRITE_PROTECT    0x00080000
  65
  66 #define SDHCI_HOST_CONTROL      0x28
  67 #define  SDHCI_CTRL_LED         0x01
  68 #define  SDHCI_CTRL_4BITBUS     0x02
  69 #define  SDHCI_CTRL_HISPD       0x04
  70 #define  SDHCI_CTRL_DMA_MASK    0x18
  71 #define   SDHCI_CTRL_SDMA       0x00
  72 #define   SDHCI_CTRL_ADMA1      0x08
  73 #define   SDHCI_CTRL_ADMA32     0x10
  74 #define   SDHCI_CTRL_ADMA64     0x18
  75
  76 #define SDHCI_POWER_CONTROL     0x29
  77 #define  SDHCI_POWER_ON         0x01
  78 #define  SDHCI_POWER_180        0x0A
  79 #define  SDHCI_POWER_300        0x0C
  80 #define  SDHCI_POWER_330        0x0E
  81
  82 #define SDHCI_BLOCK_GAP_CONTROL 0x2A
  83
  84 #define SDHCI_WAKE_UP_CONTROL   0x2B
  85
  86 #define SDHCI_CLOCK_CONTROL     0x2C
  87 #define  SDHCI_DIVIDER_SHIFT    8
  88 #define  SDHCI_CLOCK_CARD_EN    0x0004
  89 #define  SDHCI_CLOCK_INT_STABLE 0x0002
  90 #define  SDHCI_CLOCK_INT_EN     0x0001
  91
  92 #define SDHCI_TIMEOUT_CONTROL   0x2E
  93
  94 #define SDHCI_SOFTWARE_RESET    0x2F
  95 #define  SDHCI_RESET_ALL        0x01
  96 #define  SDHCI_RESET_CMD        0x02
  97 #define  SDHCI_RESET_DATA       0x04
  98
  99 #define SDHCI_INT_STATUS        0x30
 100 #define SDHCI_INT_ENABLE        0x34
 101 #define SDHCI_SIGNAL_ENABLE     0x38
 102 #define  SDHCI_INT_RESPONSE     0x00000001
 103 #define  SDHCI_INT_DATA_END     0x00000002
 104 #define  SDHCI_INT_DMA_END      0x00000008
 105 #define  SDHCI_INT_SPACE_AVAIL  0x00000010
 106 #define  SDHCI_INT_DATA_AVAIL   0x00000020
 107 #define  SDHCI_INT_CARD_INSERT  0x00000040
 108 #define  SDHCI_INT_CARD_REMOVE  0x00000080
 109 #define  SDHCI_INT_CARD_INT     0x00000100
 110 #define  SDHCI_INT_ERROR        0x00008000
 111 #define  SDHCI_INT_TIMEOUT      0x00010000
 112 #define  SDHCI_INT_CRC          0x00020000
 113 #define  SDHCI_INT_END_BIT      0x00040000
 114 #define  SDHCI_INT_INDEX        0x00080000
 115 #define  SDHCI_INT_DATA_TIMEOUT 0x00100000
 116 #define  SDHCI_INT_DATA_CRC     0x00200000
 117 #define  SDHCI_INT_DATA_END_BIT 0x00400000
 118 #define  SDHCI_INT_BUS_POWER    0x00800000
 119 #define  SDHCI_INT_ACMD12ERR    0x01000000
 120 #define  SDHCI_INT_ADMA_ERROR   0x02000000
 121
 122 #define  SDHCI_INT_NORMAL_MASK  0x00007FFF
 123 #define  SDHCI_INT_ERROR_MASK   0xFFFF8000
 124
 125 #define  SDHCI_INT_CMD_MASK     (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
 126                 SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)
 127 #define  SDHCI_INT_DATA_MASK    (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
 128                 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
 129                 SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
 130                 SDHCI_INT_DATA_END_BIT | SDHCI_ADMA_ERROR)
 131 #define SDHCI_INT_ALL_MASK      ((unsigned int)-1)
 132
 133 #define SDHCI_ACMD12_ERR        0x3C
 134
 135 /* 3E-3F reserved */
 136
 137 #define SDHCI_CAPABILITIES      0x40
 138 #define  SDHCI_TIMEOUT_CLK_MASK 0x0000003F
 139 #define  SDHCI_TIMEOUT_CLK_SHIFT 0
 140 #define  SDHCI_TIMEOUT_CLK_UNIT 0x00000080
 141 #define  SDHCI_CLOCK_BASE_MASK  0x00003F00
 142 #define  SDHCI_CLOCK_BASE_SHIFT 8
 143 #define  SDHCI_MAX_BLOCK_MASK   0x00030000
 144 #define  SDHCI_MAX_BLOCK_SHIFT  16
 145 #define  SDHCI_CAN_DO_ADMA2     0x00080000
 146 #define  SDHCI_CAN_DO_ADMA1     0x00100000
 147 #define  SDHCI_CAN_DO_HISPD     0x00200000
 148 #define  SDHCI_CAN_DO_SDMA      0x00400000
 149 #define  SDHCI_CAN_VDD_330      0x01000000
 150 #define  SDHCI_CAN_VDD_300      0x02000000
 151 #define  SDHCI_CAN_VDD_180      0x04000000
 152 #define  SDHCI_CAN_64BIT        0x10000000
 153
 154 /* 44-47 reserved for more caps */
 155
 156 #define SDHCI_MAX_CURRENT       0x48
 157
 158 /* 4C-4F reserved for more max current */
 159
 160 #define SDHCI_SET_ACMD12_ERROR  0x50
 161 #define SDHCI_SET_INT_ERROR     0x52
 162
 163 #define SDHCI_ADMA_ERROR        0x54
 164
 165 /* 55-57 reserved */
 166
 167 #define SDHCI_ADMA_ADDRESS      0x58
 168
 169 /* 60-FB reserved */
 170
 171 #define SDHCI_SLOT_INT_STATUS   0xFC
 172
 173 #define SDHCI_HOST_VERSION      0xFE
 174 #define  SDHCI_VENDOR_VER_MASK  0xFF00
 175 #define  SDHCI_VENDOR_VER_SHIFT 8
 176 #define  SDHCI_SPEC_VER_MASK    0x00FF
 177 #define  SDHCI_SPEC_VER_SHIFT   0
 178 #define   SDHCI_SPEC_100        0
 179 #define   SDHCI_SPEC_200        1
 180
 181 struct sdhci_ops;
 182
 183 struct sdhci_host {
 184         /* Data set by hardware interface driver */
 185         const char              *hw_name;       /* Hardware bus name */
 186
 187         unsigned int            quirks;         /* Deviations from spec. */
 188
 189 /* Controller doesn't honor resets unless we touch the clock register */
 190 #define SDHCI_QUIRK_CLOCK_BEFORE_RESET                  (1<<0)
 191 /* Controller has bad caps bits, but really supports DMA */
 192 #define SDHCI_QUIRK_FORCE_DMA                           (1<<1)
 193 /* Controller doesn't like to be reset when there is no card inserted. */
 194 #define SDHCI_QUIRK_NO_CARD_NO_RESET                    (1<<2)
 195 /* Controller doesn't like clearing the power reg before a change */
 196 #define SDHCI_QUIRK_SINGLE_POWER_WRITE                  (1<<3)
 197 /* Controller has flaky internal state so reset it on each ios change */
 198 #define SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS               (1<<4)
 199 /* Controller has an unusable DMA engine */
 200 #define SDHCI_QUIRK_BROKEN_DMA                          (1<<5)
 201 /* Controller has an unusable ADMA engine */
 202 #define SDHCI_QUIRK_BROKEN_ADMA                         (1<<6)
 203 /* Controller can only DMA from 32-bit aligned addresses */
 204 #define SDHCI_QUIRK_32BIT_DMA_ADDR                      (1<<7)
 205 /* Controller can only DMA chunk sizes that are a multiple of 32 bits */
 206 #define SDHCI_QUIRK_32BIT_DMA_SIZE                      (1<<8)
 207 /* Controller can only ADMA chunks that are a multiple of 32 bits */
 208 #define SDHCI_QUIRK_32BIT_ADMA_SIZE                     (1<<9)
 209 /* Controller needs to be reset after each request to stay stable */
 210 #define SDHCI_QUIRK_RESET_AFTER_REQUEST                 (1<<10)
 211 /* Controller needs voltage and power writes to happen separately */
 212 #define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER             (1<<11)
 213 /* Controller provides an incorrect timeout value for transfers */
 214 #define SDHCI_QUIRK_BROKEN_TIMEOUT_VAL                  (1<<12)
 215 /* Controller has an issue with buffer bits for small transfers */
 216 #define SDHCI_QUIRK_BROKEN_SMALL_PIO                    (1<<13)
 217 /* Controller does not provide transfer-complete interrupt when not busy */
 218 #define SDHCI_QUIRK_NO_BUSY_IRQ                         (1<<14)
 219 /* Controller has unreliable card detection */
 220 #define SDHCI_QUIRK_BROKEN_CARD_DETECTION               (1<<15)
 221 /* Controller reports inverted write-protect state */
 222 #define SDHCI_QUIRK_INVERTED_WRITE_PROTECT              (1<<16)
 223 /* Controller has nonstandard clock management */
 224 #define SDHCI_QUIRK_NONSTANDARD_CLOCK                   (1<<17)
 225 /* Controller does not like fast PIO transfers */
 226 #define SDHCI_QUIRK_PIO_NEEDS_DELAY                     (1<<18)
 227 /* Controller losing signal/interrupt enable states after reset */
 228 #define SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET            (1<<19)
 229 /* Controller has to be forced to use block size of 2048 bytes */
 230 #define SDHCI_QUIRK_FORCE_BLK_SZ_2048                   (1<<20)
 231 /* Controller cannot do multi-block transfers */
 232 #define SDHCI_QUIRK_NO_MULTIBLOCK                       (1<<21)
 233 /* Controller can only handle 1-bit data transfers */
 234 #define SDHCI_QUIRK_FORCE_1_BIT_DATA                    (1<<22)
 235 /* Controller needs 10ms delay between applying power and clock */
 236 #define SDHCI_QUIRK_DELAY_AFTER_POWER                   (1<<23)
 237 /* Controller uses SDCLK instead of TMCLK for data timeouts */
 238 #define SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK             (1<<24)
 239 /* Controller reports wrong base clock capability */
 240 #define SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN               (1<<25)
 241
 242         int                     irq;            /* Device IRQ */
 243         void __iomem *          ioaddr;         /* Mapped address */
 244
 245         const struct sdhci_ops  *ops;           /* Low level hw interface */
 246
 247         /* Internal data */
 248         struct mmc_host         *mmc;           /* MMC structure */
 249         u64                     dma_mask;       /* custom DMA mask */
 250
 251 #if defined(CONFIG_LEDS_CLASS) || defined(CONFIG_LEDS_CLASS_MODULE)
 252         struct led_classdev     led;            /* LED control */
 253         char   led_name[32];
 254 #endif
 255
 256         spinlock_t              lock;           /* Mutex */
 257
 258         int                     flags;          /* Host attributes */
 259 #define SDHCI_USE_SDMA          (1<<0)          /* Host is SDMA capable */
 260 #define SDHCI_USE_ADMA          (1<<1)          /* Host is ADMA capable */
 261 #define SDHCI_REQ_USE_DMA       (1<<2)          /* Use DMA for this req. */
 262 #define SDHCI_DEVICE_DEAD       (1<<3)          /* Device unresponsive */
 263
 264         unsigned int            version;        /* SDHCI spec. version */
 265
 266         unsigned int            max_clk;        /* Max possible freq (MHz) */
 267         unsigned int            timeout_clk;    /* Timeout freq (KHz) */
 268
 269         unsigned int            clock;          /* Current clock (MHz) */
 270         u8                      pwr;            /* Current voltage */
 271
 272         struct mmc_request      *mrq;           /* Current request */
 273         struct mmc_command      *cmd;           /* Current command */
 274         struct mmc_data         *data;          /* Current data request */
 275         unsigned int            data_early:1;   /* Data finished before cmd */
 276
 277         struct sg_mapping_iter  sg_miter;       /* SG state for PIO */
 278         unsigned int            blocks;         /* remaining PIO blocks */
 279
 280         int                     sg_count;       /* Mapped sg entries */
 281
 282         u8                      *adma_desc;     /* ADMA descriptor table */
 283         u8                      *align_buffer;  /* Bounce buffer */
 284
 285         dma_addr_t              adma_addr;      /* Mapped ADMA descr. table */
 286         dma_addr_t              align_addr;     /* Mapped bounce buffer */
 287
 288         struct tasklet_struct   card_tasklet;   /* Tasklet structures */
 289         struct tasklet_struct   finish_tasklet;
 290
 291         struct timer_list       timer;          /* Timer for timeouts */
 292
 293         unsigned long           private[0] ____cacheline_aligned;
 294 };
 295
 296
 297 struct sdhci_ops {
 298 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
 299         u32             (*readl)(struct sdhci_host *host, int reg);
 300         u16             (*readw)(struct sdhci_host *host, int reg);
 301         u8              (*readb)(struct sdhci_host *host, int reg);
 302         void            (*writel)(struct sdhci_host *host, u32 val, int reg);
 303         void            (*writew)(struct sdhci_host *host, u16 val, int reg);
 304         void            (*writeb)(struct sdhci_host *host, u8 val, int reg);
 305 #endif
 306
 307         void    (*set_clock)(struct sdhci_host *host, unsigned int clock);
 308
 309         int             (*enable_dma)(struct sdhci_host *host);
 310         unsigned int    (*get_max_clock)(struct sdhci_host *host);
 311         unsigned int    (*get_min_clock)(struct sdhci_host *host);
 312         unsigned int    (*get_timeout_clock)(struct sdhci_host *host);
 313 };
 314
 315 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
 316
 317 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
 318 {
 319         if (unlikely(host->ops->writel))
 320                 host->ops->writel(host, val, reg);
 321         else
 322                 writel(val, host->ioaddr + reg);
 323 }
 324
 325 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
 326 {
 327         if (unlikely(host->ops->writew))
 328                 host->ops->writew(host, val, reg);
 329         else
 330                 writew(val, host->ioaddr + reg);
 331 }
 332
 333 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
 334 {
 335         if (unlikely(host->ops->writeb))
 336                 host->ops->writeb(host, val, reg);
 337         else
 338                 writeb(val, host->ioaddr + reg);
 339 }
 340
 341 static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
 342 {
 343         if (unlikely(host->ops->readl))
 344                 return host->ops->readl(host, reg);
 345         else
 346                 return readl(host->ioaddr + reg);
 347 }
 348
 349 static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
 350 {
 351         if (unlikely(host->ops->readw))
 352                 return host->ops->readw(host, reg);
 353         else
 354                 return readw(host->ioaddr + reg);
 355 }
 356
 357 static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
 358 {
 359         if (unlikely(host->ops->readb))
 360                 return host->ops->readb(host, reg);
 361         else
 362                 return readb(host->ioaddr + reg);
 363 }
 364
 365 #else
 366
 367 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
 368 {
 369         writel(val, host->ioaddr + reg);
 370 }
 371
 372 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
 373 {
 374         writew(val, host->ioaddr + reg);
 375 }
 376
 377 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
 378 {
 379         writeb(val, host->ioaddr + reg);
 380 }
 381
 382 static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
 383 {
 384         return readl(host->ioaddr + reg);
 385 }
 386
 387 static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
 388 {
 389         return readw(host->ioaddr + reg);
 390 }
 391
 392 static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
 393 {
 394         return readb(host->ioaddr + reg);
 395 }
 396
 397 #endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */
 398
 399 extern struct sdhci_host *sdhci_alloc_host(struct device *dev,
 400         size_t priv_size);
 401 extern void sdhci_free_host(struct sdhci_host *host);
 402
 403 static inline void *sdhci_priv(struct sdhci_host *host)
 404 {
 405         return (void *)host->private;
 406 }
 407
 408 extern int sdhci_add_host(struct sdhci_host *host);
 409 extern void sdhci_remove_host(struct sdhci_host *host, int dead);
 410
 411 #ifdef CONFIG_PM
 412 extern int sdhci_suspend_host(struct sdhci_host *host, pm_message_t state);
 413 extern int sdhci_resume_host(struct sdhci_host *host);
 414 #endif
 415
 416 #endif /* __SDHCI_H */