2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #ifndef __RADEON_ASIC_H__
29 #define __RADEON_ASIC_H__
34 uint32_t radeon_legacy_get_engine_clock(struct radeon_device
*rdev
);
35 void radeon_legacy_set_engine_clock(struct radeon_device
*rdev
, uint32_t eng_clock
);
36 uint32_t radeon_legacy_get_memory_clock(struct radeon_device
*rdev
);
37 void radeon_legacy_set_clock_gating(struct radeon_device
*rdev
, int enable
);
39 uint32_t radeon_atom_get_engine_clock(struct radeon_device
*rdev
);
40 void radeon_atom_set_engine_clock(struct radeon_device
*rdev
, uint32_t eng_clock
);
41 uint32_t radeon_atom_get_memory_clock(struct radeon_device
*rdev
);
42 void radeon_atom_set_memory_clock(struct radeon_device
*rdev
, uint32_t mem_clock
);
43 void radeon_atom_set_clock_gating(struct radeon_device
*rdev
, int enable
);
46 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
48 extern int r100_init(struct radeon_device
*rdev
);
49 extern void r100_fini(struct radeon_device
*rdev
);
50 extern int r100_suspend(struct radeon_device
*rdev
);
51 extern int r100_resume(struct radeon_device
*rdev
);
52 uint32_t r100_mm_rreg(struct radeon_device
*rdev
, uint32_t reg
);
53 void r100_mm_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
);
54 void r100_vga_set_state(struct radeon_device
*rdev
, bool state
);
55 int r100_gpu_reset(struct radeon_device
*rdev
);
56 u32
r100_get_vblank_counter(struct radeon_device
*rdev
, int crtc
);
57 void r100_pci_gart_tlb_flush(struct radeon_device
*rdev
);
58 int r100_pci_gart_set_page(struct radeon_device
*rdev
, int i
, uint64_t addr
);
59 void r100_cp_commit(struct radeon_device
*rdev
);
60 void r100_ring_start(struct radeon_device
*rdev
);
61 int r100_irq_set(struct radeon_device
*rdev
);
62 int r100_irq_process(struct radeon_device
*rdev
);
63 void r100_fence_ring_emit(struct radeon_device
*rdev
,
64 struct radeon_fence
*fence
);
65 int r100_cs_parse(struct radeon_cs_parser
*p
);
66 void r100_pll_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
);
67 uint32_t r100_pll_rreg(struct radeon_device
*rdev
, uint32_t reg
);
68 int r100_copy_blit(struct radeon_device
*rdev
,
72 struct radeon_fence
*fence
);
73 int r100_set_surface_reg(struct radeon_device
*rdev
, int reg
,
74 uint32_t tiling_flags
, uint32_t pitch
,
75 uint32_t offset
, uint32_t obj_size
);
76 int r100_clear_surface_reg(struct radeon_device
*rdev
, int reg
);
77 void r100_bandwidth_update(struct radeon_device
*rdev
);
78 void r100_ring_ib_execute(struct radeon_device
*rdev
, struct radeon_ib
*ib
);
79 int r100_ring_test(struct radeon_device
*rdev
);
80 void r100_hdp_flush(struct radeon_device
*rdev
);
81 void r100_hpd_init(struct radeon_device
*rdev
);
82 void r100_hpd_fini(struct radeon_device
*rdev
);
83 bool r100_hpd_sense(struct radeon_device
*rdev
, enum radeon_hpd_id hpd
);
84 void r100_hpd_set_polarity(struct radeon_device
*rdev
,
85 enum radeon_hpd_id hpd
);
87 static struct radeon_asic r100_asic
= {
90 .suspend
= &r100_suspend
,
91 .resume
= &r100_resume
,
92 .vga_set_state
= &r100_vga_set_state
,
93 .gpu_reset
= &r100_gpu_reset
,
94 .gart_tlb_flush
= &r100_pci_gart_tlb_flush
,
95 .gart_set_page
= &r100_pci_gart_set_page
,
96 .cp_commit
= &r100_cp_commit
,
97 .ring_start
= &r100_ring_start
,
98 .ring_test
= &r100_ring_test
,
99 .ring_ib_execute
= &r100_ring_ib_execute
,
100 .irq_set
= &r100_irq_set
,
101 .irq_process
= &r100_irq_process
,
102 .get_vblank_counter
= &r100_get_vblank_counter
,
103 .fence_ring_emit
= &r100_fence_ring_emit
,
104 .cs_parse
= &r100_cs_parse
,
105 .copy_blit
= &r100_copy_blit
,
107 .copy
= &r100_copy_blit
,
108 .get_engine_clock
= &radeon_legacy_get_engine_clock
,
109 .set_engine_clock
= &radeon_legacy_set_engine_clock
,
110 .get_memory_clock
= &radeon_legacy_get_memory_clock
,
111 .set_memory_clock
= NULL
,
112 .set_pcie_lanes
= NULL
,
113 .set_clock_gating
= &radeon_legacy_set_clock_gating
,
114 .set_surface_reg
= r100_set_surface_reg
,
115 .clear_surface_reg
= r100_clear_surface_reg
,
116 .bandwidth_update
= &r100_bandwidth_update
,
117 .hdp_flush
= &r100_hdp_flush
,
118 .hpd_init
= &r100_hpd_init
,
119 .hpd_fini
= &r100_hpd_fini
,
120 .hpd_sense
= &r100_hpd_sense
,
121 .hpd_set_polarity
= &r100_hpd_set_polarity
,
126 * r300,r350,rv350,rv380
128 extern int r300_init(struct radeon_device
*rdev
);
129 extern void r300_fini(struct radeon_device
*rdev
);
130 extern int r300_suspend(struct radeon_device
*rdev
);
131 extern int r300_resume(struct radeon_device
*rdev
);
132 extern int r300_gpu_reset(struct radeon_device
*rdev
);
133 extern void r300_ring_start(struct radeon_device
*rdev
);
134 extern void r300_fence_ring_emit(struct radeon_device
*rdev
,
135 struct radeon_fence
*fence
);
136 extern int r300_cs_parse(struct radeon_cs_parser
*p
);
137 extern void rv370_pcie_gart_tlb_flush(struct radeon_device
*rdev
);
138 extern int rv370_pcie_gart_set_page(struct radeon_device
*rdev
, int i
, uint64_t addr
);
139 extern uint32_t rv370_pcie_rreg(struct radeon_device
*rdev
, uint32_t reg
);
140 extern void rv370_pcie_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
);
141 extern void rv370_set_pcie_lanes(struct radeon_device
*rdev
, int lanes
);
142 extern int r300_copy_dma(struct radeon_device
*rdev
,
146 struct radeon_fence
*fence
);
147 static struct radeon_asic r300_asic
= {
150 .suspend
= &r300_suspend
,
151 .resume
= &r300_resume
,
152 .vga_set_state
= &r100_vga_set_state
,
153 .gpu_reset
= &r300_gpu_reset
,
154 .gart_tlb_flush
= &r100_pci_gart_tlb_flush
,
155 .gart_set_page
= &r100_pci_gart_set_page
,
156 .cp_commit
= &r100_cp_commit
,
157 .ring_start
= &r300_ring_start
,
158 .ring_test
= &r100_ring_test
,
159 .ring_ib_execute
= &r100_ring_ib_execute
,
160 .irq_set
= &r100_irq_set
,
161 .irq_process
= &r100_irq_process
,
162 .get_vblank_counter
= &r100_get_vblank_counter
,
163 .fence_ring_emit
= &r300_fence_ring_emit
,
164 .cs_parse
= &r300_cs_parse
,
165 .copy_blit
= &r100_copy_blit
,
166 .copy_dma
= &r300_copy_dma
,
167 .copy
= &r100_copy_blit
,
168 .get_engine_clock
= &radeon_legacy_get_engine_clock
,
169 .set_engine_clock
= &radeon_legacy_set_engine_clock
,
170 .get_memory_clock
= &radeon_legacy_get_memory_clock
,
171 .set_memory_clock
= NULL
,
172 .set_pcie_lanes
= &rv370_set_pcie_lanes
,
173 .set_clock_gating
= &radeon_legacy_set_clock_gating
,
174 .set_surface_reg
= r100_set_surface_reg
,
175 .clear_surface_reg
= r100_clear_surface_reg
,
176 .bandwidth_update
= &r100_bandwidth_update
,
177 .hdp_flush
= &r100_hdp_flush
,
178 .hpd_init
= &r100_hpd_init
,
179 .hpd_fini
= &r100_hpd_fini
,
180 .hpd_sense
= &r100_hpd_sense
,
181 .hpd_set_polarity
= &r100_hpd_set_polarity
,
187 extern int r420_init(struct radeon_device
*rdev
);
188 extern void r420_fini(struct radeon_device
*rdev
);
189 extern int r420_suspend(struct radeon_device
*rdev
);
190 extern int r420_resume(struct radeon_device
*rdev
);
191 static struct radeon_asic r420_asic
= {
194 .suspend
= &r420_suspend
,
195 .resume
= &r420_resume
,
196 .vga_set_state
= &r100_vga_set_state
,
197 .gpu_reset
= &r300_gpu_reset
,
198 .gart_tlb_flush
= &rv370_pcie_gart_tlb_flush
,
199 .gart_set_page
= &rv370_pcie_gart_set_page
,
200 .cp_commit
= &r100_cp_commit
,
201 .ring_start
= &r300_ring_start
,
202 .ring_test
= &r100_ring_test
,
203 .ring_ib_execute
= &r100_ring_ib_execute
,
204 .irq_set
= &r100_irq_set
,
205 .irq_process
= &r100_irq_process
,
206 .get_vblank_counter
= &r100_get_vblank_counter
,
207 .fence_ring_emit
= &r300_fence_ring_emit
,
208 .cs_parse
= &r300_cs_parse
,
209 .copy_blit
= &r100_copy_blit
,
210 .copy_dma
= &r300_copy_dma
,
211 .copy
= &r100_copy_blit
,
212 .get_engine_clock
= &radeon_atom_get_engine_clock
,
213 .set_engine_clock
= &radeon_atom_set_engine_clock
,
214 .get_memory_clock
= &radeon_atom_get_memory_clock
,
215 .set_memory_clock
= &radeon_atom_set_memory_clock
,
216 .set_pcie_lanes
= &rv370_set_pcie_lanes
,
217 .set_clock_gating
= &radeon_atom_set_clock_gating
,
218 .set_surface_reg
= r100_set_surface_reg
,
219 .clear_surface_reg
= r100_clear_surface_reg
,
220 .bandwidth_update
= &r100_bandwidth_update
,
221 .hdp_flush
= &r100_hdp_flush
,
222 .hpd_init
= &r100_hpd_init
,
223 .hpd_fini
= &r100_hpd_fini
,
224 .hpd_sense
= &r100_hpd_sense
,
225 .hpd_set_polarity
= &r100_hpd_set_polarity
,
232 extern int rs400_init(struct radeon_device
*rdev
);
233 extern void rs400_fini(struct radeon_device
*rdev
);
234 extern int rs400_suspend(struct radeon_device
*rdev
);
235 extern int rs400_resume(struct radeon_device
*rdev
);
236 void rs400_gart_tlb_flush(struct radeon_device
*rdev
);
237 int rs400_gart_set_page(struct radeon_device
*rdev
, int i
, uint64_t addr
);
238 uint32_t rs400_mc_rreg(struct radeon_device
*rdev
, uint32_t reg
);
239 void rs400_mc_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
);
240 static struct radeon_asic rs400_asic
= {
243 .suspend
= &rs400_suspend
,
244 .resume
= &rs400_resume
,
245 .vga_set_state
= &r100_vga_set_state
,
246 .gpu_reset
= &r300_gpu_reset
,
247 .gart_tlb_flush
= &rs400_gart_tlb_flush
,
248 .gart_set_page
= &rs400_gart_set_page
,
249 .cp_commit
= &r100_cp_commit
,
250 .ring_start
= &r300_ring_start
,
251 .ring_test
= &r100_ring_test
,
252 .ring_ib_execute
= &r100_ring_ib_execute
,
253 .irq_set
= &r100_irq_set
,
254 .irq_process
= &r100_irq_process
,
255 .get_vblank_counter
= &r100_get_vblank_counter
,
256 .fence_ring_emit
= &r300_fence_ring_emit
,
257 .cs_parse
= &r300_cs_parse
,
258 .copy_blit
= &r100_copy_blit
,
259 .copy_dma
= &r300_copy_dma
,
260 .copy
= &r100_copy_blit
,
261 .get_engine_clock
= &radeon_legacy_get_engine_clock
,
262 .set_engine_clock
= &radeon_legacy_set_engine_clock
,
263 .get_memory_clock
= &radeon_legacy_get_memory_clock
,
264 .set_memory_clock
= NULL
,
265 .set_pcie_lanes
= NULL
,
266 .set_clock_gating
= &radeon_legacy_set_clock_gating
,
267 .set_surface_reg
= r100_set_surface_reg
,
268 .clear_surface_reg
= r100_clear_surface_reg
,
269 .bandwidth_update
= &r100_bandwidth_update
,
270 .hdp_flush
= &r100_hdp_flush
,
271 .hpd_init
= &r100_hpd_init
,
272 .hpd_fini
= &r100_hpd_fini
,
273 .hpd_sense
= &r100_hpd_sense
,
274 .hpd_set_polarity
= &r100_hpd_set_polarity
,
281 extern int rs600_init(struct radeon_device
*rdev
);
282 extern void rs600_fini(struct radeon_device
*rdev
);
283 extern int rs600_suspend(struct radeon_device
*rdev
);
284 extern int rs600_resume(struct radeon_device
*rdev
);
285 int rs600_irq_set(struct radeon_device
*rdev
);
286 int rs600_irq_process(struct radeon_device
*rdev
);
287 u32
rs600_get_vblank_counter(struct radeon_device
*rdev
, int crtc
);
288 void rs600_gart_tlb_flush(struct radeon_device
*rdev
);
289 int rs600_gart_set_page(struct radeon_device
*rdev
, int i
, uint64_t addr
);
290 uint32_t rs600_mc_rreg(struct radeon_device
*rdev
, uint32_t reg
);
291 void rs600_mc_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
);
292 void rs600_bandwidth_update(struct radeon_device
*rdev
);
293 void rs600_hpd_init(struct radeon_device
*rdev
);
294 void rs600_hpd_fini(struct radeon_device
*rdev
);
295 bool rs600_hpd_sense(struct radeon_device
*rdev
, enum radeon_hpd_id hpd
);
296 void rs600_hpd_set_polarity(struct radeon_device
*rdev
,
297 enum radeon_hpd_id hpd
);
299 static struct radeon_asic rs600_asic
= {
302 .suspend
= &rs600_suspend
,
303 .resume
= &rs600_resume
,
304 .vga_set_state
= &r100_vga_set_state
,
305 .gpu_reset
= &r300_gpu_reset
,
306 .gart_tlb_flush
= &rs600_gart_tlb_flush
,
307 .gart_set_page
= &rs600_gart_set_page
,
308 .cp_commit
= &r100_cp_commit
,
309 .ring_start
= &r300_ring_start
,
310 .ring_test
= &r100_ring_test
,
311 .ring_ib_execute
= &r100_ring_ib_execute
,
312 .irq_set
= &rs600_irq_set
,
313 .irq_process
= &rs600_irq_process
,
314 .get_vblank_counter
= &rs600_get_vblank_counter
,
315 .fence_ring_emit
= &r300_fence_ring_emit
,
316 .cs_parse
= &r300_cs_parse
,
317 .copy_blit
= &r100_copy_blit
,
318 .copy_dma
= &r300_copy_dma
,
319 .copy
= &r100_copy_blit
,
320 .get_engine_clock
= &radeon_atom_get_engine_clock
,
321 .set_engine_clock
= &radeon_atom_set_engine_clock
,
322 .get_memory_clock
= &radeon_atom_get_memory_clock
,
323 .set_memory_clock
= &radeon_atom_set_memory_clock
,
324 .set_pcie_lanes
= NULL
,
325 .set_clock_gating
= &radeon_atom_set_clock_gating
,
326 .bandwidth_update
= &rs600_bandwidth_update
,
327 .hdp_flush
= &r100_hdp_flush
,
328 .hpd_init
= &rs600_hpd_init
,
329 .hpd_fini
= &rs600_hpd_fini
,
330 .hpd_sense
= &rs600_hpd_sense
,
331 .hpd_set_polarity
= &rs600_hpd_set_polarity
,
338 int rs690_init(struct radeon_device
*rdev
);
339 void rs690_fini(struct radeon_device
*rdev
);
340 int rs690_resume(struct radeon_device
*rdev
);
341 int rs690_suspend(struct radeon_device
*rdev
);
342 uint32_t rs690_mc_rreg(struct radeon_device
*rdev
, uint32_t reg
);
343 void rs690_mc_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
);
344 void rs690_bandwidth_update(struct radeon_device
*rdev
);
345 static struct radeon_asic rs690_asic
= {
348 .suspend
= &rs690_suspend
,
349 .resume
= &rs690_resume
,
350 .vga_set_state
= &r100_vga_set_state
,
351 .gpu_reset
= &r300_gpu_reset
,
352 .gart_tlb_flush
= &rs400_gart_tlb_flush
,
353 .gart_set_page
= &rs400_gart_set_page
,
354 .cp_commit
= &r100_cp_commit
,
355 .ring_start
= &r300_ring_start
,
356 .ring_test
= &r100_ring_test
,
357 .ring_ib_execute
= &r100_ring_ib_execute
,
358 .irq_set
= &rs600_irq_set
,
359 .irq_process
= &rs600_irq_process
,
360 .get_vblank_counter
= &rs600_get_vblank_counter
,
361 .fence_ring_emit
= &r300_fence_ring_emit
,
362 .cs_parse
= &r300_cs_parse
,
363 .copy_blit
= &r100_copy_blit
,
364 .copy_dma
= &r300_copy_dma
,
365 .copy
= &r300_copy_dma
,
366 .get_engine_clock
= &radeon_atom_get_engine_clock
,
367 .set_engine_clock
= &radeon_atom_set_engine_clock
,
368 .get_memory_clock
= &radeon_atom_get_memory_clock
,
369 .set_memory_clock
= &radeon_atom_set_memory_clock
,
370 .set_pcie_lanes
= NULL
,
371 .set_clock_gating
= &radeon_atom_set_clock_gating
,
372 .set_surface_reg
= r100_set_surface_reg
,
373 .clear_surface_reg
= r100_clear_surface_reg
,
374 .bandwidth_update
= &rs690_bandwidth_update
,
375 .hdp_flush
= &r100_hdp_flush
,
376 .hpd_init
= &rs600_hpd_init
,
377 .hpd_fini
= &rs600_hpd_fini
,
378 .hpd_sense
= &rs600_hpd_sense
,
379 .hpd_set_polarity
= &rs600_hpd_set_polarity
,
386 int rv515_init(struct radeon_device
*rdev
);
387 void rv515_fini(struct radeon_device
*rdev
);
388 int rv515_gpu_reset(struct radeon_device
*rdev
);
389 uint32_t rv515_mc_rreg(struct radeon_device
*rdev
, uint32_t reg
);
390 void rv515_mc_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
);
391 void rv515_ring_start(struct radeon_device
*rdev
);
392 uint32_t rv515_pcie_rreg(struct radeon_device
*rdev
, uint32_t reg
);
393 void rv515_pcie_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
);
394 void rv515_bandwidth_update(struct radeon_device
*rdev
);
395 int rv515_resume(struct radeon_device
*rdev
);
396 int rv515_suspend(struct radeon_device
*rdev
);
397 static struct radeon_asic rv515_asic
= {
400 .suspend
= &rv515_suspend
,
401 .resume
= &rv515_resume
,
402 .vga_set_state
= &r100_vga_set_state
,
403 .gpu_reset
= &rv515_gpu_reset
,
404 .gart_tlb_flush
= &rv370_pcie_gart_tlb_flush
,
405 .gart_set_page
= &rv370_pcie_gart_set_page
,
406 .cp_commit
= &r100_cp_commit
,
407 .ring_start
= &rv515_ring_start
,
408 .ring_test
= &r100_ring_test
,
409 .ring_ib_execute
= &r100_ring_ib_execute
,
410 .irq_set
= &rs600_irq_set
,
411 .irq_process
= &rs600_irq_process
,
412 .get_vblank_counter
= &rs600_get_vblank_counter
,
413 .fence_ring_emit
= &r300_fence_ring_emit
,
414 .cs_parse
= &r300_cs_parse
,
415 .copy_blit
= &r100_copy_blit
,
416 .copy_dma
= &r300_copy_dma
,
417 .copy
= &r100_copy_blit
,
418 .get_engine_clock
= &radeon_atom_get_engine_clock
,
419 .set_engine_clock
= &radeon_atom_set_engine_clock
,
420 .get_memory_clock
= &radeon_atom_get_memory_clock
,
421 .set_memory_clock
= &radeon_atom_set_memory_clock
,
422 .set_pcie_lanes
= &rv370_set_pcie_lanes
,
423 .set_clock_gating
= &radeon_atom_set_clock_gating
,
424 .set_surface_reg
= r100_set_surface_reg
,
425 .clear_surface_reg
= r100_clear_surface_reg
,
426 .bandwidth_update
= &rv515_bandwidth_update
,
427 .hdp_flush
= &r100_hdp_flush
,
428 .hpd_init
= &rs600_hpd_init
,
429 .hpd_fini
= &rs600_hpd_fini
,
430 .hpd_sense
= &rs600_hpd_sense
,
431 .hpd_set_polarity
= &rs600_hpd_set_polarity
,
436 * r520,rv530,rv560,rv570,r580
438 int r520_init(struct radeon_device
*rdev
);
439 int r520_resume(struct radeon_device
*rdev
);
440 static struct radeon_asic r520_asic
= {
443 .suspend
= &rv515_suspend
,
444 .resume
= &r520_resume
,
445 .vga_set_state
= &r100_vga_set_state
,
446 .gpu_reset
= &rv515_gpu_reset
,
447 .gart_tlb_flush
= &rv370_pcie_gart_tlb_flush
,
448 .gart_set_page
= &rv370_pcie_gart_set_page
,
449 .cp_commit
= &r100_cp_commit
,
450 .ring_start
= &rv515_ring_start
,
451 .ring_test
= &r100_ring_test
,
452 .ring_ib_execute
= &r100_ring_ib_execute
,
453 .irq_set
= &rs600_irq_set
,
454 .irq_process
= &rs600_irq_process
,
455 .get_vblank_counter
= &rs600_get_vblank_counter
,
456 .fence_ring_emit
= &r300_fence_ring_emit
,
457 .cs_parse
= &r300_cs_parse
,
458 .copy_blit
= &r100_copy_blit
,
459 .copy_dma
= &r300_copy_dma
,
460 .copy
= &r100_copy_blit
,
461 .get_engine_clock
= &radeon_atom_get_engine_clock
,
462 .set_engine_clock
= &radeon_atom_set_engine_clock
,
463 .get_memory_clock
= &radeon_atom_get_memory_clock
,
464 .set_memory_clock
= &radeon_atom_set_memory_clock
,
465 .set_pcie_lanes
= &rv370_set_pcie_lanes
,
466 .set_clock_gating
= &radeon_atom_set_clock_gating
,
467 .set_surface_reg
= r100_set_surface_reg
,
468 .clear_surface_reg
= r100_clear_surface_reg
,
469 .bandwidth_update
= &rv515_bandwidth_update
,
470 .hdp_flush
= &r100_hdp_flush
,
471 .hpd_init
= &rs600_hpd_init
,
472 .hpd_fini
= &rs600_hpd_fini
,
473 .hpd_sense
= &rs600_hpd_sense
,
474 .hpd_set_polarity
= &rs600_hpd_set_polarity
,
478 * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880
480 int r600_init(struct radeon_device
*rdev
);
481 void r600_fini(struct radeon_device
*rdev
);
482 int r600_suspend(struct radeon_device
*rdev
);
483 int r600_resume(struct radeon_device
*rdev
);
484 void r600_vga_set_state(struct radeon_device
*rdev
, bool state
);
485 int r600_wb_init(struct radeon_device
*rdev
);
486 void r600_wb_fini(struct radeon_device
*rdev
);
487 void r600_cp_commit(struct radeon_device
*rdev
);
488 void r600_pcie_gart_tlb_flush(struct radeon_device
*rdev
);
489 uint32_t r600_pciep_rreg(struct radeon_device
*rdev
, uint32_t reg
);
490 void r600_pciep_wreg(struct radeon_device
*rdev
, uint32_t reg
, uint32_t v
);
491 int r600_cs_parse(struct radeon_cs_parser
*p
);
492 void r600_fence_ring_emit(struct radeon_device
*rdev
,
493 struct radeon_fence
*fence
);
494 int r600_copy_dma(struct radeon_device
*rdev
,
498 struct radeon_fence
*fence
);
499 int r600_irq_process(struct radeon_device
*rdev
);
500 int r600_irq_set(struct radeon_device
*rdev
);
501 int r600_gpu_reset(struct radeon_device
*rdev
);
502 int r600_set_surface_reg(struct radeon_device
*rdev
, int reg
,
503 uint32_t tiling_flags
, uint32_t pitch
,
504 uint32_t offset
, uint32_t obj_size
);
505 int r600_clear_surface_reg(struct radeon_device
*rdev
, int reg
);
506 void r600_ring_ib_execute(struct radeon_device
*rdev
, struct radeon_ib
*ib
);
507 int r600_ring_test(struct radeon_device
*rdev
);
508 int r600_copy_blit(struct radeon_device
*rdev
,
509 uint64_t src_offset
, uint64_t dst_offset
,
510 unsigned num_pages
, struct radeon_fence
*fence
);
511 void r600_hdp_flush(struct radeon_device
*rdev
);
512 void r600_hpd_init(struct radeon_device
*rdev
);
513 void r600_hpd_fini(struct radeon_device
*rdev
);
514 bool r600_hpd_sense(struct radeon_device
*rdev
, enum radeon_hpd_id hpd
);
515 void r600_hpd_set_polarity(struct radeon_device
*rdev
,
516 enum radeon_hpd_id hpd
);
518 static struct radeon_asic r600_asic
= {
521 .suspend
= &r600_suspend
,
522 .resume
= &r600_resume
,
523 .cp_commit
= &r600_cp_commit
,
524 .vga_set_state
= &r600_vga_set_state
,
525 .gpu_reset
= &r600_gpu_reset
,
526 .gart_tlb_flush
= &r600_pcie_gart_tlb_flush
,
527 .gart_set_page
= &rs600_gart_set_page
,
528 .ring_test
= &r600_ring_test
,
529 .ring_ib_execute
= &r600_ring_ib_execute
,
530 .irq_set
= &r600_irq_set
,
531 .irq_process
= &r600_irq_process
,
532 .get_vblank_counter
= &rs600_get_vblank_counter
,
533 .fence_ring_emit
= &r600_fence_ring_emit
,
534 .cs_parse
= &r600_cs_parse
,
535 .copy_blit
= &r600_copy_blit
,
536 .copy_dma
= &r600_copy_blit
,
537 .copy
= &r600_copy_blit
,
538 .get_engine_clock
= &radeon_atom_get_engine_clock
,
539 .set_engine_clock
= &radeon_atom_set_engine_clock
,
540 .get_memory_clock
= &radeon_atom_get_memory_clock
,
541 .set_memory_clock
= &radeon_atom_set_memory_clock
,
542 .set_pcie_lanes
= NULL
,
543 .set_clock_gating
= &radeon_atom_set_clock_gating
,
544 .set_surface_reg
= r600_set_surface_reg
,
545 .clear_surface_reg
= r600_clear_surface_reg
,
546 .bandwidth_update
= &rv515_bandwidth_update
,
547 .hdp_flush
= &r600_hdp_flush
,
548 .hpd_init
= &r600_hpd_init
,
549 .hpd_fini
= &r600_hpd_fini
,
550 .hpd_sense
= &r600_hpd_sense
,
551 .hpd_set_polarity
= &r600_hpd_set_polarity
,
555 * rv770,rv730,rv710,rv740
557 int rv770_init(struct radeon_device
*rdev
);
558 void rv770_fini(struct radeon_device
*rdev
);
559 int rv770_suspend(struct radeon_device
*rdev
);
560 int rv770_resume(struct radeon_device
*rdev
);
561 int rv770_gpu_reset(struct radeon_device
*rdev
);
563 static struct radeon_asic rv770_asic
= {
566 .suspend
= &rv770_suspend
,
567 .resume
= &rv770_resume
,
568 .cp_commit
= &r600_cp_commit
,
569 .gpu_reset
= &rv770_gpu_reset
,
570 .vga_set_state
= &r600_vga_set_state
,
571 .gart_tlb_flush
= &r600_pcie_gart_tlb_flush
,
572 .gart_set_page
= &rs600_gart_set_page
,
573 .ring_test
= &r600_ring_test
,
574 .ring_ib_execute
= &r600_ring_ib_execute
,
575 .irq_set
= &r600_irq_set
,
576 .irq_process
= &r600_irq_process
,
577 .get_vblank_counter
= &rs600_get_vblank_counter
,
578 .fence_ring_emit
= &r600_fence_ring_emit
,
579 .cs_parse
= &r600_cs_parse
,
580 .copy_blit
= &r600_copy_blit
,
581 .copy_dma
= &r600_copy_blit
,
582 .copy
= &r600_copy_blit
,
583 .get_engine_clock
= &radeon_atom_get_engine_clock
,
584 .set_engine_clock
= &radeon_atom_set_engine_clock
,
585 .get_memory_clock
= &radeon_atom_get_memory_clock
,
586 .set_memory_clock
= &radeon_atom_set_memory_clock
,
587 .set_pcie_lanes
= NULL
,
588 .set_clock_gating
= &radeon_atom_set_clock_gating
,
589 .set_surface_reg
= r600_set_surface_reg
,
590 .clear_surface_reg
= r600_clear_surface_reg
,
591 .bandwidth_update
= &rv515_bandwidth_update
,
592 .hdp_flush
= &r600_hdp_flush
,
593 .hpd_init
= &r600_hpd_init
,
594 .hpd_fini
= &r600_hpd_fini
,
595 .hpd_sense
= &r600_hpd_sense
,
596 .hpd_set_polarity
= &r600_hpd_set_polarity
,