drivers/mtd/nand/mxc_nand.c

   1 /*
   2  * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
   3  * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version 2
   8  * of the License, or (at your option) any later version.
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  17  * MA 02110-1301, USA.
  18  */
  19
  20 #include <linux/delay.h>
  21 #include <linux/slab.h>
  22 #include <linux/init.h>
  23 #include <linux/module.h>
  24 #include <linux/mtd/mtd.h>
  25 #include <linux/mtd/nand.h>
  26 #include <linux/mtd/partitions.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/device.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/clk.h>
  31 #include <linux/err.h>
  32 #include <linux/io.h>
  33
  34 #include <asm/mach/flash.h>
  35 #include <mach/mxc_nand.h>
  36 #include <mach/hardware.h>
  37
  38 #define DRIVER_NAME "mxc_nand"
  39
  40 #define nfc_is_v21()            (cpu_is_mx25() || cpu_is_mx35())
  41 #define nfc_is_v1()             (cpu_is_mx31() || cpu_is_mx27() || cpu_is_mx21())
  42
  43 /* Addresses for NFC registers */
  44 #define NFC_BUF_SIZE            0xE00
  45 #define NFC_BUF_ADDR            0xE04
  46 #define NFC_FLASH_ADDR          0xE06
  47 #define NFC_FLASH_CMD           0xE08
  48 #define NFC_CONFIG              0xE0A
  49 #define NFC_ECC_STATUS_RESULT   0xE0C
  50 #define NFC_RSLTMAIN_AREA       0xE0E
  51 #define NFC_RSLTSPARE_AREA      0xE10
  52 #define NFC_WRPROT              0xE12
  53 #define NFC_V1_UNLOCKSTART_BLKADDR      0xe14
  54 #define NFC_V1_UNLOCKEND_BLKADDR        0xe16
  55 #define NFC_V21_UNLOCKSTART_BLKADDR     0xe20
  56 #define NFC_V21_UNLOCKEND_BLKADDR       0xe22
  57 #define NFC_NF_WRPRST           0xE18
  58 #define NFC_CONFIG1             0xE1A
  59 #define NFC_CONFIG2             0xE1C
  60
  61 /* Set INT to 0, FCMD to 1, rest to 0 in NFC_CONFIG2 Register
  62  * for Command operation */
  63 #define NFC_CMD            0x1
  64
  65 /* Set INT to 0, FADD to 1, rest to 0 in NFC_CONFIG2 Register
  66  * for Address operation */
  67 #define NFC_ADDR           0x2
  68
  69 /* Set INT to 0, FDI to 1, rest to 0 in NFC_CONFIG2 Register
  70  * for Input operation */
  71 #define NFC_INPUT          0x4
  72
  73 /* Set INT to 0, FDO to 001, rest to 0 in NFC_CONFIG2 Register
  74  * for Data Output operation */
  75 #define NFC_OUTPUT         0x8
  76
  77 /* Set INT to 0, FD0 to 010, rest to 0 in NFC_CONFIG2 Register
  78  * for Read ID operation */
  79 #define NFC_ID             0x10
  80
  81 /* Set INT to 0, FDO to 100, rest to 0 in NFC_CONFIG2 Register
  82  * for Read Status operation */
  83 #define NFC_STATUS         0x20
  84
  85 /* Set INT to 1, rest to 0 in NFC_CONFIG2 Register for Read
  86  * Status operation */
  87 #define NFC_INT            0x8000
  88
  89 #define NFC_SP_EN           (1 << 2)
  90 #define NFC_ECC_EN          (1 << 3)
  91 #define NFC_INT_MSK         (1 << 4)
  92 #define NFC_BIG             (1 << 5)
  93 #define NFC_RST             (1 << 6)
  94 #define NFC_CE              (1 << 7)
  95 #define NFC_ONE_CYCLE       (1 << 8)
  96
  97 struct mxc_nand_host {
  98         struct mtd_info         mtd;
  99         struct nand_chip        nand;
 100         struct mtd_partition    *parts;
 101         struct device           *dev;
 102
 103         void                    *spare0;
 104         void                    *main_area0;
 105         void                    *main_area1;
 106
 107         void __iomem            *base;
 108         void __iomem            *regs;
 109         int                     status_request;
 110         struct clk              *clk;
 111         int                     clk_act;
 112         int                     irq;
 113
 114         wait_queue_head_t       irq_waitq;
 115
 116         uint8_t                 *data_buf;
 117         unsigned int            buf_start;
 118         int                     spare_len;
 119 };
 120
 121 /* OOB placement block for use with hardware ecc generation */
 122 static struct nand_ecclayout nandv1_hw_eccoob_smallpage = {
 123         .eccbytes = 5,
 124         .eccpos = {6, 7, 8, 9, 10},
 125         .oobfree = {{0, 5}, {12, 4}, }
 126 };
 127
 128 static struct nand_ecclayout nandv1_hw_eccoob_largepage = {
 129         .eccbytes = 20,
 130         .eccpos = {6, 7, 8, 9, 10, 22, 23, 24, 25, 26,
 131                    38, 39, 40, 41, 42, 54, 55, 56, 57, 58},
 132         .oobfree = {{2, 4}, {11, 10}, {27, 10}, {43, 10}, {59, 5}, }
 133 };
 134
 135 /* OOB description for 512 byte pages with 16 byte OOB */
 136 static struct nand_ecclayout nandv2_hw_eccoob_smallpage = {
 137         .eccbytes = 1 * 9,
 138         .eccpos = {
 139                  7,  8,  9, 10, 11, 12, 13, 14, 15
 140         },
 141         .oobfree = {
 142                 {.offset = 0, .length = 5}
 143         }
 144 };
 145
 146 /* OOB description for 2048 byte pages with 64 byte OOB */
 147 static struct nand_ecclayout nandv2_hw_eccoob_largepage = {
 148         .eccbytes = 4 * 9,
 149         .eccpos = {
 150                  7,  8,  9, 10, 11, 12, 13, 14, 15,
 151                 23, 24, 25, 26, 27, 28, 29, 30, 31,
 152                 39, 40, 41, 42, 43, 44, 45, 46, 47,
 153                 55, 56, 57, 58, 59, 60, 61, 62, 63
 154         },
 155         .oobfree = {
 156                 {.offset = 2, .length = 4},
 157                 {.offset = 16, .length = 7},
 158                 {.offset = 32, .length = 7},
 159                 {.offset = 48, .length = 7}
 160         }
 161 };
 162
 163 #ifdef CONFIG_MTD_PARTITIONS
 164 static const char *part_probes[] = { "RedBoot", "cmdlinepart", NULL };
 165 #endif
 166
 167 static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
 168 {
 169         struct mxc_nand_host *host = dev_id;
 170
 171         disable_irq_nosync(irq);
 172
 173         wake_up(&host->irq_waitq);
 174
 175         return IRQ_HANDLED;
 176 }
 177
 178 /* This function polls the NANDFC to wait for the basic operation to
 179  * complete by checking the INT bit of config2 register.
 180  */
 181 static void wait_op_done(struct mxc_nand_host *host, int useirq)
 182 {
 183         uint16_t tmp;
 184         int max_retries = 8000;
 185
 186         if (useirq) {
 187                 if ((readw(host->regs + NFC_CONFIG2) & NFC_INT) == 0) {
 188
 189                         enable_irq(host->irq);
 190
 191                         wait_event(host->irq_waitq,
 192                                 readw(host->regs + NFC_CONFIG2) & NFC_INT);
 193
 194                         tmp = readw(host->regs + NFC_CONFIG2);
 195                         tmp  &= ~NFC_INT;
 196                         writew(tmp, host->regs + NFC_CONFIG2);
 197                 }
 198         } else {
 199                 while (max_retries-- > 0) {
 200                         if (readw(host->regs + NFC_CONFIG2) & NFC_INT) {
 201                                 tmp = readw(host->regs + NFC_CONFIG2);
 202                                 tmp  &= ~NFC_INT;
 203                                 writew(tmp, host->regs + NFC_CONFIG2);
 204                                 break;
 205                         }
 206                         udelay(1);
 207                 }
 208                 if (max_retries < 0)
 209                         DEBUG(MTD_DEBUG_LEVEL0, "%s: INT not set\n",
 210                               __func__);
 211         }
 212 }
 213
 214 /* This function issues the specified command to the NAND device and
 215  * waits for completion. */
 216 static void send_cmd(struct mxc_nand_host *host, uint16_t cmd, int useirq)
 217 {
 218         DEBUG(MTD_DEBUG_LEVEL3, "send_cmd(host, 0x%x, %d)\n", cmd, useirq);
 219
 220         writew(cmd, host->regs + NFC_FLASH_CMD);
 221         writew(NFC_CMD, host->regs + NFC_CONFIG2);
 222
 223         if (cpu_is_mx21() && (cmd == NAND_CMD_RESET)) {
 224                 int max_retries = 100;
 225                 /* Reset completion is indicated by NFC_CONFIG2 */
 226                 /* being set to 0 */
 227                 while (max_retries-- > 0) {
 228                         if (readw(host->regs + NFC_CONFIG2) == 0) {
 229                                 break;
 230                         }
 231                         udelay(1);
 232                 }
 233                 if (max_retries < 0)
 234                         DEBUG(MTD_DEBUG_LEVEL0, "%s: RESET failed\n",
 235                               __func__);
 236         } else {
 237                 /* Wait for operation to complete */
 238                 wait_op_done(host, useirq);
 239         }
 240 }
 241
 242 /* This function sends an address (or partial address) to the
 243  * NAND device. The address is used to select the source/destination for
 244  * a NAND command. */
 245 static void send_addr(struct mxc_nand_host *host, uint16_t addr, int islast)
 246 {
 247         DEBUG(MTD_DEBUG_LEVEL3, "send_addr(host, 0x%x %d)\n", addr, islast);
 248
 249         writew(addr, host->regs + NFC_FLASH_ADDR);
 250         writew(NFC_ADDR, host->regs + NFC_CONFIG2);
 251
 252         /* Wait for operation to complete */
 253         wait_op_done(host, islast);
 254 }
 255
 256 static void send_page(struct mtd_info *mtd, unsigned int ops)
 257 {
 258         struct nand_chip *nand_chip = mtd->priv;
 259         struct mxc_nand_host *host = nand_chip->priv;
 260         int bufs, i;
 261
 262         if (nfc_is_v1() && mtd->writesize > 512)
 263                 bufs = 4;
 264         else
 265                 bufs = 1;
 266
 267         for (i = 0; i < bufs; i++) {
 268
 269                 /* NANDFC buffer 0 is used for page read/write */
 270                 writew(i, host->regs + NFC_BUF_ADDR);
 271
 272                 writew(ops, host->regs + NFC_CONFIG2);
 273
 274                 /* Wait for operation to complete */
 275                 wait_op_done(host, true);
 276         }
 277 }
 278
 279 /* Request the NANDFC to perform a read of the NAND device ID. */
 280 static void send_read_id(struct mxc_nand_host *host)
 281 {
 282         struct nand_chip *this = &host->nand;
 283
 284         /* NANDFC buffer 0 is used for device ID output */
 285         writew(0x0, host->regs + NFC_BUF_ADDR);
 286
 287         writew(NFC_ID, host->regs + NFC_CONFIG2);
 288
 289         /* Wait for operation to complete */
 290         wait_op_done(host, true);
 291
 292         if (this->options & NAND_BUSWIDTH_16) {
 293                 void __iomem *main_buf = host->main_area0;
 294                 /* compress the ID info */
 295                 writeb(readb(main_buf + 2), main_buf + 1);
 296                 writeb(readb(main_buf + 4), main_buf + 2);
 297                 writeb(readb(main_buf + 6), main_buf + 3);
 298                 writeb(readb(main_buf + 8), main_buf + 4);
 299                 writeb(readb(main_buf + 10), main_buf + 5);
 300         }
 301         memcpy(host->data_buf, host->main_area0, 16);
 302 }
 303
 304 /* This function requests the NANDFC to perform a read of the
 305  * NAND device status and returns the current status. */
 306 static uint16_t get_dev_status(struct mxc_nand_host *host)
 307 {
 308         void __iomem *main_buf = host->main_area1;
 309         uint32_t store;
 310         uint16_t ret;
 311         /* Issue status request to NAND device */
 312
 313         /* store the main area1 first word, later do recovery */
 314         store = readl(main_buf);
 315         /* NANDFC buffer 1 is used for device status to prevent
 316          * corruption of read/write buffer on status requests. */
 317         writew(1, host->regs + NFC_BUF_ADDR);
 318
 319         writew(NFC_STATUS, host->regs + NFC_CONFIG2);
 320
 321         /* Wait for operation to complete */
 322         wait_op_done(host, true);
 323
 324         /* Status is placed in first word of main buffer */
 325         /* get status, then recovery area 1 data */
 326         ret = readw(main_buf);
 327         writel(store, main_buf);
 328
 329         return ret;
 330 }
 331
 332 /* This functions is used by upper layer to checks if device is ready */
 333 static int mxc_nand_dev_ready(struct mtd_info *mtd)
 334 {
 335         /*
 336          * NFC handles R/B internally. Therefore, this function
 337          * always returns status as ready.
 338          */
 339         return 1;
 340 }
 341
 342 static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
 343 {
 344         /*
 345          * If HW ECC is enabled, we turn it on during init. There is
 346          * no need to enable again here.
 347          */
 348 }
 349
 350 static int mxc_nand_correct_data(struct mtd_info *mtd, u_char *dat,
 351                                  u_char *read_ecc, u_char *calc_ecc)
 352 {
 353         struct nand_chip *nand_chip = mtd->priv;
 354         struct mxc_nand_host *host = nand_chip->priv;
 355
 356         /*
 357          * 1-Bit errors are automatically corrected in HW.  No need for
 358          * additional correction.  2-Bit errors cannot be corrected by
 359          * HW ECC, so we need to return failure
 360          */
 361         uint16_t ecc_status = readw(host->regs + NFC_ECC_STATUS_RESULT);
 362
 363         if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
 364                 DEBUG(MTD_DEBUG_LEVEL0,
 365                       "MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
 366                 return -1;
 367         }
 368
 369         return 0;
 370 }
 371
 372 static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
 373                                   u_char *ecc_code)
 374 {
 375         return 0;
 376 }
 377
 378 static u_char mxc_nand_read_byte(struct mtd_info *mtd)
 379 {
 380         struct nand_chip *nand_chip = mtd->priv;
 381         struct mxc_nand_host *host = nand_chip->priv;
 382         uint8_t ret;
 383
 384         /* Check for status request */
 385         if (host->status_request)
 386                 return get_dev_status(host) & 0xFF;
 387
 388         ret = *(uint8_t *)(host->data_buf + host->buf_start);
 389         host->buf_start++;
 390
 391         return ret;
 392 }
 393
 394 static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
 395 {
 396         struct nand_chip *nand_chip = mtd->priv;
 397         struct mxc_nand_host *host = nand_chip->priv;
 398         uint16_t ret;
 399
 400         ret = *(uint16_t *)(host->data_buf + host->buf_start);
 401         host->buf_start += 2;
 402
 403         return ret;
 404 }
 405
 406 /* Write data of length len to buffer buf. The data to be
 407  * written on NAND Flash is first copied to RAMbuffer. After the Data Input
 408  * Operation by the NFC, the data is written to NAND Flash */
 409 static void mxc_nand_write_buf(struct mtd_info *mtd,
 410                                 const u_char *buf, int len)
 411 {
 412         struct nand_chip *nand_chip = mtd->priv;
 413         struct mxc_nand_host *host = nand_chip->priv;
 414         u16 col = host->buf_start;
 415         int n = mtd->oobsize + mtd->writesize - col;
 416
 417         n = min(n, len);
 418
 419         memcpy(host->data_buf + col, buf, n);
 420
 421         host->buf_start += n;
 422 }
 423
 424 /* Read the data buffer from the NAND Flash. To read the data from NAND
 425  * Flash first the data output cycle is initiated by the NFC, which copies
 426  * the data to RAMbuffer. This data of length len is then copied to buffer buf.
 427  */
 428 static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
 429 {
 430         struct nand_chip *nand_chip = mtd->priv;
 431         struct mxc_nand_host *host = nand_chip->priv;
 432         u16 col = host->buf_start;
 433         int n = mtd->oobsize + mtd->writesize - col;
 434
 435         n = min(n, len);
 436
 437         memcpy(buf, host->data_buf + col, len);
 438
 439         host->buf_start += len;
 440 }
 441
 442 /* Used by the upper layer to verify the data in NAND Flash
 443  * with the data in the buf. */
 444 static int mxc_nand_verify_buf(struct mtd_info *mtd,
 445                                 const u_char *buf, int len)
 446 {
 447         return -EFAULT;
 448 }
 449
 450 /* This function is used by upper layer for select and
 451  * deselect of the NAND chip */
 452 static void mxc_nand_select_chip(struct mtd_info *mtd, int chip)
 453 {
 454         struct nand_chip *nand_chip = mtd->priv;
 455         struct mxc_nand_host *host = nand_chip->priv;
 456
 457         switch (chip) {
 458         case -1:
 459                 /* Disable the NFC clock */
 460                 if (host->clk_act) {
 461                         clk_disable(host->clk);
 462                         host->clk_act = 0;
 463                 }
 464                 break;
 465         case 0:
 466                 /* Enable the NFC clock */
 467                 if (!host->clk_act) {
 468                         clk_enable(host->clk);
 469                         host->clk_act = 1;
 470                 }
 471                 break;
 472
 473         default:
 474                 break;
 475         }
 476 }
 477
 478 /*
 479  * Function to transfer data to/from spare area.
 480  */
 481 static void copy_spare(struct mtd_info *mtd, bool bfrom)
 482 {
 483         struct nand_chip *this = mtd->priv;
 484         struct mxc_nand_host *host = this->priv;
 485         u16 i, j;
 486         u16 n = mtd->writesize >> 9;
 487         u8 *d = host->data_buf + mtd->writesize;
 488         u8 *s = host->spare0;
 489         u16 t = host->spare_len;
 490
 491         j = (mtd->oobsize / n >> 1) << 1;
 492
 493         if (bfrom) {
 494                 for (i = 0; i < n - 1; i++)
 495                         memcpy(d + i * j, s + i * t, j);
 496
 497                 /* the last section */
 498                 memcpy(d + i * j, s + i * t, mtd->oobsize - i * j);
 499         } else {
 500                 for (i = 0; i < n - 1; i++)
 501                         memcpy(&s[i * t], &d[i * j], j);
 502
 503                 /* the last section */
 504                 memcpy(&s[i * t], &d[i * j], mtd->oobsize - i * j);
 505         }
 506 }
 507
 508 static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr)
 509 {
 510         struct nand_chip *nand_chip = mtd->priv;
 511         struct mxc_nand_host *host = nand_chip->priv;
 512
 513         /* Write out column address, if necessary */
 514         if (column != -1) {
 515                 /*
 516                  * MXC NANDFC can only perform full page+spare or
 517                  * spare-only read/write.  When the upper layers
 518                  * layers perform a read/write buf operation,
 519                  * we will used the saved column address to index into
 520                  * the full page.
 521                  */
 522                 send_addr(host, 0, page_addr == -1);
 523                 if (mtd->writesize > 512)
 524                         /* another col addr cycle for 2k page */
 525                         send_addr(host, 0, false);
 526         }
 527
 528         /* Write out page address, if necessary */
 529         if (page_addr != -1) {
 530                 /* paddr_0 - p_addr_7 */
 531                 send_addr(host, (page_addr & 0xff), false);
 532
 533                 if (mtd->writesize > 512) {
 534                         if (mtd->size >= 0x10000000) {
 535                                 /* paddr_8 - paddr_15 */
 536                                 send_addr(host, (page_addr >> 8) & 0xff, false);
 537                                 send_addr(host, (page_addr >> 16) & 0xff, true);
 538                         } else
 539                                 /* paddr_8 - paddr_15 */
 540                                 send_addr(host, (page_addr >> 8) & 0xff, true);
 541                 } else {
 542                         /* One more address cycle for higher density devices */
 543                         if (mtd->size >= 0x4000000) {
 544                                 /* paddr_8 - paddr_15 */
 545                                 send_addr(host, (page_addr >> 8) & 0xff, false);
 546                                 send_addr(host, (page_addr >> 16) & 0xff, true);
 547                         } else
 548                                 /* paddr_8 - paddr_15 */
 549                                 send_addr(host, (page_addr >> 8) & 0xff, true);
 550                 }
 551         }
 552 }
 553
 554 static void preset(struct mtd_info *mtd)
 555 {
 556         struct nand_chip *nand_chip = mtd->priv;
 557         struct mxc_nand_host *host = nand_chip->priv;
 558         uint16_t tmp;
 559
 560         /* enable interrupt, disable spare enable */
 561         tmp = readw(host->regs + NFC_CONFIG1);
 562         tmp &= ~NFC_INT_MSK;
 563         tmp &= ~NFC_SP_EN;
 564         if (nand_chip->ecc.mode == NAND_ECC_HW) {
 565                 tmp |= NFC_ECC_EN;
 566         } else {
 567                 tmp &= ~NFC_ECC_EN;
 568         }
 569         writew(tmp, host->regs + NFC_CONFIG1);
 570         /* preset operation */
 571
 572         /* Unlock the internal RAM Buffer */
 573         writew(0x2, host->regs + NFC_CONFIG);
 574
 575         /* Blocks to be unlocked */
 576         if (nfc_is_v21()) {
 577                 writew(0x0, host->regs + NFC_V21_UNLOCKSTART_BLKADDR);
 578                 writew(0xffff, host->regs + NFC_V21_UNLOCKEND_BLKADDR);
 579         } else if (nfc_is_v1()) {
 580                 writew(0x0, host->regs + NFC_V1_UNLOCKSTART_BLKADDR);
 581                 writew(0x4000, host->regs + NFC_V1_UNLOCKEND_BLKADDR);
 582         } else
 583                 BUG();
 584
 585         /* Unlock Block Command for given address range */
 586         writew(0x4, host->regs + NFC_WRPROT);
 587 }
 588
 589 /* Used by the upper layer to write command to NAND Flash for
 590  * different operations to be carried out on NAND Flash */
 591 static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
 592                                 int column, int page_addr)
 593 {
 594         struct nand_chip *nand_chip = mtd->priv;
 595         struct mxc_nand_host *host = nand_chip->priv;
 596
 597         DEBUG(MTD_DEBUG_LEVEL3,
 598               "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
 599               command, column, page_addr);
 600
 601         /* Reset command state information */
 602         host->status_request = false;
 603
 604         /* Command pre-processing step */
 605         switch (command) {
 606         case NAND_CMD_RESET:
 607                 send_cmd(host, command, false);
 608                 preset(mtd);
 609                 break;
 610
 611         case NAND_CMD_STATUS:
 612                 host->buf_start = 0;
 613                 host->status_request = true;
 614
 615                 send_cmd(host, command, true);
 616                 mxc_do_addr_cycle(mtd, column, page_addr);
 617                 break;
 618
 619         case NAND_CMD_READ0:
 620         case NAND_CMD_READOOB:
 621                 if (command == NAND_CMD_READ0)
 622                         host->buf_start = column;
 623                 else
 624                         host->buf_start = column + mtd->writesize;
 625
 626                 if (mtd->writesize > 512)
 627                         command = NAND_CMD_READ0; /* only READ0 is valid */
 628
 629                 send_cmd(host, command, false);
 630                 mxc_do_addr_cycle(mtd, column, page_addr);
 631
 632                 if (mtd->writesize > 512)
 633                         send_cmd(host, NAND_CMD_READSTART, true);
 634
 635                 send_page(mtd, NFC_OUTPUT);
 636
 637                 memcpy(host->data_buf, host->main_area0, mtd->writesize);
 638                 copy_spare(mtd, true);
 639                 break;
 640
 641         case NAND_CMD_SEQIN:
 642                 if (column >= mtd->writesize) {
 643                         /*
 644                          * FIXME: before send SEQIN command for write OOB,
 645                          * We must read one page out.
 646                          * For K9F1GXX has no READ1 command to set current HW
 647                          * pointer to spare area, we must write the whole page
 648                          * including OOB together.
 649                          */
 650                         if (mtd->writesize > 512)
 651                                 /* call ourself to read a page */
 652                                 mxc_nand_command(mtd, NAND_CMD_READ0, 0,
 653                                                 page_addr);
 654
 655                         host->buf_start = column;
 656
 657                         /* Set program pointer to spare region */
 658                         if (mtd->writesize == 512)
 659                                 send_cmd(host, NAND_CMD_READOOB, false);
 660                 } else {
 661                         host->buf_start = column;
 662
 663                         /* Set program pointer to page start */
 664                         if (mtd->writesize == 512)
 665                                 send_cmd(host, NAND_CMD_READ0, false);
 666                 }
 667
 668                 send_cmd(host, command, false);
 669                 mxc_do_addr_cycle(mtd, column, page_addr);
 670                 break;
 671
 672         case NAND_CMD_PAGEPROG:
 673                 memcpy(host->main_area0, host->data_buf, mtd->writesize);
 674                 copy_spare(mtd, false);
 675                 send_page(mtd, NFC_INPUT);
 676                 send_cmd(host, command, true);
 677                 mxc_do_addr_cycle(mtd, column, page_addr);
 678                 break;
 679
 680         case NAND_CMD_READID:
 681                 send_cmd(host, command, true);
 682                 mxc_do_addr_cycle(mtd, column, page_addr);
 683                 send_read_id(host);
 684                 host->buf_start = column;
 685                 break;
 686
 687         case NAND_CMD_ERASE1:
 688         case NAND_CMD_ERASE2:
 689         case NAND_CMD_RESET:
 690                 send_cmd(host, command, false);
 691                 mxc_do_addr_cycle(mtd, column, page_addr);
 692
 693                 break;
 694         }
 695 }
 696
 697 /*
 698  * The generic flash bbt decriptors overlap with our ecc
 699  * hardware, so define some i.MX specific ones.
 700  */
 701 static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
 702 static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
 703
 704 static struct nand_bbt_descr bbt_main_descr = {
 705         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
 706             | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
 707         .offs = 0,
 708         .len = 4,
 709         .veroffs = 4,
 710         .maxblocks = 4,
 711         .pattern = bbt_pattern,
 712 };
 713
 714 static struct nand_bbt_descr bbt_mirror_descr = {
 715         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
 716             | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
 717         .offs = 0,
 718         .len = 4,
 719         .veroffs = 4,
 720         .maxblocks = 4,
 721         .pattern = mirror_pattern,
 722 };
 723
 724 static int __init mxcnd_probe(struct platform_device *pdev)
 725 {
 726         struct nand_chip *this;
 727         struct mtd_info *mtd;
 728         struct mxc_nand_platform_data *pdata = pdev->dev.platform_data;
 729         struct mxc_nand_host *host;
 730         struct resource *res;
 731         int err = 0, nr_parts = 0;
 732         struct nand_ecclayout *oob_smallpage, *oob_largepage;
 733
 734         /* Allocate memory for MTD device structure and private data */
 735         host = kzalloc(sizeof(struct mxc_nand_host) + NAND_MAX_PAGESIZE +
 736                         NAND_MAX_OOBSIZE, GFP_KERNEL);
 737         if (!host)
 738                 return -ENOMEM;
 739
 740         host->data_buf = (uint8_t *)(host + 1);
 741
 742         host->dev = &pdev->dev;
 743         /* structures must be linked */
 744         this = &host->nand;
 745         mtd = &host->mtd;
 746         mtd->priv = this;
 747         mtd->owner = THIS_MODULE;
 748         mtd->dev.parent = &pdev->dev;
 749         mtd->name = DRIVER_NAME;
 750
 751         /* 50 us command delay time */
 752         this->chip_delay = 5;
 753
 754         this->priv = host;
 755         this->dev_ready = mxc_nand_dev_ready;
 756         this->cmdfunc = mxc_nand_command;
 757         this->select_chip = mxc_nand_select_chip;
 758         this->read_byte = mxc_nand_read_byte;
 759         this->read_word = mxc_nand_read_word;
 760         this->write_buf = mxc_nand_write_buf;
 761         this->read_buf = mxc_nand_read_buf;
 762         this->verify_buf = mxc_nand_verify_buf;
 763
 764         host->clk = clk_get(&pdev->dev, "nfc");
 765         if (IS_ERR(host->clk)) {
 766                 err = PTR_ERR(host->clk);
 767                 goto eclk;
 768         }
 769
 770         clk_enable(host->clk);
 771         host->clk_act = 1;
 772
 773         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 774         if (!res) {
 775                 err = -ENODEV;
 776                 goto eres;
 777         }
 778
 779         host->base = ioremap(res->start, resource_size(res));
 780         if (!host->base) {
 781                 err = -ENOMEM;
 782                 goto eres;
 783         }
 784
 785         host->main_area0 = host->base;
 786         host->main_area1 = host->base + 0x200;
 787
 788         if (nfc_is_v21()) {
 789                 host->regs = host->base + 0x1000;
 790                 host->spare0 = host->base + 0x1000;
 791                 host->spare_len = 64;
 792                 oob_smallpage = &nandv2_hw_eccoob_smallpage;
 793                 oob_largepage = &nandv2_hw_eccoob_largepage;
 794                 this->ecc.bytes = 9;
 795         } else if (nfc_is_v1()) {
 796                 host->regs = host->base;
 797                 host->spare0 = host->base + 0x800;
 798                 host->spare_len = 16;
 799                 oob_smallpage = &nandv1_hw_eccoob_smallpage;
 800                 oob_largepage = &nandv1_hw_eccoob_largepage;
 801                 this->ecc.bytes = 3;
 802         } else
 803                 BUG();
 804
 805         this->ecc.size = 512;
 806         this->ecc.layout = oob_smallpage;
 807
 808         if (pdata->hw_ecc) {
 809                 this->ecc.calculate = mxc_nand_calculate_ecc;
 810                 this->ecc.hwctl = mxc_nand_enable_hwecc;
 811                 this->ecc.correct = mxc_nand_correct_data;
 812                 this->ecc.mode = NAND_ECC_HW;
 813         } else {
 814                 this->ecc.mode = NAND_ECC_SOFT;
 815         }
 816
 817         /* NAND bus width determines access funtions used by upper layer */
 818         if (pdata->width == 2)
 819                 this->options |= NAND_BUSWIDTH_16;
 820
 821         if (pdata->flash_bbt) {
 822                 this->bbt_td = &bbt_main_descr;
 823                 this->bbt_md = &bbt_mirror_descr;
 824                 /* update flash based bbt */
 825                 this->options |= NAND_USE_FLASH_BBT;
 826         }
 827
 828         init_waitqueue_head(&host->irq_waitq);
 829
 830         host->irq = platform_get_irq(pdev, 0);
 831
 832         err = request_irq(host->irq, mxc_nfc_irq, IRQF_DISABLED, DRIVER_NAME, host);
 833         if (err)
 834                 goto eirq;
 835
 836         /* first scan to find the device and get the page size */
 837         if (nand_scan_ident(mtd, 1, NULL)) {
 838                 err = -ENXIO;
 839                 goto escan;
 840         }
 841
 842         if (mtd->writesize == 2048)
 843                 this->ecc.layout = oob_largepage;
 844
 845         /* second phase scan */
 846         if (nand_scan_tail(mtd)) {
 847                 err = -ENXIO;
 848                 goto escan;
 849         }
 850
 851         /* Register the partitions */
 852 #ifdef CONFIG_MTD_PARTITIONS
 853         nr_parts =
 854             parse_mtd_partitions(mtd, part_probes, &host->parts, 0);
 855         if (nr_parts > 0)
 856                 add_mtd_partitions(mtd, host->parts, nr_parts);
 857         else
 858 #endif
 859         {
 860                 pr_info("Registering %s as whole device\n", mtd->name);
 861                 add_mtd_device(mtd);
 862         }
 863
 864         platform_set_drvdata(pdev, host);
 865
 866         return 0;
 867
 868 escan:
 869         free_irq(host->irq, host);
 870 eirq:
 871         iounmap(host->base);
 872 eres:
 873         clk_put(host->clk);
 874 eclk:
 875         kfree(host);
 876
 877         return err;
 878 }
 879
 880 static int __devexit mxcnd_remove(struct platform_device *pdev)
 881 {
 882         struct mxc_nand_host *host = platform_get_drvdata(pdev);
 883
 884         clk_put(host->clk);
 885
 886         platform_set_drvdata(pdev, NULL);
 887
 888         nand_release(&host->mtd);
 889         free_irq(host->irq, host);
 890         iounmap(host->base);
 891         kfree(host);
 892
 893         return 0;
 894 }
 895
 896 #ifdef CONFIG_PM
 897 static int mxcnd_suspend(struct platform_device *pdev, pm_message_t state)
 898 {
 899         struct mtd_info *mtd = platform_get_drvdata(pdev);
 900         struct nand_chip *nand_chip = mtd->priv;
 901         struct mxc_nand_host *host = nand_chip->priv;
 902         int ret = 0;
 903
 904         DEBUG(MTD_DEBUG_LEVEL0, "MXC_ND : NAND suspend\n");
 905
 906         ret = mtd->suspend(mtd);
 907
 908         /*
 909          * nand_suspend locks the device for exclusive access, so
 910          * the clock must already be off.
 911          */
 912         BUG_ON(!ret && host->clk_act);
 913
 914         return ret;
 915 }
 916
 917 static int mxcnd_resume(struct platform_device *pdev)
 918 {
 919         struct mtd_info *mtd = platform_get_drvdata(pdev);
 920         struct nand_chip *nand_chip = mtd->priv;
 921         struct mxc_nand_host *host = nand_chip->priv;
 922         int ret = 0;
 923
 924         DEBUG(MTD_DEBUG_LEVEL0, "MXC_ND : NAND resume\n");
 925
 926         mtd->resume(mtd);
 927
 928         return ret;
 929 }
 930
 931 #else
 932 # define mxcnd_suspend   NULL
 933 # define mxcnd_resume    NULL
 934 #endif                          /* CONFIG_PM */
 935
 936 static struct platform_driver mxcnd_driver = {
 937         .driver = {
 938                    .name = DRIVER_NAME,
 939                    },
 940         .remove = __devexit_p(mxcnd_remove),
 941         .suspend = mxcnd_suspend,
 942         .resume = mxcnd_resume,
 943 };
 944
 945 static int __init mxc_nd_init(void)
 946 {
 947         return platform_driver_probe(&mxcnd_driver, mxcnd_probe);
 948 }
 949
 950 static void __exit mxc_nd_cleanup(void)
 951 {
 952         /* Unregister the device structure */
 953         platform_driver_unregister(&mxcnd_driver);
 954 }
 955
 956 module_init(mxc_nd_init);
 957 module_exit(mxc_nd_cleanup);
 958
 959 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
 960 MODULE_DESCRIPTION("MXC NAND MTD driver");
 961 MODULE_LICENSE("GPL");