2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/smp_lock.h>
23 #include <linux/interrupt.h>
24 #include <linux/mc146818rtc.h>
25 #include <linux/kernel_stat.h>
26 #include <linux/sysdev.h>
27 #include <linux/cpu.h>
28 #include <linux/clockchips.h>
29 #include <linux/acpi_pmtmr.h>
30 #include <linux/module.h>
32 #include <asm/atomic.h>
35 #include <asm/mpspec.h>
37 #include <asm/arch_hooks.h>
39 #include <asm/i8253.h>
42 #include <mach_apic.h>
43 #include <mach_apicdef.h>
51 #if (SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F
52 # error SPURIOUS_APIC_VECTOR definition error
56 * Knob to control our willingness to enable the local APIC.
58 * -1=force-disable, +1=force-enable
60 static int enable_local_apic __initdata
= 0;
62 /* Local APIC timer verification ok */
63 static int local_apic_timer_verify_ok
;
66 * Debug level, exported for io_apic.c
70 static unsigned int calibration_result
;
72 static int lapic_next_event(unsigned long delta
,
73 struct clock_event_device
*evt
);
74 static void lapic_timer_setup(enum clock_event_mode mode
,
75 struct clock_event_device
*evt
);
76 static void lapic_timer_broadcast(cpumask_t mask
);
77 static void apic_pm_activate(void);
80 * The local apic timer can be used for any function which is CPU local.
82 static struct clock_event_device lapic_clockevent
= {
84 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
85 | CLOCK_EVT_FEAT_C3STOP
| CLOCK_EVT_FEAT_DUMMY
,
87 .set_mode
= lapic_timer_setup
,
88 .set_next_event
= lapic_next_event
,
89 .broadcast
= lapic_timer_broadcast
,
93 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
95 /* Local APIC was disabled by the BIOS and enabled by the kernel */
96 static int enabled_via_apicbase
;
99 * Get the LAPIC version
101 static inline int lapic_get_version(void)
103 return GET_APIC_VERSION(apic_read(APIC_LVR
));
107 * Check, if the APIC is integrated or a seperate chip
109 static inline int lapic_is_integrated(void)
111 return APIC_INTEGRATED(lapic_get_version());
115 * Check, whether this is a modern or a first generation APIC
117 static int modern_apic(void)
119 /* AMD systems use old APIC versions, so check the CPU */
120 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
121 boot_cpu_data
.x86
>= 0xf)
123 return lapic_get_version() >= 0x14;
127 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
129 void enable_NMI_through_LVT0 (void * dummy
)
131 unsigned int v
= APIC_DM_NMI
;
133 /* Level triggered for 82489DX */
134 if (!lapic_is_integrated())
135 v
|= APIC_LVT_LEVEL_TRIGGER
;
136 apic_write_around(APIC_LVT0
, v
);
140 * get_physical_broadcast - Get number of physical broadcast IDs
142 int get_physical_broadcast(void)
144 return modern_apic() ? 0xff : 0xf;
148 * lapic_get_maxlvt - get the maximum number of local vector table entries
150 int lapic_get_maxlvt(void)
152 unsigned int v
= apic_read(APIC_LVR
);
154 /* 82489DXs do not report # of LVT entries. */
155 return APIC_INTEGRATED(GET_APIC_VERSION(v
)) ? GET_APIC_MAXLVT(v
) : 2;
162 /* Clock divisor is set to 16 */
163 #define APIC_DIVISOR 16
166 * This function sets up the local APIC timer, with a timeout of
167 * 'clocks' APIC bus clock. During calibration we actually call
168 * this function twice on the boot CPU, once with a bogus timeout
169 * value, second time for real. The other (noncalibrating) CPUs
170 * call this function only once, with the real, calibrated value.
172 * We do reads before writes even if unnecessary, to get around the
173 * P5 APIC double write bug.
175 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
177 unsigned int lvtt_value
, tmp_value
;
179 lvtt_value
= LOCAL_TIMER_VECTOR
;
181 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
182 if (!lapic_is_integrated())
183 lvtt_value
|= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV
);
186 lvtt_value
|= APIC_LVT_MASKED
;
188 apic_write_around(APIC_LVTT
, lvtt_value
);
193 tmp_value
= apic_read(APIC_TDCR
);
194 apic_write_around(APIC_TDCR
, (tmp_value
195 & ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
))
199 apic_write_around(APIC_TMICT
, clocks
/APIC_DIVISOR
);
203 * Program the next event, relative to now
205 static int lapic_next_event(unsigned long delta
,
206 struct clock_event_device
*evt
)
208 apic_write_around(APIC_TMICT
, delta
);
213 * Setup the lapic timer in periodic or oneshot mode
215 static void lapic_timer_setup(enum clock_event_mode mode
,
216 struct clock_event_device
*evt
)
221 /* Lapic used for broadcast ? */
222 if (!local_apic_timer_verify_ok
)
225 local_irq_save(flags
);
228 case CLOCK_EVT_MODE_PERIODIC
:
229 case CLOCK_EVT_MODE_ONESHOT
:
230 __setup_APIC_LVTT(calibration_result
,
231 mode
!= CLOCK_EVT_MODE_PERIODIC
, 1);
233 case CLOCK_EVT_MODE_UNUSED
:
234 case CLOCK_EVT_MODE_SHUTDOWN
:
235 v
= apic_read(APIC_LVTT
);
236 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
237 apic_write_around(APIC_LVTT
, v
);
241 local_irq_restore(flags
);
245 * Local APIC timer broadcast function
247 static void lapic_timer_broadcast(cpumask_t mask
)
250 send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
255 * Setup the local APIC timer for this CPU. Copy the initilized values
256 * of the boot CPU and register the clock event in the framework.
258 static void __devinit
setup_APIC_timer(void)
260 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
262 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
263 levt
->cpumask
= cpumask_of_cpu(smp_processor_id());
265 clockevents_register_device(levt
);
269 * In this functions we calibrate APIC bus clocks to the external timer.
271 * We want to do the calibration only once since we want to have local timer
272 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
275 * This was previously done by reading the PIT/HPET and waiting for a wrap
276 * around to find out, that a tick has elapsed. I have a box, where the PIT
277 * readout is broken, so it never gets out of the wait loop again. This was
278 * also reported by others.
280 * Monitoring the jiffies value is inaccurate and the clockevents
281 * infrastructure allows us to do a simple substitution of the interrupt
284 * The calibration routine also uses the pm_timer when possible, as the PIT
285 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
286 * back to normal later in the boot process).
289 #define LAPIC_CAL_LOOPS (HZ/10)
291 static __initdata
volatile int lapic_cal_loops
= -1;
292 static __initdata
long lapic_cal_t1
, lapic_cal_t2
;
293 static __initdata
unsigned long long lapic_cal_tsc1
, lapic_cal_tsc2
;
294 static __initdata
unsigned long lapic_cal_pm1
, lapic_cal_pm2
;
295 static __initdata
unsigned long lapic_cal_j1
, lapic_cal_j2
;
298 * Temporary interrupt handler.
300 static void __init
lapic_cal_handler(struct clock_event_device
*dev
)
302 unsigned long long tsc
= 0;
303 long tapic
= apic_read(APIC_TMCCT
);
304 unsigned long pm
= acpi_pm_read_early();
309 switch (lapic_cal_loops
++) {
311 lapic_cal_t1
= tapic
;
312 lapic_cal_tsc1
= tsc
;
314 lapic_cal_j1
= jiffies
;
317 case LAPIC_CAL_LOOPS
:
318 lapic_cal_t2
= tapic
;
319 lapic_cal_tsc2
= tsc
;
320 if (pm
< lapic_cal_pm1
)
321 pm
+= ACPI_PM_OVRRUN
;
323 lapic_cal_j2
= jiffies
;
329 * Setup the boot APIC
331 * Calibrate and verify the result.
333 void __init
setup_boot_APIC_clock(void)
335 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
336 const long pm_100ms
= PMTMR_TICKS_PER_SEC
/10;
337 const long pm_thresh
= pm_100ms
/100;
338 void (*real_handler
)(struct clock_event_device
*dev
);
339 unsigned long deltaj
;
342 apic_printk(APIC_VERBOSE
, "Using local APIC timer interrupts.\n"
343 "calibrating APIC timer ...\n");
347 /* Replace the global interrupt handler */
348 real_handler
= global_clock_event
->event_handler
;
349 global_clock_event
->event_handler
= lapic_cal_handler
;
352 * Setup the APIC counter to 1e9. There is no way the lapic
353 * can underflow in the 100ms detection time frame
355 __setup_APIC_LVTT(1000000000, 0, 0);
357 /* Let the interrupts run */
360 while(lapic_cal_loops
<= LAPIC_CAL_LOOPS
);
364 /* Restore the real event handler */
365 global_clock_event
->event_handler
= real_handler
;
367 /* Build delta t1-t2 as apic timer counts down */
368 delta
= lapic_cal_t1
- lapic_cal_t2
;
369 apic_printk(APIC_VERBOSE
, "... lapic delta = %ld\n", delta
);
371 /* Check, if the PM timer is available */
372 deltapm
= lapic_cal_pm2
- lapic_cal_pm1
;
373 apic_printk(APIC_VERBOSE
, "... PM timer delta = %ld\n", deltapm
);
379 mult
= clocksource_hz2mult(PMTMR_TICKS_PER_SEC
, 22);
381 if (deltapm
> (pm_100ms
- pm_thresh
) &&
382 deltapm
< (pm_100ms
+ pm_thresh
)) {
383 apic_printk(APIC_VERBOSE
, "... PM timer result ok\n");
385 res
= (((u64
) deltapm
) * mult
) >> 22;
386 do_div(res
, 1000000);
387 printk(KERN_WARNING
"APIC calibration not consistent "
388 "with PM Timer: %ldms instead of 100ms\n",
390 /* Correct the lapic counter value */
391 res
= (((u64
) delta
) * pm_100ms
);
392 do_div(res
, deltapm
);
393 printk(KERN_INFO
"APIC delta adjusted to PM-Timer: "
394 "%lu (%ld)\n", (unsigned long) res
, delta
);
399 /* Calculate the scaled math multiplication factor */
400 lapic_clockevent
.mult
= div_sc(delta
, TICK_NSEC
* LAPIC_CAL_LOOPS
, 32);
401 lapic_clockevent
.max_delta_ns
=
402 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
403 lapic_clockevent
.min_delta_ns
=
404 clockevent_delta2ns(0xF, &lapic_clockevent
);
406 calibration_result
= (delta
* APIC_DIVISOR
) / LAPIC_CAL_LOOPS
;
408 apic_printk(APIC_VERBOSE
, "..... delta %ld\n", delta
);
409 apic_printk(APIC_VERBOSE
, "..... mult: %ld\n", lapic_clockevent
.mult
);
410 apic_printk(APIC_VERBOSE
, "..... calibration result: %u\n",
414 delta
= (long)(lapic_cal_tsc2
- lapic_cal_tsc1
);
415 apic_printk(APIC_VERBOSE
, "..... CPU clock speed is "
417 (delta
/ LAPIC_CAL_LOOPS
) / (1000000 / HZ
),
418 (delta
/ LAPIC_CAL_LOOPS
) % (1000000 / HZ
));
421 apic_printk(APIC_VERBOSE
, "..... host bus clock speed is "
423 calibration_result
/ (1000000 / HZ
),
424 calibration_result
% (1000000 / HZ
));
427 apic_printk(APIC_VERBOSE
, "... verify APIC timer\n");
430 * Setup the apic timer manually
432 local_apic_timer_verify_ok
= 1;
433 levt
->event_handler
= lapic_cal_handler
;
434 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC
, levt
);
435 lapic_cal_loops
= -1;
437 /* Let the interrupts run */
440 while(lapic_cal_loops
<= LAPIC_CAL_LOOPS
);
444 /* Stop the lapic timer */
445 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, levt
);
450 deltaj
= lapic_cal_j2
- lapic_cal_j1
;
451 apic_printk(APIC_VERBOSE
, "... jiffies delta = %lu\n", deltaj
);
453 /* Check, if the PM timer is available */
454 deltapm
= lapic_cal_pm2
- lapic_cal_pm1
;
455 apic_printk(APIC_VERBOSE
, "... PM timer delta = %ld\n", deltapm
);
457 local_apic_timer_verify_ok
= 0;
460 if (deltapm
> (pm_100ms
- pm_thresh
) &&
461 deltapm
< (pm_100ms
+ pm_thresh
)) {
462 apic_printk(APIC_VERBOSE
, "... PM timer result ok\n");
463 /* Check, if the jiffies result is consistent */
464 if (deltaj
< LAPIC_CAL_LOOPS
-2 ||
465 deltaj
> LAPIC_CAL_LOOPS
+2) {
467 * Not sure, what we can do about this one.
468 * When high resultion timers are active
469 * and the lapic timer does not stop in C3
470 * we are fine. Otherwise more trouble might
471 * be waiting. -- tglx
473 printk(KERN_WARNING
"Global event device %s "
474 "has wrong frequency "
475 "(%lu ticks instead of %d)\n",
476 global_clock_event
->name
, deltaj
,
479 local_apic_timer_verify_ok
= 1;
482 /* Check, if the jiffies result is consistent */
483 if (deltaj
>= LAPIC_CAL_LOOPS
-2 &&
484 deltaj
<= LAPIC_CAL_LOOPS
+2) {
485 apic_printk(APIC_VERBOSE
, "... jiffies result ok\n");
486 local_apic_timer_verify_ok
= 1;
490 if (!local_apic_timer_verify_ok
) {
492 "APIC timer disabled due to verification failure.\n");
493 /* No broadcast on UP ! */
494 if (num_possible_cpus() == 1)
497 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
499 /* Setup the lapic or request the broadcast */
503 void __devinit
setup_secondary_APIC_clock(void)
509 * The guts of the apic timer interrupt
511 static void local_apic_timer_interrupt(void)
513 int cpu
= smp_processor_id();
514 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
517 * Normally we should not be here till LAPIC has been initialized but
518 * in some cases like kdump, its possible that there is a pending LAPIC
519 * timer interrupt from previous kernel's context and is delivered in
520 * new kernel the moment interrupts are enabled.
522 * Interrupts are enabled early and LAPIC is setup much later, hence
523 * its possible that when we get here evt->event_handler is NULL.
524 * Check for event_handler being NULL and discard the interrupt as
527 if (!evt
->event_handler
) {
529 "Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
531 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, evt
);
535 per_cpu(irq_stat
, cpu
).apic_timer_irqs
++;
537 evt
->event_handler(evt
);
541 * Local APIC timer interrupt. This is the most natural way for doing
542 * local interrupts, but local timer interrupts can be emulated by
543 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
545 * [ if a single-CPU system runs an SMP kernel then we call the local
546 * interrupt as well. Thus we cannot inline the local irq ... ]
549 void fastcall
smp_apic_timer_interrupt(struct pt_regs
*regs
)
551 struct pt_regs
*old_regs
= set_irq_regs(regs
);
554 * NOTE! We'd better ACK the irq immediately,
555 * because timer handling can be slow.
559 * update_process_times() expects us to have done irq_enter().
560 * Besides, if we don't timer interrupts ignore the global
561 * interrupt lock, which is the WrongThing (tm) to do.
564 local_apic_timer_interrupt();
567 set_irq_regs(old_regs
);
570 int setup_profiling_timer(unsigned int multiplier
)
576 * Local APIC start and shutdown
580 * clear_local_APIC - shutdown the local APIC
582 * This is called, when a CPU is disabled and before rebooting, so the state of
583 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
584 * leftovers during boot.
586 void clear_local_APIC(void)
588 int maxlvt
= lapic_get_maxlvt();
592 * Masking an LVT entry can trigger a local APIC error
593 * if the vector is zero. Mask LVTERR first to prevent this.
596 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
597 apic_write_around(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
600 * Careful: we have to set masks only first to deassert
601 * any level-triggered sources.
603 v
= apic_read(APIC_LVTT
);
604 apic_write_around(APIC_LVTT
, v
| APIC_LVT_MASKED
);
605 v
= apic_read(APIC_LVT0
);
606 apic_write_around(APIC_LVT0
, v
| APIC_LVT_MASKED
);
607 v
= apic_read(APIC_LVT1
);
608 apic_write_around(APIC_LVT1
, v
| APIC_LVT_MASKED
);
610 v
= apic_read(APIC_LVTPC
);
611 apic_write_around(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
614 /* lets not touch this if we didn't frob it */
615 #ifdef CONFIG_X86_MCE_P4THERMAL
617 v
= apic_read(APIC_LVTTHMR
);
618 apic_write_around(APIC_LVTTHMR
, v
| APIC_LVT_MASKED
);
622 * Clean APIC state for other OSs:
624 apic_write_around(APIC_LVTT
, APIC_LVT_MASKED
);
625 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
);
626 apic_write_around(APIC_LVT1
, APIC_LVT_MASKED
);
628 apic_write_around(APIC_LVTERR
, APIC_LVT_MASKED
);
630 apic_write_around(APIC_LVTPC
, APIC_LVT_MASKED
);
632 #ifdef CONFIG_X86_MCE_P4THERMAL
634 apic_write_around(APIC_LVTTHMR
, APIC_LVT_MASKED
);
636 /* Integrated APIC (!82489DX) ? */
637 if (lapic_is_integrated()) {
639 /* Clear ESR due to Pentium errata 3AP and 11AP */
640 apic_write(APIC_ESR
, 0);
646 * disable_local_APIC - clear and disable the local APIC
648 void disable_local_APIC(void)
655 * Disable APIC (implies clearing of registers
658 value
= apic_read(APIC_SPIV
);
659 value
&= ~APIC_SPIV_APIC_ENABLED
;
660 apic_write_around(APIC_SPIV
, value
);
663 * When LAPIC was disabled by the BIOS and enabled by the kernel,
664 * restore the disabled state.
666 if (enabled_via_apicbase
) {
669 rdmsr(MSR_IA32_APICBASE
, l
, h
);
670 l
&= ~MSR_IA32_APICBASE_ENABLE
;
671 wrmsr(MSR_IA32_APICBASE
, l
, h
);
676 * If Linux enabled the LAPIC against the BIOS default disable it down before
677 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
678 * not power-off. Additionally clear all LVT entries before disable_local_APIC
679 * for the case where Linux didn't enable the LAPIC.
681 void lapic_shutdown(void)
688 local_irq_save(flags
);
691 if (enabled_via_apicbase
)
692 disable_local_APIC();
694 local_irq_restore(flags
);
698 * This is to verify that we're looking at a real local APIC.
699 * Check these against your board if the CPUs aren't getting
700 * started for no apparent reason.
702 int __init
verify_local_APIC(void)
704 unsigned int reg0
, reg1
;
707 * The version register is read-only in a real APIC.
709 reg0
= apic_read(APIC_LVR
);
710 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
711 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
712 reg1
= apic_read(APIC_LVR
);
713 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
716 * The two version reads above should print the same
717 * numbers. If the second one is different, then we
718 * poke at a non-APIC.
724 * Check if the version looks reasonably.
726 reg1
= GET_APIC_VERSION(reg0
);
727 if (reg1
== 0x00 || reg1
== 0xff)
729 reg1
= lapic_get_maxlvt();
730 if (reg1
< 0x02 || reg1
== 0xff)
734 * The ID register is read/write in a real APIC.
736 reg0
= apic_read(APIC_ID
);
737 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
740 * The next two are just to see if we have sane values.
741 * They're only really relevant if we're in Virtual Wire
742 * compatibility mode, but most boxes are anymore.
744 reg0
= apic_read(APIC_LVT0
);
745 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
746 reg1
= apic_read(APIC_LVT1
);
747 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
753 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
755 void __init
sync_Arb_IDs(void)
758 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
766 apic_wait_icr_idle();
768 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
769 apic_write_around(APIC_ICR
, APIC_DEST_ALLINC
| APIC_INT_LEVELTRIG
774 * An initial setup of the virtual wire mode.
776 void __init
init_bsp_APIC(void)
781 * Don't do the setup now if we have a SMP BIOS as the
782 * through-I/O-APIC virtual wire mode might be active.
784 if (smp_found_config
|| !cpu_has_apic
)
788 * Do not trust the local APIC being empty at bootup.
795 value
= apic_read(APIC_SPIV
);
796 value
&= ~APIC_VECTOR_MASK
;
797 value
|= APIC_SPIV_APIC_ENABLED
;
799 /* This bit is reserved on P4/Xeon and should be cleared */
800 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
801 (boot_cpu_data
.x86
== 15))
802 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
804 value
|= APIC_SPIV_FOCUS_DISABLED
;
805 value
|= SPURIOUS_APIC_VECTOR
;
806 apic_write_around(APIC_SPIV
, value
);
809 * Set up the virtual wire mode.
811 apic_write_around(APIC_LVT0
, APIC_DM_EXTINT
);
813 if (!lapic_is_integrated()) /* 82489DX */
814 value
|= APIC_LVT_LEVEL_TRIGGER
;
815 apic_write_around(APIC_LVT1
, value
);
819 * setup_local_APIC - setup the local APIC
821 void __devinit
setup_local_APIC(void)
823 unsigned long oldvalue
, value
, maxlvt
, integrated
;
826 /* Pound the ESR really hard over the head with a big hammer - mbligh */
828 apic_write(APIC_ESR
, 0);
829 apic_write(APIC_ESR
, 0);
830 apic_write(APIC_ESR
, 0);
831 apic_write(APIC_ESR
, 0);
834 integrated
= lapic_is_integrated();
837 * Double-check whether this APIC is really registered.
839 if (!apic_id_registered())
843 * Intel recommends to set DFR, LDR and TPR before enabling
844 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
845 * document number 292116). So here it goes...
850 * Set Task Priority to 'accept all'. We never change this
853 value
= apic_read(APIC_TASKPRI
);
854 value
&= ~APIC_TPRI_MASK
;
855 apic_write_around(APIC_TASKPRI
, value
);
858 * After a crash, we no longer service the interrupts and a pending
859 * interrupt from previous kernel might still have ISR bit set.
861 * Most probably by now CPU has serviced that pending interrupt and
862 * it might not have done the ack_APIC_irq() because it thought,
863 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
864 * does not clear the ISR bit and cpu thinks it has already serivced
865 * the interrupt. Hence a vector might get locked. It was noticed
866 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
868 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
869 value
= apic_read(APIC_ISR
+ i
*0x10);
870 for (j
= 31; j
>= 0; j
--) {
877 * Now that we are all set up, enable the APIC
879 value
= apic_read(APIC_SPIV
);
880 value
&= ~APIC_VECTOR_MASK
;
884 value
|= APIC_SPIV_APIC_ENABLED
;
887 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
888 * certain networking cards. If high frequency interrupts are
889 * happening on a particular IOAPIC pin, plus the IOAPIC routing
890 * entry is masked/unmasked at a high rate as well then sooner or
891 * later IOAPIC line gets 'stuck', no more interrupts are received
892 * from the device. If focus CPU is disabled then the hang goes
895 * [ This bug can be reproduced easily with a level-triggered
896 * PCI Ne2000 networking cards and PII/PIII processors, dual
900 * Actually disabling the focus CPU check just makes the hang less
901 * frequent as it makes the interrupt distributon model be more
902 * like LRU than MRU (the short-term load is more even across CPUs).
903 * See also the comment in end_level_ioapic_irq(). --macro
906 /* Enable focus processor (bit==0) */
907 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
910 * Set spurious IRQ vector
912 value
|= SPURIOUS_APIC_VECTOR
;
913 apic_write_around(APIC_SPIV
, value
);
918 * set up through-local-APIC on the BP's LINT0. This is not
919 * strictly necessery in pure symmetric-IO mode, but sometimes
920 * we delegate interrupts to the 8259A.
923 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
925 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
926 if (!smp_processor_id() && (pic_mode
|| !value
)) {
927 value
= APIC_DM_EXTINT
;
928 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n",
931 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
932 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n",
935 apic_write_around(APIC_LVT0
, value
);
938 * only the BP should see the LINT1 NMI signal, obviously.
940 if (!smp_processor_id())
943 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
944 if (!integrated
) /* 82489DX */
945 value
|= APIC_LVT_LEVEL_TRIGGER
;
946 apic_write_around(APIC_LVT1
, value
);
948 if (integrated
&& !esr_disable
) { /* !82489DX */
949 maxlvt
= lapic_get_maxlvt();
950 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
951 apic_write(APIC_ESR
, 0);
952 oldvalue
= apic_read(APIC_ESR
);
954 /* enables sending errors */
955 value
= ERROR_APIC_VECTOR
;
956 apic_write_around(APIC_LVTERR
, value
);
958 * spec says clear errors after enabling vector.
961 apic_write(APIC_ESR
, 0);
962 value
= apic_read(APIC_ESR
);
963 if (value
!= oldvalue
)
964 apic_printk(APIC_VERBOSE
, "ESR value before enabling "
965 "vector: 0x%08lx after: 0x%08lx\n",
970 * Something untraceble is creating bad interrupts on
971 * secondary quads ... for the moment, just leave the
972 * ESR disabled - we can't do anything useful with the
973 * errors anyway - mbligh
975 printk(KERN_INFO
"Leaving ESR disabled.\n");
977 printk(KERN_INFO
"No ESR for 82489DX.\n");
980 /* Disable the local apic timer */
981 value
= apic_read(APIC_LVTT
);
982 value
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
983 apic_write_around(APIC_LVTT
, value
);
985 setup_apic_nmi_watchdog(NULL
);
990 * Detect and initialize APIC
992 static int __init
detect_init_APIC (void)
996 /* Disabled by kernel option? */
997 if (enable_local_apic
< 0)
1000 switch (boot_cpu_data
.x86_vendor
) {
1001 case X86_VENDOR_AMD
:
1002 if ((boot_cpu_data
.x86
== 6 && boot_cpu_data
.x86_model
> 1) ||
1003 (boot_cpu_data
.x86
== 15))
1006 case X86_VENDOR_INTEL
:
1007 if (boot_cpu_data
.x86
== 6 || boot_cpu_data
.x86
== 15 ||
1008 (boot_cpu_data
.x86
== 5 && cpu_has_apic
))
1015 if (!cpu_has_apic
) {
1017 * Over-ride BIOS and try to enable the local APIC only if
1018 * "lapic" specified.
1020 if (enable_local_apic
<= 0) {
1021 printk(KERN_INFO
"Local APIC disabled by BIOS -- "
1022 "you can enable it with \"lapic\"\n");
1026 * Some BIOSes disable the local APIC in the APIC_BASE
1027 * MSR. This can only be done in software for Intel P6 or later
1028 * and AMD K7 (Model > 1) or later.
1030 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1031 if (!(l
& MSR_IA32_APICBASE_ENABLE
)) {
1033 "Local APIC disabled by BIOS -- reenabling.\n");
1034 l
&= ~MSR_IA32_APICBASE_BASE
;
1035 l
|= MSR_IA32_APICBASE_ENABLE
| APIC_DEFAULT_PHYS_BASE
;
1036 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1037 enabled_via_apicbase
= 1;
1041 * The APIC feature bit should now be enabled
1044 features
= cpuid_edx(1);
1045 if (!(features
& (1 << X86_FEATURE_APIC
))) {
1046 printk(KERN_WARNING
"Could not enable APIC!\n");
1049 set_bit(X86_FEATURE_APIC
, boot_cpu_data
.x86_capability
);
1050 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1052 /* The BIOS may have set up the APIC at some other address */
1053 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1054 if (l
& MSR_IA32_APICBASE_ENABLE
)
1055 mp_lapic_addr
= l
& MSR_IA32_APICBASE_BASE
;
1057 if (nmi_watchdog
!= NMI_NONE
)
1058 nmi_watchdog
= NMI_LOCAL_APIC
;
1060 printk(KERN_INFO
"Found and enabled local APIC!\n");
1067 printk(KERN_INFO
"No local APIC present or hardware disabled\n");
1072 * init_apic_mappings - initialize APIC mappings
1074 void __init
init_apic_mappings(void)
1076 unsigned long apic_phys
;
1079 * If no local APIC can be found then set up a fake all
1080 * zeroes page to simulate the local APIC and another
1081 * one for the IO-APIC.
1083 if (!smp_found_config
&& detect_init_APIC()) {
1084 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
1085 apic_phys
= __pa(apic_phys
);
1087 apic_phys
= mp_lapic_addr
;
1089 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
1090 printk(KERN_DEBUG
"mapped APIC to %08lx (%08lx)\n", APIC_BASE
,
1094 * Fetch the APIC ID of the BSP in case we have a
1095 * default configuration (or the MP table is broken).
1097 if (boot_cpu_physical_apicid
== -1U)
1098 boot_cpu_physical_apicid
= GET_APIC_ID(apic_read(APIC_ID
));
1100 #ifdef CONFIG_X86_IO_APIC
1102 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
1105 for (i
= 0; i
< nr_ioapics
; i
++) {
1106 if (smp_found_config
) {
1107 ioapic_phys
= mp_ioapics
[i
].mpc_apicaddr
;
1110 "WARNING: bogus zero IO-APIC "
1111 "address found in MPTABLE, "
1112 "disabling IO/APIC support!\n");
1113 smp_found_config
= 0;
1114 skip_ioapic_setup
= 1;
1115 goto fake_ioapic_page
;
1119 ioapic_phys
= (unsigned long)
1120 alloc_bootmem_pages(PAGE_SIZE
);
1121 ioapic_phys
= __pa(ioapic_phys
);
1123 set_fixmap_nocache(idx
, ioapic_phys
);
1124 printk(KERN_DEBUG
"mapped IOAPIC to %08lx (%08lx)\n",
1125 __fix_to_virt(idx
), ioapic_phys
);
1133 * This initializes the IO-APIC and APIC hardware if this is
1136 int __init
APIC_init_uniprocessor (void)
1138 if (enable_local_apic
< 0)
1139 clear_bit(X86_FEATURE_APIC
, boot_cpu_data
.x86_capability
);
1141 if (!smp_found_config
&& !cpu_has_apic
)
1145 * Complain if the BIOS pretends there is one.
1147 if (!cpu_has_apic
&&
1148 APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
1149 printk(KERN_ERR
"BIOS bug, local APIC #%d not detected!...\n",
1150 boot_cpu_physical_apicid
);
1151 clear_bit(X86_FEATURE_APIC
, boot_cpu_data
.x86_capability
);
1155 verify_local_APIC();
1160 * Hack: In case of kdump, after a crash, kernel might be booting
1161 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1162 * might be zero if read from MP tables. Get it from LAPIC.
1164 #ifdef CONFIG_CRASH_DUMP
1165 boot_cpu_physical_apicid
= GET_APIC_ID(apic_read(APIC_ID
));
1167 phys_cpu_present_map
= physid_mask_of_physid(boot_cpu_physical_apicid
);
1171 #ifdef CONFIG_X86_IO_APIC
1172 if (smp_found_config
)
1173 if (!skip_ioapic_setup
&& nr_ioapics
)
1182 * APIC command line parameters
1184 static int __init
parse_lapic(char *arg
)
1186 enable_local_apic
= 1;
1189 early_param("lapic", parse_lapic
);
1191 static int __init
parse_nolapic(char *arg
)
1193 enable_local_apic
= -1;
1194 clear_bit(X86_FEATURE_APIC
, boot_cpu_data
.x86_capability
);
1197 early_param("nolapic", parse_nolapic
);
1199 static int __init
apic_set_verbosity(char *str
)
1201 if (strcmp("debug", str
) == 0)
1202 apic_verbosity
= APIC_DEBUG
;
1203 else if (strcmp("verbose", str
) == 0)
1204 apic_verbosity
= APIC_VERBOSE
;
1208 __setup("apic=", apic_set_verbosity
);
1212 * Local APIC interrupts
1216 * This interrupt should _never_ happen with our APIC/SMP architecture
1218 void smp_spurious_interrupt(struct pt_regs
*regs
)
1224 * Check if this really is a spurious interrupt and ACK it
1225 * if it is a vectored one. Just in case...
1226 * Spurious interrupts should not be ACKed.
1228 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1229 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1232 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1233 printk(KERN_INFO
"spurious APIC interrupt on CPU#%d, "
1234 "should never happen.\n", smp_processor_id());
1239 * This interrupt should never happen with our APIC/SMP architecture
1241 void smp_error_interrupt(struct pt_regs
*regs
)
1243 unsigned long v
, v1
;
1246 /* First tickle the hardware, only then report what went on. -- REW */
1247 v
= apic_read(APIC_ESR
);
1248 apic_write(APIC_ESR
, 0);
1249 v1
= apic_read(APIC_ESR
);
1251 atomic_inc(&irq_err_count
);
1253 /* Here is what the APIC error bits mean:
1256 2: Send accept error
1257 3: Receive accept error
1259 5: Send illegal vector
1260 6: Received illegal vector
1261 7: Illegal register address
1263 printk (KERN_DEBUG
"APIC error on CPU%d: %02lx(%02lx)\n",
1264 smp_processor_id(), v
, v1
);
1269 * Initialize APIC interrupts
1271 void __init
apic_intr_init(void)
1276 /* self generated IPI for local APIC timer */
1277 set_intr_gate(LOCAL_TIMER_VECTOR
, apic_timer_interrupt
);
1279 /* IPI vectors for APIC spurious and error interrupts */
1280 set_intr_gate(SPURIOUS_APIC_VECTOR
, spurious_interrupt
);
1281 set_intr_gate(ERROR_APIC_VECTOR
, error_interrupt
);
1283 /* thermal monitor LVT interrupt */
1284 #ifdef CONFIG_X86_MCE_P4THERMAL
1285 set_intr_gate(THERMAL_APIC_VECTOR
, thermal_interrupt
);
1290 * connect_bsp_APIC - attach the APIC to the interrupt system
1292 void __init
connect_bsp_APIC(void)
1296 * Do not trust the local APIC being empty at bootup.
1300 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1301 * local APIC to INT and NMI lines.
1303 apic_printk(APIC_VERBOSE
, "leaving PIC mode, "
1304 "enabling APIC mode.\n");
1312 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1313 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1315 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1318 void disconnect_bsp_APIC(int virt_wire_setup
)
1322 * Put the board back into PIC mode (has an effect only on
1323 * certain older boards). Note that APIC interrupts, including
1324 * IPIs, won't work beyond this point! The only exception are
1327 apic_printk(APIC_VERBOSE
, "disabling APIC mode, "
1328 "entering PIC mode.\n");
1332 /* Go back to Virtual Wire compatibility mode */
1333 unsigned long value
;
1335 /* For the spurious interrupt use vector F, and enable it */
1336 value
= apic_read(APIC_SPIV
);
1337 value
&= ~APIC_VECTOR_MASK
;
1338 value
|= APIC_SPIV_APIC_ENABLED
;
1340 apic_write_around(APIC_SPIV
, value
);
1342 if (!virt_wire_setup
) {
1344 * For LVT0 make it edge triggered, active high,
1345 * external and enabled
1347 value
= apic_read(APIC_LVT0
);
1348 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1349 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1350 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1351 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1352 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
1353 apic_write_around(APIC_LVT0
, value
);
1356 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
);
1360 * For LVT1 make it edge triggered, active high, nmi and
1363 value
= apic_read(APIC_LVT1
);
1365 APIC_MODE_MASK
| APIC_SEND_PENDING
|
1366 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1367 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1368 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1369 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
1370 apic_write_around(APIC_LVT1
, value
);
1381 /* r/w apic fields */
1382 unsigned int apic_id
;
1383 unsigned int apic_taskpri
;
1384 unsigned int apic_ldr
;
1385 unsigned int apic_dfr
;
1386 unsigned int apic_spiv
;
1387 unsigned int apic_lvtt
;
1388 unsigned int apic_lvtpc
;
1389 unsigned int apic_lvt0
;
1390 unsigned int apic_lvt1
;
1391 unsigned int apic_lvterr
;
1392 unsigned int apic_tmict
;
1393 unsigned int apic_tdcr
;
1394 unsigned int apic_thmr
;
1397 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
1399 unsigned long flags
;
1402 if (!apic_pm_state
.active
)
1405 maxlvt
= lapic_get_maxlvt();
1407 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
1408 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
1409 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
1410 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
1411 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
1412 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
1414 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
1415 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
1416 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
1417 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
1418 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
1419 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
1420 #ifdef CONFIG_X86_MCE_P4THERMAL
1422 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
1425 local_irq_save(flags
);
1426 disable_local_APIC();
1427 local_irq_restore(flags
);
1431 static int lapic_resume(struct sys_device
*dev
)
1434 unsigned long flags
;
1437 if (!apic_pm_state
.active
)
1440 maxlvt
= lapic_get_maxlvt();
1442 local_irq_save(flags
);
1445 * Make sure the APICBASE points to the right address
1447 * FIXME! This will be wrong if we ever support suspend on
1448 * SMP! We'll need to do this as part of the CPU restore!
1450 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1451 l
&= ~MSR_IA32_APICBASE_BASE
;
1452 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
1453 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1455 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
1456 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
1457 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
1458 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
1459 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
1460 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
1461 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
1462 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
1463 #ifdef CONFIG_X86_MCE_P4THERMAL
1465 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
1468 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
1469 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
1470 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
1471 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
1472 apic_write(APIC_ESR
, 0);
1473 apic_read(APIC_ESR
);
1474 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
1475 apic_write(APIC_ESR
, 0);
1476 apic_read(APIC_ESR
);
1477 local_irq_restore(flags
);
1482 * This device has no shutdown method - fully functioning local APICs
1483 * are needed on every CPU up until machine_halt/restart/poweroff.
1486 static struct sysdev_class lapic_sysclass
= {
1487 set_kset_name("lapic"),
1488 .resume
= lapic_resume
,
1489 .suspend
= lapic_suspend
,
1492 static struct sys_device device_lapic
= {
1494 .cls
= &lapic_sysclass
,
1497 static void __devinit
apic_pm_activate(void)
1499 apic_pm_state
.active
= 1;
1502 static int __init
init_lapic_sysfs(void)
1508 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
1510 error
= sysdev_class_register(&lapic_sysclass
);
1512 error
= sysdev_register(&device_lapic
);
1515 device_initcall(init_lapic_sysfs
);
1517 #else /* CONFIG_PM */
1519 static void apic_pm_activate(void) { }
1521 #endif /* CONFIG_PM */