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ath5k: fixing retries in ath5k_hw_setup_4word_tx_desc
[linux-2.6/kvm.git] / drivers / net / wireless / ath / ath5k / ath5k.h
blob365eccd777a36b3c39620912c8c46f1a125fe8ef
1 /*
2 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com>
4 *
5 * Permission to use, copy, modify, and distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
18 #ifndef _ATH5K_H
19 #define _ATH5K_H
20
21 /* TODO: Clean up channel debuging -doesn't work anyway- and start
22 * working on reg. control code using all available eeprom information
23 * -rev. engineering needed- */
24 #define CHAN_DEBUG 0
25
26 #include <linux/io.h>
27 #include <linux/types.h>
28 #include <net/mac80211.h>
29
30 /* RX/TX descriptor hw structs
31 * TODO: Driver part should only see sw structs */
32 #include "desc.h"
33
34 /* EEPROM structs/offsets
35 * TODO: Make a more generic struct (eg. add more stuff to ath5k_capabilities)
36 * and clean up common bits, then introduce set/get functions in eeprom.c */
37 #include "eeprom.h"
38 #include "../ath.h"
39
40 /* PCI IDs */
41 #define PCI_DEVICE_ID_ATHEROS_AR5210 0x0007 /* AR5210 */
42 #define PCI_DEVICE_ID_ATHEROS_AR5311 0x0011 /* AR5311 */
43 #define PCI_DEVICE_ID_ATHEROS_AR5211 0x0012 /* AR5211 */
44 #define PCI_DEVICE_ID_ATHEROS_AR5212 0x0013 /* AR5212 */
45 #define PCI_DEVICE_ID_3COM_3CRDAG675 0x0013 /* 3CRDAG675 (Atheros AR5212) */
46 #define PCI_DEVICE_ID_3COM_2_3CRPAG175 0x0013 /* 3CRPAG175 (Atheros AR5212) */
47 #define PCI_DEVICE_ID_ATHEROS_AR5210_AP 0x0207 /* AR5210 (Early) */
48 #define PCI_DEVICE_ID_ATHEROS_AR5212_IBM 0x1014 /* AR5212 (IBM MiniPCI) */
49 #define PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT 0x1107 /* AR5210 (no eeprom) */
50 #define PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT 0x1113 /* AR5212 (no eeprom) */
51 #define PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT 0x1112 /* AR5211 (no eeprom) */
52 #define PCI_DEVICE_ID_ATHEROS_AR5212_FPGA 0xf013 /* AR5212 (emulation board) */
53 #define PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY 0xff12 /* AR5211 (emulation board) */
54 #define PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B 0xf11b /* AR5211 (emulation board) */
55 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
56 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
57 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV8 0x0058 /* AR5312 WMAC (AP43-030) */
58 #define PCI_DEVICE_ID_ATHEROS_AR5212_0014 0x0014 /* AR5212 compatible */
59 #define PCI_DEVICE_ID_ATHEROS_AR5212_0015 0x0015 /* AR5212 compatible */
60 #define PCI_DEVICE_ID_ATHEROS_AR5212_0016 0x0016 /* AR5212 compatible */
61 #define PCI_DEVICE_ID_ATHEROS_AR5212_0017 0x0017 /* AR5212 compatible */
62 #define PCI_DEVICE_ID_ATHEROS_AR5212_0018 0x0018 /* AR5212 compatible */
63 #define PCI_DEVICE_ID_ATHEROS_AR5212_0019 0x0019 /* AR5212 compatible */
64 #define PCI_DEVICE_ID_ATHEROS_AR2413 0x001a /* AR2413 (Griffin-lite) */
65 #define PCI_DEVICE_ID_ATHEROS_AR5413 0x001b /* AR5413 (Eagle) */
66 #define PCI_DEVICE_ID_ATHEROS_AR5424 0x001c /* AR5424 (Condor PCI-E) */
67 #define PCI_DEVICE_ID_ATHEROS_AR5416 0x0023 /* AR5416 */
68 #define PCI_DEVICE_ID_ATHEROS_AR5418 0x0024 /* AR5418 */
69
70 /****************************\
71 GENERIC DRIVER DEFINITIONS
72 \****************************/
73
74 #define ATH5K_PRINTF(fmt, ...) printk("%s: " fmt, __func__, ##__VA_ARGS__)
75
76 #define ATH5K_PRINTK(_sc, _level, _fmt, ...) \
77 printk(_level "ath5k %s: " _fmt, \
78 ((_sc) && (_sc)->hw) ? wiphy_name((_sc)->hw->wiphy) : "", \
79 ##__VA_ARGS__)
80
81 #define ATH5K_PRINTK_LIMIT(_sc, _level, _fmt, ...) do { \
82 if (net_ratelimit()) \
83 ATH5K_PRINTK(_sc, _level, _fmt, ##__VA_ARGS__); \
84 } while (0)
85
86 #define ATH5K_INFO(_sc, _fmt, ...) \
87 ATH5K_PRINTK(_sc, KERN_INFO, _fmt, ##__VA_ARGS__)
88
89 #define ATH5K_WARN(_sc, _fmt, ...) \
90 ATH5K_PRINTK_LIMIT(_sc, KERN_WARNING, _fmt, ##__VA_ARGS__)
91
92 #define ATH5K_ERR(_sc, _fmt, ...) \
93 ATH5K_PRINTK_LIMIT(_sc, KERN_ERR, _fmt, ##__VA_ARGS__)
94
95 /*
96 * AR5K REGISTER ACCESS
97 */
98
99 /* Some macros to read/write fields */
100
101 /* First shift, then mask */
102 #define AR5K_REG_SM(_val, _flags) \
103 (((_val) << _flags##_S) & (_flags))
104
105 /* First mask, then shift */
106 #define AR5K_REG_MS(_val, _flags) \
107 (((_val) & (_flags)) >> _flags##_S)
108
109 /* Some registers can hold multiple values of interest. For this
110 * reason when we want to write to these registers we must first
111 * retrieve the values which we do not want to clear (lets call this
112 * old_data) and then set the register with this and our new_value:
113 * ( old_data | new_value) */
114 #define AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val) \
115 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & ~(_flags)) | \
116 (((_val) << _flags##_S) & (_flags)), _reg)
117
118 #define AR5K_REG_MASKED_BITS(ah, _reg, _flags, _mask) \
119 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & \
120 (_mask)) | (_flags), _reg)
121
122 #define AR5K_REG_ENABLE_BITS(ah, _reg, _flags) \
123 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) | (_flags), _reg)
124
125 #define AR5K_REG_DISABLE_BITS(ah, _reg, _flags) \
126 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) & ~(_flags), _reg)
127
128 /* Access to PHY registers */
129 #define AR5K_PHY_READ(ah, _reg) \
130 ath5k_hw_reg_read(ah, (ah)->ah_phy + ((_reg) << 2))
131
132 #define AR5K_PHY_WRITE(ah, _reg, _val) \
133 ath5k_hw_reg_write(ah, _val, (ah)->ah_phy + ((_reg) << 2))
134
135 /* Access QCU registers per queue */
136 #define AR5K_REG_READ_Q(ah, _reg, _queue) \
137 (ath5k_hw_reg_read(ah, _reg) & (1 << _queue)) \
138
139 #define AR5K_REG_WRITE_Q(ah, _reg, _queue) \
140 ath5k_hw_reg_write(ah, (1 << _queue), _reg)
141
142 #define AR5K_Q_ENABLE_BITS(_reg, _queue) do { \
143 _reg |= 1 << _queue; \
144 } while (0)
145
146 #define AR5K_Q_DISABLE_BITS(_reg, _queue) do { \
147 _reg &= ~(1 << _queue); \
148 } while (0)
149
150 /* Used while writing initvals */
151 #define AR5K_REG_WAIT(_i) do { \
152 if (_i % 64) \
153 udelay(1); \
154 } while (0)
155
156 /* Register dumps are done per operation mode */
157 #define AR5K_INI_RFGAIN_5GHZ 0
158 #define AR5K_INI_RFGAIN_2GHZ 1
159
160 /* TODO: Clean this up */
161 #define AR5K_INI_VAL_11A 0
162 #define AR5K_INI_VAL_11A_TURBO 1
163 #define AR5K_INI_VAL_11B 2
164 #define AR5K_INI_VAL_11G 3
165 #define AR5K_INI_VAL_11G_TURBO 4
166 #define AR5K_INI_VAL_XR 0
167 #define AR5K_INI_VAL_MAX 5
168
169 /*
170 * Some tuneable values (these should be changeable by the user)
171 * TODO: Make use of them and add more options OR use debug/configfs
172 */
173 #define AR5K_TUNE_DMA_BEACON_RESP 2
174 #define AR5K_TUNE_SW_BEACON_RESP 10
175 #define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF 0
176 #define AR5K_TUNE_RADAR_ALERT false
177 #define AR5K_TUNE_MIN_TX_FIFO_THRES 1
178 #define AR5K_TUNE_MAX_TX_FIFO_THRES ((IEEE80211_MAX_LEN / 64) + 1)
179 #define AR5K_TUNE_REGISTER_TIMEOUT 20000
180 /* Register for RSSI threshold has a mask of 0xff, so 255 seems to
181 * be the max value. */
182 #define AR5K_TUNE_RSSI_THRES 129
183 /* This must be set when setting the RSSI threshold otherwise it can
184 * prevent a reset. If AR5K_RSSI_THR is read after writing to it
185 * the BMISS_THRES will be seen as 0, seems harware doesn't keep
186 * track of it. Max value depends on harware. For AR5210 this is just 7.
187 * For AR5211+ this seems to be up to 255. */
188 #define AR5K_TUNE_BMISS_THRES 7
189 #define AR5K_TUNE_REGISTER_DWELL_TIME 20000
190 #define AR5K_TUNE_BEACON_INTERVAL 100
191 #define AR5K_TUNE_AIFS 2
192 #define AR5K_TUNE_AIFS_11B 2
193 #define AR5K_TUNE_AIFS_XR 0
194 #define AR5K_TUNE_CWMIN 15
195 #define AR5K_TUNE_CWMIN_11B 31
196 #define AR5K_TUNE_CWMIN_XR 3
197 #define AR5K_TUNE_CWMAX 1023
198 #define AR5K_TUNE_CWMAX_11B 1023
199 #define AR5K_TUNE_CWMAX_XR 7
200 #define AR5K_TUNE_NOISE_FLOOR -72
201 #define AR5K_TUNE_CCA_MAX_GOOD_VALUE -95
202 #define AR5K_TUNE_MAX_TXPOWER 63
203 #define AR5K_TUNE_DEFAULT_TXPOWER 25
204 #define AR5K_TUNE_TPC_TXPOWER false
205
206 #define AR5K_INIT_CARR_SENSE_EN 1
207
208 /*Swap RX/TX Descriptor for big endian archs*/
209 #if defined(__BIG_ENDIAN)
210 #define AR5K_INIT_CFG ( \
211 AR5K_CFG_SWTD | AR5K_CFG_SWRD \
212 )
213 #else
214 #define AR5K_INIT_CFG 0x00000000
215 #endif
216
217 /* Initial values */
218 #define AR5K_INIT_CYCRSSI_THR1 2
219 #define AR5K_INIT_TX_LATENCY 502
220 #define AR5K_INIT_USEC 39
221 #define AR5K_INIT_USEC_TURBO 79
222 #define AR5K_INIT_USEC_32 31
223 #define AR5K_INIT_SLOT_TIME 396
224 #define AR5K_INIT_SLOT_TIME_TURBO 480
225 #define AR5K_INIT_ACK_CTS_TIMEOUT 1024
226 #define AR5K_INIT_ACK_CTS_TIMEOUT_TURBO 0x08000800
227 #define AR5K_INIT_PROG_IFS 920
228 #define AR5K_INIT_PROG_IFS_TURBO 960
229 #define AR5K_INIT_EIFS 3440
230 #define AR5K_INIT_EIFS_TURBO 6880
231 #define AR5K_INIT_SIFS 560
232 #define AR5K_INIT_SIFS_TURBO 480
233 #define AR5K_INIT_SH_RETRY 10
234 #define AR5K_INIT_LG_RETRY AR5K_INIT_SH_RETRY
235 #define AR5K_INIT_SSH_RETRY 32
236 #define AR5K_INIT_SLG_RETRY AR5K_INIT_SSH_RETRY
237 #define AR5K_INIT_TX_RETRY 10
238
239 #define AR5K_INIT_TRANSMIT_LATENCY ( \
240 (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \
241 (AR5K_INIT_USEC) \
242 )
243 #define AR5K_INIT_TRANSMIT_LATENCY_TURBO ( \
244 (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \
245 (AR5K_INIT_USEC_TURBO) \
246 )
247 #define AR5K_INIT_PROTO_TIME_CNTRL ( \
248 (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS << 12) | \
249 (AR5K_INIT_PROG_IFS) \
250 )
251 #define AR5K_INIT_PROTO_TIME_CNTRL_TURBO ( \
252 (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS_TURBO << 12) | \
253 (AR5K_INIT_PROG_IFS_TURBO) \
254 )
255
256 /* token to use for aifs, cwmin, cwmax in MadWiFi */
257 #define AR5K_TXQ_USEDEFAULT ((u32) -1)
258
259 /* GENERIC CHIPSET DEFINITIONS */
260
261 /* MAC Chips */
262 enum ath5k_version {
263 AR5K_AR5210 = 0,
264 AR5K_AR5211 = 1,
265 AR5K_AR5212 = 2,
266 };
267
268 /* PHY Chips */
269 enum ath5k_radio {
270 AR5K_RF5110 = 0,
271 AR5K_RF5111 = 1,
272 AR5K_RF5112 = 2,
273 AR5K_RF2413 = 3,
274 AR5K_RF5413 = 4,
275 AR5K_RF2316 = 5,
276 AR5K_RF2317 = 6,
277 AR5K_RF2425 = 7,
278 };
279
280 /*
281 * Common silicon revision/version values
282 */
283
284 enum ath5k_srev_type {
285 AR5K_VERSION_MAC,
286 AR5K_VERSION_RAD,
287 };
288
289 struct ath5k_srev_name {
290 const char *sr_name;
291 enum ath5k_srev_type sr_type;
292 u_int sr_val;
293 };
294
295 #define AR5K_SREV_UNKNOWN 0xffff
296
297 #define AR5K_SREV_AR5210 0x00 /* Crete */
298 #define AR5K_SREV_AR5311 0x10 /* Maui 1 */
299 #define AR5K_SREV_AR5311A 0x20 /* Maui 2 */
300 #define AR5K_SREV_AR5311B 0x30 /* Spirit */
301 #define AR5K_SREV_AR5211 0x40 /* Oahu */
302 #define AR5K_SREV_AR5212 0x50 /* Venice */
303 #define AR5K_SREV_AR5212_V4 0x54 /* ??? */
304 #define AR5K_SREV_AR5213 0x55 /* ??? */
305 #define AR5K_SREV_AR5213A 0x59 /* Hainan */
306 #define AR5K_SREV_AR2413 0x78 /* Griffin lite */
307 #define AR5K_SREV_AR2414 0x70 /* Griffin */
308 #define AR5K_SREV_AR5424 0x90 /* Condor */
309 #define AR5K_SREV_AR5413 0xa4 /* Eagle lite */
310 #define AR5K_SREV_AR5414 0xa0 /* Eagle */
311 #define AR5K_SREV_AR2415 0xb0 /* Talon */
312 #define AR5K_SREV_AR5416 0xc0 /* PCI-E */
313 #define AR5K_SREV_AR5418 0xca /* PCI-E */
314 #define AR5K_SREV_AR2425 0xe0 /* Swan */
315 #define AR5K_SREV_AR2417 0xf0 /* Nala */
316
317 #define AR5K_SREV_RAD_5110 0x00
318 #define AR5K_SREV_RAD_5111 0x10
319 #define AR5K_SREV_RAD_5111A 0x15
320 #define AR5K_SREV_RAD_2111 0x20
321 #define AR5K_SREV_RAD_5112 0x30
322 #define AR5K_SREV_RAD_5112A 0x35
323 #define AR5K_SREV_RAD_5112B 0x36
324 #define AR5K_SREV_RAD_2112 0x40
325 #define AR5K_SREV_RAD_2112A 0x45
326 #define AR5K_SREV_RAD_2112B 0x46
327 #define AR5K_SREV_RAD_2413 0x50
328 #define AR5K_SREV_RAD_5413 0x60
329 #define AR5K_SREV_RAD_2316 0x70 /* Cobra SoC */
330 #define AR5K_SREV_RAD_2317 0x80
331 #define AR5K_SREV_RAD_5424 0xa0 /* Mostly same as 5413 */
332 #define AR5K_SREV_RAD_2425 0xa2
333 #define AR5K_SREV_RAD_5133 0xc0
334
335 #define AR5K_SREV_PHY_5211 0x30
336 #define AR5K_SREV_PHY_5212 0x41
337 #define AR5K_SREV_PHY_5212A 0x42
338 #define AR5K_SREV_PHY_5212B 0x43
339 #define AR5K_SREV_PHY_2413 0x45
340 #define AR5K_SREV_PHY_5413 0x61
341 #define AR5K_SREV_PHY_2425 0x70
342
343 /* IEEE defs */
344 #define IEEE80211_MAX_LEN 2500
345
346 /* TODO add support to mac80211 for vendor-specific rates and modes */
347
348 /*
349 * Some of this information is based on Documentation from:
350 *
351 * http://madwifi.org/wiki/ChipsetFeatures/SuperAG
352 *
353 * Modulation for Atheros' eXtended Range - range enhancing extension that is
354 * supposed to double the distance an Atheros client device can keep a
355 * connection with an Atheros access point. This is achieved by increasing
356 * the receiver sensitivity up to, -105dBm, which is about 20dB above what
357 * the 802.11 specifications demand. In addition, new (proprietary) data rates
358 * are introduced: 3, 2, 1, 0.5 and 0.25 MBit/s.
359 *
360 * Please note that can you either use XR or TURBO but you cannot use both,
361 * they are exclusive.
362 *
363 */
364 #define MODULATION_XR 0x00000200
365 /*
366 * Modulation for Atheros' Turbo G and Turbo A, its supposed to provide a
367 * throughput transmission speed up to 40Mbit/s-60Mbit/s at a 108Mbit/s
368 * signaling rate achieved through the bonding of two 54Mbit/s 802.11g
369 * channels. To use this feature your Access Point must also suport it.
370 * There is also a distinction between "static" and "dynamic" turbo modes:
371 *
372 * - Static: is the dumb version: devices set to this mode stick to it until
373 * the mode is turned off.
374 * - Dynamic: is the intelligent version, the network decides itself if it
375 * is ok to use turbo. As soon as traffic is detected on adjacent channels
376 * (which would get used in turbo mode), or when a non-turbo station joins
377 * the network, turbo mode won't be used until the situation changes again.
378 * Dynamic mode is achieved by Atheros' Adaptive Radio (AR) feature which
379 * monitors the used radio band in order to decide whether turbo mode may
380 * be used or not.
381 *
382 * This article claims Super G sticks to bonding of channels 5 and 6 for
383 * USA:
384 *
385 * http://www.pcworld.com/article/id,113428-page,1/article.html
386 *
387 * The channel bonding seems to be driver specific though. In addition to
388 * deciding what channels will be used, these "Turbo" modes are accomplished
389 * by also enabling the following features:
390 *
391 * - Bursting: allows multiple frames to be sent at once, rather than pausing
392 * after each frame. Bursting is a standards-compliant feature that can be
393 * used with any Access Point.
394 * - Fast frames: increases the amount of information that can be sent per
395 * frame, also resulting in a reduction of transmission overhead. It is a
396 * proprietary feature that needs to be supported by the Access Point.
397 * - Compression: data frames are compressed in real time using a Lempel Ziv
398 * algorithm. This is done transparently. Once this feature is enabled,
399 * compression and decompression takes place inside the chipset, without
400 * putting additional load on the host CPU.
401 *
402 */
403 #define MODULATION_TURBO 0x00000080
404
405 enum ath5k_driver_mode {
406 AR5K_MODE_11A = 0,
407 AR5K_MODE_11A_TURBO = 1,
408 AR5K_MODE_11B = 2,
409 AR5K_MODE_11G = 3,
410 AR5K_MODE_11G_TURBO = 4,
411 AR5K_MODE_XR = 0,
412 AR5K_MODE_MAX = 5
413 };
414
415 enum ath5k_ant_mode {
416 AR5K_ANTMODE_DEFAULT = 0, /* default antenna setup */
417 AR5K_ANTMODE_FIXED_A = 1, /* only antenna A is present */
418 AR5K_ANTMODE_FIXED_B = 2, /* only antenna B is present */
419 AR5K_ANTMODE_SINGLE_AP = 3, /* sta locked on a single ap */
420 AR5K_ANTMODE_SECTOR_AP = 4, /* AP with tx antenna set on tx desc */
421 AR5K_ANTMODE_SECTOR_STA = 5, /* STA with tx antenna set on tx desc */
422 AR5K_ANTMODE_DEBUG = 6, /* Debug mode -A -> Rx, B-> Tx- */
423 AR5K_ANTMODE_MAX,
424 };
425
426
427 /****************\
428 TX DEFINITIONS
429 \****************/
430
431 /*
432 * TX Status descriptor
433 */
434 struct ath5k_tx_status {
435 u16 ts_seqnum;
436 u16 ts_tstamp;
437 u8 ts_status;
438 u8 ts_rate[4];
439 u8 ts_retry[4];
440 u8 ts_final_idx;
441 s8 ts_rssi;
442 u8 ts_shortretry;
443 u8 ts_longretry;
444 u8 ts_virtcol;
445 u8 ts_antenna;
446 };
447
448 #define AR5K_TXSTAT_ALTRATE 0x80
449 #define AR5K_TXERR_XRETRY 0x01
450 #define AR5K_TXERR_FILT 0x02
451 #define AR5K_TXERR_FIFO 0x04
452
453 /**
454 * enum ath5k_tx_queue - Queue types used to classify tx queues.
455 * @AR5K_TX_QUEUE_INACTIVE: q is unused -- see ath5k_hw_release_tx_queue
456 * @AR5K_TX_QUEUE_DATA: A normal data queue
457 * @AR5K_TX_QUEUE_XR_DATA: An XR-data queue
458 * @AR5K_TX_QUEUE_BEACON: The beacon queue
459 * @AR5K_TX_QUEUE_CAB: The after-beacon queue
460 * @AR5K_TX_QUEUE_UAPSD: Unscheduled Automatic Power Save Delivery queue
461 */
462 enum ath5k_tx_queue {
463 AR5K_TX_QUEUE_INACTIVE = 0,
464 AR5K_TX_QUEUE_DATA,
465 AR5K_TX_QUEUE_XR_DATA,
466 AR5K_TX_QUEUE_BEACON,
467 AR5K_TX_QUEUE_CAB,
468 AR5K_TX_QUEUE_UAPSD,
469 };
470
471 #define AR5K_NUM_TX_QUEUES 10
472 #define AR5K_NUM_TX_QUEUES_NOQCU 2
473
474 /*
475 * Queue syb-types to classify normal data queues.
476 * These are the 4 Access Categories as defined in
477 * WME spec. 0 is the lowest priority and 4 is the
478 * highest. Normal data that hasn't been classified
479 * goes to the Best Effort AC.
480 */
481 enum ath5k_tx_queue_subtype {
482 AR5K_WME_AC_BK = 0, /*Background traffic*/
483 AR5K_WME_AC_BE, /*Best-effort (normal) traffic)*/
484 AR5K_WME_AC_VI, /*Video traffic*/
485 AR5K_WME_AC_VO, /*Voice traffic*/
486 };
487
488 /*
489 * Queue ID numbers as returned by the hw functions, each number
490 * represents a hw queue. If hw does not support hw queues
491 * (eg 5210) all data goes in one queue. These match
492 * d80211 definitions (net80211/MadWiFi don't use them).
493 */
494 enum ath5k_tx_queue_id {
495 AR5K_TX_QUEUE_ID_NOQCU_DATA = 0,
496 AR5K_TX_QUEUE_ID_NOQCU_BEACON = 1,
497 AR5K_TX_QUEUE_ID_DATA_MIN = 0, /*IEEE80211_TX_QUEUE_DATA0*/
498 AR5K_TX_QUEUE_ID_DATA_MAX = 4, /*IEEE80211_TX_QUEUE_DATA4*/
499 AR5K_TX_QUEUE_ID_DATA_SVP = 5, /*IEEE80211_TX_QUEUE_SVP - Spectralink Voice Protocol*/
500 AR5K_TX_QUEUE_ID_CAB = 6, /*IEEE80211_TX_QUEUE_AFTER_BEACON*/
501 AR5K_TX_QUEUE_ID_BEACON = 7, /*IEEE80211_TX_QUEUE_BEACON*/
502 AR5K_TX_QUEUE_ID_UAPSD = 8,
503 AR5K_TX_QUEUE_ID_XR_DATA = 9,
504 };
505
506 /*
507 * Flags to set hw queue's parameters...
508 */
509 #define AR5K_TXQ_FLAG_TXOKINT_ENABLE 0x0001 /* Enable TXOK interrupt */
510 #define AR5K_TXQ_FLAG_TXERRINT_ENABLE 0x0002 /* Enable TXERR interrupt */
511 #define AR5K_TXQ_FLAG_TXEOLINT_ENABLE 0x0004 /* Enable TXEOL interrupt -not used- */
512 #define AR5K_TXQ_FLAG_TXDESCINT_ENABLE 0x0008 /* Enable TXDESC interrupt -not used- */
513 #define AR5K_TXQ_FLAG_TXURNINT_ENABLE 0x0010 /* Enable TXURN interrupt */
514 #define AR5K_TXQ_FLAG_CBRORNINT_ENABLE 0x0020 /* Enable CBRORN interrupt */
515 #define AR5K_TXQ_FLAG_CBRURNINT_ENABLE 0x0040 /* Enable CBRURN interrupt */
516 #define AR5K_TXQ_FLAG_QTRIGINT_ENABLE 0x0080 /* Enable QTRIG interrupt */
517 #define AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE 0x0100 /* Enable TXNOFRM interrupt */
518 #define AR5K_TXQ_FLAG_BACKOFF_DISABLE 0x0200 /* Disable random post-backoff */
519 #define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0300 /* Enable ready time expiry policy (?)*/
520 #define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0800 /* Enable backoff while bursting */
521 #define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS 0x1000 /* Disable backoff while bursting */
522 #define AR5K_TXQ_FLAG_COMPRESSION_ENABLE 0x2000 /* Enable hw compression -not implemented-*/
523
524 /*
525 * A struct to hold tx queue's parameters
526 */
527 struct ath5k_txq_info {
528 enum ath5k_tx_queue tqi_type;
529 enum ath5k_tx_queue_subtype tqi_subtype;
530 u16 tqi_flags; /* Tx queue flags (see above) */
531 u32 tqi_aifs; /* Arbitrated Interframe Space */
532 s32 tqi_cw_min; /* Minimum Contention Window */
533 s32 tqi_cw_max; /* Maximum Contention Window */
534 u32 tqi_cbr_period; /* Constant bit rate period */
535 u32 tqi_cbr_overflow_limit;
536 u32 tqi_burst_time;
537 u32 tqi_ready_time; /* Time queue waits after an event */
538 };
539
540 /*
541 * Transmit packet types.
542 * used on tx control descriptor
543 */
544 enum ath5k_pkt_type {
545 AR5K_PKT_TYPE_NORMAL = 0,
546 AR5K_PKT_TYPE_ATIM = 1,
547 AR5K_PKT_TYPE_PSPOLL = 2,
548 AR5K_PKT_TYPE_BEACON = 3,
549 AR5K_PKT_TYPE_PROBE_RESP = 4,
550 AR5K_PKT_TYPE_PIFS = 5,
551 };
552
553 /*
554 * TX power and TPC settings
555 */
556 #define AR5K_TXPOWER_OFDM(_r, _v) ( \
557 ((0 & 1) << ((_v) + 6)) | \
558 (((ah->ah_txpower.txp_rates_power_table[(_r)]) & 0x3f) << (_v)) \
559 )
560
561 #define AR5K_TXPOWER_CCK(_r, _v) ( \
562 (ah->ah_txpower.txp_rates_power_table[(_r)] & 0x3f) << (_v) \
563 )
564
565 /*
566 * DMA size definitions (2^n+2)
567 */
568 enum ath5k_dmasize {
569 AR5K_DMASIZE_4B = 0,
570 AR5K_DMASIZE_8B,
571 AR5K_DMASIZE_16B,
572 AR5K_DMASIZE_32B,
573 AR5K_DMASIZE_64B,
574 AR5K_DMASIZE_128B,
575 AR5K_DMASIZE_256B,
576 AR5K_DMASIZE_512B
577 };
578
579
580 /****************\
581 RX DEFINITIONS
582 \****************/
583
584 /*
585 * RX Status descriptor
586 */
587 struct ath5k_rx_status {
588 u16 rs_datalen;
589 u16 rs_tstamp;
590 u8 rs_status;
591 u8 rs_phyerr;
592 s8 rs_rssi;
593 u8 rs_keyix;
594 u8 rs_rate;
595 u8 rs_antenna;
596 u8 rs_more;
597 };
598
599 #define AR5K_RXERR_CRC 0x01
600 #define AR5K_RXERR_PHY 0x02
601 #define AR5K_RXERR_FIFO 0x04
602 #define AR5K_RXERR_DECRYPT 0x08
603 #define AR5K_RXERR_MIC 0x10
604 #define AR5K_RXKEYIX_INVALID ((u8) - 1)
605 #define AR5K_TXKEYIX_INVALID ((u32) - 1)
606
607
608 /**************************\
609 BEACON TIMERS DEFINITIONS
610 \**************************/
611
612 #define AR5K_BEACON_PERIOD 0x0000ffff
613 #define AR5K_BEACON_ENA 0x00800000 /*enable beacon xmit*/
614 #define AR5K_BEACON_RESET_TSF 0x01000000 /*force a TSF reset*/
615
616 #if 0
617 /**
618 * struct ath5k_beacon_state - Per-station beacon timer state.
619 * @bs_interval: in TU's, can also include the above flags
620 * @bs_cfp_max_duration: if non-zero hw is setup to coexist with a
621 * Point Coordination Function capable AP
622 */
623 struct ath5k_beacon_state {
624 u32 bs_next_beacon;
625 u32 bs_next_dtim;
626 u32 bs_interval;
627 u8 bs_dtim_period;
628 u8 bs_cfp_period;
629 u16 bs_cfp_max_duration;
630 u16 bs_cfp_du_remain;
631 u16 bs_tim_offset;
632 u16 bs_sleep_duration;
633 u16 bs_bmiss_threshold;
634 u32 bs_cfp_next;
635 };
636 #endif
637
638
639 /*
640 * TSF to TU conversion:
641 *
642 * TSF is a 64bit value in usec (microseconds).
643 * TU is a 32bit value and defined by IEEE802.11 (page 6) as "A measurement of
644 * time equal to 1024 usec", so it's roughly milliseconds (usec / 1024).
645 */
646 #define TSF_TO_TU(_tsf) (u32)((_tsf) >> 10)
647
648
649 /*******************************\
650 GAIN OPTIMIZATION DEFINITIONS
651 \*******************************/
652
653 enum ath5k_rfgain {
654 AR5K_RFGAIN_INACTIVE = 0,
655 AR5K_RFGAIN_ACTIVE,
656 AR5K_RFGAIN_READ_REQUESTED,
657 AR5K_RFGAIN_NEED_CHANGE,
658 };
659
660 struct ath5k_gain {
661 u8 g_step_idx;
662 u8 g_current;
663 u8 g_target;
664 u8 g_low;
665 u8 g_high;
666 u8 g_f_corr;
667 u8 g_state;
668 };
669
670 /********************\
671 COMMON DEFINITIONS
672 \********************/
673
674 #define AR5K_SLOT_TIME_9 396
675 #define AR5K_SLOT_TIME_20 880
676 #define AR5K_SLOT_TIME_MAX 0xffff
677
678 /* channel_flags */
679 #define CHANNEL_CW_INT 0x0008 /* Contention Window interference detected */
680 #define CHANNEL_TURBO 0x0010 /* Turbo Channel */
681 #define CHANNEL_CCK 0x0020 /* CCK channel */
682 #define CHANNEL_OFDM 0x0040 /* OFDM channel */
683 #define CHANNEL_2GHZ 0x0080 /* 2GHz channel. */
684 #define CHANNEL_5GHZ 0x0100 /* 5GHz channel */
685 #define CHANNEL_PASSIVE 0x0200 /* Only passive scan allowed */
686 #define CHANNEL_DYN 0x0400 /* Dynamic CCK-OFDM channel (for g operation) */
687 #define CHANNEL_XR 0x0800 /* XR channel */
688
689 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
690 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
691 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
692 #define CHANNEL_T (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
693 #define CHANNEL_TG (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
694 #define CHANNEL_108A CHANNEL_T
695 #define CHANNEL_108G CHANNEL_TG
696 #define CHANNEL_X (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR)
697
698 #define CHANNEL_ALL (CHANNEL_OFDM|CHANNEL_CCK|CHANNEL_2GHZ|CHANNEL_5GHZ| \
699 CHANNEL_TURBO)
700
701 #define CHANNEL_ALL_NOTURBO (CHANNEL_ALL & ~CHANNEL_TURBO)
702 #define CHANNEL_MODES CHANNEL_ALL
703
704 /*
705 * Used internaly for reset_tx_queue).
706 * Also see struct struct ieee80211_channel.
707 */
708 #define IS_CHAN_XR(_c) ((_c->hw_value & CHANNEL_XR) != 0)
709 #define IS_CHAN_B(_c) ((_c->hw_value & CHANNEL_B) != 0)
710
711 /*
712 * The following structure is used to map 2GHz channels to
713 * 5GHz Atheros channels.
714 * TODO: Clean up
715 */
716 struct ath5k_athchan_2ghz {
717 u32 a2_flags;
718 u16 a2_athchan;
719 };
720
721
722 /******************\
723 RATE DEFINITIONS
724 \******************/
725
726 /**
727 * Seems the ar5xxx harware supports up to 32 rates, indexed by 1-32.
728 *
729 * The rate code is used to get the RX rate or set the TX rate on the
730 * hardware descriptors. It is also used for internal modulation control
731 * and settings.
732 *
733 * This is the hardware rate map we are aware of:
734 *
735 * rate_code 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08
736 * rate_kbps 3000 1000 ? ? ? 2000 500 48000
737 *
738 * rate_code 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10
739 * rate_kbps 24000 12000 6000 54000 36000 18000 9000 ?
740 *
741 * rate_code 17 18 19 20 21 22 23 24
742 * rate_kbps ? ? ? ? ? ? ? 11000
743 *
744 * rate_code 25 26 27 28 29 30 31 32
745 * rate_kbps 5500 2000 1000 11000S 5500S 2000S ? ?
746 *
747 * "S" indicates CCK rates with short preamble.
748 *
749 * AR5211 has different rate codes for CCK (802.11B) rates. It only uses the
750 * lowest 4 bits, so they are the same as below with a 0xF mask.
751 * (0xB, 0xA, 0x9 and 0x8 for 1M, 2M, 5.5M and 11M).
752 * We handle this in ath5k_setup_bands().
753 */
754 #define AR5K_MAX_RATES 32
755
756 /* B */
757 #define ATH5K_RATE_CODE_1M 0x1B
758 #define ATH5K_RATE_CODE_2M 0x1A
759 #define ATH5K_RATE_CODE_5_5M 0x19
760 #define ATH5K_RATE_CODE_11M 0x18
761 /* A and G */
762 #define ATH5K_RATE_CODE_6M 0x0B
763 #define ATH5K_RATE_CODE_9M 0x0F
764 #define ATH5K_RATE_CODE_12M 0x0A
765 #define ATH5K_RATE_CODE_18M 0x0E
766 #define ATH5K_RATE_CODE_24M 0x09
767 #define ATH5K_RATE_CODE_36M 0x0D
768 #define ATH5K_RATE_CODE_48M 0x08
769 #define ATH5K_RATE_CODE_54M 0x0C
770 /* XR */
771 #define ATH5K_RATE_CODE_XR_500K 0x07
772 #define ATH5K_RATE_CODE_XR_1M 0x02
773 #define ATH5K_RATE_CODE_XR_2M 0x06
774 #define ATH5K_RATE_CODE_XR_3M 0x01
775
776 /* adding this flag to rate_code enables short preamble */
777 #define AR5K_SET_SHORT_PREAMBLE 0x04
778
779 /*
780 * Crypto definitions
781 */
782
783 #define AR5K_KEYCACHE_SIZE 8
784
785 /***********************\
786 HW RELATED DEFINITIONS
787 \***********************/
788
789 /*
790 * Misc definitions
791 */
792 #define AR5K_RSSI_EP_MULTIPLIER (1<<7)
793
794 #define AR5K_ASSERT_ENTRY(_e, _s) do { \
795 if (_e >= _s) \
796 return (false); \
797 } while (0)
798
799 /*
800 * Hardware interrupt abstraction
801 */
802
803 /**
804 * enum ath5k_int - Hardware interrupt masks helpers
805 *
806 * @AR5K_INT_RX: mask to identify received frame interrupts, of type
807 * AR5K_ISR_RXOK or AR5K_ISR_RXERR
808 * @AR5K_INT_RXDESC: Request RX descriptor/Read RX descriptor (?)
809 * @AR5K_INT_RXNOFRM: No frame received (?)
810 * @AR5K_INT_RXEOL: received End Of List for VEOL (Virtual End Of List). The
811 * Queue Control Unit (QCU) signals an EOL interrupt only if a descriptor's
812 * LinkPtr is NULL. For more details, refer to:
813 * http://www.freepatentsonline.com/20030225739.html
814 * @AR5K_INT_RXORN: Indicates we got RX overrun (eg. no more descriptors).
815 * Note that Rx overrun is not always fatal, on some chips we can continue
816 * operation without reseting the card, that's why int_fatal is not
817 * common for all chips.
818 * @AR5K_INT_TX: mask to identify received frame interrupts, of type
819 * AR5K_ISR_TXOK or AR5K_ISR_TXERR
820 * @AR5K_INT_TXDESC: Request TX descriptor/Read TX status descriptor (?)
821 * @AR5K_INT_TXURN: received when we should increase the TX trigger threshold
822 * We currently do increments on interrupt by
823 * (AR5K_TUNE_MAX_TX_FIFO_THRES - current_trigger_level) / 2
824 * @AR5K_INT_MIB: Indicates the Management Information Base counters should be
825 * checked. We should do this with ath5k_hw_update_mib_counters() but
826 * it seems we should also then do some noise immunity work.
827 * @AR5K_INT_RXPHY: RX PHY Error
828 * @AR5K_INT_RXKCM: RX Key cache miss
829 * @AR5K_INT_SWBA: SoftWare Beacon Alert - indicates its time to send a
830 * beacon that must be handled in software. The alternative is if you
831 * have VEOL support, in that case you let the hardware deal with things.
832 * @AR5K_INT_BMISS: If in STA mode this indicates we have stopped seeing
833 * beacons from the AP have associated with, we should probably try to
834 * reassociate. When in IBSS mode this might mean we have not received
835 * any beacons from any local stations. Note that every station in an
836 * IBSS schedules to send beacons at the Target Beacon Transmission Time
837 * (TBTT) with a random backoff.
838 * @AR5K_INT_BNR: Beacon Not Ready interrupt - ??
839 * @AR5K_INT_GPIO: GPIO interrupt is used for RF Kill, disabled for now
840 * until properly handled
841 * @AR5K_INT_FATAL: Fatal errors were encountered, typically caused by DMA
842 * errors. These types of errors we can enable seem to be of type
843 * AR5K_SIMR2_MCABT, AR5K_SIMR2_SSERR and AR5K_SIMR2_DPERR.
844 * @AR5K_INT_GLOBAL: Used to clear and set the IER
845 * @AR5K_INT_NOCARD: signals the card has been removed
846 * @AR5K_INT_COMMON: common interrupts shared amogst MACs with the same
847 * bit value
848 *
849 * These are mapped to take advantage of some common bits
850 * between the MACs, to be able to set intr properties
851 * easier. Some of them are not used yet inside hw.c. Most map
852 * to the respective hw interrupt value as they are common amogst different
853 * MACs.
854 */
855 enum ath5k_int {
856 AR5K_INT_RXOK = 0x00000001,
857 AR5K_INT_RXDESC = 0x00000002,
858 AR5K_INT_RXERR = 0x00000004,
859 AR5K_INT_RXNOFRM = 0x00000008,
860 AR5K_INT_RXEOL = 0x00000010,
861 AR5K_INT_RXORN = 0x00000020,
862 AR5K_INT_TXOK = 0x00000040,
863 AR5K_INT_TXDESC = 0x00000080,
864 AR5K_INT_TXERR = 0x00000100,
865 AR5K_INT_TXNOFRM = 0x00000200,
866 AR5K_INT_TXEOL = 0x00000400,
867 AR5K_INT_TXURN = 0x00000800,
868 AR5K_INT_MIB = 0x00001000,
869 AR5K_INT_SWI = 0x00002000,
870 AR5K_INT_RXPHY = 0x00004000,
871 AR5K_INT_RXKCM = 0x00008000,
872 AR5K_INT_SWBA = 0x00010000,
873 AR5K_INT_BRSSI = 0x00020000,
874 AR5K_INT_BMISS = 0x00040000,
875 AR5K_INT_FATAL = 0x00080000, /* Non common */
876 AR5K_INT_BNR = 0x00100000, /* Non common */
877 AR5K_INT_TIM = 0x00200000, /* Non common */
878 AR5K_INT_DTIM = 0x00400000, /* Non common */
879 AR5K_INT_DTIM_SYNC = 0x00800000, /* Non common */
880 AR5K_INT_GPIO = 0x01000000,
881 AR5K_INT_BCN_TIMEOUT = 0x02000000, /* Non common */
882 AR5K_INT_CAB_TIMEOUT = 0x04000000, /* Non common */
883 AR5K_INT_RX_DOPPLER = 0x08000000, /* Non common */
884 AR5K_INT_QCBRORN = 0x10000000, /* Non common */
885 AR5K_INT_QCBRURN = 0x20000000, /* Non common */
886 AR5K_INT_QTRIG = 0x40000000, /* Non common */
887 AR5K_INT_GLOBAL = 0x80000000,
888
889 AR5K_INT_COMMON = AR5K_INT_RXOK
890 | AR5K_INT_RXDESC
891 | AR5K_INT_RXERR
892 | AR5K_INT_RXNOFRM
893 | AR5K_INT_RXEOL
894 | AR5K_INT_RXORN
895 | AR5K_INT_TXOK
896 | AR5K_INT_TXDESC
897 | AR5K_INT_TXERR
898 | AR5K_INT_TXNOFRM
899 | AR5K_INT_TXEOL
900 | AR5K_INT_TXURN
901 | AR5K_INT_MIB
902 | AR5K_INT_SWI
903 | AR5K_INT_RXPHY
904 | AR5K_INT_RXKCM
905 | AR5K_INT_SWBA
906 | AR5K_INT_BRSSI
907 | AR5K_INT_BMISS
908 | AR5K_INT_GPIO
909 | AR5K_INT_GLOBAL,
910
911 AR5K_INT_NOCARD = 0xffffffff
912 };
913
914 /* Software interrupts used for calibration */
915 enum ath5k_software_interrupt {
916 AR5K_SWI_FULL_CALIBRATION = 0x01,
917 AR5K_SWI_SHORT_CALIBRATION = 0x02,
918 };
919
920 /*
921 * Power management
922 */
923 enum ath5k_power_mode {
924 AR5K_PM_UNDEFINED = 0,
925 AR5K_PM_AUTO,
926 AR5K_PM_AWAKE,
927 AR5K_PM_FULL_SLEEP,
928 AR5K_PM_NETWORK_SLEEP,
929 };
930
931 /*
932 * These match net80211 definitions (not used in
933 * mac80211).
934 * TODO: Clean this up
935 */
936 #define AR5K_LED_INIT 0 /*IEEE80211_S_INIT*/
937 #define AR5K_LED_SCAN 1 /*IEEE80211_S_SCAN*/
938 #define AR5K_LED_AUTH 2 /*IEEE80211_S_AUTH*/
939 #define AR5K_LED_ASSOC 3 /*IEEE80211_S_ASSOC*/
940 #define AR5K_LED_RUN 4 /*IEEE80211_S_RUN*/
941
942 /* GPIO-controlled software LED */
943 #define AR5K_SOFTLED_PIN 0
944 #define AR5K_SOFTLED_ON 0
945 #define AR5K_SOFTLED_OFF 1
946
947 /*
948 * Chipset capabilities -see ath5k_hw_get_capability-
949 * get_capability function is not yet fully implemented
950 * in ath5k so most of these don't work yet...
951 * TODO: Implement these & merge with _TUNE_ stuff above
952 */
953 enum ath5k_capability_type {
954 AR5K_CAP_REG_DMN = 0, /* Used to get current reg. domain id */
955 AR5K_CAP_TKIP_MIC = 2, /* Can handle TKIP MIC in hardware */
956 AR5K_CAP_TKIP_SPLIT = 3, /* TKIP uses split keys */
957 AR5K_CAP_PHYCOUNTERS = 4, /* PHY error counters */
958 AR5K_CAP_DIVERSITY = 5, /* Supports fast diversity */
959 AR5K_CAP_NUM_TXQUEUES = 6, /* Used to get max number of hw txqueues */
960 AR5K_CAP_VEOL = 7, /* Supports virtual EOL */
961 AR5K_CAP_COMPRESSION = 8, /* Supports compression */
962 AR5K_CAP_BURST = 9, /* Supports packet bursting */
963 AR5K_CAP_FASTFRAME = 10, /* Supports fast frames */
964 AR5K_CAP_TXPOW = 11, /* Used to get global tx power limit */
965 AR5K_CAP_TPC = 12, /* Can do per-packet tx power control (needed for 802.11a) */
966 AR5K_CAP_BSSIDMASK = 13, /* Supports bssid mask */
967 AR5K_CAP_MCAST_KEYSRCH = 14, /* Supports multicast key search */
968 AR5K_CAP_TSF_ADJUST = 15, /* Supports beacon tsf adjust */
969 AR5K_CAP_XR = 16, /* Supports XR mode */
970 AR5K_CAP_WME_TKIPMIC = 17, /* Supports TKIP MIC when using WMM */
971 AR5K_CAP_CHAN_HALFRATE = 18, /* Supports half rate channels */
972 AR5K_CAP_CHAN_QUARTERRATE = 19, /* Supports quarter rate channels */
973 AR5K_CAP_RFSILENT = 20, /* Supports RFsilent */
974 };
975
976
977 /* XXX: we *may* move cap_range stuff to struct wiphy */
978 struct ath5k_capabilities {
979 /*
980 * Supported PHY modes
981 * (ie. CHANNEL_A, CHANNEL_B, ...)
982 */
983 DECLARE_BITMAP(cap_mode, AR5K_MODE_MAX);
984
985 /*
986 * Frequency range (without regulation restrictions)
987 */
988 struct {
989 u16 range_2ghz_min;
990 u16 range_2ghz_max;
991 u16 range_5ghz_min;
992 u16 range_5ghz_max;
993 } cap_range;
994
995 /*
996 * Values stored in the EEPROM (some of them...)
997 */
998 struct ath5k_eeprom_info cap_eeprom;
999
1000 /*
1001 * Queue information
1002 */
1003 struct {
1004 u8 q_tx_num;
1005 } cap_queues;
1006 };
1007
1008 /* size of noise floor history (keep it a power of two) */
1009 #define ATH5K_NF_CAL_HIST_MAX 8
1010 struct ath5k_nfcal_hist
1011 {
1012 s16 index; /* current index into nfval */
1013 s16 nfval[ATH5K_NF_CAL_HIST_MAX]; /* last few noise floors */
1014 };
1015
1016
1017 /***************************************\
1018 HARDWARE ABSTRACTION LAYER STRUCTURE
1019 \***************************************/
1020
1021 /*
1022 * Misc defines
1023 */
1024
1025 #define AR5K_MAX_GPIO 10
1026 #define AR5K_MAX_RF_BANKS 8
1027
1028 /* TODO: Clean up and merge with ath5k_softc */
1029 struct ath5k_hw {
1030 struct ath_common common;
1031
1032 struct ath5k_softc *ah_sc;
1033 void __iomem *ah_iobase;
1034
1035 enum ath5k_int ah_imr;
1036
1037 struct ieee80211_channel *ah_current_channel;
1038 bool ah_turbo;
1039 bool ah_calibration;
1040 bool ah_single_chip;
1041 bool ah_aes_support;
1042 bool ah_combined_mic;
1043
1044 enum ath5k_version ah_version;
1045 enum ath5k_radio ah_radio;
1046 u32 ah_phy;
1047 u32 ah_mac_srev;
1048 u16 ah_mac_version;
1049 u16 ah_phy_revision;
1050 u16 ah_radio_5ghz_revision;
1051 u16 ah_radio_2ghz_revision;
1052
1053 #define ah_modes ah_capabilities.cap_mode
1054 #define ah_ee_version ah_capabilities.cap_eeprom.ee_version
1055
1056 u32 ah_atim_window;
1057 u32 ah_aifs;
1058 u32 ah_cw_min;
1059 u32 ah_cw_max;
1060 u32 ah_limit_tx_retries;
1061 u8 ah_coverage_class;
1062
1063 /* Antenna Control */
1064 u32 ah_ant_ctl[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX];
1065 u8 ah_ant_mode;
1066 u8 ah_tx_ant;
1067 u8 ah_def_ant;
1068 bool ah_software_retry;
1069
1070 struct ath5k_capabilities ah_capabilities;
1071
1072 struct ath5k_txq_info ah_txq[AR5K_NUM_TX_QUEUES];
1073 u32 ah_txq_status;
1074 u32 ah_txq_imr_txok;
1075 u32 ah_txq_imr_txerr;
1076 u32 ah_txq_imr_txurn;
1077 u32 ah_txq_imr_txdesc;
1078 u32 ah_txq_imr_txeol;
1079 u32 ah_txq_imr_cbrorn;
1080 u32 ah_txq_imr_cbrurn;
1081 u32 ah_txq_imr_qtrig;
1082 u32 ah_txq_imr_nofrm;
1083 u32 ah_txq_isr;
1084 u32 *ah_rf_banks;
1085 size_t ah_rf_banks_size;
1086 size_t ah_rf_regs_count;
1087 struct ath5k_gain ah_gain;
1088 u8 ah_offset[AR5K_MAX_RF_BANKS];
1089
1090
1091 struct {
1092 /* Temporary tables used for interpolation */
1093 u8 tmpL[AR5K_EEPROM_N_PD_GAINS]
1094 [AR5K_EEPROM_POWER_TABLE_SIZE];
1095 u8 tmpR[AR5K_EEPROM_N_PD_GAINS]
1096 [AR5K_EEPROM_POWER_TABLE_SIZE];
1097 u8 txp_pd_table[AR5K_EEPROM_POWER_TABLE_SIZE * 2];
1098 u16 txp_rates_power_table[AR5K_MAX_RATES];
1099 u8 txp_min_idx;
1100 bool txp_tpc;
1101 /* Values in 0.25dB units */
1102 s16 txp_min_pwr;
1103 s16 txp_max_pwr;
1104 /* Values in 0.5dB units */
1105 s16 txp_offset;
1106 s16 txp_ofdm;
1107 s16 txp_cck_ofdm_gainf_delta;
1108 /* Value in dB units */
1109 s16 txp_cck_ofdm_pwr_delta;
1110 } ah_txpower;
1111
1112 struct {
1113 bool r_enabled;
1114 int r_last_alert;
1115 struct ieee80211_channel r_last_channel;
1116 } ah_radar;
1117
1118 struct ath5k_nfcal_hist ah_nfcal_hist;
1119
1120 /* noise floor from last periodic calibration */
1121 s32 ah_noise_floor;
1122
1123 /* Calibration timestamp */
1124 unsigned long ah_cal_tstamp;
1125
1126 /* Calibration interval (secs) */
1127 u8 ah_cal_intval;
1128
1129 /* Software interrupt mask */
1130 u8 ah_swi_mask;
1131
1132 /*
1133 * Function pointers
1134 */
1135 int (*ah_setup_rx_desc)(struct ath5k_hw *ah, struct ath5k_desc *desc,
1136 u32 size, unsigned int flags);
1137 int (*ah_setup_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1138 unsigned int, unsigned int, int, enum ath5k_pkt_type,
1139 unsigned int, unsigned int, unsigned int, unsigned int,
1140 unsigned int, unsigned int, unsigned int, unsigned int);
1141 int (*ah_setup_mrr_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1142 unsigned int, unsigned int, unsigned int, unsigned int,
1143 unsigned int, unsigned int);
1144 int (*ah_proc_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1145 struct ath5k_tx_status *);
1146 int (*ah_proc_rx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1147 struct ath5k_rx_status *);
1148 };
1149
1150 /*
1151 * Prototypes
1152 */
1153
1154 /* Attach/Detach Functions */
1155 int ath5k_hw_attach(struct ath5k_softc *sc);
1156 void ath5k_hw_detach(struct ath5k_hw *ah);
1157
1158 /* LED functions */
1159 int ath5k_init_leds(struct ath5k_softc *sc);
1160 void ath5k_led_enable(struct ath5k_softc *sc);
1161 void ath5k_led_off(struct ath5k_softc *sc);
1162 void ath5k_unregister_leds(struct ath5k_softc *sc);
1163
1164 /* Reset Functions */
1165 int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial);
1166 int ath5k_hw_on_hold(struct ath5k_hw *ah);
1167 int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
1168 struct ieee80211_channel *channel, bool change_channel);
1169 int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val,
1170 bool is_set);
1171 /* Power management functions */
1172
1173 /* DMA Related Functions */
1174 void ath5k_hw_start_rx_dma(struct ath5k_hw *ah);
1175 int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah);
1176 u32 ath5k_hw_get_rxdp(struct ath5k_hw *ah);
1177 void ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr);
1178 int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue);
1179 int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue);
1180 u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue);
1181 int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue,
1182 u32 phys_addr);
1183 int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase);
1184 /* Interrupt handling */
1185 bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah);
1186 int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask);
1187 enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask);
1188 void ath5k_hw_update_mib_counters(struct ath5k_hw *ah,
1189 struct ieee80211_low_level_stats *stats);
1190
1191 /* EEPROM access functions */
1192 int ath5k_eeprom_init(struct ath5k_hw *ah);
1193 void ath5k_eeprom_detach(struct ath5k_hw *ah);
1194 int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac);
1195
1196 /* Protocol Control Unit Functions */
1197 extern int ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype opmode);
1198 void ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class);
1199 /* BSSID Functions */
1200 int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac);
1201 void ath5k_hw_set_associd(struct ath5k_hw *ah);
1202 void ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask);
1203 /* Receive start/stop functions */
1204 void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah);
1205 void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah);
1206 /* RX Filter functions */
1207 void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1);
1208 u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah);
1209 void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter);
1210 /* Beacon control functions */
1211 u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah);
1212 void ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64);
1213 void ath5k_hw_reset_tsf(struct ath5k_hw *ah);
1214 void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval);
1215 #if 0
1216 int ath5k_hw_set_beacon_timers(struct ath5k_hw *ah,
1217 const struct ath5k_beacon_state *state);
1218 void ath5k_hw_reset_beacon(struct ath5k_hw *ah);
1219 int ath5k_hw_beaconq_finish(struct ath5k_hw *ah, unsigned long phys_addr);
1220 #endif
1221 /* ACK bit rate */
1222 void ath5k_hw_set_ack_bitrate_high(struct ath5k_hw *ah, bool high);
1223 /* Clock rate related functions */
1224 unsigned int ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec);
1225 unsigned int ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock);
1226 unsigned int ath5k_hw_get_clockrate(struct ath5k_hw *ah);
1227 /* Key table (WEP) functions */
1228 int ath5k_hw_reset_key(struct ath5k_hw *ah, u16 entry);
1229 int ath5k_hw_set_key(struct ath5k_hw *ah, u16 entry,
1230 const struct ieee80211_key_conf *key, const u8 *mac);
1231 int ath5k_hw_set_key_lladdr(struct ath5k_hw *ah, u16 entry, const u8 *mac);
1232
1233 /* Queue Control Unit, DFS Control Unit Functions */
1234 int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue,
1235 struct ath5k_txq_info *queue_info);
1236 int ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, int queue,
1237 const struct ath5k_txq_info *queue_info);
1238 int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah,
1239 enum ath5k_tx_queue queue_type,
1240 struct ath5k_txq_info *queue_info);
1241 u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue);
1242 void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue);
1243 int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue);
1244 int ath5k_hw_set_slot_time(struct ath5k_hw *ah, unsigned int slot_time);
1245
1246 /* Hardware Descriptor Functions */
1247 int ath5k_hw_init_desc_functions(struct ath5k_hw *ah);
1248
1249 /* GPIO Functions */
1250 void ath5k_hw_set_ledstate(struct ath5k_hw *ah, unsigned int state);
1251 int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio);
1252 int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio);
1253 u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio);
1254 int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val);
1255 void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio,
1256 u32 interrupt_level);
1257
1258 /* rfkill Functions */
1259 void ath5k_rfkill_hw_start(struct ath5k_hw *ah);
1260 void ath5k_rfkill_hw_stop(struct ath5k_hw *ah);
1261
1262 /* Misc functions */
1263 int ath5k_hw_set_capabilities(struct ath5k_hw *ah);
1264 int ath5k_hw_get_capability(struct ath5k_hw *ah,
1265 enum ath5k_capability_type cap_type, u32 capability,
1266 u32 *result);
1267 int ath5k_hw_enable_pspoll(struct ath5k_hw *ah, u8 *bssid, u16 assoc_id);
1268 int ath5k_hw_disable_pspoll(struct ath5k_hw *ah);
1269
1270 /* Initial register settings functions */
1271 int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel);
1272
1273 /* Initialize RF */
1274 int ath5k_hw_rfregs_init(struct ath5k_hw *ah,
1275 struct ieee80211_channel *channel,
1276 unsigned int mode);
1277 int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq);
1278 enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah);
1279 int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah);
1280 /* PHY/RF channel functions */
1281 bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags);
1282 int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel *channel);
1283 /* PHY calibration */
1284 void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah);
1285 int ath5k_hw_phy_calibrate(struct ath5k_hw *ah,
1286 struct ieee80211_channel *channel);
1287 void ath5k_hw_calibration_poll(struct ath5k_hw *ah);
1288 /* Spur mitigation */
1289 bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah,
1290 struct ieee80211_channel *channel);
1291 void ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah,
1292 struct ieee80211_channel *channel);
1293 /* Misc PHY functions */
1294 u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan);
1295 int ath5k_hw_phy_disable(struct ath5k_hw *ah);
1296 /* Antenna control */
1297 void ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode);
1298 /* TX power setup */
1299 int ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel,
1300 u8 ee_mode, u8 txpower);
1301 int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower);
1302
1303 /*
1304 * Functions used internaly
1305 */
1306
1307 static inline struct ath_common *ath5k_hw_common(struct ath5k_hw *ah)
1308 {
1309 return &ah->common;
1310 }
1311
1312 static inline struct ath_regulatory *ath5k_hw_regulatory(struct ath5k_hw *ah)
1313 {
1314 return &(ath5k_hw_common(ah)->regulatory);
1315 }
1316
1317 static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
1318 {
1319 return ioread32(ah->ah_iobase + reg);
1320 }
1321
1322 static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
1323 {
1324 iowrite32(val, ah->ah_iobase + reg);
1325 }
1326
1327 static inline u32 ath5k_hw_bitswap(u32 val, unsigned int bits)
1328 {
1329 u32 retval = 0, bit, i;
1330
1331 for (i = 0; i < bits; i++) {
1332 bit = (val >> i) & 1;
1333 retval = (retval << 1) | bit;
1334 }
1335
1336 return retval;
1337 }
1338
1339 #endif
kernel-based virtual machine