1 #include <linux/clocksource.h>
2 #include <linux/clockchips.h>
3 #include <linux/errno.h>
4 #include <linux/hpet.h>
5 #include <linux/init.h>
10 extern struct clock_event_device
*global_clock_event
;
12 #define HPET_MASK CLOCKSOURCE_MASK(32)
15 /* FSEC = 10^-15 NSEC = 10^-9 */
16 #define FSEC_PER_NSEC 1000000
19 * HPET address is set in acpi/boot.c, when an ACPI entry exists
21 unsigned long hpet_address
;
22 static void __iomem
* hpet_virt_address
;
24 static inline unsigned long hpet_readl(unsigned long a
)
26 return readl(hpet_virt_address
+ a
);
29 static inline void hpet_writel(unsigned long d
, unsigned long a
)
31 writel(d
, hpet_virt_address
+ a
);
35 * HPET command line enable / disable
37 static int boot_hpet_disable
;
39 static int __init
hpet_setup(char* str
)
42 if (!strncmp("disable", str
, 7))
43 boot_hpet_disable
= 1;
47 __setup("hpet=", hpet_setup
);
49 static inline int is_hpet_capable(void)
51 return (!boot_hpet_disable
&& hpet_address
);
55 * HPET timer interrupt enable / disable
57 static int hpet_legacy_int_enabled
;
60 * is_hpet_enabled - check whether the hpet timer interrupt is enabled
62 int is_hpet_enabled(void)
64 return is_hpet_capable() && hpet_legacy_int_enabled
;
68 * When the hpet driver (/dev/hpet) is enabled, we need to reserve
69 * timer 0 and timer 1 in case of RTC emulation.
72 static void hpet_reserve_platform_timers(unsigned long id
)
74 struct hpet __iomem
*hpet
= hpet_virt_address
;
75 struct hpet_timer __iomem
*timer
= &hpet
->hpet_timers
[2];
76 unsigned int nrtimers
, i
;
79 nrtimers
= ((id
& HPET_ID_NUMBER
) >> HPET_ID_NUMBER_SHIFT
) + 1;
81 memset(&hd
, 0, sizeof (hd
));
82 hd
.hd_phys_address
= hpet_address
;
83 hd
.hd_address
= hpet_virt_address
;
84 hd
.hd_nirqs
= nrtimers
;
85 hd
.hd_flags
= HPET_DATA_PLATFORM
;
86 hpet_reserve_timer(&hd
, 0);
88 #ifdef CONFIG_HPET_EMULATE_RTC
89 hpet_reserve_timer(&hd
, 1);
92 hd
.hd_irq
[0] = HPET_LEGACY_8254
;
93 hd
.hd_irq
[1] = HPET_LEGACY_RTC
;
95 for (i
= 2; i
< nrtimers
; timer
++, i
++)
96 hd
.hd_irq
[i
] = (timer
->hpet_config
& Tn_INT_ROUTE_CNF_MASK
) >>
97 Tn_INT_ROUTE_CNF_SHIFT
;
103 static void hpet_reserve_platform_timers(unsigned long id
) { }
109 static unsigned long hpet_period
;
111 static void hpet_set_mode(enum clock_event_mode mode
,
112 struct clock_event_device
*evt
);
113 static int hpet_next_event(unsigned long delta
,
114 struct clock_event_device
*evt
);
117 * The hpet clock event device
119 static struct clock_event_device hpet_clockevent
= {
121 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
,
122 .set_mode
= hpet_set_mode
,
123 .set_next_event
= hpet_next_event
,
128 static void hpet_start_counter(void)
130 unsigned long cfg
= hpet_readl(HPET_CFG
);
132 cfg
&= ~HPET_CFG_ENABLE
;
133 hpet_writel(cfg
, HPET_CFG
);
134 hpet_writel(0, HPET_COUNTER
);
135 hpet_writel(0, HPET_COUNTER
+ 4);
136 cfg
|= HPET_CFG_ENABLE
;
137 hpet_writel(cfg
, HPET_CFG
);
140 static void hpet_enable_int(void)
142 unsigned long cfg
= hpet_readl(HPET_CFG
);
144 cfg
|= HPET_CFG_LEGACY
;
145 hpet_writel(cfg
, HPET_CFG
);
146 hpet_legacy_int_enabled
= 1;
149 static void hpet_set_mode(enum clock_event_mode mode
,
150 struct clock_event_device
*evt
)
152 unsigned long cfg
, cmp
, now
;
156 case CLOCK_EVT_MODE_PERIODIC
:
157 delta
= ((uint64_t)(NSEC_PER_SEC
/HZ
)) * hpet_clockevent
.mult
;
158 delta
>>= hpet_clockevent
.shift
;
159 now
= hpet_readl(HPET_COUNTER
);
160 cmp
= now
+ (unsigned long) delta
;
161 cfg
= hpet_readl(HPET_T0_CFG
);
162 cfg
|= HPET_TN_ENABLE
| HPET_TN_PERIODIC
|
163 HPET_TN_SETVAL
| HPET_TN_32BIT
;
164 hpet_writel(cfg
, HPET_T0_CFG
);
166 * The first write after writing TN_SETVAL to the
167 * config register sets the counter value, the second
168 * write sets the period.
170 hpet_writel(cmp
, HPET_T0_CMP
);
172 hpet_writel((unsigned long) delta
, HPET_T0_CMP
);
175 case CLOCK_EVT_MODE_ONESHOT
:
176 cfg
= hpet_readl(HPET_T0_CFG
);
177 cfg
&= ~HPET_TN_PERIODIC
;
178 cfg
|= HPET_TN_ENABLE
| HPET_TN_32BIT
;
179 hpet_writel(cfg
, HPET_T0_CFG
);
182 case CLOCK_EVT_MODE_UNUSED
:
183 case CLOCK_EVT_MODE_SHUTDOWN
:
184 cfg
= hpet_readl(HPET_T0_CFG
);
185 cfg
&= ~HPET_TN_ENABLE
;
186 hpet_writel(cfg
, HPET_T0_CFG
);
191 static int hpet_next_event(unsigned long delta
,
192 struct clock_event_device
*evt
)
196 cnt
= hpet_readl(HPET_COUNTER
);
198 hpet_writel(cnt
, HPET_T0_CMP
);
200 return ((long)(hpet_readl(HPET_COUNTER
) - cnt
) > 0);
204 * Try to setup the HPET timer
206 int __init
hpet_enable(void)
211 if (!is_hpet_capable())
214 hpet_virt_address
= ioremap_nocache(hpet_address
, HPET_MMAP_SIZE
);
217 * Read the period and check for a sane value:
219 hpet_period
= hpet_readl(HPET_PERIOD
);
220 if (hpet_period
< HPET_MIN_PERIOD
|| hpet_period
> HPET_MAX_PERIOD
)
224 * The period is a femto seconds value. We need to calculate the
225 * scaled math multiplication factor for nanosecond to hpet tick
228 hpet_freq
= 1000000000000000ULL;
229 do_div(hpet_freq
, hpet_period
);
230 hpet_clockevent
.mult
= div_sc((unsigned long) hpet_freq
,
232 /* Calculate the min / max delta */
233 hpet_clockevent
.max_delta_ns
= clockevent_delta2ns(0x7FFFFFFF,
235 hpet_clockevent
.min_delta_ns
= clockevent_delta2ns(0x30,
239 * Read the HPET ID register to retrieve the IRQ routing
240 * information and the number of channels
242 id
= hpet_readl(HPET_ID
);
244 #ifdef CONFIG_HPET_EMULATE_RTC
246 * The legacy routing mode needs at least two channels, tick timer
247 * and the rtc emulation channel.
249 if (!(id
& HPET_ID_NUMBER
))
253 /* Start the counter */
254 hpet_start_counter();
256 if (id
& HPET_ID_LEGSUP
) {
258 hpet_reserve_platform_timers(id
);
260 * Start hpet with the boot cpu mask and make it
261 * global after the IO_APIC has been initialized.
263 hpet_clockevent
.cpumask
=cpumask_of_cpu(0);
264 clockevents_register_device(&hpet_clockevent
);
265 global_clock_event
= &hpet_clockevent
;
271 iounmap(hpet_virt_address
);
272 hpet_virt_address
= NULL
;
277 * Clock source related code
279 static cycle_t
read_hpet(void)
281 return (cycle_t
)hpet_readl(HPET_COUNTER
);
284 static struct clocksource clocksource_hpet
= {
290 .flags
= CLOCK_SOURCE_IS_CONTINUOUS
,
293 static int __init
init_hpet_clocksource(void)
297 if (!hpet_virt_address
)
301 * hpet period is in femto seconds per cycle
302 * so we need to convert this to ns/cyc units
303 * aproximated by mult/2^shift
305 * fsec/cyc * 1nsec/1000000fsec = nsec/cyc = mult/2^shift
306 * fsec/cyc * 1ns/1000000fsec * 2^shift = mult
307 * fsec/cyc * 2^shift * 1nsec/1000000fsec = mult
308 * (fsec/cyc << shift)/1000000 = mult
309 * (hpet_period << shift)/FSEC_PER_NSEC = mult
311 tmp
= (u64
)hpet_period
<< HPET_SHIFT
;
312 do_div(tmp
, FSEC_PER_NSEC
);
313 clocksource_hpet
.mult
= (u32
)tmp
;
315 return clocksource_register(&clocksource_hpet
);
318 module_init(init_hpet_clocksource
);
320 #ifdef CONFIG_HPET_EMULATE_RTC
322 /* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
323 * is enabled, we support RTC interrupt functionality in software.
324 * RTC has 3 kinds of interrupts:
325 * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
327 * 2) Alarm Interrupt - generate an interrupt at a specific time of day
328 * 3) Periodic Interrupt - generate periodic interrupt, with frequencies
329 * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
330 * (1) and (2) above are implemented using polling at a frequency of
331 * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
332 * overhead. (DEFAULT_RTC_INT_FREQ)
333 * For (3), we use interrupts at 64Hz or user specified periodic
334 * frequency, whichever is higher.
336 #include <linux/mc146818rtc.h>
337 #include <linux/rtc.h>
339 #define DEFAULT_RTC_INT_FREQ 64
340 #define DEFAULT_RTC_SHIFT 6
341 #define RTC_NUM_INTS 1
343 static unsigned long hpet_rtc_flags
;
344 static unsigned long hpet_prev_update_sec
;
345 static struct rtc_time hpet_alarm_time
;
346 static unsigned long hpet_pie_count
;
347 static unsigned long hpet_t1_cmp
;
348 static unsigned long hpet_default_delta
;
349 static unsigned long hpet_pie_delta
;
350 static unsigned long hpet_pie_limit
;
353 * Timer 1 for RTC emulation. We use one shot mode, as periodic mode
354 * is not supported by all HPET implementations for timer 1.
356 * hpet_rtc_timer_init() is called when the rtc is initialized.
358 int hpet_rtc_timer_init(void)
360 unsigned long cfg
, cnt
, delta
, flags
;
362 if (!is_hpet_enabled())
365 if (!hpet_default_delta
) {
368 clc
= (uint64_t) hpet_clockevent
.mult
* NSEC_PER_SEC
;
369 clc
>>= hpet_clockevent
.shift
+ DEFAULT_RTC_SHIFT
;
370 hpet_default_delta
= (unsigned long) clc
;
373 if (!(hpet_rtc_flags
& RTC_PIE
) || hpet_pie_limit
)
374 delta
= hpet_default_delta
;
376 delta
= hpet_pie_delta
;
378 local_irq_save(flags
);
380 cnt
= delta
+ hpet_readl(HPET_COUNTER
);
381 hpet_writel(cnt
, HPET_T1_CMP
);
384 cfg
= hpet_readl(HPET_T1_CFG
);
385 cfg
&= ~HPET_TN_PERIODIC
;
386 cfg
|= HPET_TN_ENABLE
| HPET_TN_32BIT
;
387 hpet_writel(cfg
, HPET_T1_CFG
);
389 local_irq_restore(flags
);
395 * The functions below are called from rtc driver.
396 * Return 0 if HPET is not being used.
397 * Otherwise do the necessary changes and return 1.
399 int hpet_mask_rtc_irq_bit(unsigned long bit_mask
)
401 if (!is_hpet_enabled())
404 hpet_rtc_flags
&= ~bit_mask
;
408 int hpet_set_rtc_irq_bit(unsigned long bit_mask
)
410 unsigned long oldbits
= hpet_rtc_flags
;
412 if (!is_hpet_enabled())
415 hpet_rtc_flags
|= bit_mask
;
418 hpet_rtc_timer_init();
423 int hpet_set_alarm_time(unsigned char hrs
, unsigned char min
,
426 if (!is_hpet_enabled())
429 hpet_alarm_time
.tm_hour
= hrs
;
430 hpet_alarm_time
.tm_min
= min
;
431 hpet_alarm_time
.tm_sec
= sec
;
436 int hpet_set_periodic_freq(unsigned long freq
)
440 if (!is_hpet_enabled())
443 if (freq
<= DEFAULT_RTC_INT_FREQ
)
444 hpet_pie_limit
= DEFAULT_RTC_INT_FREQ
/ freq
;
446 clc
= (uint64_t) hpet_clockevent
.mult
* NSEC_PER_SEC
;
448 clc
>>= hpet_clockevent
.shift
;
449 hpet_pie_delta
= (unsigned long) clc
;
454 int hpet_rtc_dropped_irq(void)
456 return is_hpet_enabled();
459 static void hpet_rtc_timer_reinit(void)
461 unsigned long cfg
, delta
;
464 if (unlikely(!hpet_rtc_flags
)) {
465 cfg
= hpet_readl(HPET_T1_CFG
);
466 cfg
&= ~HPET_TN_ENABLE
;
467 hpet_writel(cfg
, HPET_T1_CFG
);
471 if (!(hpet_rtc_flags
& RTC_PIE
) || hpet_pie_limit
)
472 delta
= hpet_default_delta
;
474 delta
= hpet_pie_delta
;
477 * Increment the comparator value until we are ahead of the
481 hpet_t1_cmp
+= delta
;
482 hpet_writel(hpet_t1_cmp
, HPET_T1_CMP
);
484 } while ((long)(hpet_readl(HPET_COUNTER
) - hpet_t1_cmp
) > 0);
487 if (hpet_rtc_flags
& RTC_PIE
)
488 hpet_pie_count
+= lost_ints
;
489 if (printk_ratelimit())
490 printk(KERN_WARNING
"rtc: lost %d interrupts\n",
495 irqreturn_t
hpet_rtc_interrupt(int irq
, void *dev_id
)
497 struct rtc_time curr_time
;
498 unsigned long rtc_int_flag
= 0;
500 hpet_rtc_timer_reinit();
502 if (hpet_rtc_flags
& (RTC_UIE
| RTC_AIE
))
503 rtc_get_rtc_time(&curr_time
);
505 if (hpet_rtc_flags
& RTC_UIE
&&
506 curr_time
.tm_sec
!= hpet_prev_update_sec
) {
507 rtc_int_flag
= RTC_UF
;
508 hpet_prev_update_sec
= curr_time
.tm_sec
;
511 if (hpet_rtc_flags
& RTC_PIE
&&
512 ++hpet_pie_count
>= hpet_pie_limit
) {
513 rtc_int_flag
|= RTC_PF
;
517 if (hpet_rtc_flags
& RTC_PIE
&&
518 (curr_time
.tm_sec
== hpet_alarm_time
.tm_sec
) &&
519 (curr_time
.tm_min
== hpet_alarm_time
.tm_min
) &&
520 (curr_time
.tm_hour
== hpet_alarm_time
.tm_hour
))
521 rtc_int_flag
|= RTC_AF
;
524 rtc_int_flag
|= (RTC_IRQF
| (RTC_NUM_INTS
<< 8));
525 rtc_interrupt(rtc_int_flag
, dev_id
);