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cfq-iosched: fix a kbuild regression
[linux-2.6/kvm.git] / drivers / net / 8139cp.c
blob3d4406b1665814b64b31d06e9d29eba20f9b459d
1 /* 8139cp.c: A Linux PCI Ethernet driver for the RealTek 8139C+ chips. */
2 /*
3 Copyright 2001-2004 Jeff Garzik <jgarzik@pobox.com>
4
5 Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com) [tg3.c]
6 Copyright (C) 2000, 2001 David S. Miller (davem@redhat.com) [sungem.c]
7 Copyright 2001 Manfred Spraul [natsemi.c]
8 Copyright 1999-2001 by Donald Becker. [natsemi.c]
9 Written 1997-2001 by Donald Becker. [8139too.c]
10 Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. [acenic.c]
11
12 This software may be used and distributed according to the terms of
13 the GNU General Public License (GPL), incorporated herein by reference.
14 Drivers based on or derived from this code fall under the GPL and must
15 retain the authorship, copyright and license notice. This file is not
16 a complete program and may only be used when the entire operating
17 system is licensed under the GPL.
18
19 See the file COPYING in this distribution for more information.
20
21 Contributors:
22
23 Wake-on-LAN support - Felipe Damasio <felipewd@terra.com.br>
24 PCI suspend/resume - Felipe Damasio <felipewd@terra.com.br>
25 LinkChg interrupt - Felipe Damasio <felipewd@terra.com.br>
26
27 TODO:
28 * Test Tx checksumming thoroughly
29
30 Low priority TODO:
31 * Complete reset on PciErr
32 * Consider Rx interrupt mitigation using TimerIntr
33 * Investigate using skb->priority with h/w VLAN priority
34 * Investigate using High Priority Tx Queue with skb->priority
35 * Adjust Rx FIFO threshold and Max Rx DMA burst on Rx FIFO error
36 * Adjust Tx FIFO threshold and Max Tx DMA burst on Tx FIFO error
37 * Implement Tx software interrupt mitigation via
38 Tx descriptor bit
39 * The real minimum of CP_MIN_MTU is 4 bytes. However,
40 for this to be supported, one must(?) turn on packet padding.
41 * Support external MII transceivers (patch available)
42
43 NOTES:
44 * TX checksumming is considered experimental. It is off by
45 default, use ethtool to turn it on.
46
47 */
48
49 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
50
51 #define DRV_NAME "8139cp"
52 #define DRV_VERSION "1.3"
53 #define DRV_RELDATE "Mar 22, 2004"
54
55
56 #include <linux/module.h>
57 #include <linux/moduleparam.h>
58 #include <linux/kernel.h>
59 #include <linux/compiler.h>
60 #include <linux/netdevice.h>
61 #include <linux/etherdevice.h>
62 #include <linux/init.h>
63 #include <linux/pci.h>
64 #include <linux/dma-mapping.h>
65 #include <linux/delay.h>
66 #include <linux/ethtool.h>
67 #include <linux/mii.h>
68 #include <linux/if_vlan.h>
69 #include <linux/crc32.h>
70 #include <linux/in.h>
71 #include <linux/ip.h>
72 #include <linux/tcp.h>
73 #include <linux/udp.h>
74 #include <linux/cache.h>
75 #include <asm/io.h>
76 #include <asm/irq.h>
77 #include <asm/uaccess.h>
78
79 /* VLAN tagging feature enable/disable */
80 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
81 #define CP_VLAN_TAG_USED 1
82 #define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \
83 do { (tx_desc)->opts2 = cpu_to_le32(vlan_tag_value); } while (0)
84 #else
85 #define CP_VLAN_TAG_USED 0
86 #define CP_VLAN_TX_TAG(tx_desc,vlan_tag_value) \
87 do { (tx_desc)->opts2 = 0; } while (0)
88 #endif
89
90 /* These identify the driver base version and may not be removed. */
91 static char version[] =
92 DRV_NAME ": 10/100 PCI Ethernet driver v" DRV_VERSION " (" DRV_RELDATE ")\n";
93
94 MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>");
95 MODULE_DESCRIPTION("RealTek RTL-8139C+ series 10/100 PCI Ethernet driver");
96 MODULE_VERSION(DRV_VERSION);
97 MODULE_LICENSE("GPL");
98
99 static int debug = -1;
100 module_param(debug, int, 0);
101 MODULE_PARM_DESC (debug, "8139cp: bitmapped message enable number");
102
103 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
104 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
105 static int multicast_filter_limit = 32;
106 module_param(multicast_filter_limit, int, 0);
107 MODULE_PARM_DESC (multicast_filter_limit, "8139cp: maximum number of filtered multicast addresses");
108
109 #define CP_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
110 NETIF_MSG_PROBE | \
111 NETIF_MSG_LINK)
112 #define CP_NUM_STATS 14 /* struct cp_dma_stats, plus one */
113 #define CP_STATS_SIZE 64 /* size in bytes of DMA stats block */
114 #define CP_REGS_SIZE (0xff + 1)
115 #define CP_REGS_VER 1 /* version 1 */
116 #define CP_RX_RING_SIZE 64
117 #define CP_TX_RING_SIZE 64
118 #define CP_RING_BYTES \
119 ((sizeof(struct cp_desc) * CP_RX_RING_SIZE) + \
120 (sizeof(struct cp_desc) * CP_TX_RING_SIZE) + \
121 CP_STATS_SIZE)
122 #define NEXT_TX(N) (((N) + 1) & (CP_TX_RING_SIZE - 1))
123 #define NEXT_RX(N) (((N) + 1) & (CP_RX_RING_SIZE - 1))
124 #define TX_BUFFS_AVAIL(CP) \
125 (((CP)->tx_tail <= (CP)->tx_head) ? \
126 (CP)->tx_tail + (CP_TX_RING_SIZE - 1) - (CP)->tx_head : \
127 (CP)->tx_tail - (CP)->tx_head - 1)
128
129 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
130 #define CP_INTERNAL_PHY 32
131
132 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
133 #define RX_FIFO_THRESH 5 /* Rx buffer level before first PCI xfer. */
134 #define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 */
135 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
136 #define TX_EARLY_THRESH 256 /* Early Tx threshold, in bytes */
137
138 /* Time in jiffies before concluding the transmitter is hung. */
139 #define TX_TIMEOUT (6*HZ)
140
141 /* hardware minimum and maximum for a single frame's data payload */
142 #define CP_MIN_MTU 60 /* TODO: allow lower, but pad */
143 #define CP_MAX_MTU 4096
144
145 enum {
146 /* NIC register offsets */
147 MAC0 = 0x00, /* Ethernet hardware address. */
148 MAR0 = 0x08, /* Multicast filter. */
149 StatsAddr = 0x10, /* 64-bit start addr of 64-byte DMA stats blk */
150 TxRingAddr = 0x20, /* 64-bit start addr of Tx ring */
151 HiTxRingAddr = 0x28, /* 64-bit start addr of high priority Tx ring */
152 Cmd = 0x37, /* Command register */
153 IntrMask = 0x3C, /* Interrupt mask */
154 IntrStatus = 0x3E, /* Interrupt status */
155 TxConfig = 0x40, /* Tx configuration */
156 ChipVersion = 0x43, /* 8-bit chip version, inside TxConfig */
157 RxConfig = 0x44, /* Rx configuration */
158 RxMissed = 0x4C, /* 24 bits valid, write clears */
159 Cfg9346 = 0x50, /* EEPROM select/control; Cfg reg [un]lock */
160 Config1 = 0x52, /* Config1 */
161 Config3 = 0x59, /* Config3 */
162 Config4 = 0x5A, /* Config4 */
163 MultiIntr = 0x5C, /* Multiple interrupt select */
164 BasicModeCtrl = 0x62, /* MII BMCR */
165 BasicModeStatus = 0x64, /* MII BMSR */
166 NWayAdvert = 0x66, /* MII ADVERTISE */
167 NWayLPAR = 0x68, /* MII LPA */
168 NWayExpansion = 0x6A, /* MII Expansion */
169 Config5 = 0xD8, /* Config5 */
170 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
171 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
172 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
173 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
174 RxRingAddr = 0xE4, /* 64-bit start addr of Rx ring */
175 TxThresh = 0xEC, /* Early Tx threshold */
176 OldRxBufAddr = 0x30, /* DMA address of Rx ring buffer (C mode) */
177 OldTSD0 = 0x10, /* DMA address of first Tx desc (C mode) */
178
179 /* Tx and Rx status descriptors */
180 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
181 RingEnd = (1 << 30), /* End of descriptor ring */
182 FirstFrag = (1 << 29), /* First segment of a packet */
183 LastFrag = (1 << 28), /* Final segment of a packet */
184 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
185 MSSShift = 16, /* MSS value position */
186 MSSMask = 0xfff, /* MSS value: 11 bits */
187 TxError = (1 << 23), /* Tx error summary */
188 RxError = (1 << 20), /* Rx error summary */
189 IPCS = (1 << 18), /* Calculate IP checksum */
190 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
191 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
192 TxVlanTag = (1 << 17), /* Add VLAN tag */
193 RxVlanTagged = (1 << 16), /* Rx VLAN tag available */
194 IPFail = (1 << 15), /* IP checksum failed */
195 UDPFail = (1 << 14), /* UDP/IP checksum failed */
196 TCPFail = (1 << 13), /* TCP/IP checksum failed */
197 NormalTxPoll = (1 << 6), /* One or more normal Tx packets to send */
198 PID1 = (1 << 17), /* 2 protocol id bits: 0==non-IP, */
199 PID0 = (1 << 16), /* 1==UDP/IP, 2==TCP/IP, 3==IP */
200 RxProtoTCP = 1,
201 RxProtoUDP = 2,
202 RxProtoIP = 3,
203 TxFIFOUnder = (1 << 25), /* Tx FIFO underrun */
204 TxOWC = (1 << 22), /* Tx Out-of-window collision */
205 TxLinkFail = (1 << 21), /* Link failed during Tx of packet */
206 TxMaxCol = (1 << 20), /* Tx aborted due to excessive collisions */
207 TxColCntShift = 16, /* Shift, to get 4-bit Tx collision cnt */
208 TxColCntMask = 0x01 | 0x02 | 0x04 | 0x08, /* 4-bit collision count */
209 RxErrFrame = (1 << 27), /* Rx frame alignment error */
210 RxMcast = (1 << 26), /* Rx multicast packet rcv'd */
211 RxErrCRC = (1 << 18), /* Rx CRC error */
212 RxErrRunt = (1 << 19), /* Rx error, packet < 64 bytes */
213 RxErrLong = (1 << 21), /* Rx error, packet > 4096 bytes */
214 RxErrFIFO = (1 << 22), /* Rx error, FIFO overflowed, pkt bad */
215
216 /* StatsAddr register */
217 DumpStats = (1 << 3), /* Begin stats dump */
218
219 /* RxConfig register */
220 RxCfgFIFOShift = 13, /* Shift, to get Rx FIFO thresh value */
221 RxCfgDMAShift = 8, /* Shift, to get Rx Max DMA value */
222 AcceptErr = 0x20, /* Accept packets with CRC errors */
223 AcceptRunt = 0x10, /* Accept runt (<64 bytes) packets */
224 AcceptBroadcast = 0x08, /* Accept broadcast packets */
225 AcceptMulticast = 0x04, /* Accept multicast packets */
226 AcceptMyPhys = 0x02, /* Accept pkts with our MAC as dest */
227 AcceptAllPhys = 0x01, /* Accept all pkts w/ physical dest */
228
229 /* IntrMask / IntrStatus registers */
230 PciErr = (1 << 15), /* System error on the PCI bus */
231 TimerIntr = (1 << 14), /* Asserted when TCTR reaches TimerInt value */
232 LenChg = (1 << 13), /* Cable length change */
233 SWInt = (1 << 8), /* Software-requested interrupt */
234 TxEmpty = (1 << 7), /* No Tx descriptors available */
235 RxFIFOOvr = (1 << 6), /* Rx FIFO Overflow */
236 LinkChg = (1 << 5), /* Packet underrun, or link change */
237 RxEmpty = (1 << 4), /* No Rx descriptors available */
238 TxErr = (1 << 3), /* Tx error */
239 TxOK = (1 << 2), /* Tx packet sent */
240 RxErr = (1 << 1), /* Rx error */
241 RxOK = (1 << 0), /* Rx packet received */
242 IntrResvd = (1 << 10), /* reserved, according to RealTek engineers,
243 but hardware likes to raise it */
244
245 IntrAll = PciErr | TimerIntr | LenChg | SWInt | TxEmpty |
246 RxFIFOOvr | LinkChg | RxEmpty | TxErr | TxOK |
247 RxErr | RxOK | IntrResvd,
248
249 /* C mode command register */
250 CmdReset = (1 << 4), /* Enable to reset; self-clearing */
251 RxOn = (1 << 3), /* Rx mode enable */
252 TxOn = (1 << 2), /* Tx mode enable */
253
254 /* C+ mode command register */
255 RxVlanOn = (1 << 6), /* Rx VLAN de-tagging enable */
256 RxChkSum = (1 << 5), /* Rx checksum offload enable */
257 PCIDAC = (1 << 4), /* PCI Dual Address Cycle (64-bit PCI) */
258 PCIMulRW = (1 << 3), /* Enable PCI read/write multiple */
259 CpRxOn = (1 << 1), /* Rx mode enable */
260 CpTxOn = (1 << 0), /* Tx mode enable */
261
262 /* Cfg9436 EEPROM control register */
263 Cfg9346_Lock = 0x00, /* Lock ConfigX/MII register access */
264 Cfg9346_Unlock = 0xC0, /* Unlock ConfigX/MII register access */
265
266 /* TxConfig register */
267 IFG = (1 << 25) | (1 << 24), /* standard IEEE interframe gap */
268 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
269
270 /* Early Tx Threshold register */
271 TxThreshMask = 0x3f, /* Mask bits 5-0 */
272 TxThreshMax = 2048, /* Max early Tx threshold */
273
274 /* Config1 register */
275 DriverLoaded = (1 << 5), /* Software marker, driver is loaded */
276 LWACT = (1 << 4), /* LWAKE active mode */
277 PMEnable = (1 << 0), /* Enable various PM features of chip */
278
279 /* Config3 register */
280 PARMEnable = (1 << 6), /* Enable auto-loading of PHY parms */
281 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
282 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
283
284 /* Config4 register */
285 LWPTN = (1 << 1), /* LWAKE Pattern */
286 LWPME = (1 << 4), /* LANWAKE vs PMEB */
287
288 /* Config5 register */
289 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
290 MWF = (1 << 5), /* Accept Multicast wakeup frame */
291 UWF = (1 << 4), /* Accept Unicast wakeup frame */
292 LANWake = (1 << 1), /* Enable LANWake signal */
293 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
294
295 cp_norx_intr_mask = PciErr | LinkChg | TxOK | TxErr | TxEmpty,
296 cp_rx_intr_mask = RxOK | RxErr | RxEmpty | RxFIFOOvr,
297 cp_intr_mask = cp_rx_intr_mask | cp_norx_intr_mask,
298 };
299
300 static const unsigned int cp_rx_config =
301 (RX_FIFO_THRESH << RxCfgFIFOShift) |
302 (RX_DMA_BURST << RxCfgDMAShift);
303
304 struct cp_desc {
305 __le32 opts1;
306 __le32 opts2;
307 __le64 addr;
308 };
309
310 struct cp_dma_stats {
311 __le64 tx_ok;
312 __le64 rx_ok;
313 __le64 tx_err;
314 __le32 rx_err;
315 __le16 rx_fifo;
316 __le16 frame_align;
317 __le32 tx_ok_1col;
318 __le32 tx_ok_mcol;
319 __le64 rx_ok_phys;
320 __le64 rx_ok_bcast;
321 __le32 rx_ok_mcast;
322 __le16 tx_abort;
323 __le16 tx_underrun;
324 } __attribute__((packed));
325
326 struct cp_extra_stats {
327 unsigned long rx_frags;
328 };
329
330 struct cp_private {
331 void __iomem *regs;
332 struct net_device *dev;
333 spinlock_t lock;
334 u32 msg_enable;
335
336 struct napi_struct napi;
337
338 struct pci_dev *pdev;
339 u32 rx_config;
340 u16 cpcmd;
341
342 struct cp_extra_stats cp_stats;
343
344 unsigned rx_head ____cacheline_aligned;
345 unsigned rx_tail;
346 struct cp_desc *rx_ring;
347 struct sk_buff *rx_skb[CP_RX_RING_SIZE];
348
349 unsigned tx_head ____cacheline_aligned;
350 unsigned tx_tail;
351 struct cp_desc *tx_ring;
352 struct sk_buff *tx_skb[CP_TX_RING_SIZE];
353
354 unsigned rx_buf_sz;
355 unsigned wol_enabled : 1; /* Is Wake-on-LAN enabled? */
356
357 #if CP_VLAN_TAG_USED
358 struct vlan_group *vlgrp;
359 #endif
360 dma_addr_t ring_dma;
361
362 struct mii_if_info mii_if;
363 };
364
365 #define cpr8(reg) readb(cp->regs + (reg))
366 #define cpr16(reg) readw(cp->regs + (reg))
367 #define cpr32(reg) readl(cp->regs + (reg))
368 #define cpw8(reg,val) writeb((val), cp->regs + (reg))
369 #define cpw16(reg,val) writew((val), cp->regs + (reg))
370 #define cpw32(reg,val) writel((val), cp->regs + (reg))
371 #define cpw8_f(reg,val) do { \
372 writeb((val), cp->regs + (reg)); \
373 readb(cp->regs + (reg)); \
374 } while (0)
375 #define cpw16_f(reg,val) do { \
376 writew((val), cp->regs + (reg)); \
377 readw(cp->regs + (reg)); \
378 } while (0)
379 #define cpw32_f(reg,val) do { \
380 writel((val), cp->regs + (reg)); \
381 readl(cp->regs + (reg)); \
382 } while (0)
383
384
385 static void __cp_set_rx_mode (struct net_device *dev);
386 static void cp_tx (struct cp_private *cp);
387 static void cp_clean_rings (struct cp_private *cp);
388 #ifdef CONFIG_NET_POLL_CONTROLLER
389 static void cp_poll_controller(struct net_device *dev);
390 #endif
391 static int cp_get_eeprom_len(struct net_device *dev);
392 static int cp_get_eeprom(struct net_device *dev,
393 struct ethtool_eeprom *eeprom, u8 *data);
394 static int cp_set_eeprom(struct net_device *dev,
395 struct ethtool_eeprom *eeprom, u8 *data);
396
397 static DEFINE_PCI_DEVICE_TABLE(cp_pci_tbl) = {
398 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139), },
399 { PCI_DEVICE(PCI_VENDOR_ID_TTTECH, PCI_DEVICE_ID_TTTECH_MC322), },
400 { },
401 };
402 MODULE_DEVICE_TABLE(pci, cp_pci_tbl);
403
404 static struct {
405 const char str[ETH_GSTRING_LEN];
406 } ethtool_stats_keys[] = {
407 { "tx_ok" },
408 { "rx_ok" },
409 { "tx_err" },
410 { "rx_err" },
411 { "rx_fifo" },
412 { "frame_align" },
413 { "tx_ok_1col" },
414 { "tx_ok_mcol" },
415 { "rx_ok_phys" },
416 { "rx_ok_bcast" },
417 { "rx_ok_mcast" },
418 { "tx_abort" },
419 { "tx_underrun" },
420 { "rx_frags" },
421 };
422
423
424 #if CP_VLAN_TAG_USED
425 static void cp_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
426 {
427 struct cp_private *cp = netdev_priv(dev);
428 unsigned long flags;
429
430 spin_lock_irqsave(&cp->lock, flags);
431 cp->vlgrp = grp;
432 if (grp)
433 cp->cpcmd |= RxVlanOn;
434 else
435 cp->cpcmd &= ~RxVlanOn;
436
437 cpw16(CpCmd, cp->cpcmd);
438 spin_unlock_irqrestore(&cp->lock, flags);
439 }
440 #endif /* CP_VLAN_TAG_USED */
441
442 static inline void cp_set_rxbufsize (struct cp_private *cp)
443 {
444 unsigned int mtu = cp->dev->mtu;
445
446 if (mtu > ETH_DATA_LEN)
447 /* MTU + ethernet header + FCS + optional VLAN tag */
448 cp->rx_buf_sz = mtu + ETH_HLEN + 8;
449 else
450 cp->rx_buf_sz = PKT_BUF_SZ;
451 }
452
453 static inline void cp_rx_skb (struct cp_private *cp, struct sk_buff *skb,
454 struct cp_desc *desc)
455 {
456 skb->protocol = eth_type_trans (skb, cp->dev);
457
458 cp->dev->stats.rx_packets++;
459 cp->dev->stats.rx_bytes += skb->len;
460
461 #if CP_VLAN_TAG_USED
462 if (cp->vlgrp && (desc->opts2 & cpu_to_le32(RxVlanTagged))) {
463 vlan_hwaccel_receive_skb(skb, cp->vlgrp,
464 swab16(le32_to_cpu(desc->opts2) & 0xffff));
465 } else
466 #endif
467 netif_receive_skb(skb);
468 }
469
470 static void cp_rx_err_acct (struct cp_private *cp, unsigned rx_tail,
471 u32 status, u32 len)
472 {
473 netif_dbg(cp, rx_err, cp->dev, "rx err, slot %d status 0x%x len %d\n",
474 rx_tail, status, len);
475 cp->dev->stats.rx_errors++;
476 if (status & RxErrFrame)
477 cp->dev->stats.rx_frame_errors++;
478 if (status & RxErrCRC)
479 cp->dev->stats.rx_crc_errors++;
480 if ((status & RxErrRunt) || (status & RxErrLong))
481 cp->dev->stats.rx_length_errors++;
482 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag))
483 cp->dev->stats.rx_length_errors++;
484 if (status & RxErrFIFO)
485 cp->dev->stats.rx_fifo_errors++;
486 }
487
488 static inline unsigned int cp_rx_csum_ok (u32 status)
489 {
490 unsigned int protocol = (status >> 16) & 0x3;
491
492 if (likely((protocol == RxProtoTCP) && (!(status & TCPFail))))
493 return 1;
494 else if ((protocol == RxProtoUDP) && (!(status & UDPFail)))
495 return 1;
496 else if ((protocol == RxProtoIP) && (!(status & IPFail)))
497 return 1;
498 return 0;
499 }
500
501 static int cp_rx_poll(struct napi_struct *napi, int budget)
502 {
503 struct cp_private *cp = container_of(napi, struct cp_private, napi);
504 struct net_device *dev = cp->dev;
505 unsigned int rx_tail = cp->rx_tail;
506 int rx;
507
508 rx_status_loop:
509 rx = 0;
510 cpw16(IntrStatus, cp_rx_intr_mask);
511
512 while (1) {
513 u32 status, len;
514 dma_addr_t mapping;
515 struct sk_buff *skb, *new_skb;
516 struct cp_desc *desc;
517 const unsigned buflen = cp->rx_buf_sz;
518
519 skb = cp->rx_skb[rx_tail];
520 BUG_ON(!skb);
521
522 desc = &cp->rx_ring[rx_tail];
523 status = le32_to_cpu(desc->opts1);
524 if (status & DescOwn)
525 break;
526
527 len = (status & 0x1fff) - 4;
528 mapping = le64_to_cpu(desc->addr);
529
530 if ((status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag)) {
531 /* we don't support incoming fragmented frames.
532 * instead, we attempt to ensure that the
533 * pre-allocated RX skbs are properly sized such
534 * that RX fragments are never encountered
535 */
536 cp_rx_err_acct(cp, rx_tail, status, len);
537 dev->stats.rx_dropped++;
538 cp->cp_stats.rx_frags++;
539 goto rx_next;
540 }
541
542 if (status & (RxError | RxErrFIFO)) {
543 cp_rx_err_acct(cp, rx_tail, status, len);
544 goto rx_next;
545 }
546
547 netif_dbg(cp, rx_status, dev, "rx slot %d status 0x%x len %d\n",
548 rx_tail, status, len);
549
550 new_skb = netdev_alloc_skb_ip_align(dev, buflen);
551 if (!new_skb) {
552 dev->stats.rx_dropped++;
553 goto rx_next;
554 }
555
556 dma_unmap_single(&cp->pdev->dev, mapping,
557 buflen, PCI_DMA_FROMDEVICE);
558
559 /* Handle checksum offloading for incoming packets. */
560 if (cp_rx_csum_ok(status))
561 skb->ip_summed = CHECKSUM_UNNECESSARY;
562 else
563 skb->ip_summed = CHECKSUM_NONE;
564
565 skb_put(skb, len);
566
567 mapping = dma_map_single(&cp->pdev->dev, new_skb->data, buflen,
568 PCI_DMA_FROMDEVICE);
569 cp->rx_skb[rx_tail] = new_skb;
570
571 cp_rx_skb(cp, skb, desc);
572 rx++;
573
574 rx_next:
575 cp->rx_ring[rx_tail].opts2 = 0;
576 cp->rx_ring[rx_tail].addr = cpu_to_le64(mapping);
577 if (rx_tail == (CP_RX_RING_SIZE - 1))
578 desc->opts1 = cpu_to_le32(DescOwn | RingEnd |
579 cp->rx_buf_sz);
580 else
581 desc->opts1 = cpu_to_le32(DescOwn | cp->rx_buf_sz);
582 rx_tail = NEXT_RX(rx_tail);
583
584 if (rx >= budget)
585 break;
586 }
587
588 cp->rx_tail = rx_tail;
589
590 /* if we did not reach work limit, then we're done with
591 * this round of polling
592 */
593 if (rx < budget) {
594 unsigned long flags;
595
596 if (cpr16(IntrStatus) & cp_rx_intr_mask)
597 goto rx_status_loop;
598
599 spin_lock_irqsave(&cp->lock, flags);
600 cpw16_f(IntrMask, cp_intr_mask);
601 __napi_complete(napi);
602 spin_unlock_irqrestore(&cp->lock, flags);
603 }
604
605 return rx;
606 }
607
608 static irqreturn_t cp_interrupt (int irq, void *dev_instance)
609 {
610 struct net_device *dev = dev_instance;
611 struct cp_private *cp;
612 u16 status;
613
614 if (unlikely(dev == NULL))
615 return IRQ_NONE;
616 cp = netdev_priv(dev);
617
618 status = cpr16(IntrStatus);
619 if (!status || (status == 0xFFFF))
620 return IRQ_NONE;
621
622 netif_dbg(cp, intr, dev, "intr, status %04x cmd %02x cpcmd %04x\n",
623 status, cpr8(Cmd), cpr16(CpCmd));
624
625 cpw16(IntrStatus, status & ~cp_rx_intr_mask);
626
627 spin_lock(&cp->lock);
628
629 /* close possible race's with dev_close */
630 if (unlikely(!netif_running(dev))) {
631 cpw16(IntrMask, 0);
632 spin_unlock(&cp->lock);
633 return IRQ_HANDLED;
634 }
635
636 if (status & (RxOK | RxErr | RxEmpty | RxFIFOOvr))
637 if (napi_schedule_prep(&cp->napi)) {
638 cpw16_f(IntrMask, cp_norx_intr_mask);
639 __napi_schedule(&cp->napi);
640 }
641
642 if (status & (TxOK | TxErr | TxEmpty | SWInt))
643 cp_tx(cp);
644 if (status & LinkChg)
645 mii_check_media(&cp->mii_if, netif_msg_link(cp), false);
646
647 spin_unlock(&cp->lock);
648
649 if (status & PciErr) {
650 u16 pci_status;
651
652 pci_read_config_word(cp->pdev, PCI_STATUS, &pci_status);
653 pci_write_config_word(cp->pdev, PCI_STATUS, pci_status);
654 netdev_err(dev, "PCI bus error, status=%04x, PCI status=%04x\n",
655 status, pci_status);
656
657 /* TODO: reset hardware */
658 }
659
660 return IRQ_HANDLED;
661 }
662
663 #ifdef CONFIG_NET_POLL_CONTROLLER
664 /*
665 * Polling receive - used by netconsole and other diagnostic tools
666 * to allow network i/o with interrupts disabled.
667 */
668 static void cp_poll_controller(struct net_device *dev)
669 {
670 disable_irq(dev->irq);
671 cp_interrupt(dev->irq, dev);
672 enable_irq(dev->irq);
673 }
674 #endif
675
676 static void cp_tx (struct cp_private *cp)
677 {
678 unsigned tx_head = cp->tx_head;
679 unsigned tx_tail = cp->tx_tail;
680
681 while (tx_tail != tx_head) {
682 struct cp_desc *txd = cp->tx_ring + tx_tail;
683 struct sk_buff *skb;
684 u32 status;
685
686 rmb();
687 status = le32_to_cpu(txd->opts1);
688 if (status & DescOwn)
689 break;
690
691 skb = cp->tx_skb[tx_tail];
692 BUG_ON(!skb);
693
694 dma_unmap_single(&cp->pdev->dev, le64_to_cpu(txd->addr),
695 le32_to_cpu(txd->opts1) & 0xffff,
696 PCI_DMA_TODEVICE);
697
698 if (status & LastFrag) {
699 if (status & (TxError | TxFIFOUnder)) {
700 netif_dbg(cp, tx_err, cp->dev,
701 "tx err, status 0x%x\n", status);
702 cp->dev->stats.tx_errors++;
703 if (status & TxOWC)
704 cp->dev->stats.tx_window_errors++;
705 if (status & TxMaxCol)
706 cp->dev->stats.tx_aborted_errors++;
707 if (status & TxLinkFail)
708 cp->dev->stats.tx_carrier_errors++;
709 if (status & TxFIFOUnder)
710 cp->dev->stats.tx_fifo_errors++;
711 } else {
712 cp->dev->stats.collisions +=
713 ((status >> TxColCntShift) & TxColCntMask);
714 cp->dev->stats.tx_packets++;
715 cp->dev->stats.tx_bytes += skb->len;
716 netif_dbg(cp, tx_done, cp->dev,
717 "tx done, slot %d\n", tx_tail);
718 }
719 dev_kfree_skb_irq(skb);
720 }
721
722 cp->tx_skb[tx_tail] = NULL;
723
724 tx_tail = NEXT_TX(tx_tail);
725 }
726
727 cp->tx_tail = tx_tail;
728
729 if (TX_BUFFS_AVAIL(cp) > (MAX_SKB_FRAGS + 1))
730 netif_wake_queue(cp->dev);
731 }
732
733 static netdev_tx_t cp_start_xmit (struct sk_buff *skb,
734 struct net_device *dev)
735 {
736 struct cp_private *cp = netdev_priv(dev);
737 unsigned entry;
738 u32 eor, flags;
739 unsigned long intr_flags;
740 #if CP_VLAN_TAG_USED
741 u32 vlan_tag = 0;
742 #endif
743 int mss = 0;
744
745 spin_lock_irqsave(&cp->lock, intr_flags);
746
747 /* This is a hard error, log it. */
748 if (TX_BUFFS_AVAIL(cp) <= (skb_shinfo(skb)->nr_frags + 1)) {
749 netif_stop_queue(dev);
750 spin_unlock_irqrestore(&cp->lock, intr_flags);
751 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
752 return NETDEV_TX_BUSY;
753 }
754
755 #if CP_VLAN_TAG_USED
756 if (cp->vlgrp && vlan_tx_tag_present(skb))
757 vlan_tag = TxVlanTag | swab16(vlan_tx_tag_get(skb));
758 #endif
759
760 entry = cp->tx_head;
761 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
762 if (dev->features & NETIF_F_TSO)
763 mss = skb_shinfo(skb)->gso_size;
764
765 if (skb_shinfo(skb)->nr_frags == 0) {
766 struct cp_desc *txd = &cp->tx_ring[entry];
767 u32 len;
768 dma_addr_t mapping;
769
770 len = skb->len;
771 mapping = dma_map_single(&cp->pdev->dev, skb->data, len, PCI_DMA_TODEVICE);
772 CP_VLAN_TX_TAG(txd, vlan_tag);
773 txd->addr = cpu_to_le64(mapping);
774 wmb();
775
776 flags = eor | len | DescOwn | FirstFrag | LastFrag;
777
778 if (mss)
779 flags |= LargeSend | ((mss & MSSMask) << MSSShift);
780 else if (skb->ip_summed == CHECKSUM_PARTIAL) {
781 const struct iphdr *ip = ip_hdr(skb);
782 if (ip->protocol == IPPROTO_TCP)
783 flags |= IPCS | TCPCS;
784 else if (ip->protocol == IPPROTO_UDP)
785 flags |= IPCS | UDPCS;
786 else
787 WARN_ON(1); /* we need a WARN() */
788 }
789
790 txd->opts1 = cpu_to_le32(flags);
791 wmb();
792
793 cp->tx_skb[entry] = skb;
794 entry = NEXT_TX(entry);
795 } else {
796 struct cp_desc *txd;
797 u32 first_len, first_eor;
798 dma_addr_t first_mapping;
799 int frag, first_entry = entry;
800 const struct iphdr *ip = ip_hdr(skb);
801
802 /* We must give this initial chunk to the device last.
803 * Otherwise we could race with the device.
804 */
805 first_eor = eor;
806 first_len = skb_headlen(skb);
807 first_mapping = dma_map_single(&cp->pdev->dev, skb->data,
808 first_len, PCI_DMA_TODEVICE);
809 cp->tx_skb[entry] = skb;
810 entry = NEXT_TX(entry);
811
812 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
813 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
814 u32 len;
815 u32 ctrl;
816 dma_addr_t mapping;
817
818 len = this_frag->size;
819 mapping = dma_map_single(&cp->pdev->dev,
820 ((void *) page_address(this_frag->page) +
821 this_frag->page_offset),
822 len, PCI_DMA_TODEVICE);
823 eor = (entry == (CP_TX_RING_SIZE - 1)) ? RingEnd : 0;
824
825 ctrl = eor | len | DescOwn;
826
827 if (mss)
828 ctrl |= LargeSend |
829 ((mss & MSSMask) << MSSShift);
830 else if (skb->ip_summed == CHECKSUM_PARTIAL) {
831 if (ip->protocol == IPPROTO_TCP)
832 ctrl |= IPCS | TCPCS;
833 else if (ip->protocol == IPPROTO_UDP)
834 ctrl |= IPCS | UDPCS;
835 else
836 BUG();
837 }
838
839 if (frag == skb_shinfo(skb)->nr_frags - 1)
840 ctrl |= LastFrag;
841
842 txd = &cp->tx_ring[entry];
843 CP_VLAN_TX_TAG(txd, vlan_tag);
844 txd->addr = cpu_to_le64(mapping);
845 wmb();
846
847 txd->opts1 = cpu_to_le32(ctrl);
848 wmb();
849
850 cp->tx_skb[entry] = skb;
851 entry = NEXT_TX(entry);
852 }
853
854 txd = &cp->tx_ring[first_entry];
855 CP_VLAN_TX_TAG(txd, vlan_tag);
856 txd->addr = cpu_to_le64(first_mapping);
857 wmb();
858
859 if (skb->ip_summed == CHECKSUM_PARTIAL) {
860 if (ip->protocol == IPPROTO_TCP)
861 txd->opts1 = cpu_to_le32(first_eor | first_len |
862 FirstFrag | DescOwn |
863 IPCS | TCPCS);
864 else if (ip->protocol == IPPROTO_UDP)
865 txd->opts1 = cpu_to_le32(first_eor | first_len |
866 FirstFrag | DescOwn |
867 IPCS | UDPCS);
868 else
869 BUG();
870 } else
871 txd->opts1 = cpu_to_le32(first_eor | first_len |
872 FirstFrag | DescOwn);
873 wmb();
874 }
875 cp->tx_head = entry;
876 netif_dbg(cp, tx_queued, cp->dev, "tx queued, slot %d, skblen %d\n",
877 entry, skb->len);
878 if (TX_BUFFS_AVAIL(cp) <= (MAX_SKB_FRAGS + 1))
879 netif_stop_queue(dev);
880
881 spin_unlock_irqrestore(&cp->lock, intr_flags);
882
883 cpw8(TxPoll, NormalTxPoll);
884 dev->trans_start = jiffies;
885
886 return NETDEV_TX_OK;
887 }
888
889 /* Set or clear the multicast filter for this adaptor.
890 This routine is not state sensitive and need not be SMP locked. */
891
892 static void __cp_set_rx_mode (struct net_device *dev)
893 {
894 struct cp_private *cp = netdev_priv(dev);
895 u32 mc_filter[2]; /* Multicast hash filter */
896 int rx_mode;
897 u32 tmp;
898
899 /* Note: do not reorder, GCC is clever about common statements. */
900 if (dev->flags & IFF_PROMISC) {
901 /* Unconditionally log net taps. */
902 rx_mode =
903 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
904 AcceptAllPhys;
905 mc_filter[1] = mc_filter[0] = 0xffffffff;
906 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
907 (dev->flags & IFF_ALLMULTI)) {
908 /* Too many to filter perfectly -- accept all multicasts. */
909 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
910 mc_filter[1] = mc_filter[0] = 0xffffffff;
911 } else {
912 struct dev_mc_list *mclist;
913 rx_mode = AcceptBroadcast | AcceptMyPhys;
914 mc_filter[1] = mc_filter[0] = 0;
915 netdev_for_each_mc_addr(mclist, dev) {
916 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
917
918 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
919 rx_mode |= AcceptMulticast;
920 }
921 }
922
923 /* We can safely update without stopping the chip. */
924 tmp = cp_rx_config | rx_mode;
925 if (cp->rx_config != tmp) {
926 cpw32_f (RxConfig, tmp);
927 cp->rx_config = tmp;
928 }
929 cpw32_f (MAR0 + 0, mc_filter[0]);
930 cpw32_f (MAR0 + 4, mc_filter[1]);
931 }
932
933 static void cp_set_rx_mode (struct net_device *dev)
934 {
935 unsigned long flags;
936 struct cp_private *cp = netdev_priv(dev);
937
938 spin_lock_irqsave (&cp->lock, flags);
939 __cp_set_rx_mode(dev);
940 spin_unlock_irqrestore (&cp->lock, flags);
941 }
942
943 static void __cp_get_stats(struct cp_private *cp)
944 {
945 /* only lower 24 bits valid; write any value to clear */
946 cp->dev->stats.rx_missed_errors += (cpr32 (RxMissed) & 0xffffff);
947 cpw32 (RxMissed, 0);
948 }
949
950 static struct net_device_stats *cp_get_stats(struct net_device *dev)
951 {
952 struct cp_private *cp = netdev_priv(dev);
953 unsigned long flags;
954
955 /* The chip only need report frame silently dropped. */
956 spin_lock_irqsave(&cp->lock, flags);
957 if (netif_running(dev) && netif_device_present(dev))
958 __cp_get_stats(cp);
959 spin_unlock_irqrestore(&cp->lock, flags);
960
961 return &dev->stats;
962 }
963
964 static void cp_stop_hw (struct cp_private *cp)
965 {
966 cpw16(IntrStatus, ~(cpr16(IntrStatus)));
967 cpw16_f(IntrMask, 0);
968 cpw8(Cmd, 0);
969 cpw16_f(CpCmd, 0);
970 cpw16_f(IntrStatus, ~(cpr16(IntrStatus)));
971
972 cp->rx_tail = 0;
973 cp->tx_head = cp->tx_tail = 0;
974 }
975
976 static void cp_reset_hw (struct cp_private *cp)
977 {
978 unsigned work = 1000;
979
980 cpw8(Cmd, CmdReset);
981
982 while (work--) {
983 if (!(cpr8(Cmd) & CmdReset))
984 return;
985
986 schedule_timeout_uninterruptible(10);
987 }
988
989 netdev_err(cp->dev, "hardware reset timeout\n");
990 }
991
992 static inline void cp_start_hw (struct cp_private *cp)
993 {
994 cpw16(CpCmd, cp->cpcmd);
995 cpw8(Cmd, RxOn | TxOn);
996 }
997
998 static void cp_init_hw (struct cp_private *cp)
999 {
1000 struct net_device *dev = cp->dev;
1001 dma_addr_t ring_dma;
1002
1003 cp_reset_hw(cp);
1004
1005 cpw8_f (Cfg9346, Cfg9346_Unlock);
1006
1007 /* Restore our idea of the MAC address. */
1008 cpw32_f (MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0)));
1009 cpw32_f (MAC0 + 4, le32_to_cpu (*(__le32 *) (dev->dev_addr + 4)));
1010
1011 cp_start_hw(cp);
1012 cpw8(TxThresh, 0x06); /* XXX convert magic num to a constant */
1013
1014 __cp_set_rx_mode(dev);
1015 cpw32_f (TxConfig, IFG | (TX_DMA_BURST << TxDMAShift));
1016
1017 cpw8(Config1, cpr8(Config1) | DriverLoaded | PMEnable);
1018 /* Disable Wake-on-LAN. Can be turned on with ETHTOOL_SWOL */
1019 cpw8(Config3, PARMEnable);
1020 cp->wol_enabled = 0;
1021
1022 cpw8(Config5, cpr8(Config5) & PMEStatus);
1023
1024 cpw32_f(HiTxRingAddr, 0);
1025 cpw32_f(HiTxRingAddr + 4, 0);
1026
1027 ring_dma = cp->ring_dma;
1028 cpw32_f(RxRingAddr, ring_dma & 0xffffffff);
1029 cpw32_f(RxRingAddr + 4, (ring_dma >> 16) >> 16);
1030
1031 ring_dma += sizeof(struct cp_desc) * CP_RX_RING_SIZE;
1032 cpw32_f(TxRingAddr, ring_dma & 0xffffffff);
1033 cpw32_f(TxRingAddr + 4, (ring_dma >> 16) >> 16);
1034
1035 cpw16(MultiIntr, 0);
1036
1037 cpw16_f(IntrMask, cp_intr_mask);
1038
1039 cpw8_f(Cfg9346, Cfg9346_Lock);
1040 }
1041
1042 static int cp_refill_rx(struct cp_private *cp)
1043 {
1044 struct net_device *dev = cp->dev;
1045 unsigned i;
1046
1047 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1048 struct sk_buff *skb;
1049 dma_addr_t mapping;
1050
1051 skb = netdev_alloc_skb_ip_align(dev, cp->rx_buf_sz);
1052 if (!skb)
1053 goto err_out;
1054
1055 mapping = dma_map_single(&cp->pdev->dev, skb->data,
1056 cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1057 cp->rx_skb[i] = skb;
1058
1059 cp->rx_ring[i].opts2 = 0;
1060 cp->rx_ring[i].addr = cpu_to_le64(mapping);
1061 if (i == (CP_RX_RING_SIZE - 1))
1062 cp->rx_ring[i].opts1 =
1063 cpu_to_le32(DescOwn | RingEnd | cp->rx_buf_sz);
1064 else
1065 cp->rx_ring[i].opts1 =
1066 cpu_to_le32(DescOwn | cp->rx_buf_sz);
1067 }
1068
1069 return 0;
1070
1071 err_out:
1072 cp_clean_rings(cp);
1073 return -ENOMEM;
1074 }
1075
1076 static void cp_init_rings_index (struct cp_private *cp)
1077 {
1078 cp->rx_tail = 0;
1079 cp->tx_head = cp->tx_tail = 0;
1080 }
1081
1082 static int cp_init_rings (struct cp_private *cp)
1083 {
1084 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1085 cp->tx_ring[CP_TX_RING_SIZE - 1].opts1 = cpu_to_le32(RingEnd);
1086
1087 cp_init_rings_index(cp);
1088
1089 return cp_refill_rx (cp);
1090 }
1091
1092 static int cp_alloc_rings (struct cp_private *cp)
1093 {
1094 void *mem;
1095
1096 mem = dma_alloc_coherent(&cp->pdev->dev, CP_RING_BYTES,
1097 &cp->ring_dma, GFP_KERNEL);
1098 if (!mem)
1099 return -ENOMEM;
1100
1101 cp->rx_ring = mem;
1102 cp->tx_ring = &cp->rx_ring[CP_RX_RING_SIZE];
1103
1104 return cp_init_rings(cp);
1105 }
1106
1107 static void cp_clean_rings (struct cp_private *cp)
1108 {
1109 struct cp_desc *desc;
1110 unsigned i;
1111
1112 for (i = 0; i < CP_RX_RING_SIZE; i++) {
1113 if (cp->rx_skb[i]) {
1114 desc = cp->rx_ring + i;
1115 dma_unmap_single(&cp->pdev->dev,le64_to_cpu(desc->addr),
1116 cp->rx_buf_sz, PCI_DMA_FROMDEVICE);
1117 dev_kfree_skb(cp->rx_skb[i]);
1118 }
1119 }
1120
1121 for (i = 0; i < CP_TX_RING_SIZE; i++) {
1122 if (cp->tx_skb[i]) {
1123 struct sk_buff *skb = cp->tx_skb[i];
1124
1125 desc = cp->tx_ring + i;
1126 dma_unmap_single(&cp->pdev->dev,le64_to_cpu(desc->addr),
1127 le32_to_cpu(desc->opts1) & 0xffff,
1128 PCI_DMA_TODEVICE);
1129 if (le32_to_cpu(desc->opts1) & LastFrag)
1130 dev_kfree_skb(skb);
1131 cp->dev->stats.tx_dropped++;
1132 }
1133 }
1134
1135 memset(cp->rx_ring, 0, sizeof(struct cp_desc) * CP_RX_RING_SIZE);
1136 memset(cp->tx_ring, 0, sizeof(struct cp_desc) * CP_TX_RING_SIZE);
1137
1138 memset(cp->rx_skb, 0, sizeof(struct sk_buff *) * CP_RX_RING_SIZE);
1139 memset(cp->tx_skb, 0, sizeof(struct sk_buff *) * CP_TX_RING_SIZE);
1140 }
1141
1142 static void cp_free_rings (struct cp_private *cp)
1143 {
1144 cp_clean_rings(cp);
1145 dma_free_coherent(&cp->pdev->dev, CP_RING_BYTES, cp->rx_ring,
1146 cp->ring_dma);
1147 cp->rx_ring = NULL;
1148 cp->tx_ring = NULL;
1149 }
1150
1151 static int cp_open (struct net_device *dev)
1152 {
1153 struct cp_private *cp = netdev_priv(dev);
1154 int rc;
1155
1156 netif_dbg(cp, ifup, dev, "enabling interface\n");
1157
1158 rc = cp_alloc_rings(cp);
1159 if (rc)
1160 return rc;
1161
1162 napi_enable(&cp->napi);
1163
1164 cp_init_hw(cp);
1165
1166 rc = request_irq(dev->irq, cp_interrupt, IRQF_SHARED, dev->name, dev);
1167 if (rc)
1168 goto err_out_hw;
1169
1170 netif_carrier_off(dev);
1171 mii_check_media(&cp->mii_if, netif_msg_link(cp), true);
1172 netif_start_queue(dev);
1173
1174 return 0;
1175
1176 err_out_hw:
1177 napi_disable(&cp->napi);
1178 cp_stop_hw(cp);
1179 cp_free_rings(cp);
1180 return rc;
1181 }
1182
1183 static int cp_close (struct net_device *dev)
1184 {
1185 struct cp_private *cp = netdev_priv(dev);
1186 unsigned long flags;
1187
1188 napi_disable(&cp->napi);
1189
1190 netif_dbg(cp, ifdown, dev, "disabling interface\n");
1191
1192 spin_lock_irqsave(&cp->lock, flags);
1193
1194 netif_stop_queue(dev);
1195 netif_carrier_off(dev);
1196
1197 cp_stop_hw(cp);
1198
1199 spin_unlock_irqrestore(&cp->lock, flags);
1200
1201 free_irq(dev->irq, dev);
1202
1203 cp_free_rings(cp);
1204 return 0;
1205 }
1206
1207 static void cp_tx_timeout(struct net_device *dev)
1208 {
1209 struct cp_private *cp = netdev_priv(dev);
1210 unsigned long flags;
1211 int rc;
1212
1213 netdev_warn(dev, "Transmit timeout, status %2x %4x %4x %4x\n",
1214 cpr8(Cmd), cpr16(CpCmd),
1215 cpr16(IntrStatus), cpr16(IntrMask));
1216
1217 spin_lock_irqsave(&cp->lock, flags);
1218
1219 cp_stop_hw(cp);
1220 cp_clean_rings(cp);
1221 rc = cp_init_rings(cp);
1222 cp_start_hw(cp);
1223
1224 netif_wake_queue(dev);
1225
1226 spin_unlock_irqrestore(&cp->lock, flags);
1227
1228 return;
1229 }
1230
1231 #ifdef BROKEN
1232 static int cp_change_mtu(struct net_device *dev, int new_mtu)
1233 {
1234 struct cp_private *cp = netdev_priv(dev);
1235 int rc;
1236 unsigned long flags;
1237
1238 /* check for invalid MTU, according to hardware limits */
1239 if (new_mtu < CP_MIN_MTU || new_mtu > CP_MAX_MTU)
1240 return -EINVAL;
1241
1242 /* if network interface not up, no need for complexity */
1243 if (!netif_running(dev)) {
1244 dev->mtu = new_mtu;
1245 cp_set_rxbufsize(cp); /* set new rx buf size */
1246 return 0;
1247 }
1248
1249 spin_lock_irqsave(&cp->lock, flags);
1250
1251 cp_stop_hw(cp); /* stop h/w and free rings */
1252 cp_clean_rings(cp);
1253
1254 dev->mtu = new_mtu;
1255 cp_set_rxbufsize(cp); /* set new rx buf size */
1256
1257 rc = cp_init_rings(cp); /* realloc and restart h/w */
1258 cp_start_hw(cp);
1259
1260 spin_unlock_irqrestore(&cp->lock, flags);
1261
1262 return rc;
1263 }
1264 #endif /* BROKEN */
1265
1266 static const char mii_2_8139_map[8] = {
1267 BasicModeCtrl,
1268 BasicModeStatus,
1269 0,
1270 0,
1271 NWayAdvert,
1272 NWayLPAR,
1273 NWayExpansion,
1274 0
1275 };
1276
1277 static int mdio_read(struct net_device *dev, int phy_id, int location)
1278 {
1279 struct cp_private *cp = netdev_priv(dev);
1280
1281 return location < 8 && mii_2_8139_map[location] ?
1282 readw(cp->regs + mii_2_8139_map[location]) : 0;
1283 }
1284
1285
1286 static void mdio_write(struct net_device *dev, int phy_id, int location,
1287 int value)
1288 {
1289 struct cp_private *cp = netdev_priv(dev);
1290
1291 if (location == 0) {
1292 cpw8(Cfg9346, Cfg9346_Unlock);
1293 cpw16(BasicModeCtrl, value);
1294 cpw8(Cfg9346, Cfg9346_Lock);
1295 } else if (location < 8 && mii_2_8139_map[location])
1296 cpw16(mii_2_8139_map[location], value);
1297 }
1298
1299 /* Set the ethtool Wake-on-LAN settings */
1300 static int netdev_set_wol (struct cp_private *cp,
1301 const struct ethtool_wolinfo *wol)
1302 {
1303 u8 options;
1304
1305 options = cpr8 (Config3) & ~(LinkUp | MagicPacket);
1306 /* If WOL is being disabled, no need for complexity */
1307 if (wol->wolopts) {
1308 if (wol->wolopts & WAKE_PHY) options |= LinkUp;
1309 if (wol->wolopts & WAKE_MAGIC) options |= MagicPacket;
1310 }
1311
1312 cpw8 (Cfg9346, Cfg9346_Unlock);
1313 cpw8 (Config3, options);
1314 cpw8 (Cfg9346, Cfg9346_Lock);
1315
1316 options = 0; /* Paranoia setting */
1317 options = cpr8 (Config5) & ~(UWF | MWF | BWF);
1318 /* If WOL is being disabled, no need for complexity */
1319 if (wol->wolopts) {
1320 if (wol->wolopts & WAKE_UCAST) options |= UWF;
1321 if (wol->wolopts & WAKE_BCAST) options |= BWF;
1322 if (wol->wolopts & WAKE_MCAST) options |= MWF;
1323 }
1324
1325 cpw8 (Config5, options);
1326
1327 cp->wol_enabled = (wol->wolopts) ? 1 : 0;
1328
1329 return 0;
1330 }
1331
1332 /* Get the ethtool Wake-on-LAN settings */
1333 static void netdev_get_wol (struct cp_private *cp,
1334 struct ethtool_wolinfo *wol)
1335 {
1336 u8 options;
1337
1338 wol->wolopts = 0; /* Start from scratch */
1339 wol->supported = WAKE_PHY | WAKE_BCAST | WAKE_MAGIC |
1340 WAKE_MCAST | WAKE_UCAST;
1341 /* We don't need to go on if WOL is disabled */
1342 if (!cp->wol_enabled) return;
1343
1344 options = cpr8 (Config3);
1345 if (options & LinkUp) wol->wolopts |= WAKE_PHY;
1346 if (options & MagicPacket) wol->wolopts |= WAKE_MAGIC;
1347
1348 options = 0; /* Paranoia setting */
1349 options = cpr8 (Config5);
1350 if (options & UWF) wol->wolopts |= WAKE_UCAST;
1351 if (options & BWF) wol->wolopts |= WAKE_BCAST;
1352 if (options & MWF) wol->wolopts |= WAKE_MCAST;
1353 }
1354
1355 static void cp_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
1356 {
1357 struct cp_private *cp = netdev_priv(dev);
1358
1359 strcpy (info->driver, DRV_NAME);
1360 strcpy (info->version, DRV_VERSION);
1361 strcpy (info->bus_info, pci_name(cp->pdev));
1362 }
1363
1364 static int cp_get_regs_len(struct net_device *dev)
1365 {
1366 return CP_REGS_SIZE;
1367 }
1368
1369 static int cp_get_sset_count (struct net_device *dev, int sset)
1370 {
1371 switch (sset) {
1372 case ETH_SS_STATS:
1373 return CP_NUM_STATS;
1374 default:
1375 return -EOPNOTSUPP;
1376 }
1377 }
1378
1379 static int cp_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1380 {
1381 struct cp_private *cp = netdev_priv(dev);
1382 int rc;
1383 unsigned long flags;
1384
1385 spin_lock_irqsave(&cp->lock, flags);
1386 rc = mii_ethtool_gset(&cp->mii_if, cmd);
1387 spin_unlock_irqrestore(&cp->lock, flags);
1388
1389 return rc;
1390 }
1391
1392 static int cp_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1393 {
1394 struct cp_private *cp = netdev_priv(dev);
1395 int rc;
1396 unsigned long flags;
1397
1398 spin_lock_irqsave(&cp->lock, flags);
1399 rc = mii_ethtool_sset(&cp->mii_if, cmd);
1400 spin_unlock_irqrestore(&cp->lock, flags);
1401
1402 return rc;
1403 }
1404
1405 static int cp_nway_reset(struct net_device *dev)
1406 {
1407 struct cp_private *cp = netdev_priv(dev);
1408 return mii_nway_restart(&cp->mii_if);
1409 }
1410
1411 static u32 cp_get_msglevel(struct net_device *dev)
1412 {
1413 struct cp_private *cp = netdev_priv(dev);
1414 return cp->msg_enable;
1415 }
1416
1417 static void cp_set_msglevel(struct net_device *dev, u32 value)
1418 {
1419 struct cp_private *cp = netdev_priv(dev);
1420 cp->msg_enable = value;
1421 }
1422
1423 static u32 cp_get_rx_csum(struct net_device *dev)
1424 {
1425 struct cp_private *cp = netdev_priv(dev);
1426 return (cpr16(CpCmd) & RxChkSum) ? 1 : 0;
1427 }
1428
1429 static int cp_set_rx_csum(struct net_device *dev, u32 data)
1430 {
1431 struct cp_private *cp = netdev_priv(dev);
1432 u16 cmd = cp->cpcmd, newcmd;
1433
1434 newcmd = cmd;
1435
1436 if (data)
1437 newcmd |= RxChkSum;
1438 else
1439 newcmd &= ~RxChkSum;
1440
1441 if (newcmd != cmd) {
1442 unsigned long flags;
1443
1444 spin_lock_irqsave(&cp->lock, flags);
1445 cp->cpcmd = newcmd;
1446 cpw16_f(CpCmd, newcmd);
1447 spin_unlock_irqrestore(&cp->lock, flags);
1448 }
1449
1450 return 0;
1451 }
1452
1453 static void cp_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1454 void *p)
1455 {
1456 struct cp_private *cp = netdev_priv(dev);
1457 unsigned long flags;
1458
1459 if (regs->len < CP_REGS_SIZE)
1460 return /* -EINVAL */;
1461
1462 regs->version = CP_REGS_VER;
1463
1464 spin_lock_irqsave(&cp->lock, flags);
1465 memcpy_fromio(p, cp->regs, CP_REGS_SIZE);
1466 spin_unlock_irqrestore(&cp->lock, flags);
1467 }
1468
1469 static void cp_get_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1470 {
1471 struct cp_private *cp = netdev_priv(dev);
1472 unsigned long flags;
1473
1474 spin_lock_irqsave (&cp->lock, flags);
1475 netdev_get_wol (cp, wol);
1476 spin_unlock_irqrestore (&cp->lock, flags);
1477 }
1478
1479 static int cp_set_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
1480 {
1481 struct cp_private *cp = netdev_priv(dev);
1482 unsigned long flags;
1483 int rc;
1484
1485 spin_lock_irqsave (&cp->lock, flags);
1486 rc = netdev_set_wol (cp, wol);
1487 spin_unlock_irqrestore (&cp->lock, flags);
1488
1489 return rc;
1490 }
1491
1492 static void cp_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
1493 {
1494 switch (stringset) {
1495 case ETH_SS_STATS:
1496 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
1497 break;
1498 default:
1499 BUG();
1500 break;
1501 }
1502 }
1503
1504 static void cp_get_ethtool_stats (struct net_device *dev,
1505 struct ethtool_stats *estats, u64 *tmp_stats)
1506 {
1507 struct cp_private *cp = netdev_priv(dev);
1508 struct cp_dma_stats *nic_stats;
1509 dma_addr_t dma;
1510 int i;
1511
1512 nic_stats = dma_alloc_coherent(&cp->pdev->dev, sizeof(*nic_stats),
1513 &dma, GFP_KERNEL);
1514 if (!nic_stats)
1515 return;
1516
1517 /* begin NIC statistics dump */
1518 cpw32(StatsAddr + 4, (u64)dma >> 32);
1519 cpw32(StatsAddr, ((u64)dma & DMA_BIT_MASK(32)) | DumpStats);
1520 cpr32(StatsAddr);
1521
1522 for (i = 0; i < 1000; i++) {
1523 if ((cpr32(StatsAddr) & DumpStats) == 0)
1524 break;
1525 udelay(10);
1526 }
1527 cpw32(StatsAddr, 0);
1528 cpw32(StatsAddr + 4, 0);
1529 cpr32(StatsAddr);
1530
1531 i = 0;
1532 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_ok);
1533 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok);
1534 tmp_stats[i++] = le64_to_cpu(nic_stats->tx_err);
1535 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_err);
1536 tmp_stats[i++] = le16_to_cpu(nic_stats->rx_fifo);
1537 tmp_stats[i++] = le16_to_cpu(nic_stats->frame_align);
1538 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_1col);
1539 tmp_stats[i++] = le32_to_cpu(nic_stats->tx_ok_mcol);
1540 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_phys);
1541 tmp_stats[i++] = le64_to_cpu(nic_stats->rx_ok_bcast);
1542 tmp_stats[i++] = le32_to_cpu(nic_stats->rx_ok_mcast);
1543 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_abort);
1544 tmp_stats[i++] = le16_to_cpu(nic_stats->tx_underrun);
1545 tmp_stats[i++] = cp->cp_stats.rx_frags;
1546 BUG_ON(i != CP_NUM_STATS);
1547
1548 dma_free_coherent(&cp->pdev->dev, sizeof(*nic_stats), nic_stats, dma);
1549 }
1550
1551 static const struct ethtool_ops cp_ethtool_ops = {
1552 .get_drvinfo = cp_get_drvinfo,
1553 .get_regs_len = cp_get_regs_len,
1554 .get_sset_count = cp_get_sset_count,
1555 .get_settings = cp_get_settings,
1556 .set_settings = cp_set_settings,
1557 .nway_reset = cp_nway_reset,
1558 .get_link = ethtool_op_get_link,
1559 .get_msglevel = cp_get_msglevel,
1560 .set_msglevel = cp_set_msglevel,
1561 .get_rx_csum = cp_get_rx_csum,
1562 .set_rx_csum = cp_set_rx_csum,
1563 .set_tx_csum = ethtool_op_set_tx_csum, /* local! */
1564 .set_sg = ethtool_op_set_sg,
1565 .set_tso = ethtool_op_set_tso,
1566 .get_regs = cp_get_regs,
1567 .get_wol = cp_get_wol,
1568 .set_wol = cp_set_wol,
1569 .get_strings = cp_get_strings,
1570 .get_ethtool_stats = cp_get_ethtool_stats,
1571 .get_eeprom_len = cp_get_eeprom_len,
1572 .get_eeprom = cp_get_eeprom,
1573 .set_eeprom = cp_set_eeprom,
1574 };
1575
1576 static int cp_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1577 {
1578 struct cp_private *cp = netdev_priv(dev);
1579 int rc;
1580 unsigned long flags;
1581
1582 if (!netif_running(dev))
1583 return -EINVAL;
1584
1585 spin_lock_irqsave(&cp->lock, flags);
1586 rc = generic_mii_ioctl(&cp->mii_if, if_mii(rq), cmd, NULL);
1587 spin_unlock_irqrestore(&cp->lock, flags);
1588 return rc;
1589 }
1590
1591 static int cp_set_mac_address(struct net_device *dev, void *p)
1592 {
1593 struct cp_private *cp = netdev_priv(dev);
1594 struct sockaddr *addr = p;
1595
1596 if (!is_valid_ether_addr(addr->sa_data))
1597 return -EADDRNOTAVAIL;
1598
1599 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1600
1601 spin_lock_irq(&cp->lock);
1602
1603 cpw8_f(Cfg9346, Cfg9346_Unlock);
1604 cpw32_f(MAC0 + 0, le32_to_cpu (*(__le32 *) (dev->dev_addr + 0)));
1605 cpw32_f(MAC0 + 4, le32_to_cpu (*(__le32 *) (dev->dev_addr + 4)));
1606 cpw8_f(Cfg9346, Cfg9346_Lock);
1607
1608 spin_unlock_irq(&cp->lock);
1609
1610 return 0;
1611 }
1612
1613 /* Serial EEPROM section. */
1614
1615 /* EEPROM_Ctrl bits. */
1616 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1617 #define EE_CS 0x08 /* EEPROM chip select. */
1618 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1619 #define EE_WRITE_0 0x00
1620 #define EE_WRITE_1 0x02
1621 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1622 #define EE_ENB (0x80 | EE_CS)
1623
1624 /* Delay between EEPROM clock transitions.
1625 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1626 */
1627
1628 #define eeprom_delay() readl(ee_addr)
1629
1630 /* The EEPROM commands include the alway-set leading bit. */
1631 #define EE_EXTEND_CMD (4)
1632 #define EE_WRITE_CMD (5)
1633 #define EE_READ_CMD (6)
1634 #define EE_ERASE_CMD (7)
1635
1636 #define EE_EWDS_ADDR (0)
1637 #define EE_WRAL_ADDR (1)
1638 #define EE_ERAL_ADDR (2)
1639 #define EE_EWEN_ADDR (3)
1640
1641 #define CP_EEPROM_MAGIC PCI_DEVICE_ID_REALTEK_8139
1642
1643 static void eeprom_cmd_start(void __iomem *ee_addr)
1644 {
1645 writeb (EE_ENB & ~EE_CS, ee_addr);
1646 writeb (EE_ENB, ee_addr);
1647 eeprom_delay ();
1648 }
1649
1650 static void eeprom_cmd(void __iomem *ee_addr, int cmd, int cmd_len)
1651 {
1652 int i;
1653
1654 /* Shift the command bits out. */
1655 for (i = cmd_len - 1; i >= 0; i--) {
1656 int dataval = (cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1657 writeb (EE_ENB | dataval, ee_addr);
1658 eeprom_delay ();
1659 writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
1660 eeprom_delay ();
1661 }
1662 writeb (EE_ENB, ee_addr);
1663 eeprom_delay ();
1664 }
1665
1666 static void eeprom_cmd_end(void __iomem *ee_addr)
1667 {
1668 writeb (~EE_CS, ee_addr);
1669 eeprom_delay ();
1670 }
1671
1672 static void eeprom_extend_cmd(void __iomem *ee_addr, int extend_cmd,
1673 int addr_len)
1674 {
1675 int cmd = (EE_EXTEND_CMD << addr_len) | (extend_cmd << (addr_len - 2));
1676
1677 eeprom_cmd_start(ee_addr);
1678 eeprom_cmd(ee_addr, cmd, 3 + addr_len);
1679 eeprom_cmd_end(ee_addr);
1680 }
1681
1682 static u16 read_eeprom (void __iomem *ioaddr, int location, int addr_len)
1683 {
1684 int i;
1685 u16 retval = 0;
1686 void __iomem *ee_addr = ioaddr + Cfg9346;
1687 int read_cmd = location | (EE_READ_CMD << addr_len);
1688
1689 eeprom_cmd_start(ee_addr);
1690 eeprom_cmd(ee_addr, read_cmd, 3 + addr_len);
1691
1692 for (i = 16; i > 0; i--) {
1693 writeb (EE_ENB | EE_SHIFT_CLK, ee_addr);
1694 eeprom_delay ();
1695 retval =
1696 (retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 :
1697 0);
1698 writeb (EE_ENB, ee_addr);
1699 eeprom_delay ();
1700 }
1701
1702 eeprom_cmd_end(ee_addr);
1703
1704 return retval;
1705 }
1706
1707 static void write_eeprom(void __iomem *ioaddr, int location, u16 val,
1708 int addr_len)
1709 {
1710 int i;
1711 void __iomem *ee_addr = ioaddr + Cfg9346;
1712 int write_cmd = location | (EE_WRITE_CMD << addr_len);
1713
1714 eeprom_extend_cmd(ee_addr, EE_EWEN_ADDR, addr_len);
1715
1716 eeprom_cmd_start(ee_addr);
1717 eeprom_cmd(ee_addr, write_cmd, 3 + addr_len);
1718 eeprom_cmd(ee_addr, val, 16);
1719 eeprom_cmd_end(ee_addr);
1720
1721 eeprom_cmd_start(ee_addr);
1722 for (i = 0; i < 20000; i++)
1723 if (readb(ee_addr) & EE_DATA_READ)
1724 break;
1725 eeprom_cmd_end(ee_addr);
1726
1727 eeprom_extend_cmd(ee_addr, EE_EWDS_ADDR, addr_len);
1728 }
1729
1730 static int cp_get_eeprom_len(struct net_device *dev)
1731 {
1732 struct cp_private *cp = netdev_priv(dev);
1733 int size;
1734
1735 spin_lock_irq(&cp->lock);
1736 size = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 256 : 128;
1737 spin_unlock_irq(&cp->lock);
1738
1739 return size;
1740 }
1741
1742 static int cp_get_eeprom(struct net_device *dev,
1743 struct ethtool_eeprom *eeprom, u8 *data)
1744 {
1745 struct cp_private *cp = netdev_priv(dev);
1746 unsigned int addr_len;
1747 u16 val;
1748 u32 offset = eeprom->offset >> 1;
1749 u32 len = eeprom->len;
1750 u32 i = 0;
1751
1752 eeprom->magic = CP_EEPROM_MAGIC;
1753
1754 spin_lock_irq(&cp->lock);
1755
1756 addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6;
1757
1758 if (eeprom->offset & 1) {
1759 val = read_eeprom(cp->regs, offset, addr_len);
1760 data[i++] = (u8)(val >> 8);
1761 offset++;
1762 }
1763
1764 while (i < len - 1) {
1765 val = read_eeprom(cp->regs, offset, addr_len);
1766 data[i++] = (u8)val;
1767 data[i++] = (u8)(val >> 8);
1768 offset++;
1769 }
1770
1771 if (i < len) {
1772 val = read_eeprom(cp->regs, offset, addr_len);
1773 data[i] = (u8)val;
1774 }
1775
1776 spin_unlock_irq(&cp->lock);
1777 return 0;
1778 }
1779
1780 static int cp_set_eeprom(struct net_device *dev,
1781 struct ethtool_eeprom *eeprom, u8 *data)
1782 {
1783 struct cp_private *cp = netdev_priv(dev);
1784 unsigned int addr_len;
1785 u16 val;
1786 u32 offset = eeprom->offset >> 1;
1787 u32 len = eeprom->len;
1788 u32 i = 0;
1789
1790 if (eeprom->magic != CP_EEPROM_MAGIC)
1791 return -EINVAL;
1792
1793 spin_lock_irq(&cp->lock);
1794
1795 addr_len = read_eeprom(cp->regs, 0, 8) == 0x8129 ? 8 : 6;
1796
1797 if (eeprom->offset & 1) {
1798 val = read_eeprom(cp->regs, offset, addr_len) & 0xff;
1799 val |= (u16)data[i++] << 8;
1800 write_eeprom(cp->regs, offset, val, addr_len);
1801 offset++;
1802 }
1803
1804 while (i < len - 1) {
1805 val = (u16)data[i++];
1806 val |= (u16)data[i++] << 8;
1807 write_eeprom(cp->regs, offset, val, addr_len);
1808 offset++;
1809 }
1810
1811 if (i < len) {
1812 val = read_eeprom(cp->regs, offset, addr_len) & 0xff00;
1813 val |= (u16)data[i];
1814 write_eeprom(cp->regs, offset, val, addr_len);
1815 }
1816
1817 spin_unlock_irq(&cp->lock);
1818 return 0;
1819 }
1820
1821 /* Put the board into D3cold state and wait for WakeUp signal */
1822 static void cp_set_d3_state (struct cp_private *cp)
1823 {
1824 pci_enable_wake (cp->pdev, 0, 1); /* Enable PME# generation */
1825 pci_set_power_state (cp->pdev, PCI_D3hot);
1826 }
1827
1828 static const struct net_device_ops cp_netdev_ops = {
1829 .ndo_open = cp_open,
1830 .ndo_stop = cp_close,
1831 .ndo_validate_addr = eth_validate_addr,
1832 .ndo_set_mac_address = cp_set_mac_address,
1833 .ndo_set_multicast_list = cp_set_rx_mode,
1834 .ndo_get_stats = cp_get_stats,
1835 .ndo_do_ioctl = cp_ioctl,
1836 .ndo_start_xmit = cp_start_xmit,
1837 .ndo_tx_timeout = cp_tx_timeout,
1838 #if CP_VLAN_TAG_USED
1839 .ndo_vlan_rx_register = cp_vlan_rx_register,
1840 #endif
1841 #ifdef BROKEN
1842 .ndo_change_mtu = cp_change_mtu,
1843 #endif
1844
1845 #ifdef CONFIG_NET_POLL_CONTROLLER
1846 .ndo_poll_controller = cp_poll_controller,
1847 #endif
1848 };
1849
1850 static int cp_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1851 {
1852 struct net_device *dev;
1853 struct cp_private *cp;
1854 int rc;
1855 void __iomem *regs;
1856 resource_size_t pciaddr;
1857 unsigned int addr_len, i, pci_using_dac;
1858
1859 #ifndef MODULE
1860 static int version_printed;
1861 if (version_printed++ == 0)
1862 pr_info("%s", version);
1863 #endif
1864
1865 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
1866 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pdev->revision < 0x20) {
1867 dev_info(&pdev->dev,
1868 "This (id %04x:%04x rev %02x) is not an 8139C+ compatible chip, use 8139too\n",
1869 pdev->vendor, pdev->device, pdev->revision);
1870 return -ENODEV;
1871 }
1872
1873 dev = alloc_etherdev(sizeof(struct cp_private));
1874 if (!dev)
1875 return -ENOMEM;
1876 SET_NETDEV_DEV(dev, &pdev->dev);
1877
1878 cp = netdev_priv(dev);
1879 cp->pdev = pdev;
1880 cp->dev = dev;
1881 cp->msg_enable = (debug < 0 ? CP_DEF_MSG_ENABLE : debug);
1882 spin_lock_init (&cp->lock);
1883 cp->mii_if.dev = dev;
1884 cp->mii_if.mdio_read = mdio_read;
1885 cp->mii_if.mdio_write = mdio_write;
1886 cp->mii_if.phy_id = CP_INTERNAL_PHY;
1887 cp->mii_if.phy_id_mask = 0x1f;
1888 cp->mii_if.reg_num_mask = 0x1f;
1889 cp_set_rxbufsize(cp);
1890
1891 rc = pci_enable_device(pdev);
1892 if (rc)
1893 goto err_out_free;
1894
1895 rc = pci_set_mwi(pdev);
1896 if (rc)
1897 goto err_out_disable;
1898
1899 rc = pci_request_regions(pdev, DRV_NAME);
1900 if (rc)
1901 goto err_out_mwi;
1902
1903 pciaddr = pci_resource_start(pdev, 1);
1904 if (!pciaddr) {
1905 rc = -EIO;
1906 dev_err(&pdev->dev, "no MMIO resource\n");
1907 goto err_out_res;
1908 }
1909 if (pci_resource_len(pdev, 1) < CP_REGS_SIZE) {
1910 rc = -EIO;
1911 dev_err(&pdev->dev, "MMIO resource (%llx) too small\n",
1912 (unsigned long long)pci_resource_len(pdev, 1));
1913 goto err_out_res;
1914 }
1915
1916 /* Configure DMA attributes. */
1917 if ((sizeof(dma_addr_t) > 4) &&
1918 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) &&
1919 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
1920 pci_using_dac = 1;
1921 } else {
1922 pci_using_dac = 0;
1923
1924 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1925 if (rc) {
1926 dev_err(&pdev->dev,
1927 "No usable DMA configuration, aborting\n");
1928 goto err_out_res;
1929 }
1930 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1931 if (rc) {
1932 dev_err(&pdev->dev,
1933 "No usable consistent DMA configuration, aborting\n");
1934 goto err_out_res;
1935 }
1936 }
1937
1938 cp->cpcmd = (pci_using_dac ? PCIDAC : 0) |
1939 PCIMulRW | RxChkSum | CpRxOn | CpTxOn;
1940
1941 regs = ioremap(pciaddr, CP_REGS_SIZE);
1942 if (!regs) {
1943 rc = -EIO;
1944 dev_err(&pdev->dev, "Cannot map PCI MMIO (%Lx@%Lx)\n",
1945 (unsigned long long)pci_resource_len(pdev, 1),
1946 (unsigned long long)pciaddr);
1947 goto err_out_res;
1948 }
1949 dev->base_addr = (unsigned long) regs;
1950 cp->regs = regs;
1951
1952 cp_stop_hw(cp);
1953
1954 /* read MAC address from EEPROM */
1955 addr_len = read_eeprom (regs, 0, 8) == 0x8129 ? 8 : 6;
1956 for (i = 0; i < 3; i++)
1957 ((__le16 *) (dev->dev_addr))[i] =
1958 cpu_to_le16(read_eeprom (regs, i + 7, addr_len));
1959 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1960
1961 dev->netdev_ops = &cp_netdev_ops;
1962 netif_napi_add(dev, &cp->napi, cp_rx_poll, 16);
1963 dev->ethtool_ops = &cp_ethtool_ops;
1964 dev->watchdog_timeo = TX_TIMEOUT;
1965
1966 #if CP_VLAN_TAG_USED
1967 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1968 #endif
1969
1970 if (pci_using_dac)
1971 dev->features |= NETIF_F_HIGHDMA;
1972
1973 #if 0 /* disabled by default until verified */
1974 dev->features |= NETIF_F_TSO;
1975 #endif
1976
1977 dev->irq = pdev->irq;
1978
1979 rc = register_netdev(dev);
1980 if (rc)
1981 goto err_out_iomap;
1982
1983 netdev_info(dev, "RTL-8139C+ at 0x%lx, %pM, IRQ %d\n",
1984 dev->base_addr, dev->dev_addr, dev->irq);
1985
1986 pci_set_drvdata(pdev, dev);
1987
1988 /* enable busmastering and memory-write-invalidate */
1989 pci_set_master(pdev);
1990
1991 if (cp->wol_enabled)
1992 cp_set_d3_state (cp);
1993
1994 return 0;
1995
1996 err_out_iomap:
1997 iounmap(regs);
1998 err_out_res:
1999 pci_release_regions(pdev);
2000 err_out_mwi:
2001 pci_clear_mwi(pdev);
2002 err_out_disable:
2003 pci_disable_device(pdev);
2004 err_out_free:
2005 free_netdev(dev);
2006 return rc;
2007 }
2008
2009 static void cp_remove_one (struct pci_dev *pdev)
2010 {
2011 struct net_device *dev = pci_get_drvdata(pdev);
2012 struct cp_private *cp = netdev_priv(dev);
2013
2014 unregister_netdev(dev);
2015 iounmap(cp->regs);
2016 if (cp->wol_enabled)
2017 pci_set_power_state (pdev, PCI_D0);
2018 pci_release_regions(pdev);
2019 pci_clear_mwi(pdev);
2020 pci_disable_device(pdev);
2021 pci_set_drvdata(pdev, NULL);
2022 free_netdev(dev);
2023 }
2024
2025 #ifdef CONFIG_PM
2026 static int cp_suspend (struct pci_dev *pdev, pm_message_t state)
2027 {
2028 struct net_device *dev = pci_get_drvdata(pdev);
2029 struct cp_private *cp = netdev_priv(dev);
2030 unsigned long flags;
2031
2032 if (!netif_running(dev))
2033 return 0;
2034
2035 netif_device_detach (dev);
2036 netif_stop_queue (dev);
2037
2038 spin_lock_irqsave (&cp->lock, flags);
2039
2040 /* Disable Rx and Tx */
2041 cpw16 (IntrMask, 0);
2042 cpw8 (Cmd, cpr8 (Cmd) & (~RxOn | ~TxOn));
2043
2044 spin_unlock_irqrestore (&cp->lock, flags);
2045
2046 pci_save_state(pdev);
2047 pci_enable_wake(pdev, pci_choose_state(pdev, state), cp->wol_enabled);
2048 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2049
2050 return 0;
2051 }
2052
2053 static int cp_resume (struct pci_dev *pdev)
2054 {
2055 struct net_device *dev = pci_get_drvdata (pdev);
2056 struct cp_private *cp = netdev_priv(dev);
2057 unsigned long flags;
2058
2059 if (!netif_running(dev))
2060 return 0;
2061
2062 netif_device_attach (dev);
2063
2064 pci_set_power_state(pdev, PCI_D0);
2065 pci_restore_state(pdev);
2066 pci_enable_wake(pdev, PCI_D0, 0);
2067
2068 /* FIXME: sh*t may happen if the Rx ring buffer is depleted */
2069 cp_init_rings_index (cp);
2070 cp_init_hw (cp);
2071 netif_start_queue (dev);
2072
2073 spin_lock_irqsave (&cp->lock, flags);
2074
2075 mii_check_media(&cp->mii_if, netif_msg_link(cp), false);
2076
2077 spin_unlock_irqrestore (&cp->lock, flags);
2078
2079 return 0;
2080 }
2081 #endif /* CONFIG_PM */
2082
2083 static struct pci_driver cp_driver = {
2084 .name = DRV_NAME,
2085 .id_table = cp_pci_tbl,
2086 .probe = cp_init_one,
2087 .remove = cp_remove_one,
2088 #ifdef CONFIG_PM
2089 .resume = cp_resume,
2090 .suspend = cp_suspend,
2091 #endif
2092 };
2093
2094 static int __init cp_init (void)
2095 {
2096 #ifdef MODULE
2097 pr_info("%s", version);
2098 #endif
2099 return pci_register_driver(&cp_driver);
2100 }
2101
2102 static void __exit cp_exit (void)
2103 {
2104 pci_unregister_driver (&cp_driver);
2105 }
2106
2107 module_init(cp_init);
2108 module_exit(cp_exit);
kernel-based virtual machine