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drm: radeon: Fix calculation of RB_RPTR_ADDR in non-AGP case.
[linux-2.6/kvm.git] / drivers / gpu / drm / radeon / radeon_cp.c
blob4a56e7d626a64ff1c8fae0a576c28514a85c93d4
1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
2 /*
3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * Copyright 2007 Advanced Micro Devices, Inc.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 *
27 * Authors:
28 * Kevin E. Martin <martin@valinux.com>
29 * Gareth Hughes <gareth@valinux.com>
30 */
31
32 #include "drmP.h"
33 #include "drm.h"
34 #include "drm_sarea.h"
35 #include "radeon_drm.h"
36 #include "radeon_drv.h"
37 #include "r300_reg.h"
38
39 #include "radeon_microcode.h"
40
41 #define RADEON_FIFO_DEBUG 0
42
43 static int radeon_do_cleanup_cp(struct drm_device * dev);
44 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv);
45
46 static u32 radeon_read_ring_rptr(drm_radeon_private_t *dev_priv, u32 off)
47 {
48 u32 val;
49
50 if (dev_priv->flags & RADEON_IS_AGP) {
51 val = DRM_READ32(dev_priv->ring_rptr, off);
52 } else {
53 val = *(((volatile u32 *)
54 dev_priv->ring_rptr->handle) +
55 (off / sizeof(u32)));
56 val = le32_to_cpu(val);
57 }
58 return val;
59 }
60
61 u32 radeon_get_ring_head(drm_radeon_private_t *dev_priv)
62 {
63 if (dev_priv->writeback_works)
64 return radeon_read_ring_rptr(dev_priv, 0);
65 else
66 return RADEON_READ(RADEON_CP_RB_RPTR);
67 }
68
69 static void radeon_write_ring_rptr(drm_radeon_private_t *dev_priv, u32 off, u32 val)
70 {
71 if (dev_priv->flags & RADEON_IS_AGP)
72 DRM_WRITE32(dev_priv->ring_rptr, off, val);
73 else
74 *(((volatile u32 *) dev_priv->ring_rptr->handle) +
75 (off / sizeof(u32))) = cpu_to_le32(val);
76 }
77
78 void radeon_set_ring_head(drm_radeon_private_t *dev_priv, u32 val)
79 {
80 radeon_write_ring_rptr(dev_priv, 0, val);
81 }
82
83 u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index)
84 {
85 if (dev_priv->writeback_works)
86 return radeon_read_ring_rptr(dev_priv,
87 RADEON_SCRATCHOFF(index));
88 else
89 return RADEON_READ(RADEON_SCRATCH_REG0 + 4*index);
90 }
91
92 static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
93 {
94 u32 ret;
95 RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
96 ret = RADEON_READ(R520_MC_IND_DATA);
97 RADEON_WRITE(R520_MC_IND_INDEX, 0);
98 return ret;
99 }
100
101 static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
102 {
103 u32 ret;
104 RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff);
105 ret = RADEON_READ(RS480_NB_MC_DATA);
106 RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);
107 return ret;
108 }
109
110 static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
111 {
112 u32 ret;
113 RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
114 ret = RADEON_READ(RS690_MC_DATA);
115 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK);
116 return ret;
117 }
118
119 static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
120 {
121 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
122 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
123 return RS690_READ_MCIND(dev_priv, addr);
124 else
125 return RS480_READ_MCIND(dev_priv, addr);
126 }
127
128 u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
129 {
130
131 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
132 return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
133 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
134 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
135 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
136 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
137 return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
138 else
139 return RADEON_READ(RADEON_MC_FB_LOCATION);
140 }
141
142 static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
143 {
144 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
145 R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
146 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
147 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
148 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
149 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
150 R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
151 else
152 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
153 }
154
155 static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
156 {
157 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
158 R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
159 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
160 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
161 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
162 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
163 R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
164 else
165 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
166 }
167
168 static void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
169 {
170 u32 agp_base_hi = upper_32_bits(agp_base);
171 u32 agp_base_lo = agp_base & 0xffffffff;
172
173 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
174 R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo);
175 R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi);
176 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
177 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
178 RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo);
179 RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi);
180 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
181 R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo);
182 R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi);
183 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
184 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
185 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
186 RADEON_WRITE(RS480_AGP_BASE_2, agp_base_hi);
187 } else {
188 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
189 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
190 RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi);
191 }
192 }
193
194 static int RADEON_READ_PLL(struct drm_device * dev, int addr)
195 {
196 drm_radeon_private_t *dev_priv = dev->dev_private;
197
198 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
199 return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
200 }
201
202 static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
203 {
204 RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
205 return RADEON_READ(RADEON_PCIE_DATA);
206 }
207
208 #if RADEON_FIFO_DEBUG
209 static void radeon_status(drm_radeon_private_t * dev_priv)
210 {
211 printk("%s:\n", __func__);
212 printk("RBBM_STATUS = 0x%08x\n",
213 (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
214 printk("CP_RB_RTPR = 0x%08x\n",
215 (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
216 printk("CP_RB_WTPR = 0x%08x\n",
217 (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
218 printk("AIC_CNTL = 0x%08x\n",
219 (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
220 printk("AIC_STAT = 0x%08x\n",
221 (unsigned int)RADEON_READ(RADEON_AIC_STAT));
222 printk("AIC_PT_BASE = 0x%08x\n",
223 (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
224 printk("TLB_ADDR = 0x%08x\n",
225 (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
226 printk("TLB_DATA = 0x%08x\n",
227 (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
228 }
229 #endif
230
231 /* ================================================================
232 * Engine, FIFO control
233 */
234
235 static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
236 {
237 u32 tmp;
238 int i;
239
240 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
241
242 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {
243 tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
244 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
245 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
246
247 for (i = 0; i < dev_priv->usec_timeout; i++) {
248 if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
249 & RADEON_RB3D_DC_BUSY)) {
250 return 0;
251 }
252 DRM_UDELAY(1);
253 }
254 } else {
255 /* don't flush or purge cache here or lockup */
256 return 0;
257 }
258
259 #if RADEON_FIFO_DEBUG
260 DRM_ERROR("failed!\n");
261 radeon_status(dev_priv);
262 #endif
263 return -EBUSY;
264 }
265
266 static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
267 {
268 int i;
269
270 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
271
272 for (i = 0; i < dev_priv->usec_timeout; i++) {
273 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
274 & RADEON_RBBM_FIFOCNT_MASK);
275 if (slots >= entries)
276 return 0;
277 DRM_UDELAY(1);
278 }
279 DRM_DEBUG("wait for fifo failed status : 0x%08X 0x%08X\n",
280 RADEON_READ(RADEON_RBBM_STATUS),
281 RADEON_READ(R300_VAP_CNTL_STATUS));
282
283 #if RADEON_FIFO_DEBUG
284 DRM_ERROR("failed!\n");
285 radeon_status(dev_priv);
286 #endif
287 return -EBUSY;
288 }
289
290 static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
291 {
292 int i, ret;
293
294 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
295
296 ret = radeon_do_wait_for_fifo(dev_priv, 64);
297 if (ret)
298 return ret;
299
300 for (i = 0; i < dev_priv->usec_timeout; i++) {
301 if (!(RADEON_READ(RADEON_RBBM_STATUS)
302 & RADEON_RBBM_ACTIVE)) {
303 radeon_do_pixcache_flush(dev_priv);
304 return 0;
305 }
306 DRM_UDELAY(1);
307 }
308 DRM_DEBUG("wait idle failed status : 0x%08X 0x%08X\n",
309 RADEON_READ(RADEON_RBBM_STATUS),
310 RADEON_READ(R300_VAP_CNTL_STATUS));
311
312 #if RADEON_FIFO_DEBUG
313 DRM_ERROR("failed!\n");
314 radeon_status(dev_priv);
315 #endif
316 return -EBUSY;
317 }
318
319 static void radeon_init_pipes(drm_radeon_private_t *dev_priv)
320 {
321 uint32_t gb_tile_config, gb_pipe_sel = 0;
322
323 /* RS4xx/RS6xx/R4xx/R5xx */
324 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
325 gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);
326 dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
327 } else {
328 /* R3xx */
329 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
330 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) {
331 dev_priv->num_gb_pipes = 2;
332 } else {
333 /* R3Vxx */
334 dev_priv->num_gb_pipes = 1;
335 }
336 }
337 DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes);
338
339 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/);
340
341 switch (dev_priv->num_gb_pipes) {
342 case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
343 case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
344 case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
345 default:
346 case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
347 }
348
349 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
350 RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
351 RADEON_WRITE(R500_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1));
352 }
353 RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config);
354 radeon_do_wait_for_idle(dev_priv);
355 RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG);
356 RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) |
357 R300_DC_AUTOFLUSH_ENABLE |
358 R300_DC_DC_DISABLE_IGNORE_PE));
359
360
361 }
362
363 /* ================================================================
364 * CP control, initialization
365 */
366
367 /* Load the microcode for the CP */
368 static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
369 {
370 int i;
371 DRM_DEBUG("\n");
372
373 radeon_do_wait_for_idle(dev_priv);
374
375 RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
376 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) ||
377 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) ||
378 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) ||
379 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) ||
380 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) {
381 DRM_INFO("Loading R100 Microcode\n");
382 for (i = 0; i < 256; i++) {
383 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
384 R100_cp_microcode[i][1]);
385 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
386 R100_cp_microcode[i][0]);
387 }
388 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) ||
389 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) ||
390 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) ||
391 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) {
392 DRM_INFO("Loading R200 Microcode\n");
393 for (i = 0; i < 256; i++) {
394 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
395 R200_cp_microcode[i][1]);
396 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
397 R200_cp_microcode[i][0]);
398 }
399 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
400 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) ||
401 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) ||
402 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||
403 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
404 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
405 DRM_INFO("Loading R300 Microcode\n");
406 for (i = 0; i < 256; i++) {
407 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
408 R300_cp_microcode[i][1]);
409 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
410 R300_cp_microcode[i][0]);
411 }
412 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
413 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R423) ||
414 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) {
415 DRM_INFO("Loading R400 Microcode\n");
416 for (i = 0; i < 256; i++) {
417 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
418 R420_cp_microcode[i][1]);
419 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
420 R420_cp_microcode[i][0]);
421 }
422 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
423 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
424 DRM_INFO("Loading RS690/RS740 Microcode\n");
425 for (i = 0; i < 256; i++) {
426 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
427 RS690_cp_microcode[i][1]);
428 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
429 RS690_cp_microcode[i][0]);
430 }
431 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) ||
432 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) ||
433 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) ||
434 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) ||
435 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) ||
436 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) {
437 DRM_INFO("Loading R500 Microcode\n");
438 for (i = 0; i < 256; i++) {
439 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
440 R520_cp_microcode[i][1]);
441 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
442 R520_cp_microcode[i][0]);
443 }
444 }
445 }
446
447 /* Flush any pending commands to the CP. This should only be used just
448 * prior to a wait for idle, as it informs the engine that the command
449 * stream is ending.
450 */
451 static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
452 {
453 DRM_DEBUG("\n");
454 #if 0
455 u32 tmp;
456
457 tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
458 RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
459 #endif
460 }
461
462 /* Wait for the CP to go idle.
463 */
464 int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
465 {
466 RING_LOCALS;
467 DRM_DEBUG("\n");
468
469 BEGIN_RING(6);
470
471 RADEON_PURGE_CACHE();
472 RADEON_PURGE_ZCACHE();
473 RADEON_WAIT_UNTIL_IDLE();
474
475 ADVANCE_RING();
476 COMMIT_RING();
477
478 return radeon_do_wait_for_idle(dev_priv);
479 }
480
481 /* Start the Command Processor.
482 */
483 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
484 {
485 RING_LOCALS;
486 DRM_DEBUG("\n");
487
488 radeon_do_wait_for_idle(dev_priv);
489
490 RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
491
492 dev_priv->cp_running = 1;
493
494 BEGIN_RING(8);
495 /* isync can only be written through cp on r5xx write it here */
496 OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0));
497 OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D |
498 RADEON_ISYNC_ANY3D_IDLE2D |
499 RADEON_ISYNC_WAIT_IDLEGUI |
500 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
501 RADEON_PURGE_CACHE();
502 RADEON_PURGE_ZCACHE();
503 RADEON_WAIT_UNTIL_IDLE();
504 ADVANCE_RING();
505 COMMIT_RING();
506
507 dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED;
508 }
509
510 /* Reset the Command Processor. This will not flush any pending
511 * commands, so you must wait for the CP command stream to complete
512 * before calling this routine.
513 */
514 static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
515 {
516 u32 cur_read_ptr;
517 DRM_DEBUG("\n");
518
519 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
520 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
521 SET_RING_HEAD(dev_priv, cur_read_ptr);
522 dev_priv->ring.tail = cur_read_ptr;
523 }
524
525 /* Stop the Command Processor. This will not flush any pending
526 * commands, so you must flush the command stream and wait for the CP
527 * to go idle before calling this routine.
528 */
529 static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
530 {
531 DRM_DEBUG("\n");
532
533 RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
534
535 dev_priv->cp_running = 0;
536 }
537
538 /* Reset the engine. This will stop the CP if it is running.
539 */
540 static int radeon_do_engine_reset(struct drm_device * dev)
541 {
542 drm_radeon_private_t *dev_priv = dev->dev_private;
543 u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset;
544 DRM_DEBUG("\n");
545
546 radeon_do_pixcache_flush(dev_priv);
547
548 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
549 /* may need something similar for newer chips */
550 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
551 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
552
553 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
554 RADEON_FORCEON_MCLKA |
555 RADEON_FORCEON_MCLKB |
556 RADEON_FORCEON_YCLKA |
557 RADEON_FORCEON_YCLKB |
558 RADEON_FORCEON_MC |
559 RADEON_FORCEON_AIC));
560 }
561
562 rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
563
564 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
565 RADEON_SOFT_RESET_CP |
566 RADEON_SOFT_RESET_HI |
567 RADEON_SOFT_RESET_SE |
568 RADEON_SOFT_RESET_RE |
569 RADEON_SOFT_RESET_PP |
570 RADEON_SOFT_RESET_E2 |
571 RADEON_SOFT_RESET_RB));
572 RADEON_READ(RADEON_RBBM_SOFT_RESET);
573 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
574 ~(RADEON_SOFT_RESET_CP |
575 RADEON_SOFT_RESET_HI |
576 RADEON_SOFT_RESET_SE |
577 RADEON_SOFT_RESET_RE |
578 RADEON_SOFT_RESET_PP |
579 RADEON_SOFT_RESET_E2 |
580 RADEON_SOFT_RESET_RB)));
581 RADEON_READ(RADEON_RBBM_SOFT_RESET);
582
583 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
584 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
585 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
586 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
587 }
588
589 /* setup the raster pipes */
590 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300)
591 radeon_init_pipes(dev_priv);
592
593 /* Reset the CP ring */
594 radeon_do_cp_reset(dev_priv);
595
596 /* The CP is no longer running after an engine reset */
597 dev_priv->cp_running = 0;
598
599 /* Reset any pending vertex, indirect buffers */
600 radeon_freelist_reset(dev);
601
602 return 0;
603 }
604
605 static void radeon_cp_init_ring_buffer(struct drm_device * dev,
606 drm_radeon_private_t *dev_priv,
607 struct drm_file *file_priv)
608 {
609 struct drm_radeon_master_private *master_priv;
610 u32 ring_start, cur_read_ptr;
611 u32 tmp;
612
613 /* Initialize the memory controller. With new memory map, the fb location
614 * is not changed, it should have been properly initialized already. Part
615 * of the problem is that the code below is bogus, assuming the GART is
616 * always appended to the fb which is not necessarily the case
617 */
618 if (!dev_priv->new_memmap)
619 radeon_write_fb_location(dev_priv,
620 ((dev_priv->gart_vm_start - 1) & 0xffff0000)
621 | (dev_priv->fb_location >> 16));
622
623 #if __OS_HAS_AGP
624 if (dev_priv->flags & RADEON_IS_AGP) {
625 radeon_write_agp_base(dev_priv, dev->agp->base);
626
627 radeon_write_agp_location(dev_priv,
628 (((dev_priv->gart_vm_start - 1 +
629 dev_priv->gart_size) & 0xffff0000) |
630 (dev_priv->gart_vm_start >> 16)));
631
632 ring_start = (dev_priv->cp_ring->offset
633 - dev->agp->base
634 + dev_priv->gart_vm_start);
635 } else
636 #endif
637 ring_start = (dev_priv->cp_ring->offset
638 - (unsigned long)dev->sg->virtual
639 + dev_priv->gart_vm_start);
640
641 RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
642
643 /* Set the write pointer delay */
644 RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
645
646 /* Initialize the ring buffer's read and write pointers */
647 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
648 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
649 SET_RING_HEAD(dev_priv, cur_read_ptr);
650 dev_priv->ring.tail = cur_read_ptr;
651
652 #if __OS_HAS_AGP
653 if (dev_priv->flags & RADEON_IS_AGP) {
654 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
655 dev_priv->ring_rptr->offset
656 - dev->agp->base + dev_priv->gart_vm_start);
657 } else
658 #endif
659 {
660 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
661 dev_priv->ring_rptr->offset
662 - ((unsigned long) dev->sg->virtual)
663 + dev_priv->gart_vm_start);
664 }
665
666 /* Set ring buffer size */
667 #ifdef __BIG_ENDIAN
668 RADEON_WRITE(RADEON_CP_RB_CNTL,
669 RADEON_BUF_SWAP_32BIT |
670 (dev_priv->ring.fetch_size_l2ow << 18) |
671 (dev_priv->ring.rptr_update_l2qw << 8) |
672 dev_priv->ring.size_l2qw);
673 #else
674 RADEON_WRITE(RADEON_CP_RB_CNTL,
675 (dev_priv->ring.fetch_size_l2ow << 18) |
676 (dev_priv->ring.rptr_update_l2qw << 8) |
677 dev_priv->ring.size_l2qw);
678 #endif
679
680
681 /* Initialize the scratch register pointer. This will cause
682 * the scratch register values to be written out to memory
683 * whenever they are updated.
684 *
685 * We simply put this behind the ring read pointer, this works
686 * with PCI GART as well as (whatever kind of) AGP GART
687 */
688 RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
689 + RADEON_SCRATCH_REG_OFFSET);
690
691 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
692
693 /* Turn on bus mastering */
694 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
695 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
696 /* rs600/rs690/rs740 */
697 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
698 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
699 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV350) ||
700 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
701 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
702 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
703 /* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
704 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
705 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
706 } /* PCIE cards appears to not need this */
707
708 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(0), 0);
709 RADEON_WRITE(RADEON_LAST_FRAME_REG, 0);
710
711 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
712 RADEON_WRITE(RADEON_LAST_DISPATCH_REG, 0);
713
714 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(2), 0);
715 RADEON_WRITE(RADEON_LAST_CLEAR_REG, 0);
716
717 /* reset sarea copies of these */
718 master_priv = file_priv->master->driver_priv;
719 if (master_priv->sarea_priv) {
720 master_priv->sarea_priv->last_frame = 0;
721 master_priv->sarea_priv->last_dispatch = 0;
722 master_priv->sarea_priv->last_clear = 0;
723 }
724
725 radeon_do_wait_for_idle(dev_priv);
726
727 /* Sync everything up */
728 RADEON_WRITE(RADEON_ISYNC_CNTL,
729 (RADEON_ISYNC_ANY2D_IDLE3D |
730 RADEON_ISYNC_ANY3D_IDLE2D |
731 RADEON_ISYNC_WAIT_IDLEGUI |
732 RADEON_ISYNC_CPSCRATCH_IDLEGUI));
733
734 }
735
736 static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
737 {
738 u32 tmp;
739
740 /* Start with assuming that writeback doesn't work */
741 dev_priv->writeback_works = 0;
742
743 /* Writeback doesn't seem to work everywhere, test it here and possibly
744 * enable it if it appears to work
745 */
746 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
747
748 RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
749
750 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
751 u32 val;
752
753 val = radeon_read_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1));
754 if (val == 0xdeadbeef)
755 break;
756 DRM_UDELAY(1);
757 }
758
759 if (tmp < dev_priv->usec_timeout) {
760 dev_priv->writeback_works = 1;
761 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
762 } else {
763 dev_priv->writeback_works = 0;
764 DRM_INFO("writeback test failed\n");
765 }
766 if (radeon_no_wb == 1) {
767 dev_priv->writeback_works = 0;
768 DRM_INFO("writeback forced off\n");
769 }
770
771 if (!dev_priv->writeback_works) {
772 /* Disable writeback to avoid unnecessary bus master transfer */
773 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) |
774 RADEON_RB_NO_UPDATE);
775 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
776 }
777 }
778
779 /* Enable or disable IGP GART on the chip */
780 static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
781 {
782 u32 temp;
783
784 if (on) {
785 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
786 dev_priv->gart_vm_start,
787 (long)dev_priv->gart_info.bus_addr,
788 dev_priv->gart_size);
789
790 temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
791 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
792 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
793 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |
794 RS690_BLOCK_GFX_D3_EN));
795 else
796 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
797
798 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
799 RS480_VA_SIZE_32MB));
800
801 temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID);
802 IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN |
803 RS480_TLB_ENABLE |
804 RS480_GTW_LAC_EN |
805 RS480_1LEVEL_GART));
806
807 temp = dev_priv->gart_info.bus_addr & 0xfffff000;
808 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
809 IGP_WRITE_MCIND(RS480_GART_BASE, temp);
810
811 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL);
812 IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |
813 RS480_REQ_TYPE_SNOOP_DIS));
814
815 radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start);
816
817 dev_priv->gart_size = 32*1024*1024;
818 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
819 0xffff0000) | (dev_priv->gart_vm_start >> 16));
820
821 radeon_write_agp_location(dev_priv, temp);
822
823 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);
824 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
825 RS480_VA_SIZE_32MB));
826
827 do {
828 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
829 if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
830 break;
831 DRM_UDELAY(1);
832 } while (1);
833
834 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL,
835 RS480_GART_CACHE_INVALIDATE);
836
837 do {
838 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
839 if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
840 break;
841 DRM_UDELAY(1);
842 } while (1);
843
844 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
845 } else {
846 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
847 }
848 }
849
850 static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
851 {
852 u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
853 if (on) {
854
855 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
856 dev_priv->gart_vm_start,
857 (long)dev_priv->gart_info.bus_addr,
858 dev_priv->gart_size);
859 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
860 dev_priv->gart_vm_start);
861 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
862 dev_priv->gart_info.bus_addr);
863 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
864 dev_priv->gart_vm_start);
865 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
866 dev_priv->gart_vm_start +
867 dev_priv->gart_size - 1);
868
869 radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */
870
871 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
872 RADEON_PCIE_TX_GART_EN);
873 } else {
874 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
875 tmp & ~RADEON_PCIE_TX_GART_EN);
876 }
877 }
878
879 /* Enable or disable PCI GART on the chip */
880 static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
881 {
882 u32 tmp;
883
884 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
885 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740) ||
886 (dev_priv->flags & RADEON_IS_IGPGART)) {
887 radeon_set_igpgart(dev_priv, on);
888 return;
889 }
890
891 if (dev_priv->flags & RADEON_IS_PCIE) {
892 radeon_set_pciegart(dev_priv, on);
893 return;
894 }
895
896 tmp = RADEON_READ(RADEON_AIC_CNTL);
897
898 if (on) {
899 RADEON_WRITE(RADEON_AIC_CNTL,
900 tmp | RADEON_PCIGART_TRANSLATE_EN);
901
902 /* set PCI GART page-table base address
903 */
904 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
905
906 /* set address range for PCI address translate
907 */
908 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
909 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
910 + dev_priv->gart_size - 1);
911
912 /* Turn off AGP aperture -- is this required for PCI GART?
913 */
914 radeon_write_agp_location(dev_priv, 0xffffffc0);
915 RADEON_WRITE(RADEON_AGP_COMMAND, 0); /* clear AGP_COMMAND */
916 } else {
917 RADEON_WRITE(RADEON_AIC_CNTL,
918 tmp & ~RADEON_PCIGART_TRANSLATE_EN);
919 }
920 }
921
922 static int radeon_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
923 struct drm_file *file_priv)
924 {
925 drm_radeon_private_t *dev_priv = dev->dev_private;
926 struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
927
928 DRM_DEBUG("\n");
929
930 /* if we require new memory map but we don't have it fail */
931 if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
932 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
933 radeon_do_cleanup_cp(dev);
934 return -EINVAL;
935 }
936
937 if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
938 DRM_DEBUG("Forcing AGP card to PCI mode\n");
939 dev_priv->flags &= ~RADEON_IS_AGP;
940 } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
941 && !init->is_pci) {
942 DRM_DEBUG("Restoring AGP flag\n");
943 dev_priv->flags |= RADEON_IS_AGP;
944 }
945
946 if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
947 DRM_ERROR("PCI GART memory not allocated!\n");
948 radeon_do_cleanup_cp(dev);
949 return -EINVAL;
950 }
951
952 dev_priv->usec_timeout = init->usec_timeout;
953 if (dev_priv->usec_timeout < 1 ||
954 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
955 DRM_DEBUG("TIMEOUT problem!\n");
956 radeon_do_cleanup_cp(dev);
957 return -EINVAL;
958 }
959
960 /* Enable vblank on CRTC1 for older X servers
961 */
962 dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
963
964 switch(init->func) {
965 case RADEON_INIT_R200_CP:
966 dev_priv->microcode_version = UCODE_R200;
967 break;
968 case RADEON_INIT_R300_CP:
969 dev_priv->microcode_version = UCODE_R300;
970 break;
971 default:
972 dev_priv->microcode_version = UCODE_R100;
973 }
974
975 dev_priv->do_boxes = 0;
976 dev_priv->cp_mode = init->cp_mode;
977
978 /* We don't support anything other than bus-mastering ring mode,
979 * but the ring can be in either AGP or PCI space for the ring
980 * read pointer.
981 */
982 if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
983 (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
984 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
985 radeon_do_cleanup_cp(dev);
986 return -EINVAL;
987 }
988
989 switch (init->fb_bpp) {
990 case 16:
991 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
992 break;
993 case 32:
994 default:
995 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
996 break;
997 }
998 dev_priv->front_offset = init->front_offset;
999 dev_priv->front_pitch = init->front_pitch;
1000 dev_priv->back_offset = init->back_offset;
1001 dev_priv->back_pitch = init->back_pitch;
1002
1003 switch (init->depth_bpp) {
1004 case 16:
1005 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1006 break;
1007 case 32:
1008 default:
1009 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1010 break;
1011 }
1012 dev_priv->depth_offset = init->depth_offset;
1013 dev_priv->depth_pitch = init->depth_pitch;
1014
1015 /* Hardware state for depth clears. Remove this if/when we no
1016 * longer clear the depth buffer with a 3D rectangle. Hard-code
1017 * all values to prevent unwanted 3D state from slipping through
1018 * and screwing with the clear operation.
1019 */
1020 dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1021 (dev_priv->color_fmt << 10) |
1022 (dev_priv->microcode_version ==
1023 UCODE_R100 ? RADEON_ZBLOCK16 : 0));
1024
1025 dev_priv->depth_clear.rb3d_zstencilcntl =
1026 (dev_priv->depth_fmt |
1027 RADEON_Z_TEST_ALWAYS |
1028 RADEON_STENCIL_TEST_ALWAYS |
1029 RADEON_STENCIL_S_FAIL_REPLACE |
1030 RADEON_STENCIL_ZPASS_REPLACE |
1031 RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
1032
1033 dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1034 RADEON_BFACE_SOLID |
1035 RADEON_FFACE_SOLID |
1036 RADEON_FLAT_SHADE_VTX_LAST |
1037 RADEON_DIFFUSE_SHADE_FLAT |
1038 RADEON_ALPHA_SHADE_FLAT |
1039 RADEON_SPECULAR_SHADE_FLAT |
1040 RADEON_FOG_SHADE_FLAT |
1041 RADEON_VTX_PIX_CENTER_OGL |
1042 RADEON_ROUND_MODE_TRUNC |
1043 RADEON_ROUND_PREC_8TH_PIX);
1044
1045
1046 dev_priv->ring_offset = init->ring_offset;
1047 dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1048 dev_priv->buffers_offset = init->buffers_offset;
1049 dev_priv->gart_textures_offset = init->gart_textures_offset;
1050
1051 master_priv->sarea = drm_getsarea(dev);
1052 if (!master_priv->sarea) {
1053 DRM_ERROR("could not find sarea!\n");
1054 radeon_do_cleanup_cp(dev);
1055 return -EINVAL;
1056 }
1057
1058 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1059 if (!dev_priv->cp_ring) {
1060 DRM_ERROR("could not find cp ring region!\n");
1061 radeon_do_cleanup_cp(dev);
1062 return -EINVAL;
1063 }
1064 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1065 if (!dev_priv->ring_rptr) {
1066 DRM_ERROR("could not find ring read pointer!\n");
1067 radeon_do_cleanup_cp(dev);
1068 return -EINVAL;
1069 }
1070 dev->agp_buffer_token = init->buffers_offset;
1071 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1072 if (!dev->agp_buffer_map) {
1073 DRM_ERROR("could not find dma buffer region!\n");
1074 radeon_do_cleanup_cp(dev);
1075 return -EINVAL;
1076 }
1077
1078 if (init->gart_textures_offset) {
1079 dev_priv->gart_textures =
1080 drm_core_findmap(dev, init->gart_textures_offset);
1081 if (!dev_priv->gart_textures) {
1082 DRM_ERROR("could not find GART texture region!\n");
1083 radeon_do_cleanup_cp(dev);
1084 return -EINVAL;
1085 }
1086 }
1087
1088 #if __OS_HAS_AGP
1089 if (dev_priv->flags & RADEON_IS_AGP) {
1090 drm_core_ioremap_wc(dev_priv->cp_ring, dev);
1091 drm_core_ioremap_wc(dev_priv->ring_rptr, dev);
1092 drm_core_ioremap_wc(dev->agp_buffer_map, dev);
1093 if (!dev_priv->cp_ring->handle ||
1094 !dev_priv->ring_rptr->handle ||
1095 !dev->agp_buffer_map->handle) {
1096 DRM_ERROR("could not find ioremap agp regions!\n");
1097 radeon_do_cleanup_cp(dev);
1098 return -EINVAL;
1099 }
1100 } else
1101 #endif
1102 {
1103 dev_priv->cp_ring->handle =
1104 (void *)(unsigned long)dev_priv->cp_ring->offset;
1105 dev_priv->ring_rptr->handle =
1106 (void *)(unsigned long)dev_priv->ring_rptr->offset;
1107 dev->agp_buffer_map->handle =
1108 (void *)(unsigned long)dev->agp_buffer_map->offset;
1109
1110 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1111 dev_priv->cp_ring->handle);
1112 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1113 dev_priv->ring_rptr->handle);
1114 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1115 dev->agp_buffer_map->handle);
1116 }
1117
1118 dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
1119 dev_priv->fb_size =
1120 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
1121 - dev_priv->fb_location;
1122
1123 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1124 ((dev_priv->front_offset
1125 + dev_priv->fb_location) >> 10));
1126
1127 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1128 ((dev_priv->back_offset
1129 + dev_priv->fb_location) >> 10));
1130
1131 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1132 ((dev_priv->depth_offset
1133 + dev_priv->fb_location) >> 10));
1134
1135 dev_priv->gart_size = init->gart_size;
1136
1137 /* New let's set the memory map ... */
1138 if (dev_priv->new_memmap) {
1139 u32 base = 0;
1140
1141 DRM_INFO("Setting GART location based on new memory map\n");
1142
1143 /* If using AGP, try to locate the AGP aperture at the same
1144 * location in the card and on the bus, though we have to
1145 * align it down.
1146 */
1147 #if __OS_HAS_AGP
1148 if (dev_priv->flags & RADEON_IS_AGP) {
1149 base = dev->agp->base;
1150 /* Check if valid */
1151 if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1152 base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
1153 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1154 dev->agp->base);
1155 base = 0;
1156 }
1157 }
1158 #endif
1159 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1160 if (base == 0) {
1161 base = dev_priv->fb_location + dev_priv->fb_size;
1162 if (base < dev_priv->fb_location ||
1163 ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1164 base = dev_priv->fb_location
1165 - dev_priv->gart_size;
1166 }
1167 dev_priv->gart_vm_start = base & 0xffc00000u;
1168 if (dev_priv->gart_vm_start != base)
1169 DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1170 base, dev_priv->gart_vm_start);
1171 } else {
1172 DRM_INFO("Setting GART location based on old memory map\n");
1173 dev_priv->gart_vm_start = dev_priv->fb_location +
1174 RADEON_READ(RADEON_CONFIG_APER_SIZE);
1175 }
1176
1177 #if __OS_HAS_AGP
1178 if (dev_priv->flags & RADEON_IS_AGP)
1179 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1180 - dev->agp->base
1181 + dev_priv->gart_vm_start);
1182 else
1183 #endif
1184 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1185 - (unsigned long)dev->sg->virtual
1186 + dev_priv->gart_vm_start);
1187
1188 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1189 DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1190 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1191 dev_priv->gart_buffers_offset);
1192
1193 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1194 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1195 + init->ring_size / sizeof(u32));
1196 dev_priv->ring.size = init->ring_size;
1197 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1198
1199 dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1200 dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
1201
1202 dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1203 dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
1204 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1205
1206 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1207
1208 #if __OS_HAS_AGP
1209 if (dev_priv->flags & RADEON_IS_AGP) {
1210 /* Turn off PCI GART */
1211 radeon_set_pcigart(dev_priv, 0);
1212 } else
1213 #endif
1214 {
1215 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
1216 /* if we have an offset set from userspace */
1217 if (dev_priv->pcigart_offset_set) {
1218 dev_priv->gart_info.bus_addr =
1219 (resource_size_t)dev_priv->pcigart_offset + dev_priv->fb_location;
1220 dev_priv->gart_info.mapping.offset =
1221 dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
1222 dev_priv->gart_info.mapping.size =
1223 dev_priv->gart_info.table_size;
1224
1225 drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev);
1226 dev_priv->gart_info.addr =
1227 dev_priv->gart_info.mapping.handle;
1228
1229 if (dev_priv->flags & RADEON_IS_PCIE)
1230 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
1231 else
1232 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1233 dev_priv->gart_info.gart_table_location =
1234 DRM_ATI_GART_FB;
1235
1236 DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
1237 dev_priv->gart_info.addr,
1238 dev_priv->pcigart_offset);
1239 } else {
1240 if (dev_priv->flags & RADEON_IS_IGPGART)
1241 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
1242 else
1243 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1244 dev_priv->gart_info.gart_table_location =
1245 DRM_ATI_GART_MAIN;
1246 dev_priv->gart_info.addr = NULL;
1247 dev_priv->gart_info.bus_addr = 0;
1248 if (dev_priv->flags & RADEON_IS_PCIE) {
1249 DRM_ERROR
1250 ("Cannot use PCI Express without GART in FB memory\n");
1251 radeon_do_cleanup_cp(dev);
1252 return -EINVAL;
1253 }
1254 }
1255
1256 if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
1257 DRM_ERROR("failed to init PCI GART!\n");
1258 radeon_do_cleanup_cp(dev);
1259 return -ENOMEM;
1260 }
1261
1262 /* Turn on PCI GART */
1263 radeon_set_pcigart(dev_priv, 1);
1264 }
1265
1266 radeon_cp_load_microcode(dev_priv);
1267 radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1268
1269 dev_priv->last_buf = 0;
1270
1271 radeon_do_engine_reset(dev);
1272 radeon_test_writeback(dev_priv);
1273
1274 return 0;
1275 }
1276
1277 static int radeon_do_cleanup_cp(struct drm_device * dev)
1278 {
1279 drm_radeon_private_t *dev_priv = dev->dev_private;
1280 DRM_DEBUG("\n");
1281
1282 /* Make sure interrupts are disabled here because the uninstall ioctl
1283 * may not have been called from userspace and after dev_private
1284 * is freed, it's too late.
1285 */
1286 if (dev->irq_enabled)
1287 drm_irq_uninstall(dev);
1288
1289 #if __OS_HAS_AGP
1290 if (dev_priv->flags & RADEON_IS_AGP) {
1291 if (dev_priv->cp_ring != NULL) {
1292 drm_core_ioremapfree(dev_priv->cp_ring, dev);
1293 dev_priv->cp_ring = NULL;
1294 }
1295 if (dev_priv->ring_rptr != NULL) {
1296 drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1297 dev_priv->ring_rptr = NULL;
1298 }
1299 if (dev->agp_buffer_map != NULL) {
1300 drm_core_ioremapfree(dev->agp_buffer_map, dev);
1301 dev->agp_buffer_map = NULL;
1302 }
1303 } else
1304 #endif
1305 {
1306
1307 if (dev_priv->gart_info.bus_addr) {
1308 /* Turn off PCI GART */
1309 radeon_set_pcigart(dev_priv, 0);
1310 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1311 DRM_ERROR("failed to cleanup PCI GART!\n");
1312 }
1313
1314 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1315 {
1316 drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1317 dev_priv->gart_info.addr = 0;
1318 }
1319 }
1320 /* only clear to the start of flags */
1321 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1322
1323 return 0;
1324 }
1325
1326 /* This code will reinit the Radeon CP hardware after a resume from disc.
1327 * AFAIK, it would be very difficult to pickle the state at suspend time, so
1328 * here we make sure that all Radeon hardware initialisation is re-done without
1329 * affecting running applications.
1330 *
1331 * Charl P. Botha <http://cpbotha.net>
1332 */
1333 static int radeon_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv)
1334 {
1335 drm_radeon_private_t *dev_priv = dev->dev_private;
1336
1337 if (!dev_priv) {
1338 DRM_ERROR("Called with no initialization\n");
1339 return -EINVAL;
1340 }
1341
1342 DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1343
1344 #if __OS_HAS_AGP
1345 if (dev_priv->flags & RADEON_IS_AGP) {
1346 /* Turn off PCI GART */
1347 radeon_set_pcigart(dev_priv, 0);
1348 } else
1349 #endif
1350 {
1351 /* Turn on PCI GART */
1352 radeon_set_pcigart(dev_priv, 1);
1353 }
1354
1355 radeon_cp_load_microcode(dev_priv);
1356 radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1357
1358 radeon_do_engine_reset(dev);
1359 radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
1360
1361 DRM_DEBUG("radeon_do_resume_cp() complete\n");
1362
1363 return 0;
1364 }
1365
1366 int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
1367 {
1368 drm_radeon_init_t *init = data;
1369
1370 LOCK_TEST_WITH_RETURN(dev, file_priv);
1371
1372 if (init->func == RADEON_INIT_R300_CP)
1373 r300_init_reg_flags(dev);
1374
1375 switch (init->func) {
1376 case RADEON_INIT_CP:
1377 case RADEON_INIT_R200_CP:
1378 case RADEON_INIT_R300_CP:
1379 return radeon_do_init_cp(dev, init, file_priv);
1380 case RADEON_CLEANUP_CP:
1381 return radeon_do_cleanup_cp(dev);
1382 }
1383
1384 return -EINVAL;
1385 }
1386
1387 int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
1388 {
1389 drm_radeon_private_t *dev_priv = dev->dev_private;
1390 DRM_DEBUG("\n");
1391
1392 LOCK_TEST_WITH_RETURN(dev, file_priv);
1393
1394 if (dev_priv->cp_running) {
1395 DRM_DEBUG("while CP running\n");
1396 return 0;
1397 }
1398 if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1399 DRM_DEBUG("called with bogus CP mode (%d)\n",
1400 dev_priv->cp_mode);
1401 return 0;
1402 }
1403
1404 radeon_do_cp_start(dev_priv);
1405
1406 return 0;
1407 }
1408
1409 /* Stop the CP. The engine must have been idled before calling this
1410 * routine.
1411 */
1412 int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
1413 {
1414 drm_radeon_private_t *dev_priv = dev->dev_private;
1415 drm_radeon_cp_stop_t *stop = data;
1416 int ret;
1417 DRM_DEBUG("\n");
1418
1419 LOCK_TEST_WITH_RETURN(dev, file_priv);
1420
1421 if (!dev_priv->cp_running)
1422 return 0;
1423
1424 /* Flush any pending CP commands. This ensures any outstanding
1425 * commands are exectuted by the engine before we turn it off.
1426 */
1427 if (stop->flush) {
1428 radeon_do_cp_flush(dev_priv);
1429 }
1430
1431 /* If we fail to make the engine go idle, we return an error
1432 * code so that the DRM ioctl wrapper can try again.
1433 */
1434 if (stop->idle) {
1435 ret = radeon_do_cp_idle(dev_priv);
1436 if (ret)
1437 return ret;
1438 }
1439
1440 /* Finally, we can turn off the CP. If the engine isn't idle,
1441 * we will get some dropped triangles as they won't be fully
1442 * rendered before the CP is shut down.
1443 */
1444 radeon_do_cp_stop(dev_priv);
1445
1446 /* Reset the engine */
1447 radeon_do_engine_reset(dev);
1448
1449 return 0;
1450 }
1451
1452 void radeon_do_release(struct drm_device * dev)
1453 {
1454 drm_radeon_private_t *dev_priv = dev->dev_private;
1455 int i, ret;
1456
1457 if (dev_priv) {
1458 if (dev_priv->cp_running) {
1459 /* Stop the cp */
1460 while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1461 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1462 #ifdef __linux__
1463 schedule();
1464 #else
1465 tsleep(&ret, PZERO, "rdnrel", 1);
1466 #endif
1467 }
1468 radeon_do_cp_stop(dev_priv);
1469 radeon_do_engine_reset(dev);
1470 }
1471
1472 /* Disable *all* interrupts */
1473 if (dev_priv->mmio) /* remove this after permanent addmaps */
1474 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1475
1476 if (dev_priv->mmio) { /* remove all surfaces */
1477 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1478 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
1479 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
1480 16 * i, 0);
1481 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
1482 16 * i, 0);
1483 }
1484 }
1485
1486 /* Free memory heap structures */
1487 radeon_mem_takedown(&(dev_priv->gart_heap));
1488 radeon_mem_takedown(&(dev_priv->fb_heap));
1489
1490 /* deallocate kernel resources */
1491 radeon_do_cleanup_cp(dev);
1492 }
1493 }
1494
1495 /* Just reset the CP ring. Called as part of an X Server engine reset.
1496 */
1497 int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1498 {
1499 drm_radeon_private_t *dev_priv = dev->dev_private;
1500 DRM_DEBUG("\n");
1501
1502 LOCK_TEST_WITH_RETURN(dev, file_priv);
1503
1504 if (!dev_priv) {
1505 DRM_DEBUG("called before init done\n");
1506 return -EINVAL;
1507 }
1508
1509 radeon_do_cp_reset(dev_priv);
1510
1511 /* The CP is no longer running after an engine reset */
1512 dev_priv->cp_running = 0;
1513
1514 return 0;
1515 }
1516
1517 int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
1518 {
1519 drm_radeon_private_t *dev_priv = dev->dev_private;
1520 DRM_DEBUG("\n");
1521
1522 LOCK_TEST_WITH_RETURN(dev, file_priv);
1523
1524 return radeon_do_cp_idle(dev_priv);
1525 }
1526
1527 /* Added by Charl P. Botha to call radeon_do_resume_cp().
1528 */
1529 int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
1530 {
1531 return radeon_do_resume_cp(dev, file_priv);
1532 }
1533
1534 int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1535 {
1536 DRM_DEBUG("\n");
1537
1538 LOCK_TEST_WITH_RETURN(dev, file_priv);
1539
1540 return radeon_do_engine_reset(dev);
1541 }
1542
1543 /* ================================================================
1544 * Fullscreen mode
1545 */
1546
1547 /* KW: Deprecated to say the least:
1548 */
1549 int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
1550 {
1551 return 0;
1552 }
1553
1554 /* ================================================================
1555 * Freelist management
1556 */
1557
1558 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1559 * bufs until freelist code is used. Note this hides a problem with
1560 * the scratch register * (used to keep track of last buffer
1561 * completed) being written to before * the last buffer has actually
1562 * completed rendering.
1563 *
1564 * KW: It's also a good way to find free buffers quickly.
1565 *
1566 * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1567 * sleep. However, bugs in older versions of radeon_accel.c mean that
1568 * we essentially have to do this, else old clients will break.
1569 *
1570 * However, it does leave open a potential deadlock where all the
1571 * buffers are held by other clients, which can't release them because
1572 * they can't get the lock.
1573 */
1574
1575 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1576 {
1577 struct drm_device_dma *dma = dev->dma;
1578 drm_radeon_private_t *dev_priv = dev->dev_private;
1579 drm_radeon_buf_priv_t *buf_priv;
1580 struct drm_buf *buf;
1581 int i, t;
1582 int start;
1583
1584 if (++dev_priv->last_buf >= dma->buf_count)
1585 dev_priv->last_buf = 0;
1586
1587 start = dev_priv->last_buf;
1588
1589 for (t = 0; t < dev_priv->usec_timeout; t++) {
1590 u32 done_age = GET_SCRATCH(dev_priv, 1);
1591 DRM_DEBUG("done_age = %d\n", done_age);
1592 for (i = start; i < dma->buf_count; i++) {
1593 buf = dma->buflist[i];
1594 buf_priv = buf->dev_private;
1595 if (buf->file_priv == NULL || (buf->pending &&
1596 buf_priv->age <=
1597 done_age)) {
1598 dev_priv->stats.requested_bufs++;
1599 buf->pending = 0;
1600 return buf;
1601 }
1602 start = 0;
1603 }
1604
1605 if (t) {
1606 DRM_UDELAY(1);
1607 dev_priv->stats.freelist_loops++;
1608 }
1609 }
1610
1611 DRM_DEBUG("returning NULL!\n");
1612 return NULL;
1613 }
1614
1615 #if 0
1616 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1617 {
1618 struct drm_device_dma *dma = dev->dma;
1619 drm_radeon_private_t *dev_priv = dev->dev_private;
1620 drm_radeon_buf_priv_t *buf_priv;
1621 struct drm_buf *buf;
1622 int i, t;
1623 int start;
1624 u32 done_age;
1625
1626 done_age = radeon_read_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1));
1627 if (++dev_priv->last_buf >= dma->buf_count)
1628 dev_priv->last_buf = 0;
1629
1630 start = dev_priv->last_buf;
1631 dev_priv->stats.freelist_loops++;
1632
1633 for (t = 0; t < 2; t++) {
1634 for (i = start; i < dma->buf_count; i++) {
1635 buf = dma->buflist[i];
1636 buf_priv = buf->dev_private;
1637 if (buf->file_priv == 0 || (buf->pending &&
1638 buf_priv->age <=
1639 done_age)) {
1640 dev_priv->stats.requested_bufs++;
1641 buf->pending = 0;
1642 return buf;
1643 }
1644 }
1645 start = 0;
1646 }
1647
1648 return NULL;
1649 }
1650 #endif
1651
1652 void radeon_freelist_reset(struct drm_device * dev)
1653 {
1654 struct drm_device_dma *dma = dev->dma;
1655 drm_radeon_private_t *dev_priv = dev->dev_private;
1656 int i;
1657
1658 dev_priv->last_buf = 0;
1659 for (i = 0; i < dma->buf_count; i++) {
1660 struct drm_buf *buf = dma->buflist[i];
1661 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1662 buf_priv->age = 0;
1663 }
1664 }
1665
1666 /* ================================================================
1667 * CP command submission
1668 */
1669
1670 int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
1671 {
1672 drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1673 int i;
1674 u32 last_head = GET_RING_HEAD(dev_priv);
1675
1676 for (i = 0; i < dev_priv->usec_timeout; i++) {
1677 u32 head = GET_RING_HEAD(dev_priv);
1678
1679 ring->space = (head - ring->tail) * sizeof(u32);
1680 if (ring->space <= 0)
1681 ring->space += ring->size;
1682 if (ring->space > n)
1683 return 0;
1684
1685 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1686
1687 if (head != last_head)
1688 i = 0;
1689 last_head = head;
1690
1691 DRM_UDELAY(1);
1692 }
1693
1694 /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1695 #if RADEON_FIFO_DEBUG
1696 radeon_status(dev_priv);
1697 DRM_ERROR("failed!\n");
1698 #endif
1699 return -EBUSY;
1700 }
1701
1702 static int radeon_cp_get_buffers(struct drm_device *dev,
1703 struct drm_file *file_priv,
1704 struct drm_dma * d)
1705 {
1706 int i;
1707 struct drm_buf *buf;
1708
1709 for (i = d->granted_count; i < d->request_count; i++) {
1710 buf = radeon_freelist_get(dev);
1711 if (!buf)
1712 return -EBUSY; /* NOTE: broken client */
1713
1714 buf->file_priv = file_priv;
1715
1716 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
1717 sizeof(buf->idx)))
1718 return -EFAULT;
1719 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
1720 sizeof(buf->total)))
1721 return -EFAULT;
1722
1723 d->granted_count++;
1724 }
1725 return 0;
1726 }
1727
1728 int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
1729 {
1730 struct drm_device_dma *dma = dev->dma;
1731 int ret = 0;
1732 struct drm_dma *d = data;
1733
1734 LOCK_TEST_WITH_RETURN(dev, file_priv);
1735
1736 /* Please don't send us buffers.
1737 */
1738 if (d->send_count != 0) {
1739 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
1740 DRM_CURRENTPID, d->send_count);
1741 return -EINVAL;
1742 }
1743
1744 /* We'll send you buffers.
1745 */
1746 if (d->request_count < 0 || d->request_count > dma->buf_count) {
1747 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
1748 DRM_CURRENTPID, d->request_count, dma->buf_count);
1749 return -EINVAL;
1750 }
1751
1752 d->granted_count = 0;
1753
1754 if (d->request_count) {
1755 ret = radeon_cp_get_buffers(dev, file_priv, d);
1756 }
1757
1758 return ret;
1759 }
1760
1761 int radeon_driver_load(struct drm_device *dev, unsigned long flags)
1762 {
1763 drm_radeon_private_t *dev_priv;
1764 int ret = 0;
1765
1766 dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER);
1767 if (dev_priv == NULL)
1768 return -ENOMEM;
1769
1770 memset(dev_priv, 0, sizeof(drm_radeon_private_t));
1771 dev->dev_private = (void *)dev_priv;
1772 dev_priv->flags = flags;
1773
1774 switch (flags & RADEON_FAMILY_MASK) {
1775 case CHIP_R100:
1776 case CHIP_RV200:
1777 case CHIP_R200:
1778 case CHIP_R300:
1779 case CHIP_R350:
1780 case CHIP_R420:
1781 case CHIP_R423:
1782 case CHIP_RV410:
1783 case CHIP_RV515:
1784 case CHIP_R520:
1785 case CHIP_RV570:
1786 case CHIP_R580:
1787 dev_priv->flags |= RADEON_HAS_HIERZ;
1788 break;
1789 default:
1790 /* all other chips have no hierarchical z buffer */
1791 break;
1792 }
1793
1794 if (drm_device_is_agp(dev))
1795 dev_priv->flags |= RADEON_IS_AGP;
1796 else if (drm_device_is_pcie(dev))
1797 dev_priv->flags |= RADEON_IS_PCIE;
1798 else
1799 dev_priv->flags |= RADEON_IS_PCI;
1800
1801 ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
1802 drm_get_resource_len(dev, 2), _DRM_REGISTERS,
1803 _DRM_READ_ONLY | _DRM_DRIVER, &dev_priv->mmio);
1804 if (ret != 0)
1805 return ret;
1806
1807 ret = drm_vblank_init(dev, 2);
1808 if (ret) {
1809 radeon_driver_unload(dev);
1810 return ret;
1811 }
1812
1813 DRM_DEBUG("%s card detected\n",
1814 ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
1815 return ret;
1816 }
1817
1818 int radeon_master_create(struct drm_device *dev, struct drm_master *master)
1819 {
1820 struct drm_radeon_master_private *master_priv;
1821 unsigned long sareapage;
1822 int ret;
1823
1824 master_priv = drm_calloc(1, sizeof(*master_priv), DRM_MEM_DRIVER);
1825 if (!master_priv)
1826 return -ENOMEM;
1827
1828 /* prebuild the SAREA */
1829 sareapage = max_t(unsigned long, SAREA_MAX, PAGE_SIZE);
1830 ret = drm_addmap(dev, 0, sareapage, _DRM_SHM, _DRM_CONTAINS_LOCK|_DRM_DRIVER,
1831 &master_priv->sarea);
1832 if (ret) {
1833 DRM_ERROR("SAREA setup failed\n");
1834 return ret;
1835 }
1836 master_priv->sarea_priv = master_priv->sarea->handle + sizeof(struct drm_sarea);
1837 master_priv->sarea_priv->pfCurrentPage = 0;
1838
1839 master->driver_priv = master_priv;
1840 return 0;
1841 }
1842
1843 void radeon_master_destroy(struct drm_device *dev, struct drm_master *master)
1844 {
1845 struct drm_radeon_master_private *master_priv = master->driver_priv;
1846
1847 if (!master_priv)
1848 return;
1849
1850 if (master_priv->sarea_priv &&
1851 master_priv->sarea_priv->pfCurrentPage != 0)
1852 radeon_cp_dispatch_flip(dev, master);
1853
1854 master_priv->sarea_priv = NULL;
1855 if (master_priv->sarea)
1856 drm_rmmap_locked(dev, master_priv->sarea);
1857
1858 drm_free(master_priv, sizeof(*master_priv), DRM_MEM_DRIVER);
1859
1860 master->driver_priv = NULL;
1861 }
1862
1863 /* Create mappings for registers and framebuffer so userland doesn't necessarily
1864 * have to find them.
1865 */
1866 int radeon_driver_firstopen(struct drm_device *dev)
1867 {
1868 int ret;
1869 drm_local_map_t *map;
1870 drm_radeon_private_t *dev_priv = dev->dev_private;
1871
1872 dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
1873
1874 dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0);
1875 ret = drm_addmap(dev, dev_priv->fb_aper_offset,
1876 drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER,
1877 _DRM_WRITE_COMBINING, &map);
1878 if (ret != 0)
1879 return ret;
1880
1881 return 0;
1882 }
1883
1884 int radeon_driver_unload(struct drm_device *dev)
1885 {
1886 drm_radeon_private_t *dev_priv = dev->dev_private;
1887
1888 DRM_DEBUG("\n");
1889
1890 drm_rmmap(dev, dev_priv->mmio);
1891
1892 drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
1893
1894 dev->dev_private = NULL;
1895 return 0;
1896 }
kernel-based virtual machine