arch/blackfin/kernel/cplb-nompu/cacheinit.c

   1 /*
   2  *               Copyright 2004-2007 Analog Devices Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, see the file COPYING, or write
  16  * to the Free Software Foundation, Inc.,
  17  * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  18  */
  19
  20 #include <linux/cpu.h>
  21
  22 #include <asm/cacheflush.h>
  23 #include <asm/blackfin.h>
  24 #include <asm/cplb.h>
  25 #include <asm/cplbinit.h>
  26
  27 #if defined(CONFIG_BFIN_ICACHE)
  28 void __cpuinit bfin_icache_init(struct cplb_entry *icplb_tbl)
  29 {
  30         unsigned long ctrl;
  31         int i;
  32
  33         for (i = 0; i < MAX_CPLBS; i++) {
  34                 bfin_write32(ICPLB_ADDR0 + i * 4, icplb_tbl[i].addr);
  35                 bfin_write32(ICPLB_DATA0 + i * 4, icplb_tbl[i].data);
  36         }
  37         ctrl = bfin_read_IMEM_CONTROL();
  38         ctrl |= IMC | ENICPLB;
  39         /* CSYNC to ensure load store ordering */
  40         CSYNC();
  41         bfin_write_IMEM_CONTROL(ctrl);
  42         SSYNC();
  43 }
  44 #endif
  45
  46 #if defined(CONFIG_BFIN_DCACHE)
  47 void __cpuinit bfin_dcache_init(struct cplb_entry *dcplb_tbl)
  48 {
  49         unsigned long ctrl;
  50         int i;
  51
  52         for (i = 0; i < MAX_CPLBS; i++) {
  53                 bfin_write32(DCPLB_ADDR0 + i * 4, dcplb_tbl[i].addr);
  54                 bfin_write32(DCPLB_DATA0 + i * 4, dcplb_tbl[i].data);
  55         }
  56
  57         ctrl = bfin_read_DMEM_CONTROL();
  58
  59         /*
  60          *  Anomaly notes:
  61          *  05000287 - We implement workaround #2 - Change the DMEM_CONTROL
  62          *  register, so that the port preferences for DAG0 and DAG1 are set
  63          *  to port B
  64          */
  65         ctrl |= DMEM_CNTR | PORT_PREF0 | (ANOMALY_05000287 ? PORT_PREF1 : 0);
  66         /* CSYNC to ensure load store ordering */
  67         CSYNC();
  68         bfin_write_DMEM_CONTROL(ctrl);
  69         SSYNC();
  70 }
  71 #endif