arch/arm/mach-omap2/prm-regbits-24xx.h

   1 #ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_24XX_H
   2 #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_24XX_H
   3
   4 /*
   5  * OMAP24XX Power/Reset Management register bits
   6  *
   7  * Copyright (C) 2007 Texas Instruments, Inc.
   8  * Copyright (C) 2007 Nokia Corporation
   9  *
  10  * Written by Paul Walmsley
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  */
  16
  17 #include "prm.h"
  18
  19 /* Bits shared between registers */
  20
  21 /* PRCM_IRQSTATUS_MPU, PM_IRQSTATUS_DSP, PRCM_IRQSTATUS_IVA shared bits */
  22 #define OMAP24XX_VOLTTRANS_ST                           (1 << 2)
  23 #define OMAP24XX_WKUP2_ST                               (1 << 1)
  24 #define OMAP24XX_WKUP1_ST                               (1 << 0)
  25
  26 /* PRCM_IRQENABLE_MPU, PM_IRQENABLE_DSP, PRCM_IRQENABLE_IVA shared bits */
  27 #define OMAP24XX_VOLTTRANS_EN                           (1 << 2)
  28 #define OMAP24XX_WKUP2_EN                               (1 << 1)
  29 #define OMAP24XX_WKUP1_EN                               (1 << 0)
  30
  31 /* PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_DSP, PM_WKDEP_MDM shared bits */
  32 #define OMAP24XX_EN_MPU                                 (1 << 1)
  33 #define OMAP24XX_EN_CORE                                (1 << 0)
  34
  35 /*
  36  * PM_PWSTCTRL_MPU, PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM
  37  * shared bits
  38  */
  39 #define OMAP24XX_MEMONSTATE_SHIFT                       10
  40 #define OMAP24XX_MEMONSTATE_MASK                        (0x3 << 10)
  41 #define OMAP24XX_MEMRETSTATE                            (1 << 3)
  42
  43 /* PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM shared bits */
  44 #define OMAP24XX_FORCESTATE                             (1 << 18)
  45
  46 /*
  47  * PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP,
  48  * PM_PWSTST_MDM shared bits
  49  */
  50 #define OMAP24XX_CLKACTIVITY                            (1 << 19)
  51
  52 /* PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_DSP shared bits */
  53 #define OMAP24XX_LASTSTATEENTERED_SHIFT                 4
  54 #define OMAP24XX_LASTSTATEENTERED_MASK                  (0x3 << 4)
  55
  56 /* PM_PWSTST_MPU and PM_PWSTST_DSP shared bits */
  57 #define OMAP2430_MEMSTATEST_SHIFT                       10
  58 #define OMAP2430_MEMSTATEST_MASK                        (0x3 << 10)
  59
  60 /* PM_PWSTST_GFX, PM_PWSTST_DSP, PM_PWSTST_MDM shared bits */
  61 #define OMAP24XX_POWERSTATEST_SHIFT                     0
  62 #define OMAP24XX_POWERSTATEST_MASK                      (0x3 << 0)
  63
  64
  65 /* Bits specific to each register */
  66
  67 /* PRCM_REVISION */
  68 #define OMAP24XX_REV_SHIFT                              0
  69 #define OMAP24XX_REV_MASK                               (0xff << 0)
  70
  71 /* PRCM_SYSCONFIG */
  72 #define OMAP24XX_AUTOIDLE                               (1 << 0)
  73
  74 /* PRCM_IRQSTATUS_MPU specific bits */
  75 #define OMAP2430_DPLL_RECAL_ST                          (1 << 6)
  76 #define OMAP24XX_TRANSITION_ST                          (1 << 5)
  77 #define OMAP24XX_EVGENOFF_ST                            (1 << 4)
  78 #define OMAP24XX_EVGENON_ST                             (1 << 3)
  79
  80 /* PRCM_IRQENABLE_MPU specific bits */
  81 #define OMAP2430_DPLL_RECAL_EN                          (1 << 6)
  82 #define OMAP24XX_TRANSITION_EN                          (1 << 5)
  83 #define OMAP24XX_EVGENOFF_EN                            (1 << 4)
  84 #define OMAP24XX_EVGENON_EN                             (1 << 3)
  85
  86 /* PRCM_VOLTCTRL */
  87 #define OMAP24XX_AUTO_EXTVOLT                           (1 << 15)
  88 #define OMAP24XX_FORCE_EXTVOLT                          (1 << 14)
  89 #define OMAP24XX_SETOFF_LEVEL_SHIFT                     12
  90 #define OMAP24XX_SETOFF_LEVEL_MASK                      (0x3 << 12)
  91 #define OMAP24XX_MEMRETCTRL                             (1 << 8)
  92 #define OMAP24XX_SETRET_LEVEL_SHIFT                     6
  93 #define OMAP24XX_SETRET_LEVEL_MASK                      (0x3 << 6)
  94 #define OMAP24XX_VOLT_LEVEL_SHIFT                       0
  95 #define OMAP24XX_VOLT_LEVEL_MASK                        (0x3 << 0)
  96
  97 /* PRCM_VOLTST */
  98 #define OMAP24XX_ST_VOLTLEVEL_SHIFT                     0
  99 #define OMAP24XX_ST_VOLTLEVEL_MASK                      (0x3 << 0)
 100
 101 /* PRCM_CLKSRC_CTRL specific bits */
 102
 103 /* PRCM_CLKOUT_CTRL */
 104 #define OMAP2420_CLKOUT2_EN_SHIFT                       15
 105 #define OMAP2420_CLKOUT2_EN                             (1 << 15)
 106 #define OMAP2420_CLKOUT2_DIV_SHIFT                      11
 107 #define OMAP2420_CLKOUT2_DIV_MASK                       (0x7 << 11)
 108 #define OMAP2420_CLKOUT2_SOURCE_SHIFT                   8
 109 #define OMAP2420_CLKOUT2_SOURCE_MASK                    (0x3 << 8)
 110 #define OMAP24XX_CLKOUT_EN_SHIFT                        7
 111 #define OMAP24XX_CLKOUT_EN                              (1 << 7)
 112 #define OMAP24XX_CLKOUT_DIV_SHIFT                       3
 113 #define OMAP24XX_CLKOUT_DIV_MASK                        (0x7 << 3)
 114 #define OMAP24XX_CLKOUT_SOURCE_SHIFT                    0
 115 #define OMAP24XX_CLKOUT_SOURCE_MASK                     (0x3 << 0)
 116
 117 /* PRCM_CLKEMUL_CTRL */
 118 #define OMAP24XX_EMULATION_EN_SHIFT                     0
 119 #define OMAP24XX_EMULATION_EN                           (1 << 0)
 120
 121 /* PRCM_CLKCFG_CTRL */
 122 #define OMAP24XX_VALID_CONFIG                           (1 << 0)
 123
 124 /* PRCM_CLKCFG_STATUS */
 125 #define OMAP24XX_CONFIG_STATUS                          (1 << 0)
 126
 127 /* PRCM_VOLTSETUP specific bits */
 128
 129 /* PRCM_CLKSSETUP specific bits */
 130
 131 /* PRCM_POLCTRL */
 132 #define OMAP2420_CLKOUT2_POL                            (1 << 10)
 133 #define OMAP24XX_CLKOUT_POL                             (1 << 9)
 134 #define OMAP24XX_CLKREQ_POL                             (1 << 8)
 135 #define OMAP2430_USE_POWEROK                            (1 << 2)
 136 #define OMAP2430_POWEROK_POL                            (1 << 1)
 137 #define OMAP24XX_EXTVOL_POL                             (1 << 0)
 138
 139 /* RM_RSTST_MPU specific bits */
 140 /* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" instead */
 141
 142 /* PM_WKDEP_MPU specific bits */
 143 #define OMAP2430_PM_WKDEP_MPU_EN_MDM                    (1 << 5)
 144 #define OMAP24XX_PM_WKDEP_MPU_EN_DSP                    (1 << 2)
 145
 146 /* PM_EVGENCTRL_MPU specific bits */
 147
 148 /* PM_EVEGENONTIM_MPU specific bits */
 149
 150 /* PM_EVEGENOFFTIM_MPU specific bits */
 151
 152 /* PM_PWSTCTRL_MPU specific bits */
 153 #define OMAP2430_FORCESTATE                             (1 << 18)
 154
 155 /* PM_PWSTST_MPU specific bits */
 156 /* INTRANSITION, CLKACTIVITY, POWERSTATE, MEMSTATEST are 2430 only */
 157
 158 /* PM_WKEN1_CORE specific bits */
 159
 160 /* PM_WKEN2_CORE specific bits */
 161
 162 /* PM_WKST1_CORE specific bits*/
 163
 164 /* PM_WKST2_CORE specific bits */
 165
 166 /* PM_WKDEP_CORE specific bits*/
 167 #define OMAP2430_PM_WKDEP_CORE_EN_MDM                   (1 << 5)
 168 #define OMAP24XX_PM_WKDEP_CORE_EN_GFX                   (1 << 3)
 169 #define OMAP24XX_PM_WKDEP_CORE_EN_DSP                   (1 << 2)
 170
 171 /* PM_PWSTCTRL_CORE specific bits */
 172 #define OMAP24XX_MEMORYCHANGE                           (1 << 20)
 173 #define OMAP24XX_MEM3ONSTATE_SHIFT                      14
 174 #define OMAP24XX_MEM3ONSTATE_MASK                       (0x3 << 14)
 175 #define OMAP24XX_MEM2ONSTATE_SHIFT                      12
 176 #define OMAP24XX_MEM2ONSTATE_MASK                       (0x3 << 12)
 177 #define OMAP24XX_MEM1ONSTATE_SHIFT                      10
 178 #define OMAP24XX_MEM1ONSTATE_MASK                       (0x3 << 10)
 179 #define OMAP24XX_MEM3RETSTATE                           (1 << 5)
 180 #define OMAP24XX_MEM2RETSTATE                           (1 << 4)
 181 #define OMAP24XX_MEM1RETSTATE                           (1 << 3)
 182
 183 /* PM_PWSTST_CORE specific bits */
 184 #define OMAP24XX_MEM3STATEST_SHIFT                      14
 185 #define OMAP24XX_MEM3STATEST_MASK                       (0x3 << 14)
 186 #define OMAP24XX_MEM2STATEST_SHIFT                      12
 187 #define OMAP24XX_MEM2STATEST_MASK                       (0x3 << 12)
 188 #define OMAP24XX_MEM1STATEST_SHIFT                      10
 189 #define OMAP24XX_MEM1STATEST_MASK                       (0x3 << 10)
 190
 191 /* RM_RSTCTRL_GFX */
 192 #define OMAP24XX_GFX_RST                                (1 << 0)
 193
 194 /* RM_RSTST_GFX specific bits */
 195 #define OMAP24XX_GFX_SW_RST                             (1 << 4)
 196
 197 /* PM_PWSTCTRL_GFX specific bits */
 198
 199 /* PM_WKDEP_GFX specific bits */
 200 /* 2430 often calls EN_WAKEUP "EN_WKUP" */
 201
 202 /* RM_RSTCTRL_WKUP specific bits */
 203
 204 /* RM_RSTTIME_WKUP specific bits */
 205
 206 /* RM_RSTST_WKUP specific bits */
 207 /* 2430 calls EXTWMPU_RST "EXTWARM_RST" and GLOBALWMPU_RST "GLOBALWARM_RST" */
 208 #define OMAP24XX_EXTWMPU_RST                            (1 << 6)
 209 #define OMAP24XX_SECU_WD_RST                            (1 << 5)
 210 #define OMAP24XX_MPU_WD_RST                             (1 << 4)
 211 #define OMAP24XX_SECU_VIOL_RST                          (1 << 3)
 212
 213 /* PM_WKEN_WKUP specific bits */
 214
 215 /* PM_WKST_WKUP specific bits */
 216
 217 /* RM_RSTCTRL_DSP */
 218 #define OMAP2420_RST_IVA                                (1 << 8)
 219 #define OMAP24XX_RST2_DSP                               (1 << 1)
 220 #define OMAP24XX_RST1_DSP                               (1 << 0)
 221
 222 /* RM_RSTST_DSP specific bits */
 223 /* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" */
 224 #define OMAP2420_IVA_SW_RST                             (1 << 8)
 225 #define OMAP24XX_DSP_SW_RST2                            (1 << 5)
 226 #define OMAP24XX_DSP_SW_RST1                            (1 << 4)
 227
 228 /* PM_WKDEP_DSP specific bits */
 229
 230 /* PM_PWSTCTRL_DSP specific bits */
 231 /* 2430 only: MEMONSTATE, MEMRETSTATE */
 232 #define OMAP2420_MEMIONSTATE_SHIFT                      12
 233 #define OMAP2420_MEMIONSTATE_MASK                       (0x3 << 12)
 234 #define OMAP2420_MEMIRETSTATE                           (1 << 4)
 235
 236 /* PM_PWSTST_DSP specific bits */
 237 /* MEMSTATEST is 2430 only */
 238 #define OMAP2420_MEMISTATEST_SHIFT                      12
 239 #define OMAP2420_MEMISTATEST_MASK                       (0x3 << 12)
 240
 241 /* PRCM_IRQSTATUS_DSP specific bits */
 242
 243 /* PRCM_IRQENABLE_DSP specific bits */
 244
 245 /* RM_RSTCTRL_MDM */
 246 /* 2430 only */
 247 #define OMAP2430_PWRON1_MDM                             (1 << 1)
 248 #define OMAP2430_RST1_MDM                               (1 << 0)
 249
 250 /* RM_RSTST_MDM specific bits */
 251 /* 2430 only */
 252 #define OMAP2430_MDM_SECU_VIOL                          (1 << 6)
 253 #define OMAP2430_MDM_SW_PWRON1                          (1 << 5)
 254 #define OMAP2430_MDM_SW_RST1                            (1 << 4)
 255
 256 /* PM_WKEN_MDM */
 257 /* 2430 only */
 258 #define OMAP2430_PM_WKEN_MDM_EN_MDM                     (1 << 0)
 259
 260 /* PM_WKST_MDM specific bits */
 261 /* 2430 only */
 262
 263 /* PM_WKDEP_MDM specific bits */
 264 /* 2430 only */
 265
 266 /* PM_PWSTCTRL_MDM specific bits */
 267 /* 2430 only */
 268 #define OMAP2430_KILLDOMAINWKUP                         (1 << 19)
 269
 270 /* PM_PWSTST_MDM specific bits */
 271 /* 2430 only */
 272
 273 /* PRCM_IRQSTATUS_IVA */
 274 /* 2420 only */
 275
 276 /* PRCM_IRQENABLE_IVA */
 277 /* 2420 only */
 278
 279 #endif