2 * linux/arch/arm/mach-omap2/sdrc2xxx.c
4 * SDRAM timing related functions for OMAP2xxx
6 * Copyright (C) 2005, 2008 Texas Instruments Inc.
7 * Copyright (C) 2005, 2008 Nokia Corporation
9 * Tony Lindgren <tony@atomide.com>
11 * Richard Woodruff <r-woodruff2@ti.com>
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/device.h>
21 #include <linux/list.h>
22 #include <linux/errno.h>
23 #include <linux/delay.h>
24 #include <linux/clk.h>
27 #include <mach/common.h>
28 #include <mach/clock.h>
29 #include <mach/sram.h>
33 #include <mach/sdrc.h>
36 /* Memory timing, DLL mode flags */
38 #define M_LOCK_CTRL (1 << 2)
43 static struct memory_timings mem_timings
;
44 static u32 curr_perf_level
= CORE_CLK_SRC_DPLL_X2
;
46 static u32
omap2xxx_sdrc_get_slow_dll_ctrl(void)
48 return mem_timings
.slow_dll_ctrl
;
51 static u32
omap2xxx_sdrc_get_fast_dll_ctrl(void)
53 return mem_timings
.fast_dll_ctrl
;
56 static u32
omap2xxx_sdrc_get_type(void)
58 return mem_timings
.m_type
;
62 * Check the DLL lock state, and return tue if running in unlock mode.
63 * This is needed to compensate for the shifted DLL value in unlock mode.
65 u32
omap2xxx_sdrc_dll_is_unlocked(void)
67 /* dlla and dllb are a set */
68 u32 dll_state
= sdrc_read_reg(SDRC_DLLA_CTRL
);
70 if ((dll_state
& (1 << 2)) == (1 << 2))
77 * 'level' is the value to store to CM_CLKSEL2_PLL.CORE_CLK_SRC.
78 * Practical values are CORE_CLK_SRC_DPLL (for CORE_CLK = DPLL_CLK) or
79 * CORE_CLK_SRC_DPLL_X2 (for CORE_CLK = * DPLL_CLK * 2)
81 * Used by the clock framework during CORE DPLL changes
83 u32
omap2xxx_sdrc_reprogram(u32 level
, u32 force
)
86 u32 prev
= curr_perf_level
;
89 if ((curr_perf_level
== level
) && !force
)
92 if (level
== CORE_CLK_SRC_DPLL
)
93 dll_ctrl
= omap2xxx_sdrc_get_slow_dll_ctrl();
94 else if (level
== CORE_CLK_SRC_DPLL_X2
)
95 dll_ctrl
= omap2xxx_sdrc_get_fast_dll_ctrl();
99 m_type
= omap2xxx_sdrc_get_type();
101 local_irq_save(flags
);
102 __raw_writel(0xffff, OMAP24XX_PRCM_VOLTSETUP
);
103 omap2_sram_reprogram_sdrc(level
, dll_ctrl
, m_type
);
104 curr_perf_level
= level
;
105 local_irq_restore(flags
);
110 /* Used by the clock framework during CORE DPLL changes */
111 void omap2xxx_sdrc_init_params(u32 force_lock_to_unlock_mode
)
113 unsigned long dll_cnt
;
116 /* DDR = 1, SDR = 0 */
117 mem_timings
.m_type
= !((sdrc_read_reg(SDRC_MR_0
) & 0x3) == 0x1);
119 /* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others.
120 * In the case of 2422, its ok to use CS1 instead of CS0.
122 if (cpu_is_omap2422())
123 mem_timings
.base_cs
= 1;
125 mem_timings
.base_cs
= 0;
127 if (mem_timings
.m_type
!= M_DDR
)
130 /* With DDR we need to determine the low frequency DLL value */
131 if (((mem_timings
.fast_dll_ctrl
& (1 << 2)) == M_LOCK_CTRL
))
132 mem_timings
.dll_mode
= M_UNLOCK
;
134 mem_timings
.dll_mode
= M_LOCK
;
136 if (mem_timings
.base_cs
== 0) {
137 fast_dll
= sdrc_read_reg(SDRC_DLLA_CTRL
);
138 dll_cnt
= sdrc_read_reg(SDRC_DLLA_STATUS
) & 0xff00;
140 fast_dll
= sdrc_read_reg(SDRC_DLLB_CTRL
);
141 dll_cnt
= sdrc_read_reg(SDRC_DLLB_STATUS
) & 0xff00;
143 if (force_lock_to_unlock_mode
) {
145 fast_dll
|= dll_cnt
; /* Current lock mode */
147 /* set fast timings with DLL filter disabled */
148 mem_timings
.fast_dll_ctrl
= (fast_dll
| (3 << 8));
150 /* No disruptions, DDR will be offline & C-ABI not followed */
151 omap2_sram_ddr_init(&mem_timings
.slow_dll_ctrl
,
152 mem_timings
.fast_dll_ctrl
,
154 force_lock_to_unlock_mode
);
155 mem_timings
.slow_dll_ctrl
&= 0xff00; /* Keep lock value */
157 /* Turn status into unlock ctrl */
158 mem_timings
.slow_dll_ctrl
|=
159 ((mem_timings
.fast_dll_ctrl
& 0xF) | (1 << 2));
161 /* 90 degree phase for anything below 133Mhz + disable DLL filter */
162 mem_timings
.slow_dll_ctrl
|= ((1 << 1) | (3 << 8));