3 Broadcom B43 wireless driver
5 DMA ringbuffer and descriptor allocation/management
7 Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
9 Some code in this file is derived from the b44.c driver
10 Copyright (C) 2002 David S. Miller
11 Copyright (C) Pekka Pietikainen
13 This program is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 2 of the License, or
16 (at your option) any later version.
18 This program is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with this program; see the file COPYING. If not, write to
25 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
26 Boston, MA 02110-1301, USA.
36 #include <linux/dma-mapping.h>
37 #include <linux/pci.h>
38 #include <linux/delay.h>
39 #include <linux/skbuff.h>
40 #include <linux/etherdevice.h>
41 #include <asm/div64.h>
46 struct b43_dmadesc_generic
*op32_idx2desc(struct b43_dmaring
*ring
,
48 struct b43_dmadesc_meta
**meta
)
50 struct b43_dmadesc32
*desc
;
52 *meta
= &(ring
->meta
[slot
]);
53 desc
= ring
->descbase
;
56 return (struct b43_dmadesc_generic
*)desc
;
59 static void op32_fill_descriptor(struct b43_dmaring
*ring
,
60 struct b43_dmadesc_generic
*desc
,
61 dma_addr_t dmaaddr
, u16 bufsize
,
62 int start
, int end
, int irq
)
64 struct b43_dmadesc32
*descbase
= ring
->descbase
;
70 slot
= (int)(&(desc
->dma32
) - descbase
);
71 B43_WARN_ON(!(slot
>= 0 && slot
< ring
->nr_slots
));
73 addr
= (u32
) (dmaaddr
& ~SSB_DMA_TRANSLATION_MASK
);
74 addrext
= (u32
) (dmaaddr
& SSB_DMA_TRANSLATION_MASK
)
75 >> SSB_DMA_TRANSLATION_SHIFT
;
76 addr
|= ssb_dma_translation(ring
->dev
->dev
);
77 ctl
= (bufsize
- ring
->frameoffset
)
78 & B43_DMA32_DCTL_BYTECNT
;
79 if (slot
== ring
->nr_slots
- 1)
80 ctl
|= B43_DMA32_DCTL_DTABLEEND
;
82 ctl
|= B43_DMA32_DCTL_FRAMESTART
;
84 ctl
|= B43_DMA32_DCTL_FRAMEEND
;
86 ctl
|= B43_DMA32_DCTL_IRQ
;
87 ctl
|= (addrext
<< B43_DMA32_DCTL_ADDREXT_SHIFT
)
88 & B43_DMA32_DCTL_ADDREXT_MASK
;
90 desc
->dma32
.control
= cpu_to_le32(ctl
);
91 desc
->dma32
.address
= cpu_to_le32(addr
);
94 static void op32_poke_tx(struct b43_dmaring
*ring
, int slot
)
96 b43_dma_write(ring
, B43_DMA32_TXINDEX
,
97 (u32
) (slot
* sizeof(struct b43_dmadesc32
)));
100 static void op32_tx_suspend(struct b43_dmaring
*ring
)
102 b43_dma_write(ring
, B43_DMA32_TXCTL
, b43_dma_read(ring
, B43_DMA32_TXCTL
)
103 | B43_DMA32_TXSUSPEND
);
106 static void op32_tx_resume(struct b43_dmaring
*ring
)
108 b43_dma_write(ring
, B43_DMA32_TXCTL
, b43_dma_read(ring
, B43_DMA32_TXCTL
)
109 & ~B43_DMA32_TXSUSPEND
);
112 static int op32_get_current_rxslot(struct b43_dmaring
*ring
)
116 val
= b43_dma_read(ring
, B43_DMA32_RXSTATUS
);
117 val
&= B43_DMA32_RXDPTR
;
119 return (val
/ sizeof(struct b43_dmadesc32
));
122 static void op32_set_current_rxslot(struct b43_dmaring
*ring
, int slot
)
124 b43_dma_write(ring
, B43_DMA32_RXINDEX
,
125 (u32
) (slot
* sizeof(struct b43_dmadesc32
)));
128 static const struct b43_dma_ops dma32_ops
= {
129 .idx2desc
= op32_idx2desc
,
130 .fill_descriptor
= op32_fill_descriptor
,
131 .poke_tx
= op32_poke_tx
,
132 .tx_suspend
= op32_tx_suspend
,
133 .tx_resume
= op32_tx_resume
,
134 .get_current_rxslot
= op32_get_current_rxslot
,
135 .set_current_rxslot
= op32_set_current_rxslot
,
140 struct b43_dmadesc_generic
*op64_idx2desc(struct b43_dmaring
*ring
,
142 struct b43_dmadesc_meta
**meta
)
144 struct b43_dmadesc64
*desc
;
146 *meta
= &(ring
->meta
[slot
]);
147 desc
= ring
->descbase
;
148 desc
= &(desc
[slot
]);
150 return (struct b43_dmadesc_generic
*)desc
;
153 static void op64_fill_descriptor(struct b43_dmaring
*ring
,
154 struct b43_dmadesc_generic
*desc
,
155 dma_addr_t dmaaddr
, u16 bufsize
,
156 int start
, int end
, int irq
)
158 struct b43_dmadesc64
*descbase
= ring
->descbase
;
160 u32 ctl0
= 0, ctl1
= 0;
164 slot
= (int)(&(desc
->dma64
) - descbase
);
165 B43_WARN_ON(!(slot
>= 0 && slot
< ring
->nr_slots
));
167 addrlo
= (u32
) (dmaaddr
& 0xFFFFFFFF);
168 addrhi
= (((u64
) dmaaddr
>> 32) & ~SSB_DMA_TRANSLATION_MASK
);
169 addrext
= (((u64
) dmaaddr
>> 32) & SSB_DMA_TRANSLATION_MASK
)
170 >> SSB_DMA_TRANSLATION_SHIFT
;
171 addrhi
|= (ssb_dma_translation(ring
->dev
->dev
) << 1);
172 if (slot
== ring
->nr_slots
- 1)
173 ctl0
|= B43_DMA64_DCTL0_DTABLEEND
;
175 ctl0
|= B43_DMA64_DCTL0_FRAMESTART
;
177 ctl0
|= B43_DMA64_DCTL0_FRAMEEND
;
179 ctl0
|= B43_DMA64_DCTL0_IRQ
;
180 ctl1
|= (bufsize
- ring
->frameoffset
)
181 & B43_DMA64_DCTL1_BYTECNT
;
182 ctl1
|= (addrext
<< B43_DMA64_DCTL1_ADDREXT_SHIFT
)
183 & B43_DMA64_DCTL1_ADDREXT_MASK
;
185 desc
->dma64
.control0
= cpu_to_le32(ctl0
);
186 desc
->dma64
.control1
= cpu_to_le32(ctl1
);
187 desc
->dma64
.address_low
= cpu_to_le32(addrlo
);
188 desc
->dma64
.address_high
= cpu_to_le32(addrhi
);
191 static void op64_poke_tx(struct b43_dmaring
*ring
, int slot
)
193 b43_dma_write(ring
, B43_DMA64_TXINDEX
,
194 (u32
) (slot
* sizeof(struct b43_dmadesc64
)));
197 static void op64_tx_suspend(struct b43_dmaring
*ring
)
199 b43_dma_write(ring
, B43_DMA64_TXCTL
, b43_dma_read(ring
, B43_DMA64_TXCTL
)
200 | B43_DMA64_TXSUSPEND
);
203 static void op64_tx_resume(struct b43_dmaring
*ring
)
205 b43_dma_write(ring
, B43_DMA64_TXCTL
, b43_dma_read(ring
, B43_DMA64_TXCTL
)
206 & ~B43_DMA64_TXSUSPEND
);
209 static int op64_get_current_rxslot(struct b43_dmaring
*ring
)
213 val
= b43_dma_read(ring
, B43_DMA64_RXSTATUS
);
214 val
&= B43_DMA64_RXSTATDPTR
;
216 return (val
/ sizeof(struct b43_dmadesc64
));
219 static void op64_set_current_rxslot(struct b43_dmaring
*ring
, int slot
)
221 b43_dma_write(ring
, B43_DMA64_RXINDEX
,
222 (u32
) (slot
* sizeof(struct b43_dmadesc64
)));
225 static const struct b43_dma_ops dma64_ops
= {
226 .idx2desc
= op64_idx2desc
,
227 .fill_descriptor
= op64_fill_descriptor
,
228 .poke_tx
= op64_poke_tx
,
229 .tx_suspend
= op64_tx_suspend
,
230 .tx_resume
= op64_tx_resume
,
231 .get_current_rxslot
= op64_get_current_rxslot
,
232 .set_current_rxslot
= op64_set_current_rxslot
,
235 static inline int free_slots(struct b43_dmaring
*ring
)
237 return (ring
->nr_slots
- ring
->used_slots
);
240 static inline int next_slot(struct b43_dmaring
*ring
, int slot
)
242 B43_WARN_ON(!(slot
>= -1 && slot
<= ring
->nr_slots
- 1));
243 if (slot
== ring
->nr_slots
- 1)
248 static inline int prev_slot(struct b43_dmaring
*ring
, int slot
)
250 B43_WARN_ON(!(slot
>= 0 && slot
<= ring
->nr_slots
- 1));
252 return ring
->nr_slots
- 1;
256 #ifdef CONFIG_B43_DEBUG
257 static void update_max_used_slots(struct b43_dmaring
*ring
,
258 int current_used_slots
)
260 if (current_used_slots
<= ring
->max_used_slots
)
262 ring
->max_used_slots
= current_used_slots
;
263 if (b43_debug(ring
->dev
, B43_DBG_DMAVERBOSE
)) {
264 b43dbg(ring
->dev
->wl
,
265 "max_used_slots increased to %d on %s ring %d\n",
266 ring
->max_used_slots
,
267 ring
->tx
? "TX" : "RX", ring
->index
);
272 void update_max_used_slots(struct b43_dmaring
*ring
, int current_used_slots
)
277 /* Request a slot for usage. */
278 static inline int request_slot(struct b43_dmaring
*ring
)
282 B43_WARN_ON(!ring
->tx
);
283 B43_WARN_ON(ring
->stopped
);
284 B43_WARN_ON(free_slots(ring
) == 0);
286 slot
= next_slot(ring
, ring
->current_slot
);
287 ring
->current_slot
= slot
;
290 update_max_used_slots(ring
, ring
->used_slots
);
295 static u16
b43_dmacontroller_base(enum b43_dmatype type
, int controller_idx
)
297 static const u16 map64
[] = {
298 B43_MMIO_DMA64_BASE0
,
299 B43_MMIO_DMA64_BASE1
,
300 B43_MMIO_DMA64_BASE2
,
301 B43_MMIO_DMA64_BASE3
,
302 B43_MMIO_DMA64_BASE4
,
303 B43_MMIO_DMA64_BASE5
,
305 static const u16 map32
[] = {
306 B43_MMIO_DMA32_BASE0
,
307 B43_MMIO_DMA32_BASE1
,
308 B43_MMIO_DMA32_BASE2
,
309 B43_MMIO_DMA32_BASE3
,
310 B43_MMIO_DMA32_BASE4
,
311 B43_MMIO_DMA32_BASE5
,
314 if (type
== B43_DMA_64BIT
) {
315 B43_WARN_ON(!(controller_idx
>= 0 &&
316 controller_idx
< ARRAY_SIZE(map64
)));
317 return map64
[controller_idx
];
319 B43_WARN_ON(!(controller_idx
>= 0 &&
320 controller_idx
< ARRAY_SIZE(map32
)));
321 return map32
[controller_idx
];
325 dma_addr_t
map_descbuffer(struct b43_dmaring
*ring
,
326 unsigned char *buf
, size_t len
, int tx
)
331 dmaaddr
= ssb_dma_map_single(ring
->dev
->dev
,
332 buf
, len
, DMA_TO_DEVICE
);
334 dmaaddr
= ssb_dma_map_single(ring
->dev
->dev
,
335 buf
, len
, DMA_FROM_DEVICE
);
342 void unmap_descbuffer(struct b43_dmaring
*ring
,
343 dma_addr_t addr
, size_t len
, int tx
)
346 ssb_dma_unmap_single(ring
->dev
->dev
,
347 addr
, len
, DMA_TO_DEVICE
);
349 ssb_dma_unmap_single(ring
->dev
->dev
,
350 addr
, len
, DMA_FROM_DEVICE
);
355 void sync_descbuffer_for_cpu(struct b43_dmaring
*ring
,
356 dma_addr_t addr
, size_t len
)
358 B43_WARN_ON(ring
->tx
);
359 ssb_dma_sync_single_for_cpu(ring
->dev
->dev
,
360 addr
, len
, DMA_FROM_DEVICE
);
364 void sync_descbuffer_for_device(struct b43_dmaring
*ring
,
365 dma_addr_t addr
, size_t len
)
367 B43_WARN_ON(ring
->tx
);
368 ssb_dma_sync_single_for_device(ring
->dev
->dev
,
369 addr
, len
, DMA_FROM_DEVICE
);
373 void free_descriptor_buffer(struct b43_dmaring
*ring
,
374 struct b43_dmadesc_meta
*meta
)
377 dev_kfree_skb_any(meta
->skb
);
382 static int alloc_ringmemory(struct b43_dmaring
*ring
)
384 gfp_t flags
= GFP_KERNEL
;
386 /* The specs call for 4K buffers for 30- and 32-bit DMA with 4K
387 * alignment and 8K buffers for 64-bit DMA with 8K alignment. Testing
388 * has shown that 4K is sufficient for the latter as long as the buffer
389 * does not cross an 8K boundary.
391 * For unknown reasons - possibly a hardware error - the BCM4311 rev
392 * 02, which uses 64-bit DMA, needs the ring buffer in very low memory,
393 * which accounts for the GFP_DMA flag below.
395 * The flags here must match the flags in free_ringmemory below!
397 if (ring
->type
== B43_DMA_64BIT
)
399 ring
->descbase
= ssb_dma_alloc_consistent(ring
->dev
->dev
,
401 &(ring
->dmabase
), flags
);
402 if (!ring
->descbase
) {
403 b43err(ring
->dev
->wl
, "DMA ringmemory allocation failed\n");
406 memset(ring
->descbase
, 0, B43_DMA_RINGMEMSIZE
);
411 static void free_ringmemory(struct b43_dmaring
*ring
)
413 gfp_t flags
= GFP_KERNEL
;
415 if (ring
->type
== B43_DMA_64BIT
)
418 ssb_dma_free_consistent(ring
->dev
->dev
, B43_DMA_RINGMEMSIZE
,
419 ring
->descbase
, ring
->dmabase
, flags
);
422 /* Reset the RX DMA channel */
423 static int b43_dmacontroller_rx_reset(struct b43_wldev
*dev
, u16 mmio_base
,
424 enum b43_dmatype type
)
432 offset
= (type
== B43_DMA_64BIT
) ? B43_DMA64_RXCTL
: B43_DMA32_RXCTL
;
433 b43_write32(dev
, mmio_base
+ offset
, 0);
434 for (i
= 0; i
< 10; i
++) {
435 offset
= (type
== B43_DMA_64BIT
) ? B43_DMA64_RXSTATUS
:
437 value
= b43_read32(dev
, mmio_base
+ offset
);
438 if (type
== B43_DMA_64BIT
) {
439 value
&= B43_DMA64_RXSTAT
;
440 if (value
== B43_DMA64_RXSTAT_DISABLED
) {
445 value
&= B43_DMA32_RXSTATE
;
446 if (value
== B43_DMA32_RXSTAT_DISABLED
) {
454 b43err(dev
->wl
, "DMA RX reset timed out\n");
461 /* Reset the TX DMA channel */
462 static int b43_dmacontroller_tx_reset(struct b43_wldev
*dev
, u16 mmio_base
,
463 enum b43_dmatype type
)
471 for (i
= 0; i
< 10; i
++) {
472 offset
= (type
== B43_DMA_64BIT
) ? B43_DMA64_TXSTATUS
:
474 value
= b43_read32(dev
, mmio_base
+ offset
);
475 if (type
== B43_DMA_64BIT
) {
476 value
&= B43_DMA64_TXSTAT
;
477 if (value
== B43_DMA64_TXSTAT_DISABLED
||
478 value
== B43_DMA64_TXSTAT_IDLEWAIT
||
479 value
== B43_DMA64_TXSTAT_STOPPED
)
482 value
&= B43_DMA32_TXSTATE
;
483 if (value
== B43_DMA32_TXSTAT_DISABLED
||
484 value
== B43_DMA32_TXSTAT_IDLEWAIT
||
485 value
== B43_DMA32_TXSTAT_STOPPED
)
490 offset
= (type
== B43_DMA_64BIT
) ? B43_DMA64_TXCTL
: B43_DMA32_TXCTL
;
491 b43_write32(dev
, mmio_base
+ offset
, 0);
492 for (i
= 0; i
< 10; i
++) {
493 offset
= (type
== B43_DMA_64BIT
) ? B43_DMA64_TXSTATUS
:
495 value
= b43_read32(dev
, mmio_base
+ offset
);
496 if (type
== B43_DMA_64BIT
) {
497 value
&= B43_DMA64_TXSTAT
;
498 if (value
== B43_DMA64_TXSTAT_DISABLED
) {
503 value
&= B43_DMA32_TXSTATE
;
504 if (value
== B43_DMA32_TXSTAT_DISABLED
) {
512 b43err(dev
->wl
, "DMA TX reset timed out\n");
515 /* ensure the reset is completed. */
521 /* Check if a DMA mapping address is invalid. */
522 static bool b43_dma_mapping_error(struct b43_dmaring
*ring
,
524 size_t buffersize
, bool dma_to_device
)
526 if (unlikely(ssb_dma_mapping_error(ring
->dev
->dev
, addr
)))
529 switch (ring
->type
) {
531 if ((u64
)addr
+ buffersize
> (1ULL << 30))
535 if ((u64
)addr
+ buffersize
> (1ULL << 32))
539 /* Currently we can't have addresses beyond
540 * 64bit in the kernel. */
544 /* The address is OK. */
548 /* We can't support this address. Unmap it again. */
549 unmap_descbuffer(ring
, addr
, buffersize
, dma_to_device
);
554 static int setup_rx_descbuffer(struct b43_dmaring
*ring
,
555 struct b43_dmadesc_generic
*desc
,
556 struct b43_dmadesc_meta
*meta
, gfp_t gfp_flags
)
558 struct b43_rxhdr_fw4
*rxhdr
;
562 B43_WARN_ON(ring
->tx
);
564 skb
= __dev_alloc_skb(ring
->rx_buffersize
, gfp_flags
);
567 dmaaddr
= map_descbuffer(ring
, skb
->data
, ring
->rx_buffersize
, 0);
568 if (b43_dma_mapping_error(ring
, dmaaddr
, ring
->rx_buffersize
, 0)) {
569 /* ugh. try to realloc in zone_dma */
570 gfp_flags
|= GFP_DMA
;
572 dev_kfree_skb_any(skb
);
574 skb
= __dev_alloc_skb(ring
->rx_buffersize
, gfp_flags
);
577 dmaaddr
= map_descbuffer(ring
, skb
->data
,
578 ring
->rx_buffersize
, 0);
581 if (b43_dma_mapping_error(ring
, dmaaddr
, ring
->rx_buffersize
, 0)) {
582 b43err(ring
->dev
->wl
, "RX DMA buffer allocation failed\n");
583 dev_kfree_skb_any(skb
);
588 meta
->dmaaddr
= dmaaddr
;
589 ring
->ops
->fill_descriptor(ring
, desc
, dmaaddr
,
590 ring
->rx_buffersize
, 0, 0, 0);
592 rxhdr
= (struct b43_rxhdr_fw4
*)(skb
->data
);
593 rxhdr
->frame_len
= 0;
598 /* Allocate the initial descbuffers.
599 * This is used for an RX ring only.
601 static int alloc_initial_descbuffers(struct b43_dmaring
*ring
)
603 int i
, err
= -ENOMEM
;
604 struct b43_dmadesc_generic
*desc
;
605 struct b43_dmadesc_meta
*meta
;
607 for (i
= 0; i
< ring
->nr_slots
; i
++) {
608 desc
= ring
->ops
->idx2desc(ring
, i
, &meta
);
610 err
= setup_rx_descbuffer(ring
, desc
, meta
, GFP_KERNEL
);
612 b43err(ring
->dev
->wl
,
613 "Failed to allocate initial descbuffers\n");
618 ring
->used_slots
= ring
->nr_slots
;
624 for (i
--; i
>= 0; i
--) {
625 desc
= ring
->ops
->idx2desc(ring
, i
, &meta
);
627 unmap_descbuffer(ring
, meta
->dmaaddr
, ring
->rx_buffersize
, 0);
628 dev_kfree_skb(meta
->skb
);
633 /* Do initial setup of the DMA controller.
634 * Reset the controller, write the ring busaddress
635 * and switch the "enable" bit on.
637 static int dmacontroller_setup(struct b43_dmaring
*ring
)
642 u32 trans
= ssb_dma_translation(ring
->dev
->dev
);
645 if (ring
->type
== B43_DMA_64BIT
) {
646 u64 ringbase
= (u64
) (ring
->dmabase
);
648 addrext
= ((ringbase
>> 32) & SSB_DMA_TRANSLATION_MASK
)
649 >> SSB_DMA_TRANSLATION_SHIFT
;
650 value
= B43_DMA64_TXENABLE
;
651 value
|= (addrext
<< B43_DMA64_TXADDREXT_SHIFT
)
652 & B43_DMA64_TXADDREXT_MASK
;
653 b43_dma_write(ring
, B43_DMA64_TXCTL
, value
);
654 b43_dma_write(ring
, B43_DMA64_TXRINGLO
,
655 (ringbase
& 0xFFFFFFFF));
656 b43_dma_write(ring
, B43_DMA64_TXRINGHI
,
658 ~SSB_DMA_TRANSLATION_MASK
)
661 u32 ringbase
= (u32
) (ring
->dmabase
);
663 addrext
= (ringbase
& SSB_DMA_TRANSLATION_MASK
)
664 >> SSB_DMA_TRANSLATION_SHIFT
;
665 value
= B43_DMA32_TXENABLE
;
666 value
|= (addrext
<< B43_DMA32_TXADDREXT_SHIFT
)
667 & B43_DMA32_TXADDREXT_MASK
;
668 b43_dma_write(ring
, B43_DMA32_TXCTL
, value
);
669 b43_dma_write(ring
, B43_DMA32_TXRING
,
670 (ringbase
& ~SSB_DMA_TRANSLATION_MASK
)
674 err
= alloc_initial_descbuffers(ring
);
677 if (ring
->type
== B43_DMA_64BIT
) {
678 u64 ringbase
= (u64
) (ring
->dmabase
);
680 addrext
= ((ringbase
>> 32) & SSB_DMA_TRANSLATION_MASK
)
681 >> SSB_DMA_TRANSLATION_SHIFT
;
682 value
= (ring
->frameoffset
<< B43_DMA64_RXFROFF_SHIFT
);
683 value
|= B43_DMA64_RXENABLE
;
684 value
|= (addrext
<< B43_DMA64_RXADDREXT_SHIFT
)
685 & B43_DMA64_RXADDREXT_MASK
;
686 b43_dma_write(ring
, B43_DMA64_RXCTL
, value
);
687 b43_dma_write(ring
, B43_DMA64_RXRINGLO
,
688 (ringbase
& 0xFFFFFFFF));
689 b43_dma_write(ring
, B43_DMA64_RXRINGHI
,
691 ~SSB_DMA_TRANSLATION_MASK
)
693 b43_dma_write(ring
, B43_DMA64_RXINDEX
, ring
->nr_slots
*
694 sizeof(struct b43_dmadesc64
));
696 u32 ringbase
= (u32
) (ring
->dmabase
);
698 addrext
= (ringbase
& SSB_DMA_TRANSLATION_MASK
)
699 >> SSB_DMA_TRANSLATION_SHIFT
;
700 value
= (ring
->frameoffset
<< B43_DMA32_RXFROFF_SHIFT
);
701 value
|= B43_DMA32_RXENABLE
;
702 value
|= (addrext
<< B43_DMA32_RXADDREXT_SHIFT
)
703 & B43_DMA32_RXADDREXT_MASK
;
704 b43_dma_write(ring
, B43_DMA32_RXCTL
, value
);
705 b43_dma_write(ring
, B43_DMA32_RXRING
,
706 (ringbase
& ~SSB_DMA_TRANSLATION_MASK
)
708 b43_dma_write(ring
, B43_DMA32_RXINDEX
, ring
->nr_slots
*
709 sizeof(struct b43_dmadesc32
));
717 /* Shutdown the DMA controller. */
718 static void dmacontroller_cleanup(struct b43_dmaring
*ring
)
721 b43_dmacontroller_tx_reset(ring
->dev
, ring
->mmio_base
,
723 if (ring
->type
== B43_DMA_64BIT
) {
724 b43_dma_write(ring
, B43_DMA64_TXRINGLO
, 0);
725 b43_dma_write(ring
, B43_DMA64_TXRINGHI
, 0);
727 b43_dma_write(ring
, B43_DMA32_TXRING
, 0);
729 b43_dmacontroller_rx_reset(ring
->dev
, ring
->mmio_base
,
731 if (ring
->type
== B43_DMA_64BIT
) {
732 b43_dma_write(ring
, B43_DMA64_RXRINGLO
, 0);
733 b43_dma_write(ring
, B43_DMA64_RXRINGHI
, 0);
735 b43_dma_write(ring
, B43_DMA32_RXRING
, 0);
739 static void free_all_descbuffers(struct b43_dmaring
*ring
)
741 struct b43_dmadesc_generic
*desc
;
742 struct b43_dmadesc_meta
*meta
;
745 if (!ring
->used_slots
)
747 for (i
= 0; i
< ring
->nr_slots
; i
++) {
748 desc
= ring
->ops
->idx2desc(ring
, i
, &meta
);
751 B43_WARN_ON(!ring
->tx
);
755 unmap_descbuffer(ring
, meta
->dmaaddr
,
758 unmap_descbuffer(ring
, meta
->dmaaddr
,
759 ring
->rx_buffersize
, 0);
761 free_descriptor_buffer(ring
, meta
);
765 static u64
supported_dma_mask(struct b43_wldev
*dev
)
770 tmp
= b43_read32(dev
, SSB_TMSHIGH
);
771 if (tmp
& SSB_TMSHIGH_DMA64
)
772 return DMA_64BIT_MASK
;
773 mmio_base
= b43_dmacontroller_base(0, 0);
774 b43_write32(dev
, mmio_base
+ B43_DMA32_TXCTL
, B43_DMA32_TXADDREXT_MASK
);
775 tmp
= b43_read32(dev
, mmio_base
+ B43_DMA32_TXCTL
);
776 if (tmp
& B43_DMA32_TXADDREXT_MASK
)
777 return DMA_32BIT_MASK
;
779 return DMA_30BIT_MASK
;
782 static enum b43_dmatype
dma_mask_to_engine_type(u64 dmamask
)
784 if (dmamask
== DMA_30BIT_MASK
)
785 return B43_DMA_30BIT
;
786 if (dmamask
== DMA_32BIT_MASK
)
787 return B43_DMA_32BIT
;
788 if (dmamask
== DMA_64BIT_MASK
)
789 return B43_DMA_64BIT
;
791 return B43_DMA_30BIT
;
794 /* Main initialization function. */
796 struct b43_dmaring
*b43_setup_dmaring(struct b43_wldev
*dev
,
797 int controller_index
,
799 enum b43_dmatype type
)
801 struct b43_dmaring
*ring
;
805 ring
= kzalloc(sizeof(*ring
), GFP_KERNEL
);
809 ring
->nr_slots
= B43_RXRING_SLOTS
;
811 ring
->nr_slots
= B43_TXRING_SLOTS
;
813 ring
->meta
= kcalloc(ring
->nr_slots
, sizeof(struct b43_dmadesc_meta
),
820 ring
->mmio_base
= b43_dmacontroller_base(type
, controller_index
);
821 ring
->index
= controller_index
;
822 if (type
== B43_DMA_64BIT
)
823 ring
->ops
= &dma64_ops
;
825 ring
->ops
= &dma32_ops
;
828 ring
->current_slot
= -1;
830 if (ring
->index
== 0) {
831 ring
->rx_buffersize
= B43_DMA0_RX_BUFFERSIZE
;
832 ring
->frameoffset
= B43_DMA0_RX_FRAMEOFFSET
;
833 } else if (ring
->index
== 3) {
834 ring
->rx_buffersize
= B43_DMA3_RX_BUFFERSIZE
;
835 ring
->frameoffset
= B43_DMA3_RX_FRAMEOFFSET
;
839 spin_lock_init(&ring
->lock
);
840 #ifdef CONFIG_B43_DEBUG
841 ring
->last_injected_overflow
= jiffies
;
845 ring
->txhdr_cache
= kcalloc(ring
->nr_slots
,
848 if (!ring
->txhdr_cache
)
851 /* test for ability to dma to txhdr_cache */
852 dma_test
= ssb_dma_map_single(dev
->dev
,
857 if (b43_dma_mapping_error(ring
, dma_test
,
858 b43_txhdr_size(dev
), 1)) {
860 kfree(ring
->txhdr_cache
);
861 ring
->txhdr_cache
= kcalloc(ring
->nr_slots
,
863 GFP_KERNEL
| GFP_DMA
);
864 if (!ring
->txhdr_cache
)
867 dma_test
= ssb_dma_map_single(dev
->dev
,
872 if (b43_dma_mapping_error(ring
, dma_test
,
873 b43_txhdr_size(dev
), 1)) {
876 "TXHDR DMA allocation failed\n");
877 goto err_kfree_txhdr_cache
;
881 ssb_dma_unmap_single(dev
->dev
,
882 dma_test
, b43_txhdr_size(dev
),
886 err
= alloc_ringmemory(ring
);
888 goto err_kfree_txhdr_cache
;
889 err
= dmacontroller_setup(ring
);
891 goto err_free_ringmemory
;
897 free_ringmemory(ring
);
898 err_kfree_txhdr_cache
:
899 kfree(ring
->txhdr_cache
);
908 #define divide(a, b) ({ \
914 #define modulo(a, b) ({ \
919 /* Main cleanup function. */
920 static void b43_destroy_dmaring(struct b43_dmaring
*ring
,
921 const char *ringname
)
926 #ifdef CONFIG_B43_DEBUG
928 /* Print some statistics. */
929 u64 failed_packets
= ring
->nr_failed_tx_packets
;
930 u64 succeed_packets
= ring
->nr_succeed_tx_packets
;
931 u64 nr_packets
= failed_packets
+ succeed_packets
;
932 u64 permille_failed
= 0, average_tries
= 0;
935 permille_failed
= divide(failed_packets
* 1000, nr_packets
);
937 average_tries
= divide(ring
->nr_total_packet_tries
* 100, nr_packets
);
939 b43dbg(ring
->dev
->wl
, "DMA-%u %s: "
940 "Used slots %d/%d, Failed frames %llu/%llu = %llu.%01llu%%, "
941 "Average tries %llu.%02llu\n",
942 (unsigned int)(ring
->type
), ringname
,
943 ring
->max_used_slots
,
945 (unsigned long long)failed_packets
,
946 (unsigned long long)nr_packets
,
947 (unsigned long long)divide(permille_failed
, 10),
948 (unsigned long long)modulo(permille_failed
, 10),
949 (unsigned long long)divide(average_tries
, 100),
950 (unsigned long long)modulo(average_tries
, 100));
954 /* Device IRQs are disabled prior entering this function,
955 * so no need to take care of concurrency with rx handler stuff.
957 dmacontroller_cleanup(ring
);
958 free_all_descbuffers(ring
);
959 free_ringmemory(ring
);
961 kfree(ring
->txhdr_cache
);
966 #define destroy_ring(dma, ring) do { \
967 b43_destroy_dmaring((dma)->ring, __stringify(ring)); \
968 (dma)->ring = NULL; \
971 void b43_dma_free(struct b43_wldev
*dev
)
975 if (b43_using_pio_transfers(dev
))
979 destroy_ring(dma
, rx_ring
);
980 destroy_ring(dma
, tx_ring_AC_BK
);
981 destroy_ring(dma
, tx_ring_AC_BE
);
982 destroy_ring(dma
, tx_ring_AC_VI
);
983 destroy_ring(dma
, tx_ring_AC_VO
);
984 destroy_ring(dma
, tx_ring_mcast
);
987 static int b43_dma_set_mask(struct b43_wldev
*dev
, u64 mask
)
989 u64 orig_mask
= mask
;
993 /* Try to set the DMA mask. If it fails, try falling back to a
994 * lower mask, as we can always also support a lower one. */
996 err
= ssb_dma_set_mask(dev
->dev
, mask
);
999 if (mask
== DMA_64BIT_MASK
) {
1000 mask
= DMA_32BIT_MASK
;
1004 if (mask
== DMA_32BIT_MASK
) {
1005 mask
= DMA_30BIT_MASK
;
1009 b43err(dev
->wl
, "The machine/kernel does not support "
1010 "the required %u-bit DMA mask\n",
1011 (unsigned int)dma_mask_to_engine_type(orig_mask
));
1015 b43info(dev
->wl
, "DMA mask fallback from %u-bit to %u-bit\n",
1016 (unsigned int)dma_mask_to_engine_type(orig_mask
),
1017 (unsigned int)dma_mask_to_engine_type(mask
));
1023 int b43_dma_init(struct b43_wldev
*dev
)
1025 struct b43_dma
*dma
= &dev
->dma
;
1028 enum b43_dmatype type
;
1030 dmamask
= supported_dma_mask(dev
);
1031 type
= dma_mask_to_engine_type(dmamask
);
1032 err
= b43_dma_set_mask(dev
, dmamask
);
1037 /* setup TX DMA channels. */
1038 dma
->tx_ring_AC_BK
= b43_setup_dmaring(dev
, 0, 1, type
);
1039 if (!dma
->tx_ring_AC_BK
)
1042 dma
->tx_ring_AC_BE
= b43_setup_dmaring(dev
, 1, 1, type
);
1043 if (!dma
->tx_ring_AC_BE
)
1044 goto err_destroy_bk
;
1046 dma
->tx_ring_AC_VI
= b43_setup_dmaring(dev
, 2, 1, type
);
1047 if (!dma
->tx_ring_AC_VI
)
1048 goto err_destroy_be
;
1050 dma
->tx_ring_AC_VO
= b43_setup_dmaring(dev
, 3, 1, type
);
1051 if (!dma
->tx_ring_AC_VO
)
1052 goto err_destroy_vi
;
1054 dma
->tx_ring_mcast
= b43_setup_dmaring(dev
, 4, 1, type
);
1055 if (!dma
->tx_ring_mcast
)
1056 goto err_destroy_vo
;
1058 /* setup RX DMA channel. */
1059 dma
->rx_ring
= b43_setup_dmaring(dev
, 0, 0, type
);
1061 goto err_destroy_mcast
;
1063 /* No support for the TX status DMA ring. */
1064 B43_WARN_ON(dev
->dev
->id
.revision
< 5);
1066 b43dbg(dev
->wl
, "%u-bit DMA initialized\n",
1067 (unsigned int)type
);
1073 destroy_ring(dma
, tx_ring_mcast
);
1075 destroy_ring(dma
, tx_ring_AC_VO
);
1077 destroy_ring(dma
, tx_ring_AC_VI
);
1079 destroy_ring(dma
, tx_ring_AC_BE
);
1081 destroy_ring(dma
, tx_ring_AC_BK
);
1085 /* Generate a cookie for the TX header. */
1086 static u16
generate_cookie(struct b43_dmaring
*ring
, int slot
)
1090 /* Use the upper 4 bits of the cookie as
1091 * DMA controller ID and store the slot number
1092 * in the lower 12 bits.
1093 * Note that the cookie must never be 0, as this
1094 * is a special value used in RX path.
1095 * It can also not be 0xFFFF because that is special
1096 * for multicast frames.
1098 cookie
= (((u16
)ring
->index
+ 1) << 12);
1099 B43_WARN_ON(slot
& ~0x0FFF);
1100 cookie
|= (u16
)slot
;
1105 /* Inspect a cookie and find out to which controller/slot it belongs. */
1107 struct b43_dmaring
*parse_cookie(struct b43_wldev
*dev
, u16 cookie
, int *slot
)
1109 struct b43_dma
*dma
= &dev
->dma
;
1110 struct b43_dmaring
*ring
= NULL
;
1112 switch (cookie
& 0xF000) {
1114 ring
= dma
->tx_ring_AC_BK
;
1117 ring
= dma
->tx_ring_AC_BE
;
1120 ring
= dma
->tx_ring_AC_VI
;
1123 ring
= dma
->tx_ring_AC_VO
;
1126 ring
= dma
->tx_ring_mcast
;
1131 *slot
= (cookie
& 0x0FFF);
1132 B43_WARN_ON(!(ring
&& *slot
>= 0 && *slot
< ring
->nr_slots
));
1137 static int dma_tx_fragment(struct b43_dmaring
*ring
,
1138 struct sk_buff
*skb
)
1140 const struct b43_dma_ops
*ops
= ring
->ops
;
1141 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
1143 int slot
, old_top_slot
, old_used_slots
;
1145 struct b43_dmadesc_generic
*desc
;
1146 struct b43_dmadesc_meta
*meta
;
1147 struct b43_dmadesc_meta
*meta_hdr
;
1148 struct sk_buff
*bounce_skb
;
1150 size_t hdrsize
= b43_txhdr_size(ring
->dev
);
1152 #define SLOTS_PER_PACKET 2
1154 old_top_slot
= ring
->current_slot
;
1155 old_used_slots
= ring
->used_slots
;
1157 /* Get a slot for the header. */
1158 slot
= request_slot(ring
);
1159 desc
= ops
->idx2desc(ring
, slot
, &meta_hdr
);
1160 memset(meta_hdr
, 0, sizeof(*meta_hdr
));
1162 header
= &(ring
->txhdr_cache
[slot
* hdrsize
]);
1163 cookie
= generate_cookie(ring
, slot
);
1164 err
= b43_generate_txhdr(ring
->dev
, header
,
1165 skb
->data
, skb
->len
, info
, cookie
);
1166 if (unlikely(err
)) {
1167 ring
->current_slot
= old_top_slot
;
1168 ring
->used_slots
= old_used_slots
;
1172 meta_hdr
->dmaaddr
= map_descbuffer(ring
, (unsigned char *)header
,
1174 if (b43_dma_mapping_error(ring
, meta_hdr
->dmaaddr
, hdrsize
, 1)) {
1175 ring
->current_slot
= old_top_slot
;
1176 ring
->used_slots
= old_used_slots
;
1179 ops
->fill_descriptor(ring
, desc
, meta_hdr
->dmaaddr
,
1182 /* Get a slot for the payload. */
1183 slot
= request_slot(ring
);
1184 desc
= ops
->idx2desc(ring
, slot
, &meta
);
1185 memset(meta
, 0, sizeof(*meta
));
1188 meta
->is_last_fragment
= 1;
1190 meta
->dmaaddr
= map_descbuffer(ring
, skb
->data
, skb
->len
, 1);
1191 /* create a bounce buffer in zone_dma on mapping failure. */
1192 if (b43_dma_mapping_error(ring
, meta
->dmaaddr
, skb
->len
, 1)) {
1193 bounce_skb
= __dev_alloc_skb(skb
->len
, GFP_ATOMIC
| GFP_DMA
);
1195 ring
->current_slot
= old_top_slot
;
1196 ring
->used_slots
= old_used_slots
;
1201 memcpy(skb_put(bounce_skb
, skb
->len
), skb
->data
, skb
->len
);
1202 dev_kfree_skb_any(skb
);
1205 meta
->dmaaddr
= map_descbuffer(ring
, skb
->data
, skb
->len
, 1);
1206 if (b43_dma_mapping_error(ring
, meta
->dmaaddr
, skb
->len
, 1)) {
1207 ring
->current_slot
= old_top_slot
;
1208 ring
->used_slots
= old_used_slots
;
1210 goto out_free_bounce
;
1214 ops
->fill_descriptor(ring
, desc
, meta
->dmaaddr
, skb
->len
, 0, 1, 1);
1216 if (info
->flags
& IEEE80211_TX_CTL_SEND_AFTER_DTIM
) {
1217 /* Tell the firmware about the cookie of the last
1218 * mcast frame, so it can clear the more-data bit in it. */
1219 b43_shm_write16(ring
->dev
, B43_SHM_SHARED
,
1220 B43_SHM_SH_MCASTCOOKIE
, cookie
);
1222 /* Now transfer the whole frame. */
1224 ops
->poke_tx(ring
, next_slot(ring
, slot
));
1228 dev_kfree_skb_any(skb
);
1230 unmap_descbuffer(ring
, meta_hdr
->dmaaddr
,
1235 static inline int should_inject_overflow(struct b43_dmaring
*ring
)
1237 #ifdef CONFIG_B43_DEBUG
1238 if (unlikely(b43_debug(ring
->dev
, B43_DBG_DMAOVERFLOW
))) {
1239 /* Check if we should inject another ringbuffer overflow
1240 * to test handling of this situation in the stack. */
1241 unsigned long next_overflow
;
1243 next_overflow
= ring
->last_injected_overflow
+ HZ
;
1244 if (time_after(jiffies
, next_overflow
)) {
1245 ring
->last_injected_overflow
= jiffies
;
1246 b43dbg(ring
->dev
->wl
,
1247 "Injecting TX ring overflow on "
1248 "DMA controller %d\n", ring
->index
);
1252 #endif /* CONFIG_B43_DEBUG */
1256 /* Static mapping of mac80211's queues (priorities) to b43 DMA rings. */
1257 static struct b43_dmaring
* select_ring_by_priority(struct b43_wldev
*dev
,
1260 struct b43_dmaring
*ring
;
1262 if (b43_modparam_qos
) {
1263 /* 0 = highest priority */
1264 switch (queue_prio
) {
1269 ring
= dev
->dma
.tx_ring_AC_VO
;
1272 ring
= dev
->dma
.tx_ring_AC_VI
;
1275 ring
= dev
->dma
.tx_ring_AC_BE
;
1278 ring
= dev
->dma
.tx_ring_AC_BK
;
1282 ring
= dev
->dma
.tx_ring_AC_BE
;
1287 int b43_dma_tx(struct b43_wldev
*dev
, struct sk_buff
*skb
)
1289 struct b43_dmaring
*ring
;
1290 struct ieee80211_hdr
*hdr
;
1292 unsigned long flags
;
1293 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
1295 hdr
= (struct ieee80211_hdr
*)skb
->data
;
1296 if (info
->flags
& IEEE80211_TX_CTL_SEND_AFTER_DTIM
) {
1297 /* The multicast ring will be sent after the DTIM */
1298 ring
= dev
->dma
.tx_ring_mcast
;
1299 /* Set the more-data bit. Ucode will clear it on
1300 * the last frame for us. */
1301 hdr
->frame_control
|= cpu_to_le16(IEEE80211_FCTL_MOREDATA
);
1303 /* Decide by priority where to put this frame. */
1304 ring
= select_ring_by_priority(
1305 dev
, skb_get_queue_mapping(skb
));
1308 spin_lock_irqsave(&ring
->lock
, flags
);
1309 B43_WARN_ON(!ring
->tx
);
1310 if (unlikely(free_slots(ring
) < SLOTS_PER_PACKET
)) {
1311 b43warn(dev
->wl
, "DMA queue overflow\n");
1315 /* Check if the queue was stopped in mac80211,
1316 * but we got called nevertheless.
1317 * That would be a mac80211 bug. */
1318 B43_WARN_ON(ring
->stopped
);
1320 /* Assign the queue number to the ring (if not already done before)
1321 * so TX status handling can use it. The queue to ring mapping is
1322 * static, so we don't need to store it per frame. */
1323 ring
->queue_prio
= skb_get_queue_mapping(skb
);
1325 err
= dma_tx_fragment(ring
, skb
);
1326 if (unlikely(err
== -ENOKEY
)) {
1327 /* Drop this packet, as we don't have the encryption key
1328 * anymore and must not transmit it unencrypted. */
1329 dev_kfree_skb_any(skb
);
1333 if (unlikely(err
)) {
1334 b43err(dev
->wl
, "DMA tx mapping failure\n");
1337 ring
->nr_tx_packets
++;
1338 if ((free_slots(ring
) < SLOTS_PER_PACKET
) ||
1339 should_inject_overflow(ring
)) {
1340 /* This TX ring is full. */
1341 ieee80211_stop_queue(dev
->wl
->hw
, skb_get_queue_mapping(skb
));
1343 if (b43_debug(dev
, B43_DBG_DMAVERBOSE
)) {
1344 b43dbg(dev
->wl
, "Stopped TX ring %d\n", ring
->index
);
1348 spin_unlock_irqrestore(&ring
->lock
, flags
);
1353 /* Called with IRQs disabled. */
1354 void b43_dma_handle_txstatus(struct b43_wldev
*dev
,
1355 const struct b43_txstatus
*status
)
1357 const struct b43_dma_ops
*ops
;
1358 struct b43_dmaring
*ring
;
1359 struct b43_dmadesc_generic
*desc
;
1360 struct b43_dmadesc_meta
*meta
;
1364 ring
= parse_cookie(dev
, status
->cookie
, &slot
);
1365 if (unlikely(!ring
))
1368 spin_lock(&ring
->lock
); /* IRQs are already disabled. */
1370 B43_WARN_ON(!ring
->tx
);
1373 B43_WARN_ON(!(slot
>= 0 && slot
< ring
->nr_slots
));
1374 desc
= ops
->idx2desc(ring
, slot
, &meta
);
1377 unmap_descbuffer(ring
, meta
->dmaaddr
, meta
->skb
->len
,
1380 unmap_descbuffer(ring
, meta
->dmaaddr
,
1381 b43_txhdr_size(dev
), 1);
1383 if (meta
->is_last_fragment
) {
1384 struct ieee80211_tx_info
*info
;
1388 info
= IEEE80211_SKB_CB(meta
->skb
);
1391 * Call back to inform the ieee80211 subsystem about
1392 * the status of the transmission.
1394 frame_succeed
= b43_fill_txstatus_report(dev
, info
, status
);
1395 #ifdef CONFIG_B43_DEBUG
1397 ring
->nr_succeed_tx_packets
++;
1399 ring
->nr_failed_tx_packets
++;
1400 ring
->nr_total_packet_tries
+= status
->frame_count
;
1402 ieee80211_tx_status_irqsafe(dev
->wl
->hw
, meta
->skb
);
1404 /* skb is freed by ieee80211_tx_status_irqsafe() */
1407 /* No need to call free_descriptor_buffer here, as
1408 * this is only the txhdr, which is not allocated.
1410 B43_WARN_ON(meta
->skb
);
1413 /* Everything unmapped and free'd. So it's not used anymore. */
1416 if (meta
->is_last_fragment
)
1418 slot
= next_slot(ring
, slot
);
1420 dev
->stats
.last_tx
= jiffies
;
1421 if (ring
->stopped
) {
1422 B43_WARN_ON(free_slots(ring
) < SLOTS_PER_PACKET
);
1423 ieee80211_wake_queue(dev
->wl
->hw
, ring
->queue_prio
);
1425 if (b43_debug(dev
, B43_DBG_DMAVERBOSE
)) {
1426 b43dbg(dev
->wl
, "Woke up TX ring %d\n", ring
->index
);
1430 spin_unlock(&ring
->lock
);
1433 void b43_dma_get_tx_stats(struct b43_wldev
*dev
,
1434 struct ieee80211_tx_queue_stats
*stats
)
1436 const int nr_queues
= dev
->wl
->hw
->queues
;
1437 struct b43_dmaring
*ring
;
1438 unsigned long flags
;
1441 for (i
= 0; i
< nr_queues
; i
++) {
1442 ring
= select_ring_by_priority(dev
, i
);
1444 spin_lock_irqsave(&ring
->lock
, flags
);
1445 stats
[i
].len
= ring
->used_slots
/ SLOTS_PER_PACKET
;
1446 stats
[i
].limit
= ring
->nr_slots
/ SLOTS_PER_PACKET
;
1447 stats
[i
].count
= ring
->nr_tx_packets
;
1448 spin_unlock_irqrestore(&ring
->lock
, flags
);
1452 static void dma_rx(struct b43_dmaring
*ring
, int *slot
)
1454 const struct b43_dma_ops
*ops
= ring
->ops
;
1455 struct b43_dmadesc_generic
*desc
;
1456 struct b43_dmadesc_meta
*meta
;
1457 struct b43_rxhdr_fw4
*rxhdr
;
1458 struct sk_buff
*skb
;
1463 desc
= ops
->idx2desc(ring
, *slot
, &meta
);
1465 sync_descbuffer_for_cpu(ring
, meta
->dmaaddr
, ring
->rx_buffersize
);
1468 rxhdr
= (struct b43_rxhdr_fw4
*)skb
->data
;
1469 len
= le16_to_cpu(rxhdr
->frame_len
);
1476 len
= le16_to_cpu(rxhdr
->frame_len
);
1477 } while (len
== 0 && i
++ < 5);
1478 if (unlikely(len
== 0)) {
1479 /* recycle the descriptor buffer. */
1480 sync_descbuffer_for_device(ring
, meta
->dmaaddr
,
1481 ring
->rx_buffersize
);
1485 if (unlikely(len
> ring
->rx_buffersize
)) {
1486 /* The data did not fit into one descriptor buffer
1487 * and is split over multiple buffers.
1488 * This should never happen, as we try to allocate buffers
1489 * big enough. So simply ignore this packet.
1495 desc
= ops
->idx2desc(ring
, *slot
, &meta
);
1496 /* recycle the descriptor buffer. */
1497 sync_descbuffer_for_device(ring
, meta
->dmaaddr
,
1498 ring
->rx_buffersize
);
1499 *slot
= next_slot(ring
, *slot
);
1501 tmp
-= ring
->rx_buffersize
;
1505 b43err(ring
->dev
->wl
, "DMA RX buffer too small "
1506 "(len: %u, buffer: %u, nr-dropped: %d)\n",
1507 len
, ring
->rx_buffersize
, cnt
);
1511 dmaaddr
= meta
->dmaaddr
;
1512 err
= setup_rx_descbuffer(ring
, desc
, meta
, GFP_ATOMIC
);
1513 if (unlikely(err
)) {
1514 b43dbg(ring
->dev
->wl
, "DMA RX: setup_rx_descbuffer() failed\n");
1515 sync_descbuffer_for_device(ring
, dmaaddr
, ring
->rx_buffersize
);
1519 unmap_descbuffer(ring
, dmaaddr
, ring
->rx_buffersize
, 0);
1520 skb_put(skb
, len
+ ring
->frameoffset
);
1521 skb_pull(skb
, ring
->frameoffset
);
1523 b43_rx(ring
->dev
, skb
, rxhdr
);
1528 void b43_dma_rx(struct b43_dmaring
*ring
)
1530 const struct b43_dma_ops
*ops
= ring
->ops
;
1531 int slot
, current_slot
;
1534 B43_WARN_ON(ring
->tx
);
1535 current_slot
= ops
->get_current_rxslot(ring
);
1536 B43_WARN_ON(!(current_slot
>= 0 && current_slot
< ring
->nr_slots
));
1538 slot
= ring
->current_slot
;
1539 for (; slot
!= current_slot
; slot
= next_slot(ring
, slot
)) {
1540 dma_rx(ring
, &slot
);
1541 update_max_used_slots(ring
, ++used_slots
);
1543 ops
->set_current_rxslot(ring
, slot
);
1544 ring
->current_slot
= slot
;
1547 static void b43_dma_tx_suspend_ring(struct b43_dmaring
*ring
)
1549 unsigned long flags
;
1551 spin_lock_irqsave(&ring
->lock
, flags
);
1552 B43_WARN_ON(!ring
->tx
);
1553 ring
->ops
->tx_suspend(ring
);
1554 spin_unlock_irqrestore(&ring
->lock
, flags
);
1557 static void b43_dma_tx_resume_ring(struct b43_dmaring
*ring
)
1559 unsigned long flags
;
1561 spin_lock_irqsave(&ring
->lock
, flags
);
1562 B43_WARN_ON(!ring
->tx
);
1563 ring
->ops
->tx_resume(ring
);
1564 spin_unlock_irqrestore(&ring
->lock
, flags
);
1567 void b43_dma_tx_suspend(struct b43_wldev
*dev
)
1569 b43_power_saving_ctl_bits(dev
, B43_PS_AWAKE
);
1570 b43_dma_tx_suspend_ring(dev
->dma
.tx_ring_AC_BK
);
1571 b43_dma_tx_suspend_ring(dev
->dma
.tx_ring_AC_BE
);
1572 b43_dma_tx_suspend_ring(dev
->dma
.tx_ring_AC_VI
);
1573 b43_dma_tx_suspend_ring(dev
->dma
.tx_ring_AC_VO
);
1574 b43_dma_tx_suspend_ring(dev
->dma
.tx_ring_mcast
);
1577 void b43_dma_tx_resume(struct b43_wldev
*dev
)
1579 b43_dma_tx_resume_ring(dev
->dma
.tx_ring_mcast
);
1580 b43_dma_tx_resume_ring(dev
->dma
.tx_ring_AC_VO
);
1581 b43_dma_tx_resume_ring(dev
->dma
.tx_ring_AC_VI
);
1582 b43_dma_tx_resume_ring(dev
->dma
.tx_ring_AC_BE
);
1583 b43_dma_tx_resume_ring(dev
->dma
.tx_ring_AC_BK
);
1584 b43_power_saving_ctl_bits(dev
, 0);
1587 #ifdef CONFIG_B43_PIO
1588 static void direct_fifo_rx(struct b43_wldev
*dev
, enum b43_dmatype type
,
1589 u16 mmio_base
, bool enable
)
1593 if (type
== B43_DMA_64BIT
) {
1594 ctl
= b43_read32(dev
, mmio_base
+ B43_DMA64_RXCTL
);
1595 ctl
&= ~B43_DMA64_RXDIRECTFIFO
;
1597 ctl
|= B43_DMA64_RXDIRECTFIFO
;
1598 b43_write32(dev
, mmio_base
+ B43_DMA64_RXCTL
, ctl
);
1600 ctl
= b43_read32(dev
, mmio_base
+ B43_DMA32_RXCTL
);
1601 ctl
&= ~B43_DMA32_RXDIRECTFIFO
;
1603 ctl
|= B43_DMA32_RXDIRECTFIFO
;
1604 b43_write32(dev
, mmio_base
+ B43_DMA32_RXCTL
, ctl
);
1608 /* Enable/Disable Direct FIFO Receive Mode (PIO) on a RX engine.
1609 * This is called from PIO code, so DMA structures are not available. */
1610 void b43_dma_direct_fifo_rx(struct b43_wldev
*dev
,
1611 unsigned int engine_index
, bool enable
)
1613 enum b43_dmatype type
;
1616 type
= dma_mask_to_engine_type(supported_dma_mask(dev
));
1618 mmio_base
= b43_dmacontroller_base(type
, engine_index
);
1619 direct_fifo_rx(dev
, type
, mmio_base
, enable
);
1621 #endif /* CONFIG_B43_PIO */